1 /* 2 * ARM Versatile Express emulation. 3 * 4 * Copyright (c) 2010 - 2011 B Labs Ltd. 5 * Copyright (c) 2011 Linaro Limited 6 * Written by Bahadir Balban, Amit Mahajan, Peter Maydell 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, see <http://www.gnu.org/licenses/>. 19 * 20 * Contributions after 2012-01-13 are licensed under the terms of the 21 * GNU GPL, version 2 or (at your option) any later version. 22 */ 23 24 #include "qemu/osdep.h" 25 #include "qapi/error.h" 26 #include "qemu-common.h" 27 #include "cpu.h" 28 #include "hw/sysbus.h" 29 #include "hw/arm/arm.h" 30 #include "hw/arm/primecell.h" 31 #include "hw/devices.h" 32 #include "hw/i2c/i2c.h" 33 #include "net/net.h" 34 #include "sysemu/sysemu.h" 35 #include "hw/boards.h" 36 #include "hw/loader.h" 37 #include "exec/address-spaces.h" 38 #include "hw/block/flash.h" 39 #include "sysemu/device_tree.h" 40 #include "qemu/error-report.h" 41 #include <libfdt.h> 42 #include "hw/char/pl011.h" 43 #include "hw/cpu/a9mpcore.h" 44 #include "hw/cpu/a15mpcore.h" 45 46 #define VEXPRESS_BOARD_ID 0x8e0 47 #define VEXPRESS_FLASH_SIZE (64 * 1024 * 1024) 48 #define VEXPRESS_FLASH_SECT_SIZE (256 * 1024) 49 50 /* Number of virtio transports to create (0..8; limited by 51 * number of available IRQ lines). 52 */ 53 #define NUM_VIRTIO_TRANSPORTS 4 54 55 /* Address maps for peripherals: 56 * the Versatile Express motherboard has two possible maps, 57 * the "legacy" one (used for A9) and the "Cortex-A Series" 58 * map (used for newer cores). 59 * Individual daughterboards can also have different maps for 60 * their peripherals. 61 */ 62 63 enum { 64 VE_SYSREGS, 65 VE_SP810, 66 VE_SERIALPCI, 67 VE_PL041, 68 VE_MMCI, 69 VE_KMI0, 70 VE_KMI1, 71 VE_UART0, 72 VE_UART1, 73 VE_UART2, 74 VE_UART3, 75 VE_WDT, 76 VE_TIMER01, 77 VE_TIMER23, 78 VE_SERIALDVI, 79 VE_RTC, 80 VE_COMPACTFLASH, 81 VE_CLCD, 82 VE_NORFLASH0, 83 VE_NORFLASH1, 84 VE_NORFLASHALIAS, 85 VE_SRAM, 86 VE_VIDEORAM, 87 VE_ETHERNET, 88 VE_USB, 89 VE_DAPROM, 90 VE_VIRTIO, 91 }; 92 93 static hwaddr motherboard_legacy_map[] = { 94 [VE_NORFLASHALIAS] = 0, 95 /* CS7: 0x10000000 .. 0x10020000 */ 96 [VE_SYSREGS] = 0x10000000, 97 [VE_SP810] = 0x10001000, 98 [VE_SERIALPCI] = 0x10002000, 99 [VE_PL041] = 0x10004000, 100 [VE_MMCI] = 0x10005000, 101 [VE_KMI0] = 0x10006000, 102 [VE_KMI1] = 0x10007000, 103 [VE_UART0] = 0x10009000, 104 [VE_UART1] = 0x1000a000, 105 [VE_UART2] = 0x1000b000, 106 [VE_UART3] = 0x1000c000, 107 [VE_WDT] = 0x1000f000, 108 [VE_TIMER01] = 0x10011000, 109 [VE_TIMER23] = 0x10012000, 110 [VE_VIRTIO] = 0x10013000, 111 [VE_SERIALDVI] = 0x10016000, 112 [VE_RTC] = 0x10017000, 113 [VE_COMPACTFLASH] = 0x1001a000, 114 [VE_CLCD] = 0x1001f000, 115 /* CS0: 0x40000000 .. 0x44000000 */ 116 [VE_NORFLASH0] = 0x40000000, 117 /* CS1: 0x44000000 .. 0x48000000 */ 118 [VE_NORFLASH1] = 0x44000000, 119 /* CS2: 0x48000000 .. 0x4a000000 */ 120 [VE_SRAM] = 0x48000000, 121 /* CS3: 0x4c000000 .. 0x50000000 */ 122 [VE_VIDEORAM] = 0x4c000000, 123 [VE_ETHERNET] = 0x4e000000, 124 [VE_USB] = 0x4f000000, 125 }; 126 127 static hwaddr motherboard_aseries_map[] = { 128 [VE_NORFLASHALIAS] = 0, 129 /* CS0: 0x08000000 .. 0x0c000000 */ 130 [VE_NORFLASH0] = 0x08000000, 131 /* CS4: 0x0c000000 .. 0x10000000 */ 132 [VE_NORFLASH1] = 0x0c000000, 133 /* CS5: 0x10000000 .. 0x14000000 */ 134 /* CS1: 0x14000000 .. 0x18000000 */ 135 [VE_SRAM] = 0x14000000, 136 /* CS2: 0x18000000 .. 0x1c000000 */ 137 [VE_VIDEORAM] = 0x18000000, 138 [VE_ETHERNET] = 0x1a000000, 139 [VE_USB] = 0x1b000000, 140 /* CS3: 0x1c000000 .. 0x20000000 */ 141 [VE_DAPROM] = 0x1c000000, 142 [VE_SYSREGS] = 0x1c010000, 143 [VE_SP810] = 0x1c020000, 144 [VE_SERIALPCI] = 0x1c030000, 145 [VE_PL041] = 0x1c040000, 146 [VE_MMCI] = 0x1c050000, 147 [VE_KMI0] = 0x1c060000, 148 [VE_KMI1] = 0x1c070000, 149 [VE_UART0] = 0x1c090000, 150 [VE_UART1] = 0x1c0a0000, 151 [VE_UART2] = 0x1c0b0000, 152 [VE_UART3] = 0x1c0c0000, 153 [VE_WDT] = 0x1c0f0000, 154 [VE_TIMER01] = 0x1c110000, 155 [VE_TIMER23] = 0x1c120000, 156 [VE_VIRTIO] = 0x1c130000, 157 [VE_SERIALDVI] = 0x1c160000, 158 [VE_RTC] = 0x1c170000, 159 [VE_COMPACTFLASH] = 0x1c1a0000, 160 [VE_CLCD] = 0x1c1f0000, 161 }; 162 163 /* Structure defining the peculiarities of a specific daughterboard */ 164 165 typedef struct VEDBoardInfo VEDBoardInfo; 166 167 typedef struct { 168 MachineClass parent; 169 VEDBoardInfo *daughterboard; 170 } VexpressMachineClass; 171 172 typedef struct { 173 MachineState parent; 174 bool secure; 175 } VexpressMachineState; 176 177 #define TYPE_VEXPRESS_MACHINE "vexpress" 178 #define TYPE_VEXPRESS_A9_MACHINE MACHINE_TYPE_NAME("vexpress-a9") 179 #define TYPE_VEXPRESS_A15_MACHINE MACHINE_TYPE_NAME("vexpress-a15") 180 #define VEXPRESS_MACHINE(obj) \ 181 OBJECT_CHECK(VexpressMachineState, (obj), TYPE_VEXPRESS_MACHINE) 182 #define VEXPRESS_MACHINE_GET_CLASS(obj) \ 183 OBJECT_GET_CLASS(VexpressMachineClass, obj, TYPE_VEXPRESS_MACHINE) 184 #define VEXPRESS_MACHINE_CLASS(klass) \ 185 OBJECT_CLASS_CHECK(VexpressMachineClass, klass, TYPE_VEXPRESS_MACHINE) 186 187 typedef void DBoardInitFn(const VexpressMachineState *machine, 188 ram_addr_t ram_size, 189 const char *cpu_type, 190 qemu_irq *pic); 191 192 struct VEDBoardInfo { 193 struct arm_boot_info bootinfo; 194 const hwaddr *motherboard_map; 195 hwaddr loader_start; 196 const hwaddr gic_cpu_if_addr; 197 uint32_t proc_id; 198 uint32_t num_voltage_sensors; 199 const uint32_t *voltages; 200 uint32_t num_clocks; 201 const uint32_t *clocks; 202 DBoardInitFn *init; 203 }; 204 205 static void init_cpus(const char *cpu_type, const char *privdev, 206 hwaddr periphbase, qemu_irq *pic, bool secure) 207 { 208 DeviceState *dev; 209 SysBusDevice *busdev; 210 int n; 211 212 /* Create the actual CPUs */ 213 for (n = 0; n < smp_cpus; n++) { 214 Object *cpuobj = object_new(cpu_type); 215 216 if (!secure) { 217 object_property_set_bool(cpuobj, false, "has_el3", NULL); 218 } 219 220 if (object_property_find(cpuobj, "reset-cbar", NULL)) { 221 object_property_set_int(cpuobj, periphbase, 222 "reset-cbar", &error_abort); 223 } 224 object_property_set_bool(cpuobj, true, "realized", &error_fatal); 225 } 226 227 /* Create the private peripheral devices (including the GIC); 228 * this must happen after the CPUs are created because a15mpcore_priv 229 * wires itself up to the CPU's generic_timer gpio out lines. 230 */ 231 dev = qdev_create(NULL, privdev); 232 qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); 233 qdev_init_nofail(dev); 234 busdev = SYS_BUS_DEVICE(dev); 235 sysbus_mmio_map(busdev, 0, periphbase); 236 237 /* Interrupts [42:0] are from the motherboard; 238 * [47:43] are reserved; [63:48] are daughterboard 239 * peripherals. Note that some documentation numbers 240 * external interrupts starting from 32 (because there 241 * are internal interrupts 0..31). 242 */ 243 for (n = 0; n < 64; n++) { 244 pic[n] = qdev_get_gpio_in(dev, n); 245 } 246 247 /* Connect the CPUs to the GIC */ 248 for (n = 0; n < smp_cpus; n++) { 249 DeviceState *cpudev = DEVICE(qemu_get_cpu(n)); 250 251 sysbus_connect_irq(busdev, n, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 252 sysbus_connect_irq(busdev, n + smp_cpus, 253 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 254 sysbus_connect_irq(busdev, n + 2 * smp_cpus, 255 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 256 sysbus_connect_irq(busdev, n + 3 * smp_cpus, 257 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 258 } 259 } 260 261 static void a9_daughterboard_init(const VexpressMachineState *vms, 262 ram_addr_t ram_size, 263 const char *cpu_type, 264 qemu_irq *pic) 265 { 266 MemoryRegion *sysmem = get_system_memory(); 267 MemoryRegion *ram = g_new(MemoryRegion, 1); 268 MemoryRegion *lowram = g_new(MemoryRegion, 1); 269 ram_addr_t low_ram_size; 270 271 if (ram_size > 0x40000000) { 272 /* 1GB is the maximum the address space permits */ 273 error_report("vexpress-a9: cannot model more than 1GB RAM"); 274 exit(1); 275 } 276 277 memory_region_allocate_system_memory(ram, NULL, "vexpress.highmem", 278 ram_size); 279 low_ram_size = ram_size; 280 if (low_ram_size > 0x4000000) { 281 low_ram_size = 0x4000000; 282 } 283 /* RAM is from 0x60000000 upwards. The bottom 64MB of the 284 * address space should in theory be remappable to various 285 * things including ROM or RAM; we always map the RAM there. 286 */ 287 memory_region_init_alias(lowram, NULL, "vexpress.lowmem", ram, 0, low_ram_size); 288 memory_region_add_subregion(sysmem, 0x0, lowram); 289 memory_region_add_subregion(sysmem, 0x60000000, ram); 290 291 /* 0x1e000000 A9MPCore (SCU) private memory region */ 292 init_cpus(cpu_type, TYPE_A9MPCORE_PRIV, 0x1e000000, pic, vms->secure); 293 294 /* Daughterboard peripherals : 0x10020000 .. 0x20000000 */ 295 296 /* 0x10020000 PL111 CLCD (daughterboard) */ 297 sysbus_create_simple("pl111", 0x10020000, pic[44]); 298 299 /* 0x10060000 AXI RAM */ 300 /* 0x100e0000 PL341 Dynamic Memory Controller */ 301 /* 0x100e1000 PL354 Static Memory Controller */ 302 /* 0x100e2000 System Configuration Controller */ 303 304 sysbus_create_simple("sp804", 0x100e4000, pic[48]); 305 /* 0x100e5000 SP805 Watchdog module */ 306 /* 0x100e6000 BP147 TrustZone Protection Controller */ 307 /* 0x100e9000 PL301 'Fast' AXI matrix */ 308 /* 0x100ea000 PL301 'Slow' AXI matrix */ 309 /* 0x100ec000 TrustZone Address Space Controller */ 310 /* 0x10200000 CoreSight debug APB */ 311 /* 0x1e00a000 PL310 L2 Cache Controller */ 312 sysbus_create_varargs("l2x0", 0x1e00a000, NULL); 313 } 314 315 /* Voltage values for SYS_CFG_VOLT daughterboard registers; 316 * values are in microvolts. 317 */ 318 static const uint32_t a9_voltages[] = { 319 1000000, /* VD10 : 1.0V : SoC internal logic voltage */ 320 1000000, /* VD10_S2 : 1.0V : PL310, L2 cache, RAM, non-PL310 logic */ 321 1000000, /* VD10_S3 : 1.0V : Cortex-A9, cores, MPEs, SCU, PL310 logic */ 322 1800000, /* VCC1V8 : 1.8V : DDR2 SDRAM, test chip DDR2 I/O supply */ 323 900000, /* DDR2VTT : 0.9V : DDR2 SDRAM VTT termination voltage */ 324 3300000, /* VCC3V3 : 3.3V : local board supply for misc external logic */ 325 }; 326 327 /* Reset values for daughterboard oscillators (in Hz) */ 328 static const uint32_t a9_clocks[] = { 329 45000000, /* AMBA AXI ACLK: 45MHz */ 330 23750000, /* daughterboard CLCD clock: 23.75MHz */ 331 66670000, /* Test chip reference clock: 66.67MHz */ 332 }; 333 334 static VEDBoardInfo a9_daughterboard = { 335 .motherboard_map = motherboard_legacy_map, 336 .loader_start = 0x60000000, 337 .gic_cpu_if_addr = 0x1e000100, 338 .proc_id = 0x0c000191, 339 .num_voltage_sensors = ARRAY_SIZE(a9_voltages), 340 .voltages = a9_voltages, 341 .num_clocks = ARRAY_SIZE(a9_clocks), 342 .clocks = a9_clocks, 343 .init = a9_daughterboard_init, 344 }; 345 346 static void a15_daughterboard_init(const VexpressMachineState *vms, 347 ram_addr_t ram_size, 348 const char *cpu_type, 349 qemu_irq *pic) 350 { 351 MemoryRegion *sysmem = get_system_memory(); 352 MemoryRegion *ram = g_new(MemoryRegion, 1); 353 MemoryRegion *sram = g_new(MemoryRegion, 1); 354 355 { 356 /* We have to use a separate 64 bit variable here to avoid the gcc 357 * "comparison is always false due to limited range of data type" 358 * warning if we are on a host where ram_addr_t is 32 bits. 359 */ 360 uint64_t rsz = ram_size; 361 if (rsz > (30ULL * 1024 * 1024 * 1024)) { 362 error_report("vexpress-a15: cannot model more than 30GB RAM"); 363 exit(1); 364 } 365 } 366 367 memory_region_allocate_system_memory(ram, NULL, "vexpress.highmem", 368 ram_size); 369 /* RAM is from 0x80000000 upwards; there is no low-memory alias for it. */ 370 memory_region_add_subregion(sysmem, 0x80000000, ram); 371 372 /* 0x2c000000 A15MPCore private memory region (GIC) */ 373 init_cpus(cpu_type, TYPE_A15MPCORE_PRIV, 0x2c000000, pic, vms->secure); 374 375 /* A15 daughterboard peripherals: */ 376 377 /* 0x20000000: CoreSight interfaces: not modelled */ 378 /* 0x2a000000: PL301 AXI interconnect: not modelled */ 379 /* 0x2a420000: SCC: not modelled */ 380 /* 0x2a430000: system counter: not modelled */ 381 /* 0x2b000000: HDLCD controller: not modelled */ 382 /* 0x2b060000: SP805 watchdog: not modelled */ 383 /* 0x2b0a0000: PL341 dynamic memory controller: not modelled */ 384 /* 0x2e000000: system SRAM */ 385 memory_region_init_ram(sram, NULL, "vexpress.a15sram", 0x10000, 386 &error_fatal); 387 memory_region_add_subregion(sysmem, 0x2e000000, sram); 388 389 /* 0x7ffb0000: DMA330 DMA controller: not modelled */ 390 /* 0x7ffd0000: PL354 static memory controller: not modelled */ 391 } 392 393 static const uint32_t a15_voltages[] = { 394 900000, /* Vcore: 0.9V : CPU core voltage */ 395 }; 396 397 static const uint32_t a15_clocks[] = { 398 60000000, /* OSCCLK0: 60MHz : CPU_CLK reference */ 399 0, /* OSCCLK1: reserved */ 400 0, /* OSCCLK2: reserved */ 401 0, /* OSCCLK3: reserved */ 402 40000000, /* OSCCLK4: 40MHz : external AXI master clock */ 403 23750000, /* OSCCLK5: 23.75MHz : HDLCD PLL reference */ 404 50000000, /* OSCCLK6: 50MHz : static memory controller clock */ 405 60000000, /* OSCCLK7: 60MHz : SYSCLK reference */ 406 40000000, /* OSCCLK8: 40MHz : DDR2 PLL reference */ 407 }; 408 409 static VEDBoardInfo a15_daughterboard = { 410 .motherboard_map = motherboard_aseries_map, 411 .loader_start = 0x80000000, 412 .gic_cpu_if_addr = 0x2c002000, 413 .proc_id = 0x14000237, 414 .num_voltage_sensors = ARRAY_SIZE(a15_voltages), 415 .voltages = a15_voltages, 416 .num_clocks = ARRAY_SIZE(a15_clocks), 417 .clocks = a15_clocks, 418 .init = a15_daughterboard_init, 419 }; 420 421 static int add_virtio_mmio_node(void *fdt, uint32_t acells, uint32_t scells, 422 hwaddr addr, hwaddr size, uint32_t intc, 423 int irq) 424 { 425 /* Add a virtio_mmio node to the device tree blob: 426 * virtio_mmio@ADDRESS { 427 * compatible = "virtio,mmio"; 428 * reg = <ADDRESS, SIZE>; 429 * interrupt-parent = <&intc>; 430 * interrupts = <0, irq, 1>; 431 * } 432 * (Note that the format of the interrupts property is dependent on the 433 * interrupt controller that interrupt-parent points to; these are for 434 * the ARM GIC and indicate an SPI interrupt, rising-edge-triggered.) 435 */ 436 int rc; 437 char *nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, addr); 438 439 rc = qemu_fdt_add_subnode(fdt, nodename); 440 rc |= qemu_fdt_setprop_string(fdt, nodename, 441 "compatible", "virtio,mmio"); 442 rc |= qemu_fdt_setprop_sized_cells(fdt, nodename, "reg", 443 acells, addr, scells, size); 444 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", intc); 445 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 0, irq, 1); 446 qemu_fdt_setprop(fdt, nodename, "dma-coherent", NULL, 0); 447 g_free(nodename); 448 if (rc) { 449 return -1; 450 } 451 return 0; 452 } 453 454 static uint32_t find_int_controller(void *fdt) 455 { 456 /* Find the FDT node corresponding to the interrupt controller 457 * for virtio-mmio devices. We do this by scanning the fdt for 458 * a node with the right compatibility, since we know there is 459 * only one GIC on a vexpress board. 460 * We return the phandle of the node, or 0 if none was found. 461 */ 462 const char *compat = "arm,cortex-a9-gic"; 463 int offset; 464 465 offset = fdt_node_offset_by_compatible(fdt, -1, compat); 466 if (offset >= 0) { 467 return fdt_get_phandle(fdt, offset); 468 } 469 return 0; 470 } 471 472 static void vexpress_modify_dtb(const struct arm_boot_info *info, void *fdt) 473 { 474 uint32_t acells, scells, intc; 475 const VEDBoardInfo *daughterboard = (const VEDBoardInfo *)info; 476 477 acells = qemu_fdt_getprop_cell(fdt, "/", "#address-cells", 478 NULL, &error_fatal); 479 scells = qemu_fdt_getprop_cell(fdt, "/", "#size-cells", 480 NULL, &error_fatal); 481 intc = find_int_controller(fdt); 482 if (!intc) { 483 /* Not fatal, we just won't provide virtio. This will 484 * happen with older device tree blobs. 485 */ 486 warn_report("couldn't find interrupt controller in " 487 "dtb; will not include virtio-mmio devices in the dtb"); 488 } else { 489 int i; 490 const hwaddr *map = daughterboard->motherboard_map; 491 492 /* We iterate backwards here because adding nodes 493 * to the dtb puts them in last-first. 494 */ 495 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) { 496 add_virtio_mmio_node(fdt, acells, scells, 497 map[VE_VIRTIO] + 0x200 * i, 498 0x200, intc, 40 + i); 499 } 500 } 501 } 502 503 504 /* Open code a private version of pflash registration since we 505 * need to set non-default device width for VExpress platform. 506 */ 507 static pflash_t *ve_pflash_cfi01_register(hwaddr base, const char *name, 508 DriveInfo *di) 509 { 510 DeviceState *dev = qdev_create(NULL, "cfi.pflash01"); 511 512 if (di) { 513 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(di), 514 &error_abort); 515 } 516 517 qdev_prop_set_uint32(dev, "num-blocks", 518 VEXPRESS_FLASH_SIZE / VEXPRESS_FLASH_SECT_SIZE); 519 qdev_prop_set_uint64(dev, "sector-length", VEXPRESS_FLASH_SECT_SIZE); 520 qdev_prop_set_uint8(dev, "width", 4); 521 qdev_prop_set_uint8(dev, "device-width", 2); 522 qdev_prop_set_bit(dev, "big-endian", false); 523 qdev_prop_set_uint16(dev, "id0", 0x89); 524 qdev_prop_set_uint16(dev, "id1", 0x18); 525 qdev_prop_set_uint16(dev, "id2", 0x00); 526 qdev_prop_set_uint16(dev, "id3", 0x00); 527 qdev_prop_set_string(dev, "name", name); 528 qdev_init_nofail(dev); 529 530 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 531 return OBJECT_CHECK(pflash_t, (dev), "cfi.pflash01"); 532 } 533 534 static void vexpress_common_init(MachineState *machine) 535 { 536 VexpressMachineState *vms = VEXPRESS_MACHINE(machine); 537 VexpressMachineClass *vmc = VEXPRESS_MACHINE_GET_CLASS(machine); 538 VEDBoardInfo *daughterboard = vmc->daughterboard; 539 DeviceState *dev, *sysctl, *pl041; 540 qemu_irq pic[64]; 541 uint32_t sys_id; 542 DriveInfo *dinfo; 543 pflash_t *pflash0; 544 I2CBus *i2c; 545 ram_addr_t vram_size, sram_size; 546 MemoryRegion *sysmem = get_system_memory(); 547 MemoryRegion *vram = g_new(MemoryRegion, 1); 548 MemoryRegion *sram = g_new(MemoryRegion, 1); 549 MemoryRegion *flashalias = g_new(MemoryRegion, 1); 550 MemoryRegion *flash0mem; 551 const hwaddr *map = daughterboard->motherboard_map; 552 int i; 553 554 daughterboard->init(vms, machine->ram_size, machine->cpu_type, pic); 555 556 /* 557 * If a bios file was provided, attempt to map it into memory 558 */ 559 if (bios_name) { 560 char *fn; 561 int image_size; 562 563 if (drive_get(IF_PFLASH, 0, 0)) { 564 error_report("The contents of the first flash device may be " 565 "specified with -bios or with -drive if=pflash... " 566 "but you cannot use both options at once"); 567 exit(1); 568 } 569 fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 570 if (!fn) { 571 error_report("Could not find ROM image '%s'", bios_name); 572 exit(1); 573 } 574 image_size = load_image_targphys(fn, map[VE_NORFLASH0], 575 VEXPRESS_FLASH_SIZE); 576 g_free(fn); 577 if (image_size < 0) { 578 error_report("Could not load ROM image '%s'", bios_name); 579 exit(1); 580 } 581 } 582 583 /* Motherboard peripherals: the wiring is the same but the 584 * addresses vary between the legacy and A-Series memory maps. 585 */ 586 587 sys_id = 0x1190f500; 588 589 sysctl = qdev_create(NULL, "realview_sysctl"); 590 qdev_prop_set_uint32(sysctl, "sys_id", sys_id); 591 qdev_prop_set_uint32(sysctl, "proc_id", daughterboard->proc_id); 592 qdev_prop_set_uint32(sysctl, "len-db-voltage", 593 daughterboard->num_voltage_sensors); 594 for (i = 0; i < daughterboard->num_voltage_sensors; i++) { 595 char *propname = g_strdup_printf("db-voltage[%d]", i); 596 qdev_prop_set_uint32(sysctl, propname, daughterboard->voltages[i]); 597 g_free(propname); 598 } 599 qdev_prop_set_uint32(sysctl, "len-db-clock", 600 daughterboard->num_clocks); 601 for (i = 0; i < daughterboard->num_clocks; i++) { 602 char *propname = g_strdup_printf("db-clock[%d]", i); 603 qdev_prop_set_uint32(sysctl, propname, daughterboard->clocks[i]); 604 g_free(propname); 605 } 606 qdev_init_nofail(sysctl); 607 sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, map[VE_SYSREGS]); 608 609 /* VE_SP810: not modelled */ 610 /* VE_SERIALPCI: not modelled */ 611 612 pl041 = qdev_create(NULL, "pl041"); 613 qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512); 614 qdev_init_nofail(pl041); 615 sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, map[VE_PL041]); 616 sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, pic[11]); 617 618 dev = sysbus_create_varargs("pl181", map[VE_MMCI], pic[9], pic[10], NULL); 619 /* Wire up MMC card detect and read-only signals */ 620 qdev_connect_gpio_out(dev, 0, 621 qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT)); 622 qdev_connect_gpio_out(dev, 1, 623 qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN)); 624 625 sysbus_create_simple("pl050_keyboard", map[VE_KMI0], pic[12]); 626 sysbus_create_simple("pl050_mouse", map[VE_KMI1], pic[13]); 627 628 pl011_create(map[VE_UART0], pic[5], serial_hd(0)); 629 pl011_create(map[VE_UART1], pic[6], serial_hd(1)); 630 pl011_create(map[VE_UART2], pic[7], serial_hd(2)); 631 pl011_create(map[VE_UART3], pic[8], serial_hd(3)); 632 633 sysbus_create_simple("sp804", map[VE_TIMER01], pic[2]); 634 sysbus_create_simple("sp804", map[VE_TIMER23], pic[3]); 635 636 dev = sysbus_create_simple("versatile_i2c", map[VE_SERIALDVI], NULL); 637 i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c"); 638 i2c_create_slave(i2c, "sii9022", 0x39); 639 640 sysbus_create_simple("pl031", map[VE_RTC], pic[4]); /* RTC */ 641 642 /* VE_COMPACTFLASH: not modelled */ 643 644 sysbus_create_simple("pl111", map[VE_CLCD], pic[14]); 645 646 dinfo = drive_get_next(IF_PFLASH); 647 pflash0 = ve_pflash_cfi01_register(map[VE_NORFLASH0], "vexpress.flash0", 648 dinfo); 649 if (!pflash0) { 650 error_report("vexpress: error registering flash 0"); 651 exit(1); 652 } 653 654 if (map[VE_NORFLASHALIAS] != -1) { 655 /* Map flash 0 as an alias into low memory */ 656 flash0mem = sysbus_mmio_get_region(SYS_BUS_DEVICE(pflash0), 0); 657 memory_region_init_alias(flashalias, NULL, "vexpress.flashalias", 658 flash0mem, 0, VEXPRESS_FLASH_SIZE); 659 memory_region_add_subregion(sysmem, map[VE_NORFLASHALIAS], flashalias); 660 } 661 662 dinfo = drive_get_next(IF_PFLASH); 663 if (!ve_pflash_cfi01_register(map[VE_NORFLASH1], "vexpress.flash1", 664 dinfo)) { 665 error_report("vexpress: error registering flash 1"); 666 exit(1); 667 } 668 669 sram_size = 0x2000000; 670 memory_region_init_ram(sram, NULL, "vexpress.sram", sram_size, 671 &error_fatal); 672 memory_region_add_subregion(sysmem, map[VE_SRAM], sram); 673 674 vram_size = 0x800000; 675 memory_region_init_ram(vram, NULL, "vexpress.vram", vram_size, 676 &error_fatal); 677 memory_region_add_subregion(sysmem, map[VE_VIDEORAM], vram); 678 679 /* 0x4e000000 LAN9118 Ethernet */ 680 if (nd_table[0].used) { 681 lan9118_init(&nd_table[0], map[VE_ETHERNET], pic[15]); 682 } 683 684 /* VE_USB: not modelled */ 685 686 /* VE_DAPROM: not modelled */ 687 688 /* Create mmio transports, so the user can create virtio backends 689 * (which will be automatically plugged in to the transports). If 690 * no backend is created the transport will just sit harmlessly idle. 691 */ 692 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) { 693 sysbus_create_simple("virtio-mmio", map[VE_VIRTIO] + 0x200 * i, 694 pic[40 + i]); 695 } 696 697 daughterboard->bootinfo.ram_size = machine->ram_size; 698 daughterboard->bootinfo.kernel_filename = machine->kernel_filename; 699 daughterboard->bootinfo.kernel_cmdline = machine->kernel_cmdline; 700 daughterboard->bootinfo.initrd_filename = machine->initrd_filename; 701 daughterboard->bootinfo.nb_cpus = smp_cpus; 702 daughterboard->bootinfo.board_id = VEXPRESS_BOARD_ID; 703 daughterboard->bootinfo.loader_start = daughterboard->loader_start; 704 daughterboard->bootinfo.smp_loader_start = map[VE_SRAM]; 705 daughterboard->bootinfo.smp_bootreg_addr = map[VE_SYSREGS] + 0x30; 706 daughterboard->bootinfo.gic_cpu_if_addr = daughterboard->gic_cpu_if_addr; 707 daughterboard->bootinfo.modify_dtb = vexpress_modify_dtb; 708 /* Indicate that when booting Linux we should be in secure state */ 709 daughterboard->bootinfo.secure_boot = true; 710 arm_load_kernel(ARM_CPU(first_cpu), &daughterboard->bootinfo); 711 } 712 713 static bool vexpress_get_secure(Object *obj, Error **errp) 714 { 715 VexpressMachineState *vms = VEXPRESS_MACHINE(obj); 716 717 return vms->secure; 718 } 719 720 static void vexpress_set_secure(Object *obj, bool value, Error **errp) 721 { 722 VexpressMachineState *vms = VEXPRESS_MACHINE(obj); 723 724 vms->secure = value; 725 } 726 727 static void vexpress_instance_init(Object *obj) 728 { 729 VexpressMachineState *vms = VEXPRESS_MACHINE(obj); 730 731 /* EL3 is enabled by default on vexpress */ 732 vms->secure = true; 733 object_property_add_bool(obj, "secure", vexpress_get_secure, 734 vexpress_set_secure, NULL); 735 object_property_set_description(obj, "secure", 736 "Set on/off to enable/disable the ARM " 737 "Security Extensions (TrustZone)", 738 NULL); 739 } 740 741 static void vexpress_class_init(ObjectClass *oc, void *data) 742 { 743 MachineClass *mc = MACHINE_CLASS(oc); 744 745 mc->desc = "ARM Versatile Express"; 746 mc->init = vexpress_common_init; 747 mc->max_cpus = 4; 748 mc->ignore_memory_transaction_failures = true; 749 } 750 751 static void vexpress_a9_class_init(ObjectClass *oc, void *data) 752 { 753 MachineClass *mc = MACHINE_CLASS(oc); 754 VexpressMachineClass *vmc = VEXPRESS_MACHINE_CLASS(oc); 755 756 mc->desc = "ARM Versatile Express for Cortex-A9"; 757 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9"); 758 759 vmc->daughterboard = &a9_daughterboard; 760 } 761 762 static void vexpress_a15_class_init(ObjectClass *oc, void *data) 763 { 764 MachineClass *mc = MACHINE_CLASS(oc); 765 VexpressMachineClass *vmc = VEXPRESS_MACHINE_CLASS(oc); 766 767 mc->desc = "ARM Versatile Express for Cortex-A15"; 768 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"); 769 770 vmc->daughterboard = &a15_daughterboard; 771 } 772 773 static const TypeInfo vexpress_info = { 774 .name = TYPE_VEXPRESS_MACHINE, 775 .parent = TYPE_MACHINE, 776 .abstract = true, 777 .instance_size = sizeof(VexpressMachineState), 778 .instance_init = vexpress_instance_init, 779 .class_size = sizeof(VexpressMachineClass), 780 .class_init = vexpress_class_init, 781 }; 782 783 static const TypeInfo vexpress_a9_info = { 784 .name = TYPE_VEXPRESS_A9_MACHINE, 785 .parent = TYPE_VEXPRESS_MACHINE, 786 .class_init = vexpress_a9_class_init, 787 }; 788 789 static const TypeInfo vexpress_a15_info = { 790 .name = TYPE_VEXPRESS_A15_MACHINE, 791 .parent = TYPE_VEXPRESS_MACHINE, 792 .class_init = vexpress_a15_class_init, 793 }; 794 795 static void vexpress_machine_init(void) 796 { 797 type_register_static(&vexpress_info); 798 type_register_static(&vexpress_a9_info); 799 type_register_static(&vexpress_a15_info); 800 } 801 802 type_init(vexpress_machine_init); 803