12055283bSPeter Maydell /* 22055283bSPeter Maydell * ARM Versatile Express emulation. 32055283bSPeter Maydell * 42055283bSPeter Maydell * Copyright (c) 2010 - 2011 B Labs Ltd. 52055283bSPeter Maydell * Copyright (c) 2011 Linaro Limited 62055283bSPeter Maydell * Written by Bahadir Balban, Amit Mahajan, Peter Maydell 72055283bSPeter Maydell * 82055283bSPeter Maydell * This program is free software; you can redistribute it and/or modify 92055283bSPeter Maydell * it under the terms of the GNU General Public License version 2 as 102055283bSPeter Maydell * published by the Free Software Foundation. 112055283bSPeter Maydell * 122055283bSPeter Maydell * This program is distributed in the hope that it will be useful, 132055283bSPeter Maydell * but WITHOUT ANY WARRANTY; without even the implied warranty of 142055283bSPeter Maydell * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 152055283bSPeter Maydell * GNU General Public License for more details. 162055283bSPeter Maydell * 172055283bSPeter Maydell * You should have received a copy of the GNU General Public License along 182055283bSPeter Maydell * with this program; if not, see <http://www.gnu.org/licenses/>. 196b620ca3SPaolo Bonzini * 206b620ca3SPaolo Bonzini * Contributions after 2012-01-13 are licensed under the terms of the 216b620ca3SPaolo Bonzini * GNU GPL, version 2 or (at your option) any later version. 222055283bSPeter Maydell */ 232055283bSPeter Maydell 2483c9f4caSPaolo Bonzini #include "hw/sysbus.h" 25bd2be150SPeter Maydell #include "hw/arm/arm.h" 260d09e41aSPaolo Bonzini #include "hw/arm/primecell.h" 27bd2be150SPeter Maydell #include "hw/devices.h" 281422e32dSPaolo Bonzini #include "net/net.h" 299c17d615SPaolo Bonzini #include "sysemu/sysemu.h" 3083c9f4caSPaolo Bonzini #include "hw/boards.h" 31022c62cbSPaolo Bonzini #include "exec/address-spaces.h" 329c17d615SPaolo Bonzini #include "sysemu/blockdev.h" 330d09e41aSPaolo Bonzini #include "hw/block/flash.h" 34c8a07b35SPeter Maydell #include "sysemu/device_tree.h" 35*9948c38bSPeter Maydell #include "qemu/error-report.h" 36c8a07b35SPeter Maydell #include <libfdt.h> 372055283bSPeter Maydell 382055283bSPeter Maydell #define VEXPRESS_BOARD_ID 0x8e0 393dc3e7ddSFrancesco Lavra #define VEXPRESS_FLASH_SIZE (64 * 1024 * 1024) 403dc3e7ddSFrancesco Lavra #define VEXPRESS_FLASH_SECT_SIZE (256 * 1024) 412055283bSPeter Maydell 42c8a07b35SPeter Maydell /* Number of virtio transports to create (0..8; limited by 43c8a07b35SPeter Maydell * number of available IRQ lines). 44c8a07b35SPeter Maydell */ 45c8a07b35SPeter Maydell #define NUM_VIRTIO_TRANSPORTS 4 46c8a07b35SPeter Maydell 472558e0a6SPeter Maydell /* Address maps for peripherals: 482558e0a6SPeter Maydell * the Versatile Express motherboard has two possible maps, 492558e0a6SPeter Maydell * the "legacy" one (used for A9) and the "Cortex-A Series" 502558e0a6SPeter Maydell * map (used for newer cores). 512558e0a6SPeter Maydell * Individual daughterboards can also have different maps for 522558e0a6SPeter Maydell * their peripherals. 532558e0a6SPeter Maydell */ 542558e0a6SPeter Maydell 552558e0a6SPeter Maydell enum { 562558e0a6SPeter Maydell VE_SYSREGS, 572558e0a6SPeter Maydell VE_SP810, 582558e0a6SPeter Maydell VE_SERIALPCI, 592558e0a6SPeter Maydell VE_PL041, 602558e0a6SPeter Maydell VE_MMCI, 612558e0a6SPeter Maydell VE_KMI0, 622558e0a6SPeter Maydell VE_KMI1, 632558e0a6SPeter Maydell VE_UART0, 642558e0a6SPeter Maydell VE_UART1, 652558e0a6SPeter Maydell VE_UART2, 662558e0a6SPeter Maydell VE_UART3, 672558e0a6SPeter Maydell VE_WDT, 682558e0a6SPeter Maydell VE_TIMER01, 692558e0a6SPeter Maydell VE_TIMER23, 702558e0a6SPeter Maydell VE_SERIALDVI, 712558e0a6SPeter Maydell VE_RTC, 722558e0a6SPeter Maydell VE_COMPACTFLASH, 732558e0a6SPeter Maydell VE_CLCD, 742558e0a6SPeter Maydell VE_NORFLASH0, 752558e0a6SPeter Maydell VE_NORFLASH1, 768941d6ceSPeter Maydell VE_NORFLASHALIAS, 772558e0a6SPeter Maydell VE_SRAM, 782558e0a6SPeter Maydell VE_VIDEORAM, 792558e0a6SPeter Maydell VE_ETHERNET, 802558e0a6SPeter Maydell VE_USB, 812558e0a6SPeter Maydell VE_DAPROM, 82c8a07b35SPeter Maydell VE_VIRTIO, 832558e0a6SPeter Maydell }; 842558e0a6SPeter Maydell 85a8170e5eSAvi Kivity static hwaddr motherboard_legacy_map[] = { 862558e0a6SPeter Maydell /* CS7: 0x10000000 .. 0x10020000 */ 872558e0a6SPeter Maydell [VE_SYSREGS] = 0x10000000, 882558e0a6SPeter Maydell [VE_SP810] = 0x10001000, 892558e0a6SPeter Maydell [VE_SERIALPCI] = 0x10002000, 902558e0a6SPeter Maydell [VE_PL041] = 0x10004000, 912558e0a6SPeter Maydell [VE_MMCI] = 0x10005000, 922558e0a6SPeter Maydell [VE_KMI0] = 0x10006000, 932558e0a6SPeter Maydell [VE_KMI1] = 0x10007000, 942558e0a6SPeter Maydell [VE_UART0] = 0x10009000, 952558e0a6SPeter Maydell [VE_UART1] = 0x1000a000, 962558e0a6SPeter Maydell [VE_UART2] = 0x1000b000, 972558e0a6SPeter Maydell [VE_UART3] = 0x1000c000, 982558e0a6SPeter Maydell [VE_WDT] = 0x1000f000, 992558e0a6SPeter Maydell [VE_TIMER01] = 0x10011000, 1002558e0a6SPeter Maydell [VE_TIMER23] = 0x10012000, 101c8a07b35SPeter Maydell [VE_VIRTIO] = 0x10013000, 1022558e0a6SPeter Maydell [VE_SERIALDVI] = 0x10016000, 1032558e0a6SPeter Maydell [VE_RTC] = 0x10017000, 1042558e0a6SPeter Maydell [VE_COMPACTFLASH] = 0x1001a000, 1052558e0a6SPeter Maydell [VE_CLCD] = 0x1001f000, 1062558e0a6SPeter Maydell /* CS0: 0x40000000 .. 0x44000000 */ 1072558e0a6SPeter Maydell [VE_NORFLASH0] = 0x40000000, 1082558e0a6SPeter Maydell /* CS1: 0x44000000 .. 0x48000000 */ 1092558e0a6SPeter Maydell [VE_NORFLASH1] = 0x44000000, 1102558e0a6SPeter Maydell /* CS2: 0x48000000 .. 0x4a000000 */ 1112558e0a6SPeter Maydell [VE_SRAM] = 0x48000000, 1122558e0a6SPeter Maydell /* CS3: 0x4c000000 .. 0x50000000 */ 1132558e0a6SPeter Maydell [VE_VIDEORAM] = 0x4c000000, 1142558e0a6SPeter Maydell [VE_ETHERNET] = 0x4e000000, 1152558e0a6SPeter Maydell [VE_USB] = 0x4f000000, 1168941d6ceSPeter Maydell [VE_NORFLASHALIAS] = -1, /* not present */ 1172055283bSPeter Maydell }; 1182055283bSPeter Maydell 119a8170e5eSAvi Kivity static hwaddr motherboard_aseries_map[] = { 1208941d6ceSPeter Maydell [VE_NORFLASHALIAS] = 0, 121661bafb3SFrancesco Lavra /* CS0: 0x08000000 .. 0x0c000000 */ 122661bafb3SFrancesco Lavra [VE_NORFLASH0] = 0x08000000, 123961f195eSPeter Maydell /* CS4: 0x0c000000 .. 0x10000000 */ 124961f195eSPeter Maydell [VE_NORFLASH1] = 0x0c000000, 125961f195eSPeter Maydell /* CS5: 0x10000000 .. 0x14000000 */ 126961f195eSPeter Maydell /* CS1: 0x14000000 .. 0x18000000 */ 127961f195eSPeter Maydell [VE_SRAM] = 0x14000000, 128961f195eSPeter Maydell /* CS2: 0x18000000 .. 0x1c000000 */ 129961f195eSPeter Maydell [VE_VIDEORAM] = 0x18000000, 130961f195eSPeter Maydell [VE_ETHERNET] = 0x1a000000, 131961f195eSPeter Maydell [VE_USB] = 0x1b000000, 132961f195eSPeter Maydell /* CS3: 0x1c000000 .. 0x20000000 */ 133961f195eSPeter Maydell [VE_DAPROM] = 0x1c000000, 134961f195eSPeter Maydell [VE_SYSREGS] = 0x1c010000, 135961f195eSPeter Maydell [VE_SP810] = 0x1c020000, 136961f195eSPeter Maydell [VE_SERIALPCI] = 0x1c030000, 137961f195eSPeter Maydell [VE_PL041] = 0x1c040000, 138961f195eSPeter Maydell [VE_MMCI] = 0x1c050000, 139961f195eSPeter Maydell [VE_KMI0] = 0x1c060000, 140961f195eSPeter Maydell [VE_KMI1] = 0x1c070000, 141961f195eSPeter Maydell [VE_UART0] = 0x1c090000, 142961f195eSPeter Maydell [VE_UART1] = 0x1c0a0000, 143961f195eSPeter Maydell [VE_UART2] = 0x1c0b0000, 144961f195eSPeter Maydell [VE_UART3] = 0x1c0c0000, 145961f195eSPeter Maydell [VE_WDT] = 0x1c0f0000, 146961f195eSPeter Maydell [VE_TIMER01] = 0x1c110000, 147961f195eSPeter Maydell [VE_TIMER23] = 0x1c120000, 148c8a07b35SPeter Maydell [VE_VIRTIO] = 0x1c130000, 149961f195eSPeter Maydell [VE_SERIALDVI] = 0x1c160000, 150961f195eSPeter Maydell [VE_RTC] = 0x1c170000, 151961f195eSPeter Maydell [VE_COMPACTFLASH] = 0x1c1a0000, 152961f195eSPeter Maydell [VE_CLCD] = 0x1c1f0000, 153961f195eSPeter Maydell }; 154961f195eSPeter Maydell 1554c3b29b8SPeter Maydell /* Structure defining the peculiarities of a specific daughterboard */ 1564c3b29b8SPeter Maydell 1574c3b29b8SPeter Maydell typedef struct VEDBoardInfo VEDBoardInfo; 1584c3b29b8SPeter Maydell 1594c3b29b8SPeter Maydell typedef void DBoardInitFn(const VEDBoardInfo *daughterboard, 1604c3b29b8SPeter Maydell ram_addr_t ram_size, 1614c3b29b8SPeter Maydell const char *cpu_model, 162cdef10bbSPeter Maydell qemu_irq *pic); 1634c3b29b8SPeter Maydell 1644c3b29b8SPeter Maydell struct VEDBoardInfo { 165cef04a26SPeter Maydell struct arm_boot_info bootinfo; 166a8170e5eSAvi Kivity const hwaddr *motherboard_map; 167a8170e5eSAvi Kivity hwaddr loader_start; 168a8170e5eSAvi Kivity const hwaddr gic_cpu_if_addr; 169cdef10bbSPeter Maydell uint32_t proc_id; 17031410948SPeter Maydell uint32_t num_voltage_sensors; 17131410948SPeter Maydell const uint32_t *voltages; 1729c7d4893SPeter Maydell uint32_t num_clocks; 1739c7d4893SPeter Maydell const uint32_t *clocks; 1744c3b29b8SPeter Maydell DBoardInitFn *init; 1754c3b29b8SPeter Maydell }; 1764c3b29b8SPeter Maydell 177*9948c38bSPeter Maydell static void init_cpus(const char *cpu_model, const char *privdev, 178*9948c38bSPeter Maydell hwaddr periphbase, qemu_irq *pic) 179*9948c38bSPeter Maydell { 180*9948c38bSPeter Maydell ObjectClass *cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model); 181*9948c38bSPeter Maydell DeviceState *dev; 182*9948c38bSPeter Maydell SysBusDevice *busdev; 183*9948c38bSPeter Maydell int n; 184*9948c38bSPeter Maydell 185*9948c38bSPeter Maydell if (!cpu_oc) { 186*9948c38bSPeter Maydell fprintf(stderr, "Unable to find CPU definition\n"); 187*9948c38bSPeter Maydell exit(1); 188*9948c38bSPeter Maydell } 189*9948c38bSPeter Maydell 190*9948c38bSPeter Maydell /* Create the actual CPUs */ 191*9948c38bSPeter Maydell for (n = 0; n < smp_cpus; n++) { 192*9948c38bSPeter Maydell Object *cpuobj = object_new(object_class_get_name(cpu_oc)); 193*9948c38bSPeter Maydell Error *err = NULL; 194*9948c38bSPeter Maydell 195*9948c38bSPeter Maydell object_property_set_int(cpuobj, periphbase, "reset-cbar", &err); 196*9948c38bSPeter Maydell if (err) { 197*9948c38bSPeter Maydell error_report("%s", error_get_pretty(err)); 198*9948c38bSPeter Maydell exit(1); 199*9948c38bSPeter Maydell } 200*9948c38bSPeter Maydell object_property_set_bool(cpuobj, true, "realized", &err); 201*9948c38bSPeter Maydell if (err) { 202*9948c38bSPeter Maydell error_report("%s", error_get_pretty(err)); 203*9948c38bSPeter Maydell exit(1); 204*9948c38bSPeter Maydell } 205*9948c38bSPeter Maydell } 206*9948c38bSPeter Maydell 207*9948c38bSPeter Maydell /* Create the private peripheral devices (including the GIC); 208*9948c38bSPeter Maydell * this must happen after the CPUs are created because a15mpcore_priv 209*9948c38bSPeter Maydell * wires itself up to the CPU's generic_timer gpio out lines. 210*9948c38bSPeter Maydell */ 211*9948c38bSPeter Maydell dev = qdev_create(NULL, privdev); 212*9948c38bSPeter Maydell qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); 213*9948c38bSPeter Maydell qdev_init_nofail(dev); 214*9948c38bSPeter Maydell busdev = SYS_BUS_DEVICE(dev); 215*9948c38bSPeter Maydell sysbus_mmio_map(busdev, 0, periphbase); 216*9948c38bSPeter Maydell 217*9948c38bSPeter Maydell /* Interrupts [42:0] are from the motherboard; 218*9948c38bSPeter Maydell * [47:43] are reserved; [63:48] are daughterboard 219*9948c38bSPeter Maydell * peripherals. Note that some documentation numbers 220*9948c38bSPeter Maydell * external interrupts starting from 32 (because there 221*9948c38bSPeter Maydell * are internal interrupts 0..31). 222*9948c38bSPeter Maydell */ 223*9948c38bSPeter Maydell for (n = 0; n < 64; n++) { 224*9948c38bSPeter Maydell pic[n] = qdev_get_gpio_in(dev, n); 225*9948c38bSPeter Maydell } 226*9948c38bSPeter Maydell 227*9948c38bSPeter Maydell /* Connect the CPUs to the GIC */ 228*9948c38bSPeter Maydell for (n = 0; n < smp_cpus; n++) { 229*9948c38bSPeter Maydell DeviceState *cpudev = DEVICE(qemu_get_cpu(n)); 230*9948c38bSPeter Maydell 231*9948c38bSPeter Maydell sysbus_connect_irq(busdev, n, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 232*9948c38bSPeter Maydell } 233*9948c38bSPeter Maydell } 234*9948c38bSPeter Maydell 2354c3b29b8SPeter Maydell static void a9_daughterboard_init(const VEDBoardInfo *daughterboard, 2364c3b29b8SPeter Maydell ram_addr_t ram_size, 2374c3b29b8SPeter Maydell const char *cpu_model, 238cdef10bbSPeter Maydell qemu_irq *pic) 2392055283bSPeter Maydell { 240e6d17b05SAvi Kivity MemoryRegion *sysmem = get_system_memory(); 241e6d17b05SAvi Kivity MemoryRegion *ram = g_new(MemoryRegion, 1); 242e6d17b05SAvi Kivity MemoryRegion *lowram = g_new(MemoryRegion, 1); 2434c3b29b8SPeter Maydell ram_addr_t low_ram_size; 2442055283bSPeter Maydell 2452055283bSPeter Maydell if (!cpu_model) { 2462055283bSPeter Maydell cpu_model = "cortex-a9"; 2472055283bSPeter Maydell } 2482055283bSPeter Maydell 2492055283bSPeter Maydell if (ram_size > 0x40000000) { 2502055283bSPeter Maydell /* 1GB is the maximum the address space permits */ 2514c3b29b8SPeter Maydell fprintf(stderr, "vexpress-a9: cannot model more than 1GB RAM\n"); 2522055283bSPeter Maydell exit(1); 2532055283bSPeter Maydell } 2542055283bSPeter Maydell 2552c9b15caSPaolo Bonzini memory_region_init_ram(ram, NULL, "vexpress.highmem", ram_size); 256c5705a77SAvi Kivity vmstate_register_ram_global(ram); 2572055283bSPeter Maydell low_ram_size = ram_size; 2582055283bSPeter Maydell if (low_ram_size > 0x4000000) { 2592055283bSPeter Maydell low_ram_size = 0x4000000; 2602055283bSPeter Maydell } 2612055283bSPeter Maydell /* RAM is from 0x60000000 upwards. The bottom 64MB of the 2622055283bSPeter Maydell * address space should in theory be remappable to various 2632055283bSPeter Maydell * things including ROM or RAM; we always map the RAM there. 2642055283bSPeter Maydell */ 2652c9b15caSPaolo Bonzini memory_region_init_alias(lowram, NULL, "vexpress.lowmem", ram, 0, low_ram_size); 266e6d17b05SAvi Kivity memory_region_add_subregion(sysmem, 0x0, lowram); 267e6d17b05SAvi Kivity memory_region_add_subregion(sysmem, 0x60000000, ram); 2682055283bSPeter Maydell 2692055283bSPeter Maydell /* 0x1e000000 A9MPCore (SCU) private memory region */ 270*9948c38bSPeter Maydell init_cpus(cpu_model, "a9mpcore_priv", 0x1e000000, pic); 2712055283bSPeter Maydell 2724c3b29b8SPeter Maydell /* Daughterboard peripherals : 0x10020000 .. 0x20000000 */ 2734c3b29b8SPeter Maydell 2744c3b29b8SPeter Maydell /* 0x10020000 PL111 CLCD (daughterboard) */ 2754c3b29b8SPeter Maydell sysbus_create_simple("pl111", 0x10020000, pic[44]); 2764c3b29b8SPeter Maydell 2774c3b29b8SPeter Maydell /* 0x10060000 AXI RAM */ 2784c3b29b8SPeter Maydell /* 0x100e0000 PL341 Dynamic Memory Controller */ 2794c3b29b8SPeter Maydell /* 0x100e1000 PL354 Static Memory Controller */ 2804c3b29b8SPeter Maydell /* 0x100e2000 System Configuration Controller */ 2814c3b29b8SPeter Maydell 2824c3b29b8SPeter Maydell sysbus_create_simple("sp804", 0x100e4000, pic[48]); 2834c3b29b8SPeter Maydell /* 0x100e5000 SP805 Watchdog module */ 2844c3b29b8SPeter Maydell /* 0x100e6000 BP147 TrustZone Protection Controller */ 2854c3b29b8SPeter Maydell /* 0x100e9000 PL301 'Fast' AXI matrix */ 2864c3b29b8SPeter Maydell /* 0x100ea000 PL301 'Slow' AXI matrix */ 2874c3b29b8SPeter Maydell /* 0x100ec000 TrustZone Address Space Controller */ 2884c3b29b8SPeter Maydell /* 0x10200000 CoreSight debug APB */ 2894c3b29b8SPeter Maydell /* 0x1e00a000 PL310 L2 Cache Controller */ 2904c3b29b8SPeter Maydell sysbus_create_varargs("l2x0", 0x1e00a000, NULL); 2914c3b29b8SPeter Maydell } 2924c3b29b8SPeter Maydell 29331410948SPeter Maydell /* Voltage values for SYS_CFG_VOLT daughterboard registers; 29431410948SPeter Maydell * values are in microvolts. 29531410948SPeter Maydell */ 29631410948SPeter Maydell static const uint32_t a9_voltages[] = { 29731410948SPeter Maydell 1000000, /* VD10 : 1.0V : SoC internal logic voltage */ 29831410948SPeter Maydell 1000000, /* VD10_S2 : 1.0V : PL310, L2 cache, RAM, non-PL310 logic */ 29931410948SPeter Maydell 1000000, /* VD10_S3 : 1.0V : Cortex-A9, cores, MPEs, SCU, PL310 logic */ 30031410948SPeter Maydell 1800000, /* VCC1V8 : 1.8V : DDR2 SDRAM, test chip DDR2 I/O supply */ 30131410948SPeter Maydell 900000, /* DDR2VTT : 0.9V : DDR2 SDRAM VTT termination voltage */ 30231410948SPeter Maydell 3300000, /* VCC3V3 : 3.3V : local board supply for misc external logic */ 30331410948SPeter Maydell }; 30431410948SPeter Maydell 3059c7d4893SPeter Maydell /* Reset values for daughterboard oscillators (in Hz) */ 3069c7d4893SPeter Maydell static const uint32_t a9_clocks[] = { 3079c7d4893SPeter Maydell 45000000, /* AMBA AXI ACLK: 45MHz */ 3089c7d4893SPeter Maydell 23750000, /* daughterboard CLCD clock: 23.75MHz */ 3099c7d4893SPeter Maydell 66670000, /* Test chip reference clock: 66.67MHz */ 3109c7d4893SPeter Maydell }; 3119c7d4893SPeter Maydell 312cef04a26SPeter Maydell static VEDBoardInfo a9_daughterboard = { 3134c3b29b8SPeter Maydell .motherboard_map = motherboard_legacy_map, 3144c3b29b8SPeter Maydell .loader_start = 0x60000000, 31596eacf64SPeter Maydell .gic_cpu_if_addr = 0x1e000100, 316cdef10bbSPeter Maydell .proc_id = 0x0c000191, 31731410948SPeter Maydell .num_voltage_sensors = ARRAY_SIZE(a9_voltages), 31831410948SPeter Maydell .voltages = a9_voltages, 3199c7d4893SPeter Maydell .num_clocks = ARRAY_SIZE(a9_clocks), 3209c7d4893SPeter Maydell .clocks = a9_clocks, 3214c3b29b8SPeter Maydell .init = a9_daughterboard_init, 3224c3b29b8SPeter Maydell }; 3234c3b29b8SPeter Maydell 324961f195eSPeter Maydell static void a15_daughterboard_init(const VEDBoardInfo *daughterboard, 325961f195eSPeter Maydell ram_addr_t ram_size, 326961f195eSPeter Maydell const char *cpu_model, 327cdef10bbSPeter Maydell qemu_irq *pic) 328961f195eSPeter Maydell { 329961f195eSPeter Maydell MemoryRegion *sysmem = get_system_memory(); 330961f195eSPeter Maydell MemoryRegion *ram = g_new(MemoryRegion, 1); 331961f195eSPeter Maydell MemoryRegion *sram = g_new(MemoryRegion, 1); 332961f195eSPeter Maydell 333961f195eSPeter Maydell if (!cpu_model) { 334961f195eSPeter Maydell cpu_model = "cortex-a15"; 335961f195eSPeter Maydell } 336961f195eSPeter Maydell 33725d71699SPeter Maydell { 33825d71699SPeter Maydell /* We have to use a separate 64 bit variable here to avoid the gcc 33925d71699SPeter Maydell * "comparison is always false due to limited range of data type" 34025d71699SPeter Maydell * warning if we are on a host where ram_addr_t is 32 bits. 34125d71699SPeter Maydell */ 34225d71699SPeter Maydell uint64_t rsz = ram_size; 34325d71699SPeter Maydell if (rsz > (30ULL * 1024 * 1024 * 1024)) { 34425d71699SPeter Maydell fprintf(stderr, "vexpress-a15: cannot model more than 30GB RAM\n"); 345961f195eSPeter Maydell exit(1); 346961f195eSPeter Maydell } 34725d71699SPeter Maydell } 348961f195eSPeter Maydell 3492c9b15caSPaolo Bonzini memory_region_init_ram(ram, NULL, "vexpress.highmem", ram_size); 350961f195eSPeter Maydell vmstate_register_ram_global(ram); 351961f195eSPeter Maydell /* RAM is from 0x80000000 upwards; there is no low-memory alias for it. */ 352961f195eSPeter Maydell memory_region_add_subregion(sysmem, 0x80000000, ram); 353961f195eSPeter Maydell 354961f195eSPeter Maydell /* 0x2c000000 A15MPCore private memory region (GIC) */ 355*9948c38bSPeter Maydell init_cpus(cpu_model, "a15mpcore_priv", 0x2c000000, pic); 356961f195eSPeter Maydell 357961f195eSPeter Maydell /* A15 daughterboard peripherals: */ 358961f195eSPeter Maydell 359961f195eSPeter Maydell /* 0x20000000: CoreSight interfaces: not modelled */ 360961f195eSPeter Maydell /* 0x2a000000: PL301 AXI interconnect: not modelled */ 361961f195eSPeter Maydell /* 0x2a420000: SCC: not modelled */ 362961f195eSPeter Maydell /* 0x2a430000: system counter: not modelled */ 363961f195eSPeter Maydell /* 0x2b000000: HDLCD controller: not modelled */ 364961f195eSPeter Maydell /* 0x2b060000: SP805 watchdog: not modelled */ 365961f195eSPeter Maydell /* 0x2b0a0000: PL341 dynamic memory controller: not modelled */ 366961f195eSPeter Maydell /* 0x2e000000: system SRAM */ 3672c9b15caSPaolo Bonzini memory_region_init_ram(sram, NULL, "vexpress.a15sram", 0x10000); 368961f195eSPeter Maydell vmstate_register_ram_global(sram); 369961f195eSPeter Maydell memory_region_add_subregion(sysmem, 0x2e000000, sram); 370961f195eSPeter Maydell 371961f195eSPeter Maydell /* 0x7ffb0000: DMA330 DMA controller: not modelled */ 372961f195eSPeter Maydell /* 0x7ffd0000: PL354 static memory controller: not modelled */ 373961f195eSPeter Maydell } 374961f195eSPeter Maydell 37531410948SPeter Maydell static const uint32_t a15_voltages[] = { 37631410948SPeter Maydell 900000, /* Vcore: 0.9V : CPU core voltage */ 37731410948SPeter Maydell }; 37831410948SPeter Maydell 3799c7d4893SPeter Maydell static const uint32_t a15_clocks[] = { 3809c7d4893SPeter Maydell 60000000, /* OSCCLK0: 60MHz : CPU_CLK reference */ 3819c7d4893SPeter Maydell 0, /* OSCCLK1: reserved */ 3829c7d4893SPeter Maydell 0, /* OSCCLK2: reserved */ 3839c7d4893SPeter Maydell 0, /* OSCCLK3: reserved */ 3849c7d4893SPeter Maydell 40000000, /* OSCCLK4: 40MHz : external AXI master clock */ 3859c7d4893SPeter Maydell 23750000, /* OSCCLK5: 23.75MHz : HDLCD PLL reference */ 3869c7d4893SPeter Maydell 50000000, /* OSCCLK6: 50MHz : static memory controller clock */ 3879c7d4893SPeter Maydell 60000000, /* OSCCLK7: 60MHz : SYSCLK reference */ 3889c7d4893SPeter Maydell 40000000, /* OSCCLK8: 40MHz : DDR2 PLL reference */ 3899c7d4893SPeter Maydell }; 3909c7d4893SPeter Maydell 391cef04a26SPeter Maydell static VEDBoardInfo a15_daughterboard = { 392961f195eSPeter Maydell .motherboard_map = motherboard_aseries_map, 393961f195eSPeter Maydell .loader_start = 0x80000000, 394961f195eSPeter Maydell .gic_cpu_if_addr = 0x2c002000, 395cdef10bbSPeter Maydell .proc_id = 0x14000237, 39631410948SPeter Maydell .num_voltage_sensors = ARRAY_SIZE(a15_voltages), 39731410948SPeter Maydell .voltages = a15_voltages, 3989c7d4893SPeter Maydell .num_clocks = ARRAY_SIZE(a15_clocks), 3999c7d4893SPeter Maydell .clocks = a15_clocks, 400961f195eSPeter Maydell .init = a15_daughterboard_init, 401961f195eSPeter Maydell }; 402961f195eSPeter Maydell 403c8a07b35SPeter Maydell static int add_virtio_mmio_node(void *fdt, uint32_t acells, uint32_t scells, 404c8a07b35SPeter Maydell hwaddr addr, hwaddr size, uint32_t intc, 405c8a07b35SPeter Maydell int irq) 406c8a07b35SPeter Maydell { 407c8a07b35SPeter Maydell /* Add a virtio_mmio node to the device tree blob: 408c8a07b35SPeter Maydell * virtio_mmio@ADDRESS { 409c8a07b35SPeter Maydell * compatible = "virtio,mmio"; 410c8a07b35SPeter Maydell * reg = <ADDRESS, SIZE>; 411c8a07b35SPeter Maydell * interrupt-parent = <&intc>; 412c8a07b35SPeter Maydell * interrupts = <0, irq, 1>; 413c8a07b35SPeter Maydell * } 414c8a07b35SPeter Maydell * (Note that the format of the interrupts property is dependent on the 415c8a07b35SPeter Maydell * interrupt controller that interrupt-parent points to; these are for 416c8a07b35SPeter Maydell * the ARM GIC and indicate an SPI interrupt, rising-edge-triggered.) 417c8a07b35SPeter Maydell */ 418c8a07b35SPeter Maydell int rc; 419c8a07b35SPeter Maydell char *nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, addr); 420c8a07b35SPeter Maydell 4215a4348d1SPeter Crosthwaite rc = qemu_fdt_add_subnode(fdt, nodename); 4225a4348d1SPeter Crosthwaite rc |= qemu_fdt_setprop_string(fdt, nodename, 423c8a07b35SPeter Maydell "compatible", "virtio,mmio"); 4245a4348d1SPeter Crosthwaite rc |= qemu_fdt_setprop_sized_cells(fdt, nodename, "reg", 425c8a07b35SPeter Maydell acells, addr, scells, size); 4265a4348d1SPeter Crosthwaite qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", intc); 4275a4348d1SPeter Crosthwaite qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 0, irq, 1); 428c8a07b35SPeter Maydell g_free(nodename); 429c8a07b35SPeter Maydell if (rc) { 430c8a07b35SPeter Maydell return -1; 431c8a07b35SPeter Maydell } 432c8a07b35SPeter Maydell return 0; 433c8a07b35SPeter Maydell } 434c8a07b35SPeter Maydell 435c8a07b35SPeter Maydell static uint32_t find_int_controller(void *fdt) 436c8a07b35SPeter Maydell { 437c8a07b35SPeter Maydell /* Find the FDT node corresponding to the interrupt controller 438c8a07b35SPeter Maydell * for virtio-mmio devices. We do this by scanning the fdt for 439c8a07b35SPeter Maydell * a node with the right compatibility, since we know there is 440c8a07b35SPeter Maydell * only one GIC on a vexpress board. 441c8a07b35SPeter Maydell * We return the phandle of the node, or 0 if none was found. 442c8a07b35SPeter Maydell */ 443c8a07b35SPeter Maydell const char *compat = "arm,cortex-a9-gic"; 444c8a07b35SPeter Maydell int offset; 445c8a07b35SPeter Maydell 446c8a07b35SPeter Maydell offset = fdt_node_offset_by_compatible(fdt, -1, compat); 447c8a07b35SPeter Maydell if (offset >= 0) { 448c8a07b35SPeter Maydell return fdt_get_phandle(fdt, offset); 449c8a07b35SPeter Maydell } 450c8a07b35SPeter Maydell return 0; 451c8a07b35SPeter Maydell } 452c8a07b35SPeter Maydell 453c8a07b35SPeter Maydell static void vexpress_modify_dtb(const struct arm_boot_info *info, void *fdt) 454c8a07b35SPeter Maydell { 455c8a07b35SPeter Maydell uint32_t acells, scells, intc; 456c8a07b35SPeter Maydell const VEDBoardInfo *daughterboard = (const VEDBoardInfo *)info; 457c8a07b35SPeter Maydell 4585a4348d1SPeter Crosthwaite acells = qemu_fdt_getprop_cell(fdt, "/", "#address-cells"); 4595a4348d1SPeter Crosthwaite scells = qemu_fdt_getprop_cell(fdt, "/", "#size-cells"); 460c8a07b35SPeter Maydell intc = find_int_controller(fdt); 461c8a07b35SPeter Maydell if (!intc) { 462c8a07b35SPeter Maydell /* Not fatal, we just won't provide virtio. This will 463c8a07b35SPeter Maydell * happen with older device tree blobs. 464c8a07b35SPeter Maydell */ 465c8a07b35SPeter Maydell fprintf(stderr, "QEMU: warning: couldn't find interrupt controller in " 466c8a07b35SPeter Maydell "dtb; will not include virtio-mmio devices in the dtb.\n"); 467c8a07b35SPeter Maydell } else { 468c8a07b35SPeter Maydell int i; 469c8a07b35SPeter Maydell const hwaddr *map = daughterboard->motherboard_map; 470c8a07b35SPeter Maydell 471c8a07b35SPeter Maydell /* We iterate backwards here because adding nodes 472c8a07b35SPeter Maydell * to the dtb puts them in last-first. 473c8a07b35SPeter Maydell */ 474c8a07b35SPeter Maydell for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) { 475c8a07b35SPeter Maydell add_virtio_mmio_node(fdt, acells, scells, 476c8a07b35SPeter Maydell map[VE_VIRTIO] + 0x200 * i, 477c8a07b35SPeter Maydell 0x200, intc, 40 + i); 478c8a07b35SPeter Maydell } 479c8a07b35SPeter Maydell } 480c8a07b35SPeter Maydell } 481c8a07b35SPeter Maydell 482b8433303SRoy Franz 483b8433303SRoy Franz /* Open code a private version of pflash registration since we 484b8433303SRoy Franz * need to set non-default device width for VExpress platform. 485b8433303SRoy Franz */ 486b8433303SRoy Franz static pflash_t *ve_pflash_cfi01_register(hwaddr base, const char *name, 487b8433303SRoy Franz DriveInfo *di) 488b8433303SRoy Franz { 489b8433303SRoy Franz DeviceState *dev = qdev_create(NULL, "cfi.pflash01"); 490b8433303SRoy Franz 491b8433303SRoy Franz if (di && qdev_prop_set_drive(dev, "drive", di->bdrv)) { 492b8433303SRoy Franz abort(); 493b8433303SRoy Franz } 494b8433303SRoy Franz 495b8433303SRoy Franz qdev_prop_set_uint32(dev, "num-blocks", 496b8433303SRoy Franz VEXPRESS_FLASH_SIZE / VEXPRESS_FLASH_SECT_SIZE); 497b8433303SRoy Franz qdev_prop_set_uint64(dev, "sector-length", VEXPRESS_FLASH_SECT_SIZE); 498b8433303SRoy Franz qdev_prop_set_uint8(dev, "width", 4); 499b8433303SRoy Franz qdev_prop_set_uint8(dev, "device-width", 2); 500b8433303SRoy Franz qdev_prop_set_uint8(dev, "big-endian", 0); 5010163a2dcSRoy Franz qdev_prop_set_uint16(dev, "id0", 0x89); 5020163a2dcSRoy Franz qdev_prop_set_uint16(dev, "id1", 0x18); 503b8433303SRoy Franz qdev_prop_set_uint16(dev, "id2", 0x00); 5040163a2dcSRoy Franz qdev_prop_set_uint16(dev, "id3", 0x00); 505b8433303SRoy Franz qdev_prop_set_string(dev, "name", name); 506b8433303SRoy Franz qdev_init_nofail(dev); 507b8433303SRoy Franz 508b8433303SRoy Franz sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 509b8433303SRoy Franz return OBJECT_CHECK(pflash_t, (dev), "cfi.pflash01"); 510b8433303SRoy Franz } 511b8433303SRoy Franz 512cef04a26SPeter Maydell static void vexpress_common_init(VEDBoardInfo *daughterboard, 513f3cdbc32SPeter Maydell QEMUMachineInitArgs *args) 5144c3b29b8SPeter Maydell { 5154c3b29b8SPeter Maydell DeviceState *dev, *sysctl, *pl041; 5164c3b29b8SPeter Maydell qemu_irq pic[64]; 5174c3b29b8SPeter Maydell uint32_t sys_id; 5183dc3e7ddSFrancesco Lavra DriveInfo *dinfo; 5198941d6ceSPeter Maydell pflash_t *pflash0; 5204c3b29b8SPeter Maydell ram_addr_t vram_size, sram_size; 5214c3b29b8SPeter Maydell MemoryRegion *sysmem = get_system_memory(); 5224c3b29b8SPeter Maydell MemoryRegion *vram = g_new(MemoryRegion, 1); 5234c3b29b8SPeter Maydell MemoryRegion *sram = g_new(MemoryRegion, 1); 5248941d6ceSPeter Maydell MemoryRegion *flashalias = g_new(MemoryRegion, 1); 5258941d6ceSPeter Maydell MemoryRegion *flash0mem; 526a8170e5eSAvi Kivity const hwaddr *map = daughterboard->motherboard_map; 52731410948SPeter Maydell int i; 5284c3b29b8SPeter Maydell 529cdef10bbSPeter Maydell daughterboard->init(daughterboard, args->ram_size, args->cpu_model, pic); 5304c3b29b8SPeter Maydell 5312558e0a6SPeter Maydell /* Motherboard peripherals: the wiring is the same but the 5322558e0a6SPeter Maydell * addresses vary between the legacy and A-Series memory maps. 5332558e0a6SPeter Maydell */ 5342558e0a6SPeter Maydell 5352055283bSPeter Maydell sys_id = 0x1190f500; 5362055283bSPeter Maydell 5372055283bSPeter Maydell sysctl = qdev_create(NULL, "realview_sysctl"); 5382055283bSPeter Maydell qdev_prop_set_uint32(sysctl, "sys_id", sys_id); 539cdef10bbSPeter Maydell qdev_prop_set_uint32(sysctl, "proc_id", daughterboard->proc_id); 54031410948SPeter Maydell qdev_prop_set_uint32(sysctl, "len-db-voltage", 54131410948SPeter Maydell daughterboard->num_voltage_sensors); 54231410948SPeter Maydell for (i = 0; i < daughterboard->num_voltage_sensors; i++) { 54331410948SPeter Maydell char *propname = g_strdup_printf("db-voltage[%d]", i); 54431410948SPeter Maydell qdev_prop_set_uint32(sysctl, propname, daughterboard->voltages[i]); 54531410948SPeter Maydell g_free(propname); 54631410948SPeter Maydell } 5479c7d4893SPeter Maydell qdev_prop_set_uint32(sysctl, "len-db-clock", 5489c7d4893SPeter Maydell daughterboard->num_clocks); 5499c7d4893SPeter Maydell for (i = 0; i < daughterboard->num_clocks; i++) { 5509c7d4893SPeter Maydell char *propname = g_strdup_printf("db-clock[%d]", i); 5519c7d4893SPeter Maydell qdev_prop_set_uint32(sysctl, propname, daughterboard->clocks[i]); 5529c7d4893SPeter Maydell g_free(propname); 5539c7d4893SPeter Maydell } 5547a65c8ccSPeter Maydell qdev_init_nofail(sysctl); 5551356b98dSAndreas Färber sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, map[VE_SYSREGS]); 5562055283bSPeter Maydell 5572558e0a6SPeter Maydell /* VE_SP810: not modelled */ 5582558e0a6SPeter Maydell /* VE_SERIALPCI: not modelled */ 5592558e0a6SPeter Maydell 56003a0e944SPeter Maydell pl041 = qdev_create(NULL, "pl041"); 56103a0e944SPeter Maydell qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512); 56203a0e944SPeter Maydell qdev_init_nofail(pl041); 5631356b98dSAndreas Färber sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, map[VE_PL041]); 5641356b98dSAndreas Färber sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, pic[11]); 5652055283bSPeter Maydell 5662558e0a6SPeter Maydell dev = sysbus_create_varargs("pl181", map[VE_MMCI], pic[9], pic[10], NULL); 5672055283bSPeter Maydell /* Wire up MMC card detect and read-only signals */ 5682055283bSPeter Maydell qdev_connect_gpio_out(dev, 0, 5692055283bSPeter Maydell qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT)); 5702055283bSPeter Maydell qdev_connect_gpio_out(dev, 1, 5712055283bSPeter Maydell qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN)); 5722055283bSPeter Maydell 5732558e0a6SPeter Maydell sysbus_create_simple("pl050_keyboard", map[VE_KMI0], pic[12]); 5742558e0a6SPeter Maydell sysbus_create_simple("pl050_mouse", map[VE_KMI1], pic[13]); 5752055283bSPeter Maydell 5762558e0a6SPeter Maydell sysbus_create_simple("pl011", map[VE_UART0], pic[5]); 5772558e0a6SPeter Maydell sysbus_create_simple("pl011", map[VE_UART1], pic[6]); 5782558e0a6SPeter Maydell sysbus_create_simple("pl011", map[VE_UART2], pic[7]); 5792558e0a6SPeter Maydell sysbus_create_simple("pl011", map[VE_UART3], pic[8]); 5802055283bSPeter Maydell 5812558e0a6SPeter Maydell sysbus_create_simple("sp804", map[VE_TIMER01], pic[2]); 5822558e0a6SPeter Maydell sysbus_create_simple("sp804", map[VE_TIMER23], pic[3]); 5832055283bSPeter Maydell 5842558e0a6SPeter Maydell /* VE_SERIALDVI: not modelled */ 5852055283bSPeter Maydell 5862558e0a6SPeter Maydell sysbus_create_simple("pl031", map[VE_RTC], pic[4]); /* RTC */ 5872055283bSPeter Maydell 5882558e0a6SPeter Maydell /* VE_COMPACTFLASH: not modelled */ 5892055283bSPeter Maydell 590b7206878SPeter Maydell sysbus_create_simple("pl111", map[VE_CLCD], pic[14]); 5912055283bSPeter Maydell 5923dc3e7ddSFrancesco Lavra dinfo = drive_get_next(IF_PFLASH); 593b8433303SRoy Franz pflash0 = ve_pflash_cfi01_register(map[VE_NORFLASH0], "vexpress.flash0", 594b8433303SRoy Franz dinfo); 5958941d6ceSPeter Maydell if (!pflash0) { 5963dc3e7ddSFrancesco Lavra fprintf(stderr, "vexpress: error registering flash 0.\n"); 5973dc3e7ddSFrancesco Lavra exit(1); 5983dc3e7ddSFrancesco Lavra } 5993dc3e7ddSFrancesco Lavra 6008941d6ceSPeter Maydell if (map[VE_NORFLASHALIAS] != -1) { 6018941d6ceSPeter Maydell /* Map flash 0 as an alias into low memory */ 6028941d6ceSPeter Maydell flash0mem = sysbus_mmio_get_region(SYS_BUS_DEVICE(pflash0), 0); 6038941d6ceSPeter Maydell memory_region_init_alias(flashalias, NULL, "vexpress.flashalias", 6048941d6ceSPeter Maydell flash0mem, 0, VEXPRESS_FLASH_SIZE); 6058941d6ceSPeter Maydell memory_region_add_subregion(sysmem, map[VE_NORFLASHALIAS], flashalias); 6068941d6ceSPeter Maydell } 6078941d6ceSPeter Maydell 6083dc3e7ddSFrancesco Lavra dinfo = drive_get_next(IF_PFLASH); 609b8433303SRoy Franz if (!ve_pflash_cfi01_register(map[VE_NORFLASH1], "vexpress.flash1", 610b8433303SRoy Franz dinfo)) { 6113dc3e7ddSFrancesco Lavra fprintf(stderr, "vexpress: error registering flash 1.\n"); 6123dc3e7ddSFrancesco Lavra exit(1); 6133dc3e7ddSFrancesco Lavra } 6142558e0a6SPeter Maydell 6152055283bSPeter Maydell sram_size = 0x2000000; 6162c9b15caSPaolo Bonzini memory_region_init_ram(sram, NULL, "vexpress.sram", sram_size); 617c5705a77SAvi Kivity vmstate_register_ram_global(sram); 6182558e0a6SPeter Maydell memory_region_add_subregion(sysmem, map[VE_SRAM], sram); 6192055283bSPeter Maydell 6202055283bSPeter Maydell vram_size = 0x800000; 6212c9b15caSPaolo Bonzini memory_region_init_ram(vram, NULL, "vexpress.vram", vram_size); 622c5705a77SAvi Kivity vmstate_register_ram_global(vram); 6232558e0a6SPeter Maydell memory_region_add_subregion(sysmem, map[VE_VIDEORAM], vram); 6242055283bSPeter Maydell 6252055283bSPeter Maydell /* 0x4e000000 LAN9118 Ethernet */ 626a005d073SStefan Hajnoczi if (nd_table[0].used) { 6272558e0a6SPeter Maydell lan9118_init(&nd_table[0], map[VE_ETHERNET], pic[15]); 6282055283bSPeter Maydell } 6292055283bSPeter Maydell 6302558e0a6SPeter Maydell /* VE_USB: not modelled */ 6312558e0a6SPeter Maydell 6322558e0a6SPeter Maydell /* VE_DAPROM: not modelled */ 6332055283bSPeter Maydell 634c8a07b35SPeter Maydell /* Create mmio transports, so the user can create virtio backends 635c8a07b35SPeter Maydell * (which will be automatically plugged in to the transports). If 636c8a07b35SPeter Maydell * no backend is created the transport will just sit harmlessly idle. 637c8a07b35SPeter Maydell */ 638c8a07b35SPeter Maydell for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) { 639c8a07b35SPeter Maydell sysbus_create_simple("virtio-mmio", map[VE_VIRTIO] + 0x200 * i, 640c8a07b35SPeter Maydell pic[40 + i]); 641c8a07b35SPeter Maydell } 642c8a07b35SPeter Maydell 643cef04a26SPeter Maydell daughterboard->bootinfo.ram_size = args->ram_size; 644cef04a26SPeter Maydell daughterboard->bootinfo.kernel_filename = args->kernel_filename; 645cef04a26SPeter Maydell daughterboard->bootinfo.kernel_cmdline = args->kernel_cmdline; 646cef04a26SPeter Maydell daughterboard->bootinfo.initrd_filename = args->initrd_filename; 647cef04a26SPeter Maydell daughterboard->bootinfo.nb_cpus = smp_cpus; 648cef04a26SPeter Maydell daughterboard->bootinfo.board_id = VEXPRESS_BOARD_ID; 649cef04a26SPeter Maydell daughterboard->bootinfo.loader_start = daughterboard->loader_start; 650cef04a26SPeter Maydell daughterboard->bootinfo.smp_loader_start = map[VE_SRAM]; 651cef04a26SPeter Maydell daughterboard->bootinfo.smp_bootreg_addr = map[VE_SYSREGS] + 0x30; 652cef04a26SPeter Maydell daughterboard->bootinfo.gic_cpu_if_addr = daughterboard->gic_cpu_if_addr; 653c8a07b35SPeter Maydell daughterboard->bootinfo.modify_dtb = vexpress_modify_dtb; 654cef04a26SPeter Maydell arm_load_kernel(ARM_CPU(first_cpu), &daughterboard->bootinfo); 6552055283bSPeter Maydell } 6562055283bSPeter Maydell 6575f072e1fSEduardo Habkost static void vexpress_a9_init(QEMUMachineInitArgs *args) 6584c3b29b8SPeter Maydell { 659f3cdbc32SPeter Maydell vexpress_common_init(&a9_daughterboard, args); 6604c3b29b8SPeter Maydell } 6612055283bSPeter Maydell 6625f072e1fSEduardo Habkost static void vexpress_a15_init(QEMUMachineInitArgs *args) 663961f195eSPeter Maydell { 664f3cdbc32SPeter Maydell vexpress_common_init(&a15_daughterboard, args); 665961f195eSPeter Maydell } 666961f195eSPeter Maydell 6672055283bSPeter Maydell static QEMUMachine vexpress_a9_machine = { 6682055283bSPeter Maydell .name = "vexpress-a9", 6692055283bSPeter Maydell .desc = "ARM Versatile Express for Cortex-A9", 6702055283bSPeter Maydell .init = vexpress_a9_init, 6712d0d2837SChristian Borntraeger .block_default_type = IF_SCSI, 6722055283bSPeter Maydell .max_cpus = 4, 6732055283bSPeter Maydell }; 6742055283bSPeter Maydell 675961f195eSPeter Maydell static QEMUMachine vexpress_a15_machine = { 676961f195eSPeter Maydell .name = "vexpress-a15", 677961f195eSPeter Maydell .desc = "ARM Versatile Express for Cortex-A15", 678961f195eSPeter Maydell .init = vexpress_a15_init, 6792d0d2837SChristian Borntraeger .block_default_type = IF_SCSI, 680961f195eSPeter Maydell .max_cpus = 4, 681961f195eSPeter Maydell }; 682961f195eSPeter Maydell 6832055283bSPeter Maydell static void vexpress_machine_init(void) 6842055283bSPeter Maydell { 6852055283bSPeter Maydell qemu_register_machine(&vexpress_a9_machine); 686961f195eSPeter Maydell qemu_register_machine(&vexpress_a15_machine); 6872055283bSPeter Maydell } 6882055283bSPeter Maydell 6892055283bSPeter Maydell machine_init(vexpress_machine_init); 690