1 /* 2 * ARM Versatile Platform/Application Baseboard System emulation. 3 * 4 * Copyright (c) 2005-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qapi/error.h" 12 #include "hw/sysbus.h" 13 #include "migration/vmstate.h" 14 #include "hw/arm/boot.h" 15 #include "hw/net/smc91c111.h" 16 #include "net/net.h" 17 #include "system/system.h" 18 #include "hw/pci/pci.h" 19 #include "hw/i2c/i2c.h" 20 #include "hw/i2c/arm_sbcon_i2c.h" 21 #include "hw/irq.h" 22 #include "hw/boards.h" 23 #include "hw/block/flash.h" 24 #include "qemu/error-report.h" 25 #include "hw/char/pl011.h" 26 #include "hw/sd/sd.h" 27 #include "qom/object.h" 28 #include "audio/audio.h" 29 #include "target/arm/cpu-qom.h" 30 #include "qemu/log.h" 31 32 #define VERSATILE_FLASH_ADDR 0x34000000 33 #define VERSATILE_FLASH_SIZE (64 * 1024 * 1024) 34 #define VERSATILE_FLASH_SECT_SIZE (256 * 1024) 35 36 /* Primary interrupt controller. */ 37 38 #define TYPE_VERSATILE_PB_SIC "versatilepb_sic" 39 OBJECT_DECLARE_SIMPLE_TYPE(vpb_sic_state, VERSATILE_PB_SIC) 40 41 struct vpb_sic_state { 42 SysBusDevice parent_obj; 43 44 MemoryRegion iomem; 45 uint32_t level; 46 uint32_t mask; 47 uint32_t pic_enable; 48 qemu_irq parent[32]; 49 int irq; 50 }; 51 52 static const VMStateDescription vmstate_vpb_sic = { 53 .name = "versatilepb_sic", 54 .version_id = 1, 55 .minimum_version_id = 1, 56 .fields = (const VMStateField[]) { 57 VMSTATE_UINT32(level, vpb_sic_state), 58 VMSTATE_UINT32(mask, vpb_sic_state), 59 VMSTATE_UINT32(pic_enable, vpb_sic_state), 60 VMSTATE_END_OF_LIST() 61 } 62 }; 63 64 static void vpb_sic_update(vpb_sic_state *s) 65 { 66 uint32_t flags; 67 68 flags = s->level & s->mask; 69 qemu_set_irq(s->parent[s->irq], flags != 0); 70 } 71 72 static void vpb_sic_update_pic(vpb_sic_state *s) 73 { 74 int i; 75 uint32_t mask; 76 77 for (i = 21; i <= 30; i++) { 78 mask = 1u << i; 79 if (!(s->pic_enable & mask)) 80 continue; 81 qemu_set_irq(s->parent[i], (s->level & mask) != 0); 82 } 83 } 84 85 static void vpb_sic_set_irq(void *opaque, int irq, int level) 86 { 87 vpb_sic_state *s = (vpb_sic_state *)opaque; 88 if (level) 89 s->level |= 1u << irq; 90 else 91 s->level &= ~(1u << irq); 92 if (s->pic_enable & (1u << irq)) 93 qemu_set_irq(s->parent[irq], level); 94 vpb_sic_update(s); 95 } 96 97 static uint64_t vpb_sic_read(void *opaque, hwaddr offset, 98 unsigned size) 99 { 100 vpb_sic_state *s = (vpb_sic_state *)opaque; 101 102 switch (offset >> 2) { 103 case 0: /* STATUS */ 104 return s->level & s->mask; 105 case 1: /* RAWSTAT */ 106 return s->level; 107 case 2: /* ENABLE */ 108 return s->mask; 109 case 4: /* SOFTINT */ 110 return s->level & 1; 111 case 8: /* PICENABLE */ 112 return s->pic_enable; 113 default: 114 qemu_log_mask(LOG_GUEST_ERROR, 115 "vpb_sic_read: Bad register offset 0x%x\n", (int)offset); 116 return 0; 117 } 118 } 119 120 static void vpb_sic_write(void *opaque, hwaddr offset, 121 uint64_t value, unsigned size) 122 { 123 vpb_sic_state *s = (vpb_sic_state *)opaque; 124 125 switch (offset >> 2) { 126 case 2: /* ENSET */ 127 s->mask |= value; 128 break; 129 case 3: /* ENCLR */ 130 s->mask &= ~value; 131 break; 132 case 4: /* SOFTINTSET */ 133 if (value) 134 s->mask |= 1; 135 break; 136 case 5: /* SOFTINTCLR */ 137 if (value) 138 s->mask &= ~1u; 139 break; 140 case 8: /* PICENSET */ 141 s->pic_enable |= (value & 0x7fe00000); 142 vpb_sic_update_pic(s); 143 break; 144 case 9: /* PICENCLR */ 145 s->pic_enable &= ~value; 146 vpb_sic_update_pic(s); 147 break; 148 default: 149 qemu_log_mask(LOG_GUEST_ERROR, 150 "vpb_sic_write: Bad register offset 0x%x\n", (int)offset); 151 return; 152 } 153 vpb_sic_update(s); 154 } 155 156 static const MemoryRegionOps vpb_sic_ops = { 157 .read = vpb_sic_read, 158 .write = vpb_sic_write, 159 .endianness = DEVICE_NATIVE_ENDIAN, 160 }; 161 162 static void vpb_sic_init(Object *obj) 163 { 164 DeviceState *dev = DEVICE(obj); 165 vpb_sic_state *s = VERSATILE_PB_SIC(obj); 166 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 167 int i; 168 169 qdev_init_gpio_in(dev, vpb_sic_set_irq, 32); 170 for (i = 0; i < 32; i++) { 171 sysbus_init_irq(sbd, &s->parent[i]); 172 } 173 s->irq = 31; 174 memory_region_init_io(&s->iomem, obj, &vpb_sic_ops, s, 175 "vpb-sic", 0x1000); 176 sysbus_init_mmio(sbd, &s->iomem); 177 } 178 179 /* Board init. */ 180 181 /* The AB and PB boards both use the same core, just with different 182 peripherals and expansion busses. For now we emulate a subset of the 183 PB peripherals and just change the board ID. */ 184 185 static struct arm_boot_info versatile_binfo; 186 187 static void versatile_init(MachineState *machine, int board_id) 188 { 189 Object *cpuobj; 190 ARMCPU *cpu; 191 MemoryRegion *sysmem = get_system_memory(); 192 qemu_irq pic[32]; 193 qemu_irq sic[32]; 194 DeviceState *dev, *sysctl; 195 SysBusDevice *busdev; 196 DeviceState *pl041; 197 PCIBus *pci_bus; 198 I2CBus *i2c; 199 int n; 200 DriveInfo *dinfo; 201 202 if (machine->ram_size > 0x10000000) { 203 /* Device starting at address 0x10000000, 204 * and memory cannot overlap with devices. 205 * Refuse to run rather than behaving very confusingly. 206 */ 207 error_report("versatilepb: memory size must not exceed 256MB"); 208 exit(1); 209 } 210 211 cpuobj = object_new(machine->cpu_type); 212 213 /* By default ARM1176 CPUs have EL3 enabled. This board does not 214 * currently support EL3 so the CPU EL3 property is disabled before 215 * realization. 216 */ 217 if (object_property_find(cpuobj, "has_el3")) { 218 object_property_set_bool(cpuobj, "has_el3", false, &error_fatal); 219 } 220 221 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); 222 223 cpu = ARM_CPU(cpuobj); 224 225 /* ??? RAM should repeat to fill physical memory space. */ 226 /* SDRAM at address zero. */ 227 memory_region_add_subregion(sysmem, 0, machine->ram); 228 229 sysctl = qdev_new("realview_sysctl"); 230 qdev_prop_set_uint32(sysctl, "sys_id", 0x41007004); 231 qdev_prop_set_uint32(sysctl, "proc_id", 0x02000000); 232 sysbus_realize_and_unref(SYS_BUS_DEVICE(sysctl), &error_fatal); 233 sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, 0x10000000); 234 235 dev = sysbus_create_varargs("pl190", 0x10140000, 236 qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ), 237 qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ), 238 NULL); 239 for (n = 0; n < 32; n++) { 240 pic[n] = qdev_get_gpio_in(dev, n); 241 } 242 dev = sysbus_create_simple(TYPE_VERSATILE_PB_SIC, 0x10003000, NULL); 243 for (n = 0; n < 32; n++) { 244 sysbus_connect_irq(SYS_BUS_DEVICE(dev), n, pic[n]); 245 sic[n] = qdev_get_gpio_in(dev, n); 246 } 247 248 sysbus_create_simple("pl050_keyboard", 0x10006000, sic[3]); 249 sysbus_create_simple("pl050_mouse", 0x10007000, sic[4]); 250 251 dev = qdev_new("versatile_pci"); 252 busdev = SYS_BUS_DEVICE(dev); 253 sysbus_realize_and_unref(busdev, &error_fatal); 254 sysbus_mmio_map(busdev, 0, 0x10001000); /* PCI controller regs */ 255 sysbus_mmio_map(busdev, 1, 0x41000000); /* PCI self-config */ 256 sysbus_mmio_map(busdev, 2, 0x42000000); /* PCI config */ 257 sysbus_mmio_map(busdev, 3, 0x43000000); /* PCI I/O */ 258 sysbus_mmio_map(busdev, 4, 0x44000000); /* PCI memory window 1 */ 259 sysbus_mmio_map(busdev, 5, 0x50000000); /* PCI memory window 2 */ 260 sysbus_mmio_map(busdev, 6, 0x60000000); /* PCI memory window 3 */ 261 sysbus_connect_irq(busdev, 0, sic[27]); 262 sysbus_connect_irq(busdev, 1, sic[28]); 263 sysbus_connect_irq(busdev, 2, sic[29]); 264 sysbus_connect_irq(busdev, 3, sic[30]); 265 pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci"); 266 267 if (qemu_find_nic_info("smc91c111", true, NULL)) { 268 smc91c111_init(0x10010000, sic[25]); 269 } 270 pci_init_nic_devices(pci_bus, "rtl8139"); 271 272 if (machine_usb(machine)) { 273 pci_create_simple(pci_bus, -1, "pci-ohci"); 274 } 275 n = drive_get_max_bus(IF_SCSI); 276 while (n >= 0) { 277 dev = DEVICE(pci_create_simple(pci_bus, -1, "lsi53c895a")); 278 lsi53c8xx_handle_legacy_cmdline(dev); 279 n--; 280 } 281 282 pl011_create(0x101f1000, pic[12], serial_hd(0)); 283 pl011_create(0x101f2000, pic[13], serial_hd(1)); 284 pl011_create(0x101f3000, pic[14], serial_hd(2)); 285 pl011_create(0x10009000, sic[6], serial_hd(3)); 286 287 dev = qdev_new("pl080"); 288 object_property_set_link(OBJECT(dev), "downstream", OBJECT(sysmem), 289 &error_fatal); 290 busdev = SYS_BUS_DEVICE(dev); 291 sysbus_realize_and_unref(busdev, &error_fatal); 292 sysbus_mmio_map(busdev, 0, 0x10130000); 293 sysbus_connect_irq(busdev, 0, pic[17]); 294 295 sysbus_create_simple("sp804", 0x101e2000, pic[4]); 296 sysbus_create_simple("sp804", 0x101e3000, pic[5]); 297 298 sysbus_create_simple("pl061", 0x101e4000, pic[6]); 299 sysbus_create_simple("pl061", 0x101e5000, pic[7]); 300 sysbus_create_simple("pl061", 0x101e6000, pic[8]); 301 sysbus_create_simple("pl061", 0x101e7000, pic[9]); 302 303 /* The versatile/PB actually has a modified Color LCD controller 304 that includes hardware cursor support from the PL111. */ 305 dev = qdev_new("pl110_versatile"); 306 object_property_set_link(OBJECT(dev), "framebuffer-memory", 307 OBJECT(sysmem), &error_fatal); 308 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 309 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0x10120000); 310 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[16]); 311 312 /* Wire up the mux control signals from the SYS_CLCD register */ 313 qdev_connect_gpio_out(sysctl, 0, qdev_get_gpio_in(dev, 0)); 314 315 dev = sysbus_create_varargs("pl181", 0x10005000, sic[22], sic[1], NULL); 316 dinfo = drive_get(IF_SD, 0, 0); 317 if (dinfo) { 318 DeviceState *card; 319 320 card = qdev_new(TYPE_SD_CARD); 321 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo), 322 &error_fatal); 323 qdev_realize_and_unref(card, qdev_get_child_bus(dev, "sd-bus"), 324 &error_fatal); 325 } 326 327 dev = sysbus_create_varargs("pl181", 0x1000b000, sic[23], sic[2], NULL); 328 dinfo = drive_get(IF_SD, 0, 1); 329 if (dinfo) { 330 DeviceState *card; 331 332 card = qdev_new(TYPE_SD_CARD); 333 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo), 334 &error_fatal); 335 qdev_realize_and_unref(card, qdev_get_child_bus(dev, "sd-bus"), 336 &error_fatal); 337 } 338 339 /* Add PL031 Real Time Clock. */ 340 sysbus_create_simple("pl031", 0x101e8000, pic[10]); 341 342 dev = sysbus_create_simple(TYPE_ARM_SBCON_I2C, 0x10002000, NULL); 343 i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c"); 344 i2c_slave_create_simple(i2c, "ds1338", 0x68); 345 346 /* Add PL041 AACI Interface to the LM4549 codec */ 347 pl041 = qdev_new("pl041"); 348 qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512); 349 if (machine->audiodev) { 350 qdev_prop_set_string(pl041, "audiodev", machine->audiodev); 351 } 352 sysbus_realize_and_unref(SYS_BUS_DEVICE(pl041), &error_fatal); 353 sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, 0x10004000); 354 sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, sic[24]); 355 356 /* Memory map for Versatile/PB: */ 357 /* 0x10000000 System registers. */ 358 /* 0x10001000 PCI controller config registers. */ 359 /* 0x10002000 Serial bus interface. */ 360 /* 0x10003000 Secondary interrupt controller. */ 361 /* 0x10004000 AACI (audio). */ 362 /* 0x10005000 MMCI0. */ 363 /* 0x10006000 KMI0 (keyboard). */ 364 /* 0x10007000 KMI1 (mouse). */ 365 /* 0x10008000 Character LCD Interface. */ 366 /* 0x10009000 UART3. */ 367 /* 0x1000a000 Smart card 1. */ 368 /* 0x1000b000 MMCI1. */ 369 /* 0x10010000 Ethernet. */ 370 /* 0x10020000 USB. */ 371 /* 0x10100000 SSMC. */ 372 /* 0x10110000 MPMC. */ 373 /* 0x10120000 CLCD Controller. */ 374 /* 0x10130000 DMA Controller. */ 375 /* 0x10140000 Vectored interrupt controller. */ 376 /* 0x101d0000 AHB Monitor Interface. */ 377 /* 0x101e0000 System Controller. */ 378 /* 0x101e1000 Watchdog Interface. */ 379 /* 0x101e2000 Timer 0/1. */ 380 /* 0x101e3000 Timer 2/3. */ 381 /* 0x101e4000 GPIO port 0. */ 382 /* 0x101e5000 GPIO port 1. */ 383 /* 0x101e6000 GPIO port 2. */ 384 /* 0x101e7000 GPIO port 3. */ 385 /* 0x101e8000 RTC. */ 386 /* 0x101f0000 Smart card 0. */ 387 /* 0x101f1000 UART0. */ 388 /* 0x101f2000 UART1. */ 389 /* 0x101f3000 UART2. */ 390 /* 0x101f4000 SSPI. */ 391 /* 0x34000000 NOR Flash */ 392 393 dinfo = drive_get(IF_PFLASH, 0, 0); 394 pflash_cfi01_register(VERSATILE_FLASH_ADDR, "versatile.flash", 395 VERSATILE_FLASH_SIZE, 396 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, 397 VERSATILE_FLASH_SECT_SIZE, 398 4, 0x0089, 0x0018, 0x0000, 0x0, 0); 399 400 versatile_binfo.ram_size = machine->ram_size; 401 versatile_binfo.board_id = board_id; 402 arm_load_kernel(cpu, machine, &versatile_binfo); 403 } 404 405 static void vpb_init(MachineState *machine) 406 { 407 versatile_init(machine, 0x183); 408 } 409 410 static void vab_init(MachineState *machine) 411 { 412 versatile_init(machine, 0x25e); 413 } 414 415 static void versatilepb_class_init(ObjectClass *oc, void *data) 416 { 417 MachineClass *mc = MACHINE_CLASS(oc); 418 419 mc->desc = "ARM Versatile/PB (ARM926EJ-S)"; 420 mc->init = vpb_init; 421 mc->block_default_type = IF_SCSI; 422 mc->ignore_memory_transaction_failures = true; 423 mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926"); 424 mc->default_ram_id = "versatile.ram"; 425 mc->auto_create_sdcard = true; 426 427 machine_add_audiodev_property(mc); 428 } 429 430 static const TypeInfo versatilepb_type = { 431 .name = MACHINE_TYPE_NAME("versatilepb"), 432 .parent = TYPE_MACHINE, 433 .class_init = versatilepb_class_init, 434 }; 435 436 static void versatileab_class_init(ObjectClass *oc, void *data) 437 { 438 MachineClass *mc = MACHINE_CLASS(oc); 439 440 mc->desc = "ARM Versatile/AB (ARM926EJ-S)"; 441 mc->init = vab_init; 442 mc->block_default_type = IF_SCSI; 443 mc->ignore_memory_transaction_failures = true; 444 mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926"); 445 mc->default_ram_id = "versatile.ram"; 446 mc->auto_create_sdcard = true; 447 448 machine_add_audiodev_property(mc); 449 } 450 451 static const TypeInfo versatileab_type = { 452 .name = MACHINE_TYPE_NAME("versatileab"), 453 .parent = TYPE_MACHINE, 454 .class_init = versatileab_class_init, 455 }; 456 457 static void versatile_machine_init(void) 458 { 459 type_register_static(&versatilepb_type); 460 type_register_static(&versatileab_type); 461 } 462 463 type_init(versatile_machine_init) 464 465 static void vpb_sic_class_init(ObjectClass *klass, void *data) 466 { 467 DeviceClass *dc = DEVICE_CLASS(klass); 468 469 dc->vmsd = &vmstate_vpb_sic; 470 } 471 472 static const TypeInfo vpb_sic_info = { 473 .name = TYPE_VERSATILE_PB_SIC, 474 .parent = TYPE_SYS_BUS_DEVICE, 475 .instance_size = sizeof(vpb_sic_state), 476 .instance_init = vpb_sic_init, 477 .class_init = vpb_sic_class_init, 478 }; 479 480 static void versatilepb_register_types(void) 481 { 482 type_register_static(&vpb_sic_info); 483 } 484 485 type_init(versatilepb_register_types) 486