1529fc5fdSAlistair Francis /* 2529fc5fdSAlistair Francis * STM32F405 SoC 3529fc5fdSAlistair Francis * 4529fc5fdSAlistair Francis * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me> 5529fc5fdSAlistair Francis * 6529fc5fdSAlistair Francis * Permission is hereby granted, free of charge, to any person obtaining a copy 7529fc5fdSAlistair Francis * of this software and associated documentation files (the "Software"), to deal 8529fc5fdSAlistair Francis * in the Software without restriction, including without limitation the rights 9529fc5fdSAlistair Francis * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10529fc5fdSAlistair Francis * copies of the Software, and to permit persons to whom the Software is 11529fc5fdSAlistair Francis * furnished to do so, subject to the following conditions: 12529fc5fdSAlistair Francis * 13529fc5fdSAlistair Francis * The above copyright notice and this permission notice shall be included in 14529fc5fdSAlistair Francis * all copies or substantial portions of the Software. 15529fc5fdSAlistair Francis * 16529fc5fdSAlistair Francis * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17529fc5fdSAlistair Francis * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18529fc5fdSAlistair Francis * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19529fc5fdSAlistair Francis * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20529fc5fdSAlistair Francis * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21529fc5fdSAlistair Francis * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22529fc5fdSAlistair Francis * THE SOFTWARE. 23529fc5fdSAlistair Francis */ 24529fc5fdSAlistair Francis 25529fc5fdSAlistair Francis #include "qemu/osdep.h" 26529fc5fdSAlistair Francis #include "qapi/error.h" 27529fc5fdSAlistair Francis #include "qemu-common.h" 28529fc5fdSAlistair Francis #include "exec/address-spaces.h" 29529fc5fdSAlistair Francis #include "sysemu/sysemu.h" 30529fc5fdSAlistair Francis #include "hw/arm/stm32f405_soc.h" 31*66e6a438SPeter Maydell #include "hw/qdev-clock.h" 32529fc5fdSAlistair Francis #include "hw/misc/unimp.h" 33529fc5fdSAlistair Francis 34529fc5fdSAlistair Francis #define SYSCFG_ADD 0x40013800 35529fc5fdSAlistair Francis static const uint32_t usart_addr[] = { 0x40011000, 0x40004400, 0x40004800, 36529fc5fdSAlistair Francis 0x40004C00, 0x40005000, 0x40011400, 37529fc5fdSAlistair Francis 0x40007800, 0x40007C00 }; 38529fc5fdSAlistair Francis /* At the moment only Timer 2 to 5 are modelled */ 39529fc5fdSAlistair Francis static const uint32_t timer_addr[] = { 0x40000000, 0x40000400, 40529fc5fdSAlistair Francis 0x40000800, 0x40000C00 }; 412fb1f7d2SMarkus Armbruster static const uint32_t adc_addr[] = { 0x40012000, 0x40012100, 0x40012200, 422fb1f7d2SMarkus Armbruster 0x40012300, 0x40012400, 0x40012500 }; 43529fc5fdSAlistair Francis static const uint32_t spi_addr[] = { 0x40013000, 0x40003800, 0x40003C00, 44529fc5fdSAlistair Francis 0x40013400, 0x40015000, 0x40015400 }; 45529fc5fdSAlistair Francis #define EXTI_ADDR 0x40013C00 46529fc5fdSAlistair Francis 47529fc5fdSAlistair Francis #define SYSCFG_IRQ 71 48529fc5fdSAlistair Francis static const int usart_irq[] = { 37, 38, 39, 52, 53, 71, 82, 83 }; 49529fc5fdSAlistair Francis static const int timer_irq[] = { 28, 29, 30, 50 }; 50529fc5fdSAlistair Francis #define ADC_IRQ 18 51529fc5fdSAlistair Francis static const int spi_irq[] = { 35, 36, 51, 0, 0, 0 }; 52529fc5fdSAlistair Francis static const int exti_irq[] = { 6, 7, 8, 9, 10, 23, 23, 23, 23, 23, 40, 53529fc5fdSAlistair Francis 40, 40, 40, 40, 40} ; 54529fc5fdSAlistair Francis 55529fc5fdSAlistair Francis 56529fc5fdSAlistair Francis static void stm32f405_soc_initfn(Object *obj) 57529fc5fdSAlistair Francis { 58529fc5fdSAlistair Francis STM32F405State *s = STM32F405_SOC(obj); 59529fc5fdSAlistair Francis int i; 60529fc5fdSAlistair Francis 61db873cc5SMarkus Armbruster object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M); 62529fc5fdSAlistair Francis 63db873cc5SMarkus Armbruster object_initialize_child(obj, "syscfg", &s->syscfg, TYPE_STM32F4XX_SYSCFG); 64529fc5fdSAlistair Francis 65529fc5fdSAlistair Francis for (i = 0; i < STM_NUM_USARTS; i++) { 66db873cc5SMarkus Armbruster object_initialize_child(obj, "usart[*]", &s->usart[i], 67db873cc5SMarkus Armbruster TYPE_STM32F2XX_USART); 68529fc5fdSAlistair Francis } 69529fc5fdSAlistair Francis 70529fc5fdSAlistair Francis for (i = 0; i < STM_NUM_TIMERS; i++) { 71db873cc5SMarkus Armbruster object_initialize_child(obj, "timer[*]", &s->timer[i], 72db873cc5SMarkus Armbruster TYPE_STM32F2XX_TIMER); 73529fc5fdSAlistair Francis } 74529fc5fdSAlistair Francis 75529fc5fdSAlistair Francis for (i = 0; i < STM_NUM_ADCS; i++) { 76db873cc5SMarkus Armbruster object_initialize_child(obj, "adc[*]", &s->adc[i], TYPE_STM32F2XX_ADC); 77529fc5fdSAlistair Francis } 78529fc5fdSAlistair Francis 79529fc5fdSAlistair Francis for (i = 0; i < STM_NUM_SPIS; i++) { 80db873cc5SMarkus Armbruster object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_STM32F2XX_SPI); 81529fc5fdSAlistair Francis } 82529fc5fdSAlistair Francis 83db873cc5SMarkus Armbruster object_initialize_child(obj, "exti", &s->exti, TYPE_STM32F4XX_EXTI); 84*66e6a438SPeter Maydell 85*66e6a438SPeter Maydell s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0); 86*66e6a438SPeter Maydell s->refclk = qdev_init_clock_in(DEVICE(s), "refclk", NULL, NULL, 0); 87529fc5fdSAlistair Francis } 88529fc5fdSAlistair Francis 89529fc5fdSAlistair Francis static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp) 90529fc5fdSAlistair Francis { 91529fc5fdSAlistair Francis STM32F405State *s = STM32F405_SOC(dev_soc); 92529fc5fdSAlistair Francis MemoryRegion *system_memory = get_system_memory(); 93529fc5fdSAlistair Francis DeviceState *dev, *armv7m; 94529fc5fdSAlistair Francis SysBusDevice *busdev; 95529fc5fdSAlistair Francis Error *err = NULL; 96529fc5fdSAlistair Francis int i; 97529fc5fdSAlistair Francis 98*66e6a438SPeter Maydell /* 99*66e6a438SPeter Maydell * We use s->refclk internally and only define it with qdev_init_clock_in() 100*66e6a438SPeter Maydell * so it is correctly parented and not leaked on an init/deinit; it is not 101*66e6a438SPeter Maydell * intended as an externally exposed clock. 102*66e6a438SPeter Maydell */ 103*66e6a438SPeter Maydell if (clock_has_source(s->refclk)) { 104*66e6a438SPeter Maydell error_setg(errp, "refclk clock must not be wired up by the board code"); 105*66e6a438SPeter Maydell return; 106*66e6a438SPeter Maydell } 107*66e6a438SPeter Maydell 108*66e6a438SPeter Maydell if (!clock_has_source(s->sysclk)) { 109*66e6a438SPeter Maydell error_setg(errp, "sysclk clock must be wired up by the board code"); 110*66e6a438SPeter Maydell return; 111*66e6a438SPeter Maydell } 112*66e6a438SPeter Maydell 113*66e6a438SPeter Maydell /* 114*66e6a438SPeter Maydell * TODO: ideally we should model the SoC RCC and its ability to 115*66e6a438SPeter Maydell * change the sysclk frequency and define different sysclk sources. 116*66e6a438SPeter Maydell */ 117*66e6a438SPeter Maydell 118*66e6a438SPeter Maydell /* The refclk always runs at frequency HCLK / 8 */ 119*66e6a438SPeter Maydell clock_set_mul_div(s->refclk, 8, 1); 120*66e6a438SPeter Maydell clock_set_source(s->refclk, s->sysclk); 121*66e6a438SPeter Maydell 12232b9523aSPhilippe Mathieu-Daudé memory_region_init_rom(&s->flash, OBJECT(dev_soc), "STM32F405.flash", 12332b9523aSPhilippe Mathieu-Daudé FLASH_SIZE, &err); 124529fc5fdSAlistair Francis if (err != NULL) { 125529fc5fdSAlistair Francis error_propagate(errp, err); 126529fc5fdSAlistair Francis return; 127529fc5fdSAlistair Francis } 12832b9523aSPhilippe Mathieu-Daudé memory_region_init_alias(&s->flash_alias, OBJECT(dev_soc), 12932b9523aSPhilippe Mathieu-Daudé "STM32F405.flash.alias", &s->flash, 0, 13032b9523aSPhilippe Mathieu-Daudé FLASH_SIZE); 131529fc5fdSAlistair Francis 132529fc5fdSAlistair Francis memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, &s->flash); 133529fc5fdSAlistair Francis memory_region_add_subregion(system_memory, 0, &s->flash_alias); 134529fc5fdSAlistair Francis 135529fc5fdSAlistair Francis memory_region_init_ram(&s->sram, NULL, "STM32F405.sram", SRAM_SIZE, 136529fc5fdSAlistair Francis &err); 137529fc5fdSAlistair Francis if (err != NULL) { 138529fc5fdSAlistair Francis error_propagate(errp, err); 139529fc5fdSAlistair Francis return; 140529fc5fdSAlistair Francis } 141529fc5fdSAlistair Francis memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, &s->sram); 142529fc5fdSAlistair Francis 143529fc5fdSAlistair Francis armv7m = DEVICE(&s->armv7m); 144529fc5fdSAlistair Francis qdev_prop_set_uint32(armv7m, "num-irq", 96); 145529fc5fdSAlistair Francis qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type); 146529fc5fdSAlistair Francis qdev_prop_set_bit(armv7m, "enable-bitband", true); 147*66e6a438SPeter Maydell qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk); 148*66e6a438SPeter Maydell qdev_connect_clock_in(armv7m, "refclk", s->refclk); 1495325cc34SMarkus Armbruster object_property_set_link(OBJECT(&s->armv7m), "memory", 1505325cc34SMarkus Armbruster OBJECT(system_memory), &error_abort); 151668f62ecSMarkus Armbruster if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), errp)) { 152529fc5fdSAlistair Francis return; 153529fc5fdSAlistair Francis } 154529fc5fdSAlistair Francis 155529fc5fdSAlistair Francis /* System configuration controller */ 156529fc5fdSAlistair Francis dev = DEVICE(&s->syscfg); 157668f62ecSMarkus Armbruster if (!sysbus_realize(SYS_BUS_DEVICE(&s->syscfg), errp)) { 158529fc5fdSAlistair Francis return; 159529fc5fdSAlistair Francis } 160529fc5fdSAlistair Francis busdev = SYS_BUS_DEVICE(dev); 161529fc5fdSAlistair Francis sysbus_mmio_map(busdev, 0, SYSCFG_ADD); 162529fc5fdSAlistair Francis sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, SYSCFG_IRQ)); 163529fc5fdSAlistair Francis 164529fc5fdSAlistair Francis /* Attach UART (uses USART registers) and USART controllers */ 165529fc5fdSAlistair Francis for (i = 0; i < STM_NUM_USARTS; i++) { 166529fc5fdSAlistair Francis dev = DEVICE(&(s->usart[i])); 167529fc5fdSAlistair Francis qdev_prop_set_chr(dev, "chardev", serial_hd(i)); 168668f62ecSMarkus Armbruster if (!sysbus_realize(SYS_BUS_DEVICE(&s->usart[i]), errp)) { 169529fc5fdSAlistair Francis return; 170529fc5fdSAlistair Francis } 171529fc5fdSAlistair Francis busdev = SYS_BUS_DEVICE(dev); 172529fc5fdSAlistair Francis sysbus_mmio_map(busdev, 0, usart_addr[i]); 173529fc5fdSAlistair Francis sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i])); 174529fc5fdSAlistair Francis } 175529fc5fdSAlistair Francis 176529fc5fdSAlistair Francis /* Timer 2 to 5 */ 177529fc5fdSAlistair Francis for (i = 0; i < STM_NUM_TIMERS; i++) { 178529fc5fdSAlistair Francis dev = DEVICE(&(s->timer[i])); 179529fc5fdSAlistair Francis qdev_prop_set_uint64(dev, "clock-frequency", 1000000000); 180668f62ecSMarkus Armbruster if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer[i]), errp)) { 181529fc5fdSAlistair Francis return; 182529fc5fdSAlistair Francis } 183529fc5fdSAlistair Francis busdev = SYS_BUS_DEVICE(dev); 184529fc5fdSAlistair Francis sysbus_mmio_map(busdev, 0, timer_addr[i]); 185529fc5fdSAlistair Francis sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, timer_irq[i])); 186529fc5fdSAlistair Francis } 187529fc5fdSAlistair Francis 188529fc5fdSAlistair Francis /* ADC device, the IRQs are ORed together */ 189778a2dc5SMarkus Armbruster if (!object_initialize_child_with_props(OBJECT(s), "adc-orirq", 190778a2dc5SMarkus Armbruster &s->adc_irqs, sizeof(s->adc_irqs), 191668f62ecSMarkus Armbruster TYPE_OR_IRQ, errp, NULL)) { 192529fc5fdSAlistair Francis return; 193529fc5fdSAlistair Francis } 1945325cc34SMarkus Armbruster object_property_set_int(OBJECT(&s->adc_irqs), "num-lines", STM_NUM_ADCS, 1955325cc34SMarkus Armbruster &error_abort); 196668f62ecSMarkus Armbruster if (!qdev_realize(DEVICE(&s->adc_irqs), NULL, errp)) { 197529fc5fdSAlistair Francis return; 198529fc5fdSAlistair Francis } 199529fc5fdSAlistair Francis qdev_connect_gpio_out(DEVICE(&s->adc_irqs), 0, 200529fc5fdSAlistair Francis qdev_get_gpio_in(armv7m, ADC_IRQ)); 201529fc5fdSAlistair Francis 2022fb1f7d2SMarkus Armbruster for (i = 0; i < STM_NUM_ADCS; i++) { 203529fc5fdSAlistair Francis dev = DEVICE(&(s->adc[i])); 204668f62ecSMarkus Armbruster if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc[i]), errp)) { 205529fc5fdSAlistair Francis return; 206529fc5fdSAlistair Francis } 207529fc5fdSAlistair Francis busdev = SYS_BUS_DEVICE(dev); 2082fb1f7d2SMarkus Armbruster sysbus_mmio_map(busdev, 0, adc_addr[i]); 209529fc5fdSAlistair Francis sysbus_connect_irq(busdev, 0, 210529fc5fdSAlistair Francis qdev_get_gpio_in(DEVICE(&s->adc_irqs), i)); 2112fb1f7d2SMarkus Armbruster } 212529fc5fdSAlistair Francis 213529fc5fdSAlistair Francis /* SPI devices */ 214529fc5fdSAlistair Francis for (i = 0; i < STM_NUM_SPIS; i++) { 215529fc5fdSAlistair Francis dev = DEVICE(&(s->spi[i])); 216668f62ecSMarkus Armbruster if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { 217529fc5fdSAlistair Francis return; 218529fc5fdSAlistair Francis } 219529fc5fdSAlistair Francis busdev = SYS_BUS_DEVICE(dev); 220529fc5fdSAlistair Francis sysbus_mmio_map(busdev, 0, spi_addr[i]); 221529fc5fdSAlistair Francis sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, spi_irq[i])); 222529fc5fdSAlistair Francis } 223529fc5fdSAlistair Francis 224529fc5fdSAlistair Francis /* EXTI device */ 225529fc5fdSAlistair Francis dev = DEVICE(&s->exti); 226668f62ecSMarkus Armbruster if (!sysbus_realize(SYS_BUS_DEVICE(&s->exti), errp)) { 227529fc5fdSAlistair Francis return; 228529fc5fdSAlistair Francis } 229529fc5fdSAlistair Francis busdev = SYS_BUS_DEVICE(dev); 230529fc5fdSAlistair Francis sysbus_mmio_map(busdev, 0, EXTI_ADDR); 231529fc5fdSAlistair Francis for (i = 0; i < 16; i++) { 232529fc5fdSAlistair Francis sysbus_connect_irq(busdev, i, qdev_get_gpio_in(armv7m, exti_irq[i])); 233529fc5fdSAlistair Francis } 234529fc5fdSAlistair Francis for (i = 0; i < 16; i++) { 235529fc5fdSAlistair Francis qdev_connect_gpio_out(DEVICE(&s->syscfg), i, qdev_get_gpio_in(dev, i)); 236529fc5fdSAlistair Francis } 237529fc5fdSAlistair Francis 238529fc5fdSAlistair Francis create_unimplemented_device("timer[7]", 0x40001400, 0x400); 239529fc5fdSAlistair Francis create_unimplemented_device("timer[12]", 0x40001800, 0x400); 240529fc5fdSAlistair Francis create_unimplemented_device("timer[6]", 0x40001000, 0x400); 241529fc5fdSAlistair Francis create_unimplemented_device("timer[13]", 0x40001C00, 0x400); 242529fc5fdSAlistair Francis create_unimplemented_device("timer[14]", 0x40002000, 0x400); 243529fc5fdSAlistair Francis create_unimplemented_device("RTC and BKP", 0x40002800, 0x400); 244529fc5fdSAlistair Francis create_unimplemented_device("WWDG", 0x40002C00, 0x400); 245529fc5fdSAlistair Francis create_unimplemented_device("IWDG", 0x40003000, 0x400); 246529fc5fdSAlistair Francis create_unimplemented_device("I2S2ext", 0x40003000, 0x400); 247529fc5fdSAlistair Francis create_unimplemented_device("I2S3ext", 0x40004000, 0x400); 248529fc5fdSAlistair Francis create_unimplemented_device("I2C1", 0x40005400, 0x400); 249529fc5fdSAlistair Francis create_unimplemented_device("I2C2", 0x40005800, 0x400); 250529fc5fdSAlistair Francis create_unimplemented_device("I2C3", 0x40005C00, 0x400); 251529fc5fdSAlistair Francis create_unimplemented_device("CAN1", 0x40006400, 0x400); 252529fc5fdSAlistair Francis create_unimplemented_device("CAN2", 0x40006800, 0x400); 253529fc5fdSAlistair Francis create_unimplemented_device("PWR", 0x40007000, 0x400); 254529fc5fdSAlistair Francis create_unimplemented_device("DAC", 0x40007400, 0x400); 255529fc5fdSAlistair Francis create_unimplemented_device("timer[1]", 0x40010000, 0x400); 256529fc5fdSAlistair Francis create_unimplemented_device("timer[8]", 0x40010400, 0x400); 257529fc5fdSAlistair Francis create_unimplemented_device("SDIO", 0x40012C00, 0x400); 258529fc5fdSAlistair Francis create_unimplemented_device("timer[9]", 0x40014000, 0x400); 259529fc5fdSAlistair Francis create_unimplemented_device("timer[10]", 0x40014400, 0x400); 260529fc5fdSAlistair Francis create_unimplemented_device("timer[11]", 0x40014800, 0x400); 261529fc5fdSAlistair Francis create_unimplemented_device("GPIOA", 0x40020000, 0x400); 262529fc5fdSAlistair Francis create_unimplemented_device("GPIOB", 0x40020400, 0x400); 263529fc5fdSAlistair Francis create_unimplemented_device("GPIOC", 0x40020800, 0x400); 264529fc5fdSAlistair Francis create_unimplemented_device("GPIOD", 0x40020C00, 0x400); 265529fc5fdSAlistair Francis create_unimplemented_device("GPIOE", 0x40021000, 0x400); 266529fc5fdSAlistair Francis create_unimplemented_device("GPIOF", 0x40021400, 0x400); 267529fc5fdSAlistair Francis create_unimplemented_device("GPIOG", 0x40021800, 0x400); 268529fc5fdSAlistair Francis create_unimplemented_device("GPIOH", 0x40021C00, 0x400); 269529fc5fdSAlistair Francis create_unimplemented_device("GPIOI", 0x40022000, 0x400); 270529fc5fdSAlistair Francis create_unimplemented_device("CRC", 0x40023000, 0x400); 271529fc5fdSAlistair Francis create_unimplemented_device("RCC", 0x40023800, 0x400); 272529fc5fdSAlistair Francis create_unimplemented_device("Flash Int", 0x40023C00, 0x400); 273529fc5fdSAlistair Francis create_unimplemented_device("BKPSRAM", 0x40024000, 0x400); 274529fc5fdSAlistair Francis create_unimplemented_device("DMA1", 0x40026000, 0x400); 275529fc5fdSAlistair Francis create_unimplemented_device("DMA2", 0x40026400, 0x400); 276529fc5fdSAlistair Francis create_unimplemented_device("Ethernet", 0x40028000, 0x1400); 277529fc5fdSAlistair Francis create_unimplemented_device("USB OTG HS", 0x40040000, 0x30000); 278529fc5fdSAlistair Francis create_unimplemented_device("USB OTG FS", 0x50000000, 0x31000); 279529fc5fdSAlistair Francis create_unimplemented_device("DCMI", 0x50050000, 0x400); 280529fc5fdSAlistair Francis create_unimplemented_device("RNG", 0x50060800, 0x400); 281529fc5fdSAlistair Francis } 282529fc5fdSAlistair Francis 283529fc5fdSAlistair Francis static Property stm32f405_soc_properties[] = { 284529fc5fdSAlistair Francis DEFINE_PROP_STRING("cpu-type", STM32F405State, cpu_type), 285529fc5fdSAlistair Francis DEFINE_PROP_END_OF_LIST(), 286529fc5fdSAlistair Francis }; 287529fc5fdSAlistair Francis 288529fc5fdSAlistair Francis static void stm32f405_soc_class_init(ObjectClass *klass, void *data) 289529fc5fdSAlistair Francis { 290529fc5fdSAlistair Francis DeviceClass *dc = DEVICE_CLASS(klass); 291529fc5fdSAlistair Francis 292529fc5fdSAlistair Francis dc->realize = stm32f405_soc_realize; 2934f67d30bSMarc-André Lureau device_class_set_props(dc, stm32f405_soc_properties); 294529fc5fdSAlistair Francis /* No vmstate or reset required: device has no internal state */ 295529fc5fdSAlistair Francis } 296529fc5fdSAlistair Francis 297529fc5fdSAlistair Francis static const TypeInfo stm32f405_soc_info = { 298529fc5fdSAlistair Francis .name = TYPE_STM32F405_SOC, 299529fc5fdSAlistair Francis .parent = TYPE_SYS_BUS_DEVICE, 300529fc5fdSAlistair Francis .instance_size = sizeof(STM32F405State), 301529fc5fdSAlistair Francis .instance_init = stm32f405_soc_initfn, 302529fc5fdSAlistair Francis .class_init = stm32f405_soc_class_init, 303529fc5fdSAlistair Francis }; 304529fc5fdSAlistair Francis 305529fc5fdSAlistair Francis static void stm32f405_soc_types(void) 306529fc5fdSAlistair Francis { 307529fc5fdSAlistair Francis type_register_static(&stm32f405_soc_info); 308529fc5fdSAlistair Francis } 309529fc5fdSAlistair Francis 310529fc5fdSAlistair Francis type_init(stm32f405_soc_types) 311