1db635521SAlistair Francis /* 2db635521SAlistair Francis * STM32F205 SoC 3db635521SAlistair Francis * 4db635521SAlistair Francis * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me> 5db635521SAlistair Francis * 6db635521SAlistair Francis * Permission is hereby granted, free of charge, to any person obtaining a copy 7db635521SAlistair Francis * of this software and associated documentation files (the "Software"), to deal 8db635521SAlistair Francis * in the Software without restriction, including without limitation the rights 9db635521SAlistair Francis * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10db635521SAlistair Francis * copies of the Software, and to permit persons to whom the Software is 11db635521SAlistair Francis * furnished to do so, subject to the following conditions: 12db635521SAlistair Francis * 13db635521SAlistair Francis * The above copyright notice and this permission notice shall be included in 14db635521SAlistair Francis * all copies or substantial portions of the Software. 15db635521SAlistair Francis * 16db635521SAlistair Francis * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17db635521SAlistair Francis * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18db635521SAlistair Francis * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19db635521SAlistair Francis * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20db635521SAlistair Francis * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21db635521SAlistair Francis * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22db635521SAlistair Francis * THE SOFTWARE. 23db635521SAlistair Francis */ 24db635521SAlistair Francis 2512b16722SPeter Maydell #include "qemu/osdep.h" 26da34e65cSMarkus Armbruster #include "qapi/error.h" 274771d756SPaolo Bonzini #include "qemu-common.h" 28db635521SAlistair Francis #include "hw/arm/arm.h" 29db635521SAlistair Francis #include "exec/address-spaces.h" 30db635521SAlistair Francis #include "hw/arm/stm32f205_soc.h" 31db635521SAlistair Francis 32db635521SAlistair Francis /* At the moment only Timer 2 to 5 are modelled */ 33db635521SAlistair Francis static const uint32_t timer_addr[STM_NUM_TIMERS] = { 0x40000000, 0x40000400, 34db635521SAlistair Francis 0x40000800, 0x40000C00 }; 35db635521SAlistair Francis static const uint32_t usart_addr[STM_NUM_USARTS] = { 0x40011000, 0x40004400, 36db635521SAlistair Francis 0x40004800, 0x40004C00, 0x40005000, 0x40011400 }; 37b63041c8SAlistair Francis static const uint32_t adc_addr[STM_NUM_ADCS] = { 0x40012000, 0x40012100, 38b63041c8SAlistair Francis 0x40012200 }; 39540a8f34SAlistair Francis static const uint32_t spi_addr[STM_NUM_SPIS] = { 0x40013000, 0x40003800, 40540a8f34SAlistair Francis 0x40003C00 }; 41db635521SAlistair Francis 42db635521SAlistair Francis static const int timer_irq[STM_NUM_TIMERS] = {28, 29, 30, 50}; 43db635521SAlistair Francis static const int usart_irq[STM_NUM_USARTS] = {37, 38, 39, 52, 53, 71}; 44b63041c8SAlistair Francis #define ADC_IRQ 18 45540a8f34SAlistair Francis static const int spi_irq[STM_NUM_SPIS] = {35, 36, 51}; 46db635521SAlistair Francis 47db635521SAlistair Francis static void stm32f205_soc_initfn(Object *obj) 48db635521SAlistair Francis { 49db635521SAlistair Francis STM32F205State *s = STM32F205_SOC(obj); 50db635521SAlistair Francis int i; 51db635521SAlistair Francis 52*b72e2f68SPeter Maydell object_initialize(&s->armv7m, sizeof(s->armv7m), TYPE_ARMV7M); 53*b72e2f68SPeter Maydell qdev_set_parent_bus(DEVICE(&s->armv7m), sysbus_get_default()); 54*b72e2f68SPeter Maydell 55db635521SAlistair Francis object_initialize(&s->syscfg, sizeof(s->syscfg), TYPE_STM32F2XX_SYSCFG); 56db635521SAlistair Francis qdev_set_parent_bus(DEVICE(&s->syscfg), sysbus_get_default()); 57db635521SAlistair Francis 58db635521SAlistair Francis for (i = 0; i < STM_NUM_USARTS; i++) { 59db635521SAlistair Francis object_initialize(&s->usart[i], sizeof(s->usart[i]), 60db635521SAlistair Francis TYPE_STM32F2XX_USART); 61db635521SAlistair Francis qdev_set_parent_bus(DEVICE(&s->usart[i]), sysbus_get_default()); 62db635521SAlistair Francis } 63db635521SAlistair Francis 64db635521SAlistair Francis for (i = 0; i < STM_NUM_TIMERS; i++) { 65db635521SAlistair Francis object_initialize(&s->timer[i], sizeof(s->timer[i]), 66db635521SAlistair Francis TYPE_STM32F2XX_TIMER); 67db635521SAlistair Francis qdev_set_parent_bus(DEVICE(&s->timer[i]), sysbus_get_default()); 68db635521SAlistair Francis } 69b63041c8SAlistair Francis 70b63041c8SAlistair Francis s->adc_irqs = OR_IRQ(object_new(TYPE_OR_IRQ)); 71b63041c8SAlistair Francis 72b63041c8SAlistair Francis for (i = 0; i < STM_NUM_ADCS; i++) { 73b63041c8SAlistair Francis object_initialize(&s->adc[i], sizeof(s->adc[i]), 74b63041c8SAlistair Francis TYPE_STM32F2XX_ADC); 75b63041c8SAlistair Francis qdev_set_parent_bus(DEVICE(&s->adc[i]), sysbus_get_default()); 76b63041c8SAlistair Francis } 77540a8f34SAlistair Francis 78540a8f34SAlistair Francis for (i = 0; i < STM_NUM_SPIS; i++) { 79540a8f34SAlistair Francis object_initialize(&s->spi[i], sizeof(s->spi[i]), 80540a8f34SAlistair Francis TYPE_STM32F2XX_SPI); 81540a8f34SAlistair Francis qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default()); 82540a8f34SAlistair Francis } 83db635521SAlistair Francis } 84db635521SAlistair Francis 85db635521SAlistair Francis static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp) 86db635521SAlistair Francis { 87db635521SAlistair Francis STM32F205State *s = STM32F205_SOC(dev_soc); 8881fed1d0SAlistair Francis DeviceState *dev, *nvic; 8981fed1d0SAlistair Francis SysBusDevice *busdev; 90db635521SAlistair Francis Error *err = NULL; 91db635521SAlistair Francis int i; 92db635521SAlistair Francis 93db635521SAlistair Francis MemoryRegion *system_memory = get_system_memory(); 94db635521SAlistair Francis MemoryRegion *sram = g_new(MemoryRegion, 1); 95db635521SAlistair Francis MemoryRegion *flash = g_new(MemoryRegion, 1); 96db635521SAlistair Francis MemoryRegion *flash_alias = g_new(MemoryRegion, 1); 97db635521SAlistair Francis 98db635521SAlistair Francis memory_region_init_ram(flash, NULL, "STM32F205.flash", FLASH_SIZE, 99f8ed85acSMarkus Armbruster &error_fatal); 100db635521SAlistair Francis memory_region_init_alias(flash_alias, NULL, "STM32F205.flash.alias", 101db635521SAlistair Francis flash, 0, FLASH_SIZE); 102db635521SAlistair Francis 103db635521SAlistair Francis vmstate_register_ram_global(flash); 104db635521SAlistair Francis 105db635521SAlistair Francis memory_region_set_readonly(flash, true); 106db635521SAlistair Francis memory_region_set_readonly(flash_alias, true); 107db635521SAlistair Francis 108db635521SAlistair Francis memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, flash); 109db635521SAlistair Francis memory_region_add_subregion(system_memory, 0, flash_alias); 110db635521SAlistair Francis 111db635521SAlistair Francis memory_region_init_ram(sram, NULL, "STM32F205.sram", SRAM_SIZE, 112f8ed85acSMarkus Armbruster &error_fatal); 113db635521SAlistair Francis vmstate_register_ram_global(sram); 114db635521SAlistair Francis memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram); 115db635521SAlistair Francis 116*b72e2f68SPeter Maydell nvic = DEVICE(&s->armv7m); 117*b72e2f68SPeter Maydell qdev_prop_set_uint32(nvic, "num-irq", 96); 118*b72e2f68SPeter Maydell qdev_prop_set_string(nvic, "cpu-model", s->cpu_model); 119*b72e2f68SPeter Maydell object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()), 120*b72e2f68SPeter Maydell "memory", &error_abort); 121*b72e2f68SPeter Maydell object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err); 122*b72e2f68SPeter Maydell if (err != NULL) { 123*b72e2f68SPeter Maydell error_propagate(errp, err); 124*b72e2f68SPeter Maydell return; 125*b72e2f68SPeter Maydell } 126db635521SAlistair Francis 127db635521SAlistair Francis /* System configuration controller */ 12881fed1d0SAlistair Francis dev = DEVICE(&s->syscfg); 129db635521SAlistair Francis object_property_set_bool(OBJECT(&s->syscfg), true, "realized", &err); 130db635521SAlistair Francis if (err != NULL) { 131db635521SAlistair Francis error_propagate(errp, err); 132db635521SAlistair Francis return; 133db635521SAlistair Francis } 13481fed1d0SAlistair Francis busdev = SYS_BUS_DEVICE(dev); 13581fed1d0SAlistair Francis sysbus_mmio_map(busdev, 0, 0x40013800); 13681fed1d0SAlistair Francis sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(nvic, 71)); 137db635521SAlistair Francis 138db635521SAlistair Francis /* Attach UART (uses USART registers) and USART controllers */ 139db635521SAlistair Francis for (i = 0; i < STM_NUM_USARTS; i++) { 14081fed1d0SAlistair Francis dev = DEVICE(&(s->usart[i])); 14181fed1d0SAlistair Francis qdev_prop_set_chr(dev, "chardev", 14281fed1d0SAlistair Francis i < MAX_SERIAL_PORTS ? serial_hds[i] : NULL); 143db635521SAlistair Francis object_property_set_bool(OBJECT(&s->usart[i]), true, "realized", &err); 144db635521SAlistair Francis if (err != NULL) { 145db635521SAlistair Francis error_propagate(errp, err); 146db635521SAlistair Francis return; 147db635521SAlistair Francis } 14881fed1d0SAlistair Francis busdev = SYS_BUS_DEVICE(dev); 14981fed1d0SAlistair Francis sysbus_mmio_map(busdev, 0, usart_addr[i]); 15081fed1d0SAlistair Francis sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(nvic, usart_irq[i])); 151db635521SAlistair Francis } 152db635521SAlistair Francis 153db635521SAlistair Francis /* Timer 2 to 5 */ 154db635521SAlistair Francis for (i = 0; i < STM_NUM_TIMERS; i++) { 15581fed1d0SAlistair Francis dev = DEVICE(&(s->timer[i])); 15681fed1d0SAlistair Francis qdev_prop_set_uint64(dev, "clock-frequency", 1000000000); 157db635521SAlistair Francis object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err); 158db635521SAlistair Francis if (err != NULL) { 159db635521SAlistair Francis error_propagate(errp, err); 160db635521SAlistair Francis return; 161db635521SAlistair Francis } 16281fed1d0SAlistair Francis busdev = SYS_BUS_DEVICE(dev); 16381fed1d0SAlistair Francis sysbus_mmio_map(busdev, 0, timer_addr[i]); 16481fed1d0SAlistair Francis sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(nvic, timer_irq[i])); 165db635521SAlistair Francis } 166b63041c8SAlistair Francis 167b63041c8SAlistair Francis /* ADC 1 to 3 */ 168b63041c8SAlistair Francis object_property_set_int(OBJECT(s->adc_irqs), STM_NUM_ADCS, 169b63041c8SAlistair Francis "num-lines", &err); 170b63041c8SAlistair Francis object_property_set_bool(OBJECT(s->adc_irqs), true, "realized", &err); 171b63041c8SAlistair Francis if (err != NULL) { 172b63041c8SAlistair Francis error_propagate(errp, err); 173b63041c8SAlistair Francis return; 174b63041c8SAlistair Francis } 175b63041c8SAlistair Francis qdev_connect_gpio_out(DEVICE(s->adc_irqs), 0, 176b63041c8SAlistair Francis qdev_get_gpio_in(nvic, ADC_IRQ)); 177b63041c8SAlistair Francis 178b63041c8SAlistair Francis for (i = 0; i < STM_NUM_ADCS; i++) { 179b63041c8SAlistair Francis dev = DEVICE(&(s->adc[i])); 180b63041c8SAlistair Francis object_property_set_bool(OBJECT(&s->adc[i]), true, "realized", &err); 181b63041c8SAlistair Francis if (err != NULL) { 182b63041c8SAlistair Francis error_propagate(errp, err); 183b63041c8SAlistair Francis return; 184b63041c8SAlistair Francis } 185b63041c8SAlistair Francis busdev = SYS_BUS_DEVICE(dev); 186b63041c8SAlistair Francis sysbus_mmio_map(busdev, 0, adc_addr[i]); 187b63041c8SAlistair Francis sysbus_connect_irq(busdev, 0, 188b63041c8SAlistair Francis qdev_get_gpio_in(DEVICE(s->adc_irqs), i)); 189b63041c8SAlistair Francis } 190540a8f34SAlistair Francis 191540a8f34SAlistair Francis /* SPI 1 and 2 */ 192540a8f34SAlistair Francis for (i = 0; i < STM_NUM_SPIS; i++) { 193540a8f34SAlistair Francis dev = DEVICE(&(s->spi[i])); 194540a8f34SAlistair Francis object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err); 195540a8f34SAlistair Francis if (err != NULL) { 196540a8f34SAlistair Francis error_propagate(errp, err); 197540a8f34SAlistair Francis return; 198540a8f34SAlistair Francis } 199540a8f34SAlistair Francis busdev = SYS_BUS_DEVICE(dev); 200540a8f34SAlistair Francis sysbus_mmio_map(busdev, 0, spi_addr[i]); 201540a8f34SAlistair Francis sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(nvic, spi_irq[i])); 202540a8f34SAlistair Francis } 203db635521SAlistair Francis } 204db635521SAlistair Francis 205db635521SAlistair Francis static Property stm32f205_soc_properties[] = { 206db635521SAlistair Francis DEFINE_PROP_STRING("cpu-model", STM32F205State, cpu_model), 207db635521SAlistair Francis DEFINE_PROP_END_OF_LIST(), 208db635521SAlistair Francis }; 209db635521SAlistair Francis 210db635521SAlistair Francis static void stm32f205_soc_class_init(ObjectClass *klass, void *data) 211db635521SAlistair Francis { 212db635521SAlistair Francis DeviceClass *dc = DEVICE_CLASS(klass); 213db635521SAlistair Francis 214db635521SAlistair Francis dc->realize = stm32f205_soc_realize; 215db635521SAlistair Francis dc->props = stm32f205_soc_properties; 216db635521SAlistair Francis } 217db635521SAlistair Francis 218db635521SAlistair Francis static const TypeInfo stm32f205_soc_info = { 219db635521SAlistair Francis .name = TYPE_STM32F205_SOC, 220db635521SAlistair Francis .parent = TYPE_SYS_BUS_DEVICE, 221db635521SAlistair Francis .instance_size = sizeof(STM32F205State), 222db635521SAlistair Francis .instance_init = stm32f205_soc_initfn, 223db635521SAlistair Francis .class_init = stm32f205_soc_class_init, 224db635521SAlistair Francis }; 225db635521SAlistair Francis 226db635521SAlistair Francis static void stm32f205_soc_types(void) 227db635521SAlistair Francis { 228db635521SAlistair Francis type_register_static(&stm32f205_soc_info); 229db635521SAlistair Francis } 230db635521SAlistair Francis 231db635521SAlistair Francis type_init(stm32f205_soc_types) 232