1 /* 2 * Luminary Micro Stellaris peripherals 3 * 4 * Copyright (c) 2006 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qapi/error.h" 12 #include "hw/sysbus.h" 13 #include "hw/ssi/ssi.h" 14 #include "hw/arm/boot.h" 15 #include "qemu/timer.h" 16 #include "hw/i2c/i2c.h" 17 #include "net/net.h" 18 #include "hw/boards.h" 19 #include "qemu/log.h" 20 #include "exec/address-spaces.h" 21 #include "sysemu/sysemu.h" 22 #include "hw/arm/armv7m.h" 23 #include "hw/char/pl011.h" 24 #include "hw/input/gamepad.h" 25 #include "hw/irq.h" 26 #include "hw/watchdog/cmsdk-apb-watchdog.h" 27 #include "migration/vmstate.h" 28 #include "hw/misc/unimp.h" 29 #include "hw/timer/stellaris-gptm.h" 30 #include "hw/qdev-clock.h" 31 #include "qom/object.h" 32 33 #define GPIO_A 0 34 #define GPIO_B 1 35 #define GPIO_C 2 36 #define GPIO_D 3 37 #define GPIO_E 4 38 #define GPIO_F 5 39 #define GPIO_G 6 40 41 #define BP_OLED_I2C 0x01 42 #define BP_OLED_SSI 0x02 43 #define BP_GAMEPAD 0x04 44 45 #define NUM_IRQ_LINES 64 46 47 typedef const struct { 48 const char *name; 49 uint32_t did0; 50 uint32_t did1; 51 uint32_t dc0; 52 uint32_t dc1; 53 uint32_t dc2; 54 uint32_t dc3; 55 uint32_t dc4; 56 uint32_t peripherals; 57 } stellaris_board_info; 58 59 /* System controller. */ 60 61 #define TYPE_STELLARIS_SYS "stellaris-sys" 62 OBJECT_DECLARE_SIMPLE_TYPE(ssys_state, STELLARIS_SYS) 63 64 struct ssys_state { 65 SysBusDevice parent_obj; 66 67 MemoryRegion iomem; 68 uint32_t pborctl; 69 uint32_t ldopctl; 70 uint32_t int_status; 71 uint32_t int_mask; 72 uint32_t resc; 73 uint32_t rcc; 74 uint32_t rcc2; 75 uint32_t rcgc[3]; 76 uint32_t scgc[3]; 77 uint32_t dcgc[3]; 78 uint32_t clkvclr; 79 uint32_t ldoarst; 80 qemu_irq irq; 81 Clock *sysclk; 82 /* Properties (all read-only registers) */ 83 uint32_t user0; 84 uint32_t user1; 85 uint32_t did0; 86 uint32_t did1; 87 uint32_t dc0; 88 uint32_t dc1; 89 uint32_t dc2; 90 uint32_t dc3; 91 uint32_t dc4; 92 }; 93 94 static void ssys_update(ssys_state *s) 95 { 96 qemu_set_irq(s->irq, (s->int_status & s->int_mask) != 0); 97 } 98 99 static uint32_t pllcfg_sandstorm[16] = { 100 0x31c0, /* 1 Mhz */ 101 0x1ae0, /* 1.8432 Mhz */ 102 0x18c0, /* 2 Mhz */ 103 0xd573, /* 2.4576 Mhz */ 104 0x37a6, /* 3.57954 Mhz */ 105 0x1ae2, /* 3.6864 Mhz */ 106 0x0c40, /* 4 Mhz */ 107 0x98bc, /* 4.906 Mhz */ 108 0x935b, /* 4.9152 Mhz */ 109 0x09c0, /* 5 Mhz */ 110 0x4dee, /* 5.12 Mhz */ 111 0x0c41, /* 6 Mhz */ 112 0x75db, /* 6.144 Mhz */ 113 0x1ae6, /* 7.3728 Mhz */ 114 0x0600, /* 8 Mhz */ 115 0x585b /* 8.192 Mhz */ 116 }; 117 118 static uint32_t pllcfg_fury[16] = { 119 0x3200, /* 1 Mhz */ 120 0x1b20, /* 1.8432 Mhz */ 121 0x1900, /* 2 Mhz */ 122 0xf42b, /* 2.4576 Mhz */ 123 0x37e3, /* 3.57954 Mhz */ 124 0x1b21, /* 3.6864 Mhz */ 125 0x0c80, /* 4 Mhz */ 126 0x98ee, /* 4.906 Mhz */ 127 0xd5b4, /* 4.9152 Mhz */ 128 0x0a00, /* 5 Mhz */ 129 0x4e27, /* 5.12 Mhz */ 130 0x1902, /* 6 Mhz */ 131 0xec1c, /* 6.144 Mhz */ 132 0x1b23, /* 7.3728 Mhz */ 133 0x0640, /* 8 Mhz */ 134 0xb11c /* 8.192 Mhz */ 135 }; 136 137 #define DID0_VER_MASK 0x70000000 138 #define DID0_VER_0 0x00000000 139 #define DID0_VER_1 0x10000000 140 141 #define DID0_CLASS_MASK 0x00FF0000 142 #define DID0_CLASS_SANDSTORM 0x00000000 143 #define DID0_CLASS_FURY 0x00010000 144 145 static int ssys_board_class(const ssys_state *s) 146 { 147 uint32_t did0 = s->did0; 148 switch (did0 & DID0_VER_MASK) { 149 case DID0_VER_0: 150 return DID0_CLASS_SANDSTORM; 151 case DID0_VER_1: 152 switch (did0 & DID0_CLASS_MASK) { 153 case DID0_CLASS_SANDSTORM: 154 case DID0_CLASS_FURY: 155 return did0 & DID0_CLASS_MASK; 156 } 157 /* for unknown classes, fall through */ 158 default: 159 /* This can only happen if the hardwired constant did0 value 160 * in this board's stellaris_board_info struct is wrong. 161 */ 162 g_assert_not_reached(); 163 } 164 } 165 166 static uint64_t ssys_read(void *opaque, hwaddr offset, 167 unsigned size) 168 { 169 ssys_state *s = (ssys_state *)opaque; 170 171 switch (offset) { 172 case 0x000: /* DID0 */ 173 return s->did0; 174 case 0x004: /* DID1 */ 175 return s->did1; 176 case 0x008: /* DC0 */ 177 return s->dc0; 178 case 0x010: /* DC1 */ 179 return s->dc1; 180 case 0x014: /* DC2 */ 181 return s->dc2; 182 case 0x018: /* DC3 */ 183 return s->dc3; 184 case 0x01c: /* DC4 */ 185 return s->dc4; 186 case 0x030: /* PBORCTL */ 187 return s->pborctl; 188 case 0x034: /* LDOPCTL */ 189 return s->ldopctl; 190 case 0x040: /* SRCR0 */ 191 return 0; 192 case 0x044: /* SRCR1 */ 193 return 0; 194 case 0x048: /* SRCR2 */ 195 return 0; 196 case 0x050: /* RIS */ 197 return s->int_status; 198 case 0x054: /* IMC */ 199 return s->int_mask; 200 case 0x058: /* MISC */ 201 return s->int_status & s->int_mask; 202 case 0x05c: /* RESC */ 203 return s->resc; 204 case 0x060: /* RCC */ 205 return s->rcc; 206 case 0x064: /* PLLCFG */ 207 { 208 int xtal; 209 xtal = (s->rcc >> 6) & 0xf; 210 switch (ssys_board_class(s)) { 211 case DID0_CLASS_FURY: 212 return pllcfg_fury[xtal]; 213 case DID0_CLASS_SANDSTORM: 214 return pllcfg_sandstorm[xtal]; 215 default: 216 g_assert_not_reached(); 217 } 218 } 219 case 0x070: /* RCC2 */ 220 return s->rcc2; 221 case 0x100: /* RCGC0 */ 222 return s->rcgc[0]; 223 case 0x104: /* RCGC1 */ 224 return s->rcgc[1]; 225 case 0x108: /* RCGC2 */ 226 return s->rcgc[2]; 227 case 0x110: /* SCGC0 */ 228 return s->scgc[0]; 229 case 0x114: /* SCGC1 */ 230 return s->scgc[1]; 231 case 0x118: /* SCGC2 */ 232 return s->scgc[2]; 233 case 0x120: /* DCGC0 */ 234 return s->dcgc[0]; 235 case 0x124: /* DCGC1 */ 236 return s->dcgc[1]; 237 case 0x128: /* DCGC2 */ 238 return s->dcgc[2]; 239 case 0x150: /* CLKVCLR */ 240 return s->clkvclr; 241 case 0x160: /* LDOARST */ 242 return s->ldoarst; 243 case 0x1e0: /* USER0 */ 244 return s->user0; 245 case 0x1e4: /* USER1 */ 246 return s->user1; 247 default: 248 qemu_log_mask(LOG_GUEST_ERROR, 249 "SSYS: read at bad offset 0x%x\n", (int)offset); 250 return 0; 251 } 252 } 253 254 static bool ssys_use_rcc2(ssys_state *s) 255 { 256 return (s->rcc2 >> 31) & 0x1; 257 } 258 259 /* 260 * Calculate the system clock period. We only want to propagate 261 * this change to the rest of the system if we're not being called 262 * from migration post-load. 263 */ 264 static void ssys_calculate_system_clock(ssys_state *s, bool propagate_clock) 265 { 266 /* 267 * SYSDIV field specifies divisor: 0 == /1, 1 == /2, etc. Input 268 * clock is 200MHz, which is a period of 5 ns. Dividing the clock 269 * frequency by X is the same as multiplying the period by X. 270 */ 271 if (ssys_use_rcc2(s)) { 272 system_clock_scale = 5 * (((s->rcc2 >> 23) & 0x3f) + 1); 273 } else { 274 system_clock_scale = 5 * (((s->rcc >> 23) & 0xf) + 1); 275 } 276 clock_set_ns(s->sysclk, system_clock_scale); 277 if (propagate_clock) { 278 clock_propagate(s->sysclk); 279 } 280 } 281 282 static void ssys_write(void *opaque, hwaddr offset, 283 uint64_t value, unsigned size) 284 { 285 ssys_state *s = (ssys_state *)opaque; 286 287 switch (offset) { 288 case 0x030: /* PBORCTL */ 289 s->pborctl = value & 0xffff; 290 break; 291 case 0x034: /* LDOPCTL */ 292 s->ldopctl = value & 0x1f; 293 break; 294 case 0x040: /* SRCR0 */ 295 case 0x044: /* SRCR1 */ 296 case 0x048: /* SRCR2 */ 297 qemu_log_mask(LOG_UNIMP, "Peripheral reset not implemented\n"); 298 break; 299 case 0x054: /* IMC */ 300 s->int_mask = value & 0x7f; 301 break; 302 case 0x058: /* MISC */ 303 s->int_status &= ~value; 304 break; 305 case 0x05c: /* RESC */ 306 s->resc = value & 0x3f; 307 break; 308 case 0x060: /* RCC */ 309 if ((s->rcc & (1 << 13)) != 0 && (value & (1 << 13)) == 0) { 310 /* PLL enable. */ 311 s->int_status |= (1 << 6); 312 } 313 s->rcc = value; 314 ssys_calculate_system_clock(s, true); 315 break; 316 case 0x070: /* RCC2 */ 317 if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) { 318 break; 319 } 320 321 if ((s->rcc2 & (1 << 13)) != 0 && (value & (1 << 13)) == 0) { 322 /* PLL enable. */ 323 s->int_status |= (1 << 6); 324 } 325 s->rcc2 = value; 326 ssys_calculate_system_clock(s, true); 327 break; 328 case 0x100: /* RCGC0 */ 329 s->rcgc[0] = value; 330 break; 331 case 0x104: /* RCGC1 */ 332 s->rcgc[1] = value; 333 break; 334 case 0x108: /* RCGC2 */ 335 s->rcgc[2] = value; 336 break; 337 case 0x110: /* SCGC0 */ 338 s->scgc[0] = value; 339 break; 340 case 0x114: /* SCGC1 */ 341 s->scgc[1] = value; 342 break; 343 case 0x118: /* SCGC2 */ 344 s->scgc[2] = value; 345 break; 346 case 0x120: /* DCGC0 */ 347 s->dcgc[0] = value; 348 break; 349 case 0x124: /* DCGC1 */ 350 s->dcgc[1] = value; 351 break; 352 case 0x128: /* DCGC2 */ 353 s->dcgc[2] = value; 354 break; 355 case 0x150: /* CLKVCLR */ 356 s->clkvclr = value; 357 break; 358 case 0x160: /* LDOARST */ 359 s->ldoarst = value; 360 break; 361 default: 362 qemu_log_mask(LOG_GUEST_ERROR, 363 "SSYS: write at bad offset 0x%x\n", (int)offset); 364 } 365 ssys_update(s); 366 } 367 368 static const MemoryRegionOps ssys_ops = { 369 .read = ssys_read, 370 .write = ssys_write, 371 .endianness = DEVICE_NATIVE_ENDIAN, 372 }; 373 374 static void stellaris_sys_reset_enter(Object *obj, ResetType type) 375 { 376 ssys_state *s = STELLARIS_SYS(obj); 377 378 s->pborctl = 0x7ffd; 379 s->rcc = 0x078e3ac0; 380 381 if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) { 382 s->rcc2 = 0; 383 } else { 384 s->rcc2 = 0x07802810; 385 } 386 s->rcgc[0] = 1; 387 s->scgc[0] = 1; 388 s->dcgc[0] = 1; 389 } 390 391 static void stellaris_sys_reset_hold(Object *obj) 392 { 393 ssys_state *s = STELLARIS_SYS(obj); 394 395 /* OK to propagate clocks from the hold phase */ 396 ssys_calculate_system_clock(s, true); 397 } 398 399 static void stellaris_sys_reset_exit(Object *obj) 400 { 401 } 402 403 static int stellaris_sys_post_load(void *opaque, int version_id) 404 { 405 ssys_state *s = opaque; 406 407 ssys_calculate_system_clock(s, false); 408 409 return 0; 410 } 411 412 static const VMStateDescription vmstate_stellaris_sys = { 413 .name = "stellaris_sys", 414 .version_id = 2, 415 .minimum_version_id = 1, 416 .post_load = stellaris_sys_post_load, 417 .fields = (VMStateField[]) { 418 VMSTATE_UINT32(pborctl, ssys_state), 419 VMSTATE_UINT32(ldopctl, ssys_state), 420 VMSTATE_UINT32(int_mask, ssys_state), 421 VMSTATE_UINT32(int_status, ssys_state), 422 VMSTATE_UINT32(resc, ssys_state), 423 VMSTATE_UINT32(rcc, ssys_state), 424 VMSTATE_UINT32_V(rcc2, ssys_state, 2), 425 VMSTATE_UINT32_ARRAY(rcgc, ssys_state, 3), 426 VMSTATE_UINT32_ARRAY(scgc, ssys_state, 3), 427 VMSTATE_UINT32_ARRAY(dcgc, ssys_state, 3), 428 VMSTATE_UINT32(clkvclr, ssys_state), 429 VMSTATE_UINT32(ldoarst, ssys_state), 430 /* No field for sysclk -- handled in post-load instead */ 431 VMSTATE_END_OF_LIST() 432 } 433 }; 434 435 static Property stellaris_sys_properties[] = { 436 DEFINE_PROP_UINT32("user0", ssys_state, user0, 0), 437 DEFINE_PROP_UINT32("user1", ssys_state, user1, 0), 438 DEFINE_PROP_UINT32("did0", ssys_state, did0, 0), 439 DEFINE_PROP_UINT32("did1", ssys_state, did1, 0), 440 DEFINE_PROP_UINT32("dc0", ssys_state, dc0, 0), 441 DEFINE_PROP_UINT32("dc1", ssys_state, dc1, 0), 442 DEFINE_PROP_UINT32("dc2", ssys_state, dc2, 0), 443 DEFINE_PROP_UINT32("dc3", ssys_state, dc3, 0), 444 DEFINE_PROP_UINT32("dc4", ssys_state, dc4, 0), 445 DEFINE_PROP_END_OF_LIST() 446 }; 447 448 static void stellaris_sys_instance_init(Object *obj) 449 { 450 ssys_state *s = STELLARIS_SYS(obj); 451 SysBusDevice *sbd = SYS_BUS_DEVICE(s); 452 453 memory_region_init_io(&s->iomem, obj, &ssys_ops, s, "ssys", 0x00001000); 454 sysbus_init_mmio(sbd, &s->iomem); 455 sysbus_init_irq(sbd, &s->irq); 456 s->sysclk = qdev_init_clock_out(DEVICE(s), "SYSCLK"); 457 } 458 459 /* I2C controller. */ 460 461 #define TYPE_STELLARIS_I2C "stellaris-i2c" 462 OBJECT_DECLARE_SIMPLE_TYPE(stellaris_i2c_state, STELLARIS_I2C) 463 464 struct stellaris_i2c_state { 465 SysBusDevice parent_obj; 466 467 I2CBus *bus; 468 qemu_irq irq; 469 MemoryRegion iomem; 470 uint32_t msa; 471 uint32_t mcs; 472 uint32_t mdr; 473 uint32_t mtpr; 474 uint32_t mimr; 475 uint32_t mris; 476 uint32_t mcr; 477 }; 478 479 #define STELLARIS_I2C_MCS_BUSY 0x01 480 #define STELLARIS_I2C_MCS_ERROR 0x02 481 #define STELLARIS_I2C_MCS_ADRACK 0x04 482 #define STELLARIS_I2C_MCS_DATACK 0x08 483 #define STELLARIS_I2C_MCS_ARBLST 0x10 484 #define STELLARIS_I2C_MCS_IDLE 0x20 485 #define STELLARIS_I2C_MCS_BUSBSY 0x40 486 487 static uint64_t stellaris_i2c_read(void *opaque, hwaddr offset, 488 unsigned size) 489 { 490 stellaris_i2c_state *s = (stellaris_i2c_state *)opaque; 491 492 switch (offset) { 493 case 0x00: /* MSA */ 494 return s->msa; 495 case 0x04: /* MCS */ 496 /* We don't emulate timing, so the controller is never busy. */ 497 return s->mcs | STELLARIS_I2C_MCS_IDLE; 498 case 0x08: /* MDR */ 499 return s->mdr; 500 case 0x0c: /* MTPR */ 501 return s->mtpr; 502 case 0x10: /* MIMR */ 503 return s->mimr; 504 case 0x14: /* MRIS */ 505 return s->mris; 506 case 0x18: /* MMIS */ 507 return s->mris & s->mimr; 508 case 0x20: /* MCR */ 509 return s->mcr; 510 default: 511 qemu_log_mask(LOG_GUEST_ERROR, 512 "stellaris_i2c: read at bad offset 0x%x\n", (int)offset); 513 return 0; 514 } 515 } 516 517 static void stellaris_i2c_update(stellaris_i2c_state *s) 518 { 519 int level; 520 521 level = (s->mris & s->mimr) != 0; 522 qemu_set_irq(s->irq, level); 523 } 524 525 static void stellaris_i2c_write(void *opaque, hwaddr offset, 526 uint64_t value, unsigned size) 527 { 528 stellaris_i2c_state *s = (stellaris_i2c_state *)opaque; 529 530 switch (offset) { 531 case 0x00: /* MSA */ 532 s->msa = value & 0xff; 533 break; 534 case 0x04: /* MCS */ 535 if ((s->mcr & 0x10) == 0) { 536 /* Disabled. Do nothing. */ 537 break; 538 } 539 /* Grab the bus if this is starting a transfer. */ 540 if ((value & 2) && (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) { 541 if (i2c_start_transfer(s->bus, s->msa >> 1, s->msa & 1)) { 542 s->mcs |= STELLARIS_I2C_MCS_ARBLST; 543 } else { 544 s->mcs &= ~STELLARIS_I2C_MCS_ARBLST; 545 s->mcs |= STELLARIS_I2C_MCS_BUSBSY; 546 } 547 } 548 /* If we don't have the bus then indicate an error. */ 549 if (!i2c_bus_busy(s->bus) 550 || (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) { 551 s->mcs |= STELLARIS_I2C_MCS_ERROR; 552 break; 553 } 554 s->mcs &= ~STELLARIS_I2C_MCS_ERROR; 555 if (value & 1) { 556 /* Transfer a byte. */ 557 /* TODO: Handle errors. */ 558 if (s->msa & 1) { 559 /* Recv */ 560 s->mdr = i2c_recv(s->bus); 561 } else { 562 /* Send */ 563 i2c_send(s->bus, s->mdr); 564 } 565 /* Raise an interrupt. */ 566 s->mris |= 1; 567 } 568 if (value & 4) { 569 /* Finish transfer. */ 570 i2c_end_transfer(s->bus); 571 s->mcs &= ~STELLARIS_I2C_MCS_BUSBSY; 572 } 573 break; 574 case 0x08: /* MDR */ 575 s->mdr = value & 0xff; 576 break; 577 case 0x0c: /* MTPR */ 578 s->mtpr = value & 0xff; 579 break; 580 case 0x10: /* MIMR */ 581 s->mimr = 1; 582 break; 583 case 0x1c: /* MICR */ 584 s->mris &= ~value; 585 break; 586 case 0x20: /* MCR */ 587 if (value & 1) { 588 qemu_log_mask(LOG_UNIMP, 589 "stellaris_i2c: Loopback not implemented\n"); 590 } 591 if (value & 0x20) { 592 qemu_log_mask(LOG_UNIMP, 593 "stellaris_i2c: Slave mode not implemented\n"); 594 } 595 s->mcr = value & 0x31; 596 break; 597 default: 598 qemu_log_mask(LOG_GUEST_ERROR, 599 "stellaris_i2c: write at bad offset 0x%x\n", (int)offset); 600 } 601 stellaris_i2c_update(s); 602 } 603 604 static void stellaris_i2c_reset(stellaris_i2c_state *s) 605 { 606 if (s->mcs & STELLARIS_I2C_MCS_BUSBSY) 607 i2c_end_transfer(s->bus); 608 609 s->msa = 0; 610 s->mcs = 0; 611 s->mdr = 0; 612 s->mtpr = 1; 613 s->mimr = 0; 614 s->mris = 0; 615 s->mcr = 0; 616 stellaris_i2c_update(s); 617 } 618 619 static const MemoryRegionOps stellaris_i2c_ops = { 620 .read = stellaris_i2c_read, 621 .write = stellaris_i2c_write, 622 .endianness = DEVICE_NATIVE_ENDIAN, 623 }; 624 625 static const VMStateDescription vmstate_stellaris_i2c = { 626 .name = "stellaris_i2c", 627 .version_id = 1, 628 .minimum_version_id = 1, 629 .fields = (VMStateField[]) { 630 VMSTATE_UINT32(msa, stellaris_i2c_state), 631 VMSTATE_UINT32(mcs, stellaris_i2c_state), 632 VMSTATE_UINT32(mdr, stellaris_i2c_state), 633 VMSTATE_UINT32(mtpr, stellaris_i2c_state), 634 VMSTATE_UINT32(mimr, stellaris_i2c_state), 635 VMSTATE_UINT32(mris, stellaris_i2c_state), 636 VMSTATE_UINT32(mcr, stellaris_i2c_state), 637 VMSTATE_END_OF_LIST() 638 } 639 }; 640 641 static void stellaris_i2c_init(Object *obj) 642 { 643 DeviceState *dev = DEVICE(obj); 644 stellaris_i2c_state *s = STELLARIS_I2C(obj); 645 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 646 I2CBus *bus; 647 648 sysbus_init_irq(sbd, &s->irq); 649 bus = i2c_init_bus(dev, "i2c"); 650 s->bus = bus; 651 652 memory_region_init_io(&s->iomem, obj, &stellaris_i2c_ops, s, 653 "i2c", 0x1000); 654 sysbus_init_mmio(sbd, &s->iomem); 655 /* ??? For now we only implement the master interface. */ 656 stellaris_i2c_reset(s); 657 } 658 659 /* Analogue to Digital Converter. This is only partially implemented, 660 enough for applications that use a combined ADC and timer tick. */ 661 662 #define STELLARIS_ADC_EM_CONTROLLER 0 663 #define STELLARIS_ADC_EM_COMP 1 664 #define STELLARIS_ADC_EM_EXTERNAL 4 665 #define STELLARIS_ADC_EM_TIMER 5 666 #define STELLARIS_ADC_EM_PWM0 6 667 #define STELLARIS_ADC_EM_PWM1 7 668 #define STELLARIS_ADC_EM_PWM2 8 669 670 #define STELLARIS_ADC_FIFO_EMPTY 0x0100 671 #define STELLARIS_ADC_FIFO_FULL 0x1000 672 673 #define TYPE_STELLARIS_ADC "stellaris-adc" 674 typedef struct StellarisADCState stellaris_adc_state; 675 DECLARE_INSTANCE_CHECKER(stellaris_adc_state, STELLARIS_ADC, 676 TYPE_STELLARIS_ADC) 677 678 struct StellarisADCState { 679 SysBusDevice parent_obj; 680 681 MemoryRegion iomem; 682 uint32_t actss; 683 uint32_t ris; 684 uint32_t im; 685 uint32_t emux; 686 uint32_t ostat; 687 uint32_t ustat; 688 uint32_t sspri; 689 uint32_t sac; 690 struct { 691 uint32_t state; 692 uint32_t data[16]; 693 } fifo[4]; 694 uint32_t ssmux[4]; 695 uint32_t ssctl[4]; 696 uint32_t noise; 697 qemu_irq irq[4]; 698 }; 699 700 static uint32_t stellaris_adc_fifo_read(stellaris_adc_state *s, int n) 701 { 702 int tail; 703 704 tail = s->fifo[n].state & 0xf; 705 if (s->fifo[n].state & STELLARIS_ADC_FIFO_EMPTY) { 706 s->ustat |= 1 << n; 707 } else { 708 s->fifo[n].state = (s->fifo[n].state & ~0xf) | ((tail + 1) & 0xf); 709 s->fifo[n].state &= ~STELLARIS_ADC_FIFO_FULL; 710 if (tail + 1 == ((s->fifo[n].state >> 4) & 0xf)) 711 s->fifo[n].state |= STELLARIS_ADC_FIFO_EMPTY; 712 } 713 return s->fifo[n].data[tail]; 714 } 715 716 static void stellaris_adc_fifo_write(stellaris_adc_state *s, int n, 717 uint32_t value) 718 { 719 int head; 720 721 /* TODO: Real hardware has limited size FIFOs. We have a full 16 entry 722 FIFO fir each sequencer. */ 723 head = (s->fifo[n].state >> 4) & 0xf; 724 if (s->fifo[n].state & STELLARIS_ADC_FIFO_FULL) { 725 s->ostat |= 1 << n; 726 return; 727 } 728 s->fifo[n].data[head] = value; 729 head = (head + 1) & 0xf; 730 s->fifo[n].state &= ~STELLARIS_ADC_FIFO_EMPTY; 731 s->fifo[n].state = (s->fifo[n].state & ~0xf0) | (head << 4); 732 if ((s->fifo[n].state & 0xf) == head) 733 s->fifo[n].state |= STELLARIS_ADC_FIFO_FULL; 734 } 735 736 static void stellaris_adc_update(stellaris_adc_state *s) 737 { 738 int level; 739 int n; 740 741 for (n = 0; n < 4; n++) { 742 level = (s->ris & s->im & (1 << n)) != 0; 743 qemu_set_irq(s->irq[n], level); 744 } 745 } 746 747 static void stellaris_adc_trigger(void *opaque, int irq, int level) 748 { 749 stellaris_adc_state *s = (stellaris_adc_state *)opaque; 750 int n; 751 752 for (n = 0; n < 4; n++) { 753 if ((s->actss & (1 << n)) == 0) { 754 continue; 755 } 756 757 if (((s->emux >> (n * 4)) & 0xff) != 5) { 758 continue; 759 } 760 761 /* Some applications use the ADC as a random number source, so introduce 762 some variation into the signal. */ 763 s->noise = s->noise * 314159 + 1; 764 /* ??? actual inputs not implemented. Return an arbitrary value. */ 765 stellaris_adc_fifo_write(s, n, 0x200 + ((s->noise >> 16) & 7)); 766 s->ris |= (1 << n); 767 stellaris_adc_update(s); 768 } 769 } 770 771 static void stellaris_adc_reset(stellaris_adc_state *s) 772 { 773 int n; 774 775 for (n = 0; n < 4; n++) { 776 s->ssmux[n] = 0; 777 s->ssctl[n] = 0; 778 s->fifo[n].state = STELLARIS_ADC_FIFO_EMPTY; 779 } 780 } 781 782 static uint64_t stellaris_adc_read(void *opaque, hwaddr offset, 783 unsigned size) 784 { 785 stellaris_adc_state *s = (stellaris_adc_state *)opaque; 786 787 /* TODO: Implement this. */ 788 if (offset >= 0x40 && offset < 0xc0) { 789 int n; 790 n = (offset - 0x40) >> 5; 791 switch (offset & 0x1f) { 792 case 0x00: /* SSMUX */ 793 return s->ssmux[n]; 794 case 0x04: /* SSCTL */ 795 return s->ssctl[n]; 796 case 0x08: /* SSFIFO */ 797 return stellaris_adc_fifo_read(s, n); 798 case 0x0c: /* SSFSTAT */ 799 return s->fifo[n].state; 800 default: 801 break; 802 } 803 } 804 switch (offset) { 805 case 0x00: /* ACTSS */ 806 return s->actss; 807 case 0x04: /* RIS */ 808 return s->ris; 809 case 0x08: /* IM */ 810 return s->im; 811 case 0x0c: /* ISC */ 812 return s->ris & s->im; 813 case 0x10: /* OSTAT */ 814 return s->ostat; 815 case 0x14: /* EMUX */ 816 return s->emux; 817 case 0x18: /* USTAT */ 818 return s->ustat; 819 case 0x20: /* SSPRI */ 820 return s->sspri; 821 case 0x30: /* SAC */ 822 return s->sac; 823 default: 824 qemu_log_mask(LOG_GUEST_ERROR, 825 "stellaris_adc: read at bad offset 0x%x\n", (int)offset); 826 return 0; 827 } 828 } 829 830 static void stellaris_adc_write(void *opaque, hwaddr offset, 831 uint64_t value, unsigned size) 832 { 833 stellaris_adc_state *s = (stellaris_adc_state *)opaque; 834 835 /* TODO: Implement this. */ 836 if (offset >= 0x40 && offset < 0xc0) { 837 int n; 838 n = (offset - 0x40) >> 5; 839 switch (offset & 0x1f) { 840 case 0x00: /* SSMUX */ 841 s->ssmux[n] = value & 0x33333333; 842 return; 843 case 0x04: /* SSCTL */ 844 if (value != 6) { 845 qemu_log_mask(LOG_UNIMP, 846 "ADC: Unimplemented sequence %" PRIx64 "\n", 847 value); 848 } 849 s->ssctl[n] = value; 850 return; 851 default: 852 break; 853 } 854 } 855 switch (offset) { 856 case 0x00: /* ACTSS */ 857 s->actss = value & 0xf; 858 break; 859 case 0x08: /* IM */ 860 s->im = value; 861 break; 862 case 0x0c: /* ISC */ 863 s->ris &= ~value; 864 break; 865 case 0x10: /* OSTAT */ 866 s->ostat &= ~value; 867 break; 868 case 0x14: /* EMUX */ 869 s->emux = value; 870 break; 871 case 0x18: /* USTAT */ 872 s->ustat &= ~value; 873 break; 874 case 0x20: /* SSPRI */ 875 s->sspri = value; 876 break; 877 case 0x28: /* PSSI */ 878 qemu_log_mask(LOG_UNIMP, "ADC: sample initiate unimplemented\n"); 879 break; 880 case 0x30: /* SAC */ 881 s->sac = value; 882 break; 883 default: 884 qemu_log_mask(LOG_GUEST_ERROR, 885 "stellaris_adc: write at bad offset 0x%x\n", (int)offset); 886 } 887 stellaris_adc_update(s); 888 } 889 890 static const MemoryRegionOps stellaris_adc_ops = { 891 .read = stellaris_adc_read, 892 .write = stellaris_adc_write, 893 .endianness = DEVICE_NATIVE_ENDIAN, 894 }; 895 896 static const VMStateDescription vmstate_stellaris_adc = { 897 .name = "stellaris_adc", 898 .version_id = 1, 899 .minimum_version_id = 1, 900 .fields = (VMStateField[]) { 901 VMSTATE_UINT32(actss, stellaris_adc_state), 902 VMSTATE_UINT32(ris, stellaris_adc_state), 903 VMSTATE_UINT32(im, stellaris_adc_state), 904 VMSTATE_UINT32(emux, stellaris_adc_state), 905 VMSTATE_UINT32(ostat, stellaris_adc_state), 906 VMSTATE_UINT32(ustat, stellaris_adc_state), 907 VMSTATE_UINT32(sspri, stellaris_adc_state), 908 VMSTATE_UINT32(sac, stellaris_adc_state), 909 VMSTATE_UINT32(fifo[0].state, stellaris_adc_state), 910 VMSTATE_UINT32_ARRAY(fifo[0].data, stellaris_adc_state, 16), 911 VMSTATE_UINT32(ssmux[0], stellaris_adc_state), 912 VMSTATE_UINT32(ssctl[0], stellaris_adc_state), 913 VMSTATE_UINT32(fifo[1].state, stellaris_adc_state), 914 VMSTATE_UINT32_ARRAY(fifo[1].data, stellaris_adc_state, 16), 915 VMSTATE_UINT32(ssmux[1], stellaris_adc_state), 916 VMSTATE_UINT32(ssctl[1], stellaris_adc_state), 917 VMSTATE_UINT32(fifo[2].state, stellaris_adc_state), 918 VMSTATE_UINT32_ARRAY(fifo[2].data, stellaris_adc_state, 16), 919 VMSTATE_UINT32(ssmux[2], stellaris_adc_state), 920 VMSTATE_UINT32(ssctl[2], stellaris_adc_state), 921 VMSTATE_UINT32(fifo[3].state, stellaris_adc_state), 922 VMSTATE_UINT32_ARRAY(fifo[3].data, stellaris_adc_state, 16), 923 VMSTATE_UINT32(ssmux[3], stellaris_adc_state), 924 VMSTATE_UINT32(ssctl[3], stellaris_adc_state), 925 VMSTATE_UINT32(noise, stellaris_adc_state), 926 VMSTATE_END_OF_LIST() 927 } 928 }; 929 930 static void stellaris_adc_init(Object *obj) 931 { 932 DeviceState *dev = DEVICE(obj); 933 stellaris_adc_state *s = STELLARIS_ADC(obj); 934 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 935 int n; 936 937 for (n = 0; n < 4; n++) { 938 sysbus_init_irq(sbd, &s->irq[n]); 939 } 940 941 memory_region_init_io(&s->iomem, obj, &stellaris_adc_ops, s, 942 "adc", 0x1000); 943 sysbus_init_mmio(sbd, &s->iomem); 944 stellaris_adc_reset(s); 945 qdev_init_gpio_in(dev, stellaris_adc_trigger, 1); 946 } 947 948 /* Board init. */ 949 static stellaris_board_info stellaris_boards[] = { 950 { "LM3S811EVB", 951 0, 952 0x0032000e, 953 0x001f001f, /* dc0 */ 954 0x001132bf, 955 0x01071013, 956 0x3f0f01ff, 957 0x0000001f, 958 BP_OLED_I2C 959 }, 960 { "LM3S6965EVB", 961 0x10010002, 962 0x1073402e, 963 0x00ff007f, /* dc0 */ 964 0x001133ff, 965 0x030f5317, 966 0x0f0f87ff, 967 0x5000007f, 968 BP_OLED_SSI | BP_GAMEPAD 969 } 970 }; 971 972 static void stellaris_init(MachineState *ms, stellaris_board_info *board) 973 { 974 static const int uart_irq[] = {5, 6, 33, 34}; 975 static const int timer_irq[] = {19, 21, 23, 35}; 976 static const uint32_t gpio_addr[7] = 977 { 0x40004000, 0x40005000, 0x40006000, 0x40007000, 978 0x40024000, 0x40025000, 0x40026000}; 979 static const int gpio_irq[7] = {0, 1, 2, 3, 4, 30, 31}; 980 981 /* Memory map of SoC devices, from 982 * Stellaris LM3S6965 Microcontroller Data Sheet (rev I) 983 * http://www.ti.com/lit/ds/symlink/lm3s6965.pdf 984 * 985 * 40000000 wdtimer 986 * 40002000 i2c (unimplemented) 987 * 40004000 GPIO 988 * 40005000 GPIO 989 * 40006000 GPIO 990 * 40007000 GPIO 991 * 40008000 SSI 992 * 4000c000 UART 993 * 4000d000 UART 994 * 4000e000 UART 995 * 40020000 i2c 996 * 40021000 i2c (unimplemented) 997 * 40024000 GPIO 998 * 40025000 GPIO 999 * 40026000 GPIO 1000 * 40028000 PWM (unimplemented) 1001 * 4002c000 QEI (unimplemented) 1002 * 4002d000 QEI (unimplemented) 1003 * 40030000 gptimer 1004 * 40031000 gptimer 1005 * 40032000 gptimer 1006 * 40033000 gptimer 1007 * 40038000 ADC 1008 * 4003c000 analogue comparator (unimplemented) 1009 * 40048000 ethernet 1010 * 400fc000 hibernation module (unimplemented) 1011 * 400fd000 flash memory control (unimplemented) 1012 * 400fe000 system control 1013 */ 1014 1015 DeviceState *gpio_dev[7], *nvic; 1016 qemu_irq gpio_in[7][8]; 1017 qemu_irq gpio_out[7][8]; 1018 qemu_irq adc; 1019 int sram_size; 1020 int flash_size; 1021 I2CBus *i2c; 1022 DeviceState *dev; 1023 DeviceState *ssys_dev; 1024 int i; 1025 int j; 1026 const uint8_t *macaddr; 1027 1028 MemoryRegion *sram = g_new(MemoryRegion, 1); 1029 MemoryRegion *flash = g_new(MemoryRegion, 1); 1030 MemoryRegion *system_memory = get_system_memory(); 1031 1032 flash_size = (((board->dc0 & 0xffff) + 1) << 1) * 1024; 1033 sram_size = ((board->dc0 >> 18) + 1) * 1024; 1034 1035 /* Flash programming is done via the SCU, so pretend it is ROM. */ 1036 memory_region_init_rom(flash, NULL, "stellaris.flash", flash_size, 1037 &error_fatal); 1038 memory_region_add_subregion(system_memory, 0, flash); 1039 1040 memory_region_init_ram(sram, NULL, "stellaris.sram", sram_size, 1041 &error_fatal); 1042 memory_region_add_subregion(system_memory, 0x20000000, sram); 1043 1044 /* 1045 * Create the system-registers object early, because we will 1046 * need its sysclk output. 1047 */ 1048 ssys_dev = qdev_new(TYPE_STELLARIS_SYS); 1049 /* Most devices come preprogrammed with a MAC address in the user data. */ 1050 macaddr = nd_table[0].macaddr.a; 1051 qdev_prop_set_uint32(ssys_dev, "user0", 1052 macaddr[0] | (macaddr[1] << 8) | (macaddr[2] << 16)); 1053 qdev_prop_set_uint32(ssys_dev, "user1", 1054 macaddr[3] | (macaddr[4] << 8) | (macaddr[5] << 16)); 1055 qdev_prop_set_uint32(ssys_dev, "did0", board->did0); 1056 qdev_prop_set_uint32(ssys_dev, "did1", board->did1); 1057 qdev_prop_set_uint32(ssys_dev, "dc0", board->dc0); 1058 qdev_prop_set_uint32(ssys_dev, "dc1", board->dc1); 1059 qdev_prop_set_uint32(ssys_dev, "dc2", board->dc2); 1060 qdev_prop_set_uint32(ssys_dev, "dc3", board->dc3); 1061 qdev_prop_set_uint32(ssys_dev, "dc4", board->dc4); 1062 sysbus_realize_and_unref(SYS_BUS_DEVICE(ssys_dev), &error_fatal); 1063 1064 nvic = qdev_new(TYPE_ARMV7M); 1065 qdev_prop_set_uint32(nvic, "num-irq", NUM_IRQ_LINES); 1066 qdev_prop_set_string(nvic, "cpu-type", ms->cpu_type); 1067 qdev_prop_set_bit(nvic, "enable-bitband", true); 1068 qdev_connect_clock_in(nvic, "cpuclk", 1069 qdev_get_clock_out(ssys_dev, "SYSCLK")); 1070 /* This SoC does not connect the systick reference clock */ 1071 object_property_set_link(OBJECT(nvic), "memory", 1072 OBJECT(get_system_memory()), &error_abort); 1073 /* This will exit with an error if the user passed us a bad cpu_type */ 1074 sysbus_realize_and_unref(SYS_BUS_DEVICE(nvic), &error_fatal); 1075 1076 /* Now we can wire up the IRQ and MMIO of the system registers */ 1077 sysbus_mmio_map(SYS_BUS_DEVICE(ssys_dev), 0, 0x400fe000); 1078 sysbus_connect_irq(SYS_BUS_DEVICE(ssys_dev), 0, qdev_get_gpio_in(nvic, 28)); 1079 1080 if (board->dc1 & (1 << 16)) { 1081 dev = sysbus_create_varargs(TYPE_STELLARIS_ADC, 0x40038000, 1082 qdev_get_gpio_in(nvic, 14), 1083 qdev_get_gpio_in(nvic, 15), 1084 qdev_get_gpio_in(nvic, 16), 1085 qdev_get_gpio_in(nvic, 17), 1086 NULL); 1087 adc = qdev_get_gpio_in(dev, 0); 1088 } else { 1089 adc = NULL; 1090 } 1091 for (i = 0; i < 4; i++) { 1092 if (board->dc2 & (0x10000 << i)) { 1093 dev = sysbus_create_simple(TYPE_STELLARIS_GPTM, 1094 0x40030000 + i * 0x1000, 1095 qdev_get_gpio_in(nvic, timer_irq[i])); 1096 /* TODO: This is incorrect, but we get away with it because 1097 the ADC output is only ever pulsed. */ 1098 qdev_connect_gpio_out(dev, 0, adc); 1099 } 1100 } 1101 1102 if (board->dc1 & (1 << 3)) { /* watchdog present */ 1103 dev = qdev_new(TYPE_LUMINARY_WATCHDOG); 1104 1105 qdev_connect_clock_in(dev, "WDOGCLK", 1106 qdev_get_clock_out(ssys_dev, "SYSCLK")); 1107 1108 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1109 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1110 0, 1111 0x40000000u); 1112 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1113 0, 1114 qdev_get_gpio_in(nvic, 18)); 1115 } 1116 1117 1118 for (i = 0; i < 7; i++) { 1119 if (board->dc4 & (1 << i)) { 1120 gpio_dev[i] = sysbus_create_simple("pl061_luminary", gpio_addr[i], 1121 qdev_get_gpio_in(nvic, 1122 gpio_irq[i])); 1123 for (j = 0; j < 8; j++) { 1124 gpio_in[i][j] = qdev_get_gpio_in(gpio_dev[i], j); 1125 gpio_out[i][j] = NULL; 1126 } 1127 } 1128 } 1129 1130 if (board->dc2 & (1 << 12)) { 1131 dev = sysbus_create_simple(TYPE_STELLARIS_I2C, 0x40020000, 1132 qdev_get_gpio_in(nvic, 8)); 1133 i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c"); 1134 if (board->peripherals & BP_OLED_I2C) { 1135 i2c_slave_create_simple(i2c, "ssd0303", 0x3d); 1136 } 1137 } 1138 1139 for (i = 0; i < 4; i++) { 1140 if (board->dc2 & (1 << i)) { 1141 pl011_luminary_create(0x4000c000 + i * 0x1000, 1142 qdev_get_gpio_in(nvic, uart_irq[i]), 1143 serial_hd(i)); 1144 } 1145 } 1146 if (board->dc2 & (1 << 4)) { 1147 dev = sysbus_create_simple("pl022", 0x40008000, 1148 qdev_get_gpio_in(nvic, 7)); 1149 if (board->peripherals & BP_OLED_SSI) { 1150 void *bus; 1151 DeviceState *sddev; 1152 DeviceState *ssddev; 1153 1154 /* 1155 * Some boards have both an OLED controller and SD card connected to 1156 * the same SSI port, with the SD card chip select connected to a 1157 * GPIO pin. Technically the OLED chip select is connected to the 1158 * SSI Fss pin. We do not bother emulating that as both devices 1159 * should never be selected simultaneously, and our OLED controller 1160 * ignores stray 0xff commands that occur when deselecting the SD 1161 * card. 1162 * 1163 * The h/w wiring is: 1164 * - GPIO pin D0 is wired to the active-low SD card chip select 1165 * - GPIO pin A3 is wired to the active-low OLED chip select 1166 * - The SoC wiring of the PL061 "auxiliary function" for A3 is 1167 * SSI0Fss ("frame signal"), which is an output from the SoC's 1168 * SSI controller. The SSI controller takes SSI0Fss low when it 1169 * transmits a frame, so it can work as a chip-select signal. 1170 * - GPIO A4 is aux-function SSI0Rx, and wired to the SD card Tx 1171 * (the OLED never sends data to the CPU, so no wiring needed) 1172 * - GPIO A5 is aux-function SSI0Tx, and wired to the SD card Rx 1173 * and the OLED display-data-in 1174 * - GPIO A2 is aux-function SSI0Clk, wired to SD card and OLED 1175 * serial-clock input 1176 * So a guest that wants to use the OLED can configure the PL061 1177 * to make pins A2, A3, A5 aux-function, so they are connected 1178 * directly to the SSI controller. When the SSI controller sends 1179 * data it asserts SSI0Fss which selects the OLED. 1180 * A guest that wants to use the SD card configures A2, A4 and A5 1181 * as aux-function, but leaves A3 as a software-controlled GPIO 1182 * line. It asserts the SD card chip-select by using the PL061 1183 * to control pin D0, and lets the SSI controller handle Clk, Tx 1184 * and Rx. (The SSI controller asserts Fss during tx cycles as 1185 * usual, but because A3 is not set to aux-function this is not 1186 * forwarded to the OLED, and so the OLED stays unselected.) 1187 * 1188 * The QEMU implementation instead is: 1189 * - GPIO pin D0 is wired to the active-low SD card chip select, 1190 * and also to the OLED chip-select which is implemented 1191 * as *active-high* 1192 * - SSI controller signals go to the devices regardless of 1193 * whether the guest programs A2, A4, A5 as aux-function or not 1194 * 1195 * The problem with this implementation is if the guest doesn't 1196 * care about the SD card and only uses the OLED. In that case it 1197 * may choose never to do anything with D0 (leaving it in its 1198 * default floating state, which reliably leaves the card disabled 1199 * because an SD card has a pullup on CS within the card itself), 1200 * and only set up A2, A3, A5. This for us would mean the OLED 1201 * never gets the chip-select assert it needs. We work around 1202 * this with a manual raise of D0 here (despite board creation 1203 * code being the wrong place to raise IRQ lines) to put the OLED 1204 * into an initially selected state. 1205 * 1206 * In theory the right way to model this would be: 1207 * - Implement aux-function support in the PL061, with an 1208 * extra set of AFIN and AFOUT GPIO lines (set up so that 1209 * if a GPIO line is in auxfn mode the main GPIO in and out 1210 * track the AFIN and AFOUT lines) 1211 * - Wire the AFOUT for D0 up to either a line from the 1212 * SSI controller that's pulled low around every transmit, 1213 * or at least to an always-0 line here on the board 1214 * - Make the ssd0323 OLED controller chipselect active-low 1215 */ 1216 bus = qdev_get_child_bus(dev, "ssi"); 1217 1218 sddev = ssi_create_peripheral(bus, "ssi-sd"); 1219 ssddev = ssi_create_peripheral(bus, "ssd0323"); 1220 gpio_out[GPIO_D][0] = qemu_irq_split( 1221 qdev_get_gpio_in_named(sddev, SSI_GPIO_CS, 0), 1222 qdev_get_gpio_in_named(ssddev, SSI_GPIO_CS, 0)); 1223 gpio_out[GPIO_C][7] = qdev_get_gpio_in(ssddev, 0); 1224 1225 /* Make sure the select pin is high. */ 1226 qemu_irq_raise(gpio_out[GPIO_D][0]); 1227 } 1228 } 1229 if (board->dc4 & (1 << 28)) { 1230 DeviceState *enet; 1231 1232 qemu_check_nic_model(&nd_table[0], "stellaris"); 1233 1234 enet = qdev_new("stellaris_enet"); 1235 qdev_set_nic_properties(enet, &nd_table[0]); 1236 sysbus_realize_and_unref(SYS_BUS_DEVICE(enet), &error_fatal); 1237 sysbus_mmio_map(SYS_BUS_DEVICE(enet), 0, 0x40048000); 1238 sysbus_connect_irq(SYS_BUS_DEVICE(enet), 0, qdev_get_gpio_in(nvic, 42)); 1239 } 1240 if (board->peripherals & BP_GAMEPAD) { 1241 qemu_irq gpad_irq[5]; 1242 static const int gpad_keycode[5] = { 0xc8, 0xd0, 0xcb, 0xcd, 0x1d }; 1243 1244 gpad_irq[0] = qemu_irq_invert(gpio_in[GPIO_E][0]); /* up */ 1245 gpad_irq[1] = qemu_irq_invert(gpio_in[GPIO_E][1]); /* down */ 1246 gpad_irq[2] = qemu_irq_invert(gpio_in[GPIO_E][2]); /* left */ 1247 gpad_irq[3] = qemu_irq_invert(gpio_in[GPIO_E][3]); /* right */ 1248 gpad_irq[4] = qemu_irq_invert(gpio_in[GPIO_F][1]); /* select */ 1249 1250 stellaris_gamepad_init(5, gpad_irq, gpad_keycode); 1251 } 1252 for (i = 0; i < 7; i++) { 1253 if (board->dc4 & (1 << i)) { 1254 for (j = 0; j < 8; j++) { 1255 if (gpio_out[i][j]) { 1256 qdev_connect_gpio_out(gpio_dev[i], j, gpio_out[i][j]); 1257 } 1258 } 1259 } 1260 } 1261 1262 /* Add dummy regions for the devices we don't implement yet, 1263 * so guest accesses don't cause unlogged crashes. 1264 */ 1265 create_unimplemented_device("i2c-0", 0x40002000, 0x1000); 1266 create_unimplemented_device("i2c-2", 0x40021000, 0x1000); 1267 create_unimplemented_device("PWM", 0x40028000, 0x1000); 1268 create_unimplemented_device("QEI-0", 0x4002c000, 0x1000); 1269 create_unimplemented_device("QEI-1", 0x4002d000, 0x1000); 1270 create_unimplemented_device("analogue-comparator", 0x4003c000, 0x1000); 1271 create_unimplemented_device("hibernation", 0x400fc000, 0x1000); 1272 create_unimplemented_device("flash-control", 0x400fd000, 0x1000); 1273 1274 armv7m_load_kernel(ARM_CPU(first_cpu), ms->kernel_filename, flash_size); 1275 } 1276 1277 /* FIXME: Figure out how to generate these from stellaris_boards. */ 1278 static void lm3s811evb_init(MachineState *machine) 1279 { 1280 stellaris_init(machine, &stellaris_boards[0]); 1281 } 1282 1283 static void lm3s6965evb_init(MachineState *machine) 1284 { 1285 stellaris_init(machine, &stellaris_boards[1]); 1286 } 1287 1288 static void lm3s811evb_class_init(ObjectClass *oc, void *data) 1289 { 1290 MachineClass *mc = MACHINE_CLASS(oc); 1291 1292 mc->desc = "Stellaris LM3S811EVB (Cortex-M3)"; 1293 mc->init = lm3s811evb_init; 1294 mc->ignore_memory_transaction_failures = true; 1295 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3"); 1296 } 1297 1298 static const TypeInfo lm3s811evb_type = { 1299 .name = MACHINE_TYPE_NAME("lm3s811evb"), 1300 .parent = TYPE_MACHINE, 1301 .class_init = lm3s811evb_class_init, 1302 }; 1303 1304 static void lm3s6965evb_class_init(ObjectClass *oc, void *data) 1305 { 1306 MachineClass *mc = MACHINE_CLASS(oc); 1307 1308 mc->desc = "Stellaris LM3S6965EVB (Cortex-M3)"; 1309 mc->init = lm3s6965evb_init; 1310 mc->ignore_memory_transaction_failures = true; 1311 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3"); 1312 } 1313 1314 static const TypeInfo lm3s6965evb_type = { 1315 .name = MACHINE_TYPE_NAME("lm3s6965evb"), 1316 .parent = TYPE_MACHINE, 1317 .class_init = lm3s6965evb_class_init, 1318 }; 1319 1320 static void stellaris_machine_init(void) 1321 { 1322 type_register_static(&lm3s811evb_type); 1323 type_register_static(&lm3s6965evb_type); 1324 } 1325 1326 type_init(stellaris_machine_init) 1327 1328 static void stellaris_i2c_class_init(ObjectClass *klass, void *data) 1329 { 1330 DeviceClass *dc = DEVICE_CLASS(klass); 1331 1332 dc->vmsd = &vmstate_stellaris_i2c; 1333 } 1334 1335 static const TypeInfo stellaris_i2c_info = { 1336 .name = TYPE_STELLARIS_I2C, 1337 .parent = TYPE_SYS_BUS_DEVICE, 1338 .instance_size = sizeof(stellaris_i2c_state), 1339 .instance_init = stellaris_i2c_init, 1340 .class_init = stellaris_i2c_class_init, 1341 }; 1342 1343 static void stellaris_adc_class_init(ObjectClass *klass, void *data) 1344 { 1345 DeviceClass *dc = DEVICE_CLASS(klass); 1346 1347 dc->vmsd = &vmstate_stellaris_adc; 1348 } 1349 1350 static const TypeInfo stellaris_adc_info = { 1351 .name = TYPE_STELLARIS_ADC, 1352 .parent = TYPE_SYS_BUS_DEVICE, 1353 .instance_size = sizeof(stellaris_adc_state), 1354 .instance_init = stellaris_adc_init, 1355 .class_init = stellaris_adc_class_init, 1356 }; 1357 1358 static void stellaris_sys_class_init(ObjectClass *klass, void *data) 1359 { 1360 DeviceClass *dc = DEVICE_CLASS(klass); 1361 ResettableClass *rc = RESETTABLE_CLASS(klass); 1362 1363 dc->vmsd = &vmstate_stellaris_sys; 1364 rc->phases.enter = stellaris_sys_reset_enter; 1365 rc->phases.hold = stellaris_sys_reset_hold; 1366 rc->phases.exit = stellaris_sys_reset_exit; 1367 device_class_set_props(dc, stellaris_sys_properties); 1368 } 1369 1370 static const TypeInfo stellaris_sys_info = { 1371 .name = TYPE_STELLARIS_SYS, 1372 .parent = TYPE_SYS_BUS_DEVICE, 1373 .instance_size = sizeof(ssys_state), 1374 .instance_init = stellaris_sys_instance_init, 1375 .class_init = stellaris_sys_class_init, 1376 }; 1377 1378 static void stellaris_register_types(void) 1379 { 1380 type_register_static(&stellaris_i2c_info); 1381 type_register_static(&stellaris_adc_info); 1382 type_register_static(&stellaris_sys_info); 1383 } 1384 1385 type_init(stellaris_register_types) 1386