1 /* 2 * Luminary Micro Stellaris peripherals 3 * 4 * Copyright (c) 2006 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qapi/error.h" 12 #include "hw/core/split-irq.h" 13 #include "hw/sysbus.h" 14 #include "hw/sd/sd.h" 15 #include "hw/ssi/ssi.h" 16 #include "hw/arm/boot.h" 17 #include "qemu/timer.h" 18 #include "hw/i2c/i2c.h" 19 #include "net/net.h" 20 #include "hw/boards.h" 21 #include "qemu/log.h" 22 #include "exec/address-spaces.h" 23 #include "system/system.h" 24 #include "hw/arm/armv7m.h" 25 #include "hw/char/pl011.h" 26 #include "hw/input/stellaris_gamepad.h" 27 #include "hw/irq.h" 28 #include "hw/watchdog/cmsdk-apb-watchdog.h" 29 #include "migration/vmstate.h" 30 #include "hw/misc/unimp.h" 31 #include "hw/timer/stellaris-gptm.h" 32 #include "hw/qdev-clock.h" 33 #include "qom/object.h" 34 #include "qapi/qmp/qlist.h" 35 #include "ui/input.h" 36 37 #define GPIO_A 0 38 #define GPIO_B 1 39 #define GPIO_C 2 40 #define GPIO_D 3 41 #define GPIO_E 4 42 #define GPIO_F 5 43 #define GPIO_G 6 44 45 #define BP_OLED_I2C 0x01 46 #define BP_OLED_SSI 0x02 47 #define BP_GAMEPAD 0x04 48 49 #define NUM_IRQ_LINES 64 50 #define NUM_PRIO_BITS 3 51 52 typedef const struct { 53 const char *name; 54 uint32_t did0; 55 uint32_t did1; 56 uint32_t dc0; 57 uint32_t dc1; 58 uint32_t dc2; 59 uint32_t dc3; 60 uint32_t dc4; 61 uint32_t peripherals; 62 } stellaris_board_info; 63 64 /* System controller. */ 65 66 #define TYPE_STELLARIS_SYS "stellaris-sys" 67 OBJECT_DECLARE_SIMPLE_TYPE(ssys_state, STELLARIS_SYS) 68 69 struct ssys_state { 70 SysBusDevice parent_obj; 71 72 MemoryRegion iomem; 73 uint32_t pborctl; 74 uint32_t ldopctl; 75 uint32_t int_status; 76 uint32_t int_mask; 77 uint32_t resc; 78 uint32_t rcc; 79 uint32_t rcc2; 80 uint32_t rcgc[3]; 81 uint32_t scgc[3]; 82 uint32_t dcgc[3]; 83 uint32_t clkvclr; 84 uint32_t ldoarst; 85 qemu_irq irq; 86 Clock *sysclk; 87 /* Properties (all read-only registers) */ 88 uint32_t user0; 89 uint32_t user1; 90 uint32_t did0; 91 uint32_t did1; 92 uint32_t dc0; 93 uint32_t dc1; 94 uint32_t dc2; 95 uint32_t dc3; 96 uint32_t dc4; 97 }; 98 99 static void ssys_update(ssys_state *s) 100 { 101 qemu_set_irq(s->irq, (s->int_status & s->int_mask) != 0); 102 } 103 104 static uint32_t pllcfg_sandstorm[16] = { 105 0x31c0, /* 1 Mhz */ 106 0x1ae0, /* 1.8432 Mhz */ 107 0x18c0, /* 2 Mhz */ 108 0xd573, /* 2.4576 Mhz */ 109 0x37a6, /* 3.57954 Mhz */ 110 0x1ae2, /* 3.6864 Mhz */ 111 0x0c40, /* 4 Mhz */ 112 0x98bc, /* 4.906 Mhz */ 113 0x935b, /* 4.9152 Mhz */ 114 0x09c0, /* 5 Mhz */ 115 0x4dee, /* 5.12 Mhz */ 116 0x0c41, /* 6 Mhz */ 117 0x75db, /* 6.144 Mhz */ 118 0x1ae6, /* 7.3728 Mhz */ 119 0x0600, /* 8 Mhz */ 120 0x585b /* 8.192 Mhz */ 121 }; 122 123 static uint32_t pllcfg_fury[16] = { 124 0x3200, /* 1 Mhz */ 125 0x1b20, /* 1.8432 Mhz */ 126 0x1900, /* 2 Mhz */ 127 0xf42b, /* 2.4576 Mhz */ 128 0x37e3, /* 3.57954 Mhz */ 129 0x1b21, /* 3.6864 Mhz */ 130 0x0c80, /* 4 Mhz */ 131 0x98ee, /* 4.906 Mhz */ 132 0xd5b4, /* 4.9152 Mhz */ 133 0x0a00, /* 5 Mhz */ 134 0x4e27, /* 5.12 Mhz */ 135 0x1902, /* 6 Mhz */ 136 0xec1c, /* 6.144 Mhz */ 137 0x1b23, /* 7.3728 Mhz */ 138 0x0640, /* 8 Mhz */ 139 0xb11c /* 8.192 Mhz */ 140 }; 141 142 #define DID0_VER_MASK 0x70000000 143 #define DID0_VER_0 0x00000000 144 #define DID0_VER_1 0x10000000 145 146 #define DID0_CLASS_MASK 0x00FF0000 147 #define DID0_CLASS_SANDSTORM 0x00000000 148 #define DID0_CLASS_FURY 0x00010000 149 150 static int ssys_board_class(const ssys_state *s) 151 { 152 uint32_t did0 = s->did0; 153 switch (did0 & DID0_VER_MASK) { 154 case DID0_VER_0: 155 return DID0_CLASS_SANDSTORM; 156 case DID0_VER_1: 157 switch (did0 & DID0_CLASS_MASK) { 158 case DID0_CLASS_SANDSTORM: 159 case DID0_CLASS_FURY: 160 return did0 & DID0_CLASS_MASK; 161 } 162 /* for unknown classes, fall through */ 163 default: 164 /* This can only happen if the hardwired constant did0 value 165 * in this board's stellaris_board_info struct is wrong. 166 */ 167 g_assert_not_reached(); 168 } 169 } 170 171 static uint64_t ssys_read(void *opaque, hwaddr offset, 172 unsigned size) 173 { 174 ssys_state *s = (ssys_state *)opaque; 175 176 switch (offset) { 177 case 0x000: /* DID0 */ 178 return s->did0; 179 case 0x004: /* DID1 */ 180 return s->did1; 181 case 0x008: /* DC0 */ 182 return s->dc0; 183 case 0x010: /* DC1 */ 184 return s->dc1; 185 case 0x014: /* DC2 */ 186 return s->dc2; 187 case 0x018: /* DC3 */ 188 return s->dc3; 189 case 0x01c: /* DC4 */ 190 return s->dc4; 191 case 0x030: /* PBORCTL */ 192 return s->pborctl; 193 case 0x034: /* LDOPCTL */ 194 return s->ldopctl; 195 case 0x040: /* SRCR0 */ 196 return 0; 197 case 0x044: /* SRCR1 */ 198 return 0; 199 case 0x048: /* SRCR2 */ 200 return 0; 201 case 0x050: /* RIS */ 202 return s->int_status; 203 case 0x054: /* IMC */ 204 return s->int_mask; 205 case 0x058: /* MISC */ 206 return s->int_status & s->int_mask; 207 case 0x05c: /* RESC */ 208 return s->resc; 209 case 0x060: /* RCC */ 210 return s->rcc; 211 case 0x064: /* PLLCFG */ 212 { 213 int xtal; 214 xtal = (s->rcc >> 6) & 0xf; 215 switch (ssys_board_class(s)) { 216 case DID0_CLASS_FURY: 217 return pllcfg_fury[xtal]; 218 case DID0_CLASS_SANDSTORM: 219 return pllcfg_sandstorm[xtal]; 220 default: 221 g_assert_not_reached(); 222 } 223 } 224 case 0x070: /* RCC2 */ 225 return s->rcc2; 226 case 0x100: /* RCGC0 */ 227 return s->rcgc[0]; 228 case 0x104: /* RCGC1 */ 229 return s->rcgc[1]; 230 case 0x108: /* RCGC2 */ 231 return s->rcgc[2]; 232 case 0x110: /* SCGC0 */ 233 return s->scgc[0]; 234 case 0x114: /* SCGC1 */ 235 return s->scgc[1]; 236 case 0x118: /* SCGC2 */ 237 return s->scgc[2]; 238 case 0x120: /* DCGC0 */ 239 return s->dcgc[0]; 240 case 0x124: /* DCGC1 */ 241 return s->dcgc[1]; 242 case 0x128: /* DCGC2 */ 243 return s->dcgc[2]; 244 case 0x150: /* CLKVCLR */ 245 return s->clkvclr; 246 case 0x160: /* LDOARST */ 247 return s->ldoarst; 248 case 0x1e0: /* USER0 */ 249 return s->user0; 250 case 0x1e4: /* USER1 */ 251 return s->user1; 252 default: 253 qemu_log_mask(LOG_GUEST_ERROR, 254 "SSYS: read at bad offset 0x%x\n", (int)offset); 255 return 0; 256 } 257 } 258 259 static bool ssys_use_rcc2(ssys_state *s) 260 { 261 return (s->rcc2 >> 31) & 0x1; 262 } 263 264 /* 265 * Calculate the system clock period. We only want to propagate 266 * this change to the rest of the system if we're not being called 267 * from migration post-load. 268 */ 269 static void ssys_calculate_system_clock(ssys_state *s, bool propagate_clock) 270 { 271 int period_ns; 272 /* 273 * SYSDIV field specifies divisor: 0 == /1, 1 == /2, etc. Input 274 * clock is 200MHz, which is a period of 5 ns. Dividing the clock 275 * frequency by X is the same as multiplying the period by X. 276 */ 277 if (ssys_use_rcc2(s)) { 278 period_ns = 5 * (((s->rcc2 >> 23) & 0x3f) + 1); 279 } else { 280 period_ns = 5 * (((s->rcc >> 23) & 0xf) + 1); 281 } 282 clock_set_ns(s->sysclk, period_ns); 283 if (propagate_clock) { 284 clock_propagate(s->sysclk); 285 } 286 } 287 288 static void ssys_write(void *opaque, hwaddr offset, 289 uint64_t value, unsigned size) 290 { 291 ssys_state *s = (ssys_state *)opaque; 292 293 switch (offset) { 294 case 0x030: /* PBORCTL */ 295 s->pborctl = value & 0xffff; 296 break; 297 case 0x034: /* LDOPCTL */ 298 s->ldopctl = value & 0x1f; 299 break; 300 case 0x040: /* SRCR0 */ 301 case 0x044: /* SRCR1 */ 302 case 0x048: /* SRCR2 */ 303 qemu_log_mask(LOG_UNIMP, "Peripheral reset not implemented\n"); 304 break; 305 case 0x054: /* IMC */ 306 s->int_mask = value & 0x7f; 307 break; 308 case 0x058: /* MISC */ 309 s->int_status &= ~value; 310 break; 311 case 0x05c: /* RESC */ 312 s->resc = value & 0x3f; 313 break; 314 case 0x060: /* RCC */ 315 if ((s->rcc & (1 << 13)) != 0 && (value & (1 << 13)) == 0) { 316 /* PLL enable. */ 317 s->int_status |= (1 << 6); 318 } 319 s->rcc = value; 320 ssys_calculate_system_clock(s, true); 321 break; 322 case 0x070: /* RCC2 */ 323 if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) { 324 break; 325 } 326 327 if ((s->rcc2 & (1 << 13)) != 0 && (value & (1 << 13)) == 0) { 328 /* PLL enable. */ 329 s->int_status |= (1 << 6); 330 } 331 s->rcc2 = value; 332 ssys_calculate_system_clock(s, true); 333 break; 334 case 0x100: /* RCGC0 */ 335 s->rcgc[0] = value; 336 break; 337 case 0x104: /* RCGC1 */ 338 s->rcgc[1] = value; 339 break; 340 case 0x108: /* RCGC2 */ 341 s->rcgc[2] = value; 342 break; 343 case 0x110: /* SCGC0 */ 344 s->scgc[0] = value; 345 break; 346 case 0x114: /* SCGC1 */ 347 s->scgc[1] = value; 348 break; 349 case 0x118: /* SCGC2 */ 350 s->scgc[2] = value; 351 break; 352 case 0x120: /* DCGC0 */ 353 s->dcgc[0] = value; 354 break; 355 case 0x124: /* DCGC1 */ 356 s->dcgc[1] = value; 357 break; 358 case 0x128: /* DCGC2 */ 359 s->dcgc[2] = value; 360 break; 361 case 0x150: /* CLKVCLR */ 362 s->clkvclr = value; 363 break; 364 case 0x160: /* LDOARST */ 365 s->ldoarst = value; 366 break; 367 default: 368 qemu_log_mask(LOG_GUEST_ERROR, 369 "SSYS: write at bad offset 0x%x\n", (int)offset); 370 } 371 ssys_update(s); 372 } 373 374 static const MemoryRegionOps ssys_ops = { 375 .read = ssys_read, 376 .write = ssys_write, 377 .endianness = DEVICE_NATIVE_ENDIAN, 378 }; 379 380 static void stellaris_sys_reset_enter(Object *obj, ResetType type) 381 { 382 ssys_state *s = STELLARIS_SYS(obj); 383 384 s->pborctl = 0x7ffd; 385 s->rcc = 0x078e3ac0; 386 387 if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) { 388 s->rcc2 = 0; 389 } else { 390 s->rcc2 = 0x07802810; 391 } 392 s->rcgc[0] = 1; 393 s->scgc[0] = 1; 394 s->dcgc[0] = 1; 395 } 396 397 static void stellaris_sys_reset_hold(Object *obj, ResetType type) 398 { 399 ssys_state *s = STELLARIS_SYS(obj); 400 401 /* OK to propagate clocks from the hold phase */ 402 ssys_calculate_system_clock(s, true); 403 } 404 405 static void stellaris_sys_reset_exit(Object *obj, ResetType type) 406 { 407 } 408 409 static int stellaris_sys_post_load(void *opaque, int version_id) 410 { 411 ssys_state *s = opaque; 412 413 ssys_calculate_system_clock(s, false); 414 415 return 0; 416 } 417 418 static const VMStateDescription vmstate_stellaris_sys = { 419 .name = "stellaris_sys", 420 .version_id = 2, 421 .minimum_version_id = 1, 422 .post_load = stellaris_sys_post_load, 423 .fields = (const VMStateField[]) { 424 VMSTATE_UINT32(pborctl, ssys_state), 425 VMSTATE_UINT32(ldopctl, ssys_state), 426 VMSTATE_UINT32(int_mask, ssys_state), 427 VMSTATE_UINT32(int_status, ssys_state), 428 VMSTATE_UINT32(resc, ssys_state), 429 VMSTATE_UINT32(rcc, ssys_state), 430 VMSTATE_UINT32_V(rcc2, ssys_state, 2), 431 VMSTATE_UINT32_ARRAY(rcgc, ssys_state, 3), 432 VMSTATE_UINT32_ARRAY(scgc, ssys_state, 3), 433 VMSTATE_UINT32_ARRAY(dcgc, ssys_state, 3), 434 VMSTATE_UINT32(clkvclr, ssys_state), 435 VMSTATE_UINT32(ldoarst, ssys_state), 436 /* No field for sysclk -- handled in post-load instead */ 437 VMSTATE_END_OF_LIST() 438 } 439 }; 440 441 static const Property stellaris_sys_properties[] = { 442 DEFINE_PROP_UINT32("user0", ssys_state, user0, 0), 443 DEFINE_PROP_UINT32("user1", ssys_state, user1, 0), 444 DEFINE_PROP_UINT32("did0", ssys_state, did0, 0), 445 DEFINE_PROP_UINT32("did1", ssys_state, did1, 0), 446 DEFINE_PROP_UINT32("dc0", ssys_state, dc0, 0), 447 DEFINE_PROP_UINT32("dc1", ssys_state, dc1, 0), 448 DEFINE_PROP_UINT32("dc2", ssys_state, dc2, 0), 449 DEFINE_PROP_UINT32("dc3", ssys_state, dc3, 0), 450 DEFINE_PROP_UINT32("dc4", ssys_state, dc4, 0), 451 }; 452 453 static void stellaris_sys_instance_init(Object *obj) 454 { 455 ssys_state *s = STELLARIS_SYS(obj); 456 SysBusDevice *sbd = SYS_BUS_DEVICE(s); 457 458 memory_region_init_io(&s->iomem, obj, &ssys_ops, s, "ssys", 0x00001000); 459 sysbus_init_mmio(sbd, &s->iomem); 460 sysbus_init_irq(sbd, &s->irq); 461 s->sysclk = qdev_init_clock_out(DEVICE(s), "SYSCLK"); 462 } 463 464 /* 465 * I2C controller. 466 * ??? For now we only implement the master interface. 467 */ 468 469 #define TYPE_STELLARIS_I2C "stellaris-i2c" 470 OBJECT_DECLARE_SIMPLE_TYPE(stellaris_i2c_state, STELLARIS_I2C) 471 472 struct stellaris_i2c_state { 473 SysBusDevice parent_obj; 474 475 I2CBus *bus; 476 qemu_irq irq; 477 MemoryRegion iomem; 478 uint32_t msa; 479 uint32_t mcs; 480 uint32_t mdr; 481 uint32_t mtpr; 482 uint32_t mimr; 483 uint32_t mris; 484 uint32_t mcr; 485 }; 486 487 #define STELLARIS_I2C_MCS_BUSY 0x01 488 #define STELLARIS_I2C_MCS_ERROR 0x02 489 #define STELLARIS_I2C_MCS_ADRACK 0x04 490 #define STELLARIS_I2C_MCS_DATACK 0x08 491 #define STELLARIS_I2C_MCS_ARBLST 0x10 492 #define STELLARIS_I2C_MCS_IDLE 0x20 493 #define STELLARIS_I2C_MCS_BUSBSY 0x40 494 495 static uint64_t stellaris_i2c_read(void *opaque, hwaddr offset, 496 unsigned size) 497 { 498 stellaris_i2c_state *s = (stellaris_i2c_state *)opaque; 499 500 switch (offset) { 501 case 0x00: /* MSA */ 502 return s->msa; 503 case 0x04: /* MCS */ 504 /* We don't emulate timing, so the controller is never busy. */ 505 return s->mcs | STELLARIS_I2C_MCS_IDLE; 506 case 0x08: /* MDR */ 507 return s->mdr; 508 case 0x0c: /* MTPR */ 509 return s->mtpr; 510 case 0x10: /* MIMR */ 511 return s->mimr; 512 case 0x14: /* MRIS */ 513 return s->mris; 514 case 0x18: /* MMIS */ 515 return s->mris & s->mimr; 516 case 0x20: /* MCR */ 517 return s->mcr; 518 default: 519 qemu_log_mask(LOG_GUEST_ERROR, 520 "stellaris_i2c: read at bad offset 0x%x\n", (int)offset); 521 return 0; 522 } 523 } 524 525 static void stellaris_i2c_update(stellaris_i2c_state *s) 526 { 527 int level; 528 529 level = (s->mris & s->mimr) != 0; 530 qemu_set_irq(s->irq, level); 531 } 532 533 static void stellaris_i2c_write(void *opaque, hwaddr offset, 534 uint64_t value, unsigned size) 535 { 536 stellaris_i2c_state *s = (stellaris_i2c_state *)opaque; 537 538 switch (offset) { 539 case 0x00: /* MSA */ 540 s->msa = value & 0xff; 541 break; 542 case 0x04: /* MCS */ 543 if ((s->mcr & 0x10) == 0) { 544 /* Disabled. Do nothing. */ 545 break; 546 } 547 /* Grab the bus if this is starting a transfer. */ 548 if ((value & 2) && (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) { 549 if (i2c_start_transfer(s->bus, s->msa >> 1, s->msa & 1)) { 550 s->mcs |= STELLARIS_I2C_MCS_ARBLST; 551 } else { 552 s->mcs &= ~STELLARIS_I2C_MCS_ARBLST; 553 s->mcs |= STELLARIS_I2C_MCS_BUSBSY; 554 } 555 } 556 /* If we don't have the bus then indicate an error. */ 557 if (!i2c_bus_busy(s->bus) 558 || (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) { 559 s->mcs |= STELLARIS_I2C_MCS_ERROR; 560 break; 561 } 562 s->mcs &= ~STELLARIS_I2C_MCS_ERROR; 563 if (value & 1) { 564 /* Transfer a byte. */ 565 /* TODO: Handle errors. */ 566 if (s->msa & 1) { 567 /* Recv */ 568 s->mdr = i2c_recv(s->bus); 569 } else { 570 /* Send */ 571 i2c_send(s->bus, s->mdr); 572 } 573 /* Raise an interrupt. */ 574 s->mris |= 1; 575 } 576 if (value & 4) { 577 /* Finish transfer. */ 578 i2c_end_transfer(s->bus); 579 s->mcs &= ~STELLARIS_I2C_MCS_BUSBSY; 580 } 581 break; 582 case 0x08: /* MDR */ 583 s->mdr = value & 0xff; 584 break; 585 case 0x0c: /* MTPR */ 586 s->mtpr = value & 0xff; 587 break; 588 case 0x10: /* MIMR */ 589 s->mimr = 1; 590 break; 591 case 0x1c: /* MICR */ 592 s->mris &= ~value; 593 break; 594 case 0x20: /* MCR */ 595 if (value & 1) { 596 qemu_log_mask(LOG_UNIMP, 597 "stellaris_i2c: Loopback not implemented\n"); 598 } 599 if (value & 0x20) { 600 qemu_log_mask(LOG_UNIMP, 601 "stellaris_i2c: Slave mode not implemented\n"); 602 } 603 s->mcr = value & 0x31; 604 break; 605 default: 606 qemu_log_mask(LOG_GUEST_ERROR, 607 "stellaris_i2c: write at bad offset 0x%x\n", (int)offset); 608 } 609 stellaris_i2c_update(s); 610 } 611 612 static void stellaris_i2c_reset_enter(Object *obj, ResetType type) 613 { 614 stellaris_i2c_state *s = STELLARIS_I2C(obj); 615 616 if (s->mcs & STELLARIS_I2C_MCS_BUSBSY) 617 i2c_end_transfer(s->bus); 618 } 619 620 static void stellaris_i2c_reset_hold(Object *obj, ResetType type) 621 { 622 stellaris_i2c_state *s = STELLARIS_I2C(obj); 623 624 s->msa = 0; 625 s->mcs = 0; 626 s->mdr = 0; 627 s->mtpr = 1; 628 s->mimr = 0; 629 s->mris = 0; 630 s->mcr = 0; 631 } 632 633 static void stellaris_i2c_reset_exit(Object *obj, ResetType type) 634 { 635 stellaris_i2c_state *s = STELLARIS_I2C(obj); 636 637 stellaris_i2c_update(s); 638 } 639 640 static const MemoryRegionOps stellaris_i2c_ops = { 641 .read = stellaris_i2c_read, 642 .write = stellaris_i2c_write, 643 .endianness = DEVICE_NATIVE_ENDIAN, 644 }; 645 646 static const VMStateDescription vmstate_stellaris_i2c = { 647 .name = "stellaris_i2c", 648 .version_id = 1, 649 .minimum_version_id = 1, 650 .fields = (const VMStateField[]) { 651 VMSTATE_UINT32(msa, stellaris_i2c_state), 652 VMSTATE_UINT32(mcs, stellaris_i2c_state), 653 VMSTATE_UINT32(mdr, stellaris_i2c_state), 654 VMSTATE_UINT32(mtpr, stellaris_i2c_state), 655 VMSTATE_UINT32(mimr, stellaris_i2c_state), 656 VMSTATE_UINT32(mris, stellaris_i2c_state), 657 VMSTATE_UINT32(mcr, stellaris_i2c_state), 658 VMSTATE_END_OF_LIST() 659 } 660 }; 661 662 static void stellaris_i2c_init(Object *obj) 663 { 664 DeviceState *dev = DEVICE(obj); 665 stellaris_i2c_state *s = STELLARIS_I2C(obj); 666 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 667 I2CBus *bus; 668 669 sysbus_init_irq(sbd, &s->irq); 670 bus = i2c_init_bus(dev, "i2c"); 671 s->bus = bus; 672 673 memory_region_init_io(&s->iomem, obj, &stellaris_i2c_ops, s, 674 "i2c", 0x1000); 675 sysbus_init_mmio(sbd, &s->iomem); 676 } 677 678 /* Analogue to Digital Converter. This is only partially implemented, 679 enough for applications that use a combined ADC and timer tick. */ 680 681 #define STELLARIS_ADC_EM_CONTROLLER 0 682 #define STELLARIS_ADC_EM_COMP 1 683 #define STELLARIS_ADC_EM_EXTERNAL 4 684 #define STELLARIS_ADC_EM_TIMER 5 685 #define STELLARIS_ADC_EM_PWM0 6 686 #define STELLARIS_ADC_EM_PWM1 7 687 #define STELLARIS_ADC_EM_PWM2 8 688 689 #define STELLARIS_ADC_FIFO_EMPTY 0x0100 690 #define STELLARIS_ADC_FIFO_FULL 0x1000 691 692 #define TYPE_STELLARIS_ADC "stellaris-adc" 693 typedef struct StellarisADCState StellarisADCState; 694 DECLARE_INSTANCE_CHECKER(StellarisADCState, STELLARIS_ADC, TYPE_STELLARIS_ADC) 695 696 struct StellarisADCState { 697 SysBusDevice parent_obj; 698 699 MemoryRegion iomem; 700 uint32_t actss; 701 uint32_t ris; 702 uint32_t im; 703 uint32_t emux; 704 uint32_t ostat; 705 uint32_t ustat; 706 uint32_t sspri; 707 uint32_t sac; 708 struct { 709 uint32_t state; 710 uint32_t data[16]; 711 } fifo[4]; 712 uint32_t ssmux[4]; 713 uint32_t ssctl[4]; 714 uint32_t noise; 715 qemu_irq irq[4]; 716 }; 717 718 static uint32_t stellaris_adc_fifo_read(StellarisADCState *s, int n) 719 { 720 int tail; 721 722 tail = s->fifo[n].state & 0xf; 723 if (s->fifo[n].state & STELLARIS_ADC_FIFO_EMPTY) { 724 s->ustat |= 1 << n; 725 } else { 726 s->fifo[n].state = (s->fifo[n].state & ~0xf) | ((tail + 1) & 0xf); 727 s->fifo[n].state &= ~STELLARIS_ADC_FIFO_FULL; 728 if (tail + 1 == ((s->fifo[n].state >> 4) & 0xf)) 729 s->fifo[n].state |= STELLARIS_ADC_FIFO_EMPTY; 730 } 731 return s->fifo[n].data[tail]; 732 } 733 734 static void stellaris_adc_fifo_write(StellarisADCState *s, int n, 735 uint32_t value) 736 { 737 int head; 738 739 /* TODO: Real hardware has limited size FIFOs. We have a full 16 entry 740 FIFO fir each sequencer. */ 741 head = (s->fifo[n].state >> 4) & 0xf; 742 if (s->fifo[n].state & STELLARIS_ADC_FIFO_FULL) { 743 s->ostat |= 1 << n; 744 return; 745 } 746 s->fifo[n].data[head] = value; 747 head = (head + 1) & 0xf; 748 s->fifo[n].state &= ~STELLARIS_ADC_FIFO_EMPTY; 749 s->fifo[n].state = (s->fifo[n].state & ~0xf0) | (head << 4); 750 if ((s->fifo[n].state & 0xf) == head) 751 s->fifo[n].state |= STELLARIS_ADC_FIFO_FULL; 752 } 753 754 static void stellaris_adc_update(StellarisADCState *s) 755 { 756 int level; 757 int n; 758 759 for (n = 0; n < 4; n++) { 760 level = (s->ris & s->im & (1 << n)) != 0; 761 qemu_set_irq(s->irq[n], level); 762 } 763 } 764 765 static void stellaris_adc_trigger(void *opaque, int irq, int level) 766 { 767 StellarisADCState *s = opaque; 768 int n; 769 770 for (n = 0; n < 4; n++) { 771 if ((s->actss & (1 << n)) == 0) { 772 continue; 773 } 774 775 if (((s->emux >> (n * 4)) & 0xff) != 5) { 776 continue; 777 } 778 779 /* Some applications use the ADC as a random number source, so introduce 780 some variation into the signal. */ 781 s->noise = s->noise * 314159 + 1; 782 /* ??? actual inputs not implemented. Return an arbitrary value. */ 783 stellaris_adc_fifo_write(s, n, 0x200 + ((s->noise >> 16) & 7)); 784 s->ris |= (1 << n); 785 stellaris_adc_update(s); 786 } 787 } 788 789 static void stellaris_adc_reset_hold(Object *obj, ResetType type) 790 { 791 StellarisADCState *s = STELLARIS_ADC(obj); 792 int n; 793 794 for (n = 0; n < 4; n++) { 795 s->ssmux[n] = 0; 796 s->ssctl[n] = 0; 797 s->fifo[n].state = STELLARIS_ADC_FIFO_EMPTY; 798 } 799 } 800 801 static uint64_t stellaris_adc_read(void *opaque, hwaddr offset, 802 unsigned size) 803 { 804 StellarisADCState *s = opaque; 805 806 /* TODO: Implement this. */ 807 if (offset >= 0x40 && offset < 0xc0) { 808 int n; 809 n = (offset - 0x40) >> 5; 810 switch (offset & 0x1f) { 811 case 0x00: /* SSMUX */ 812 return s->ssmux[n]; 813 case 0x04: /* SSCTL */ 814 return s->ssctl[n]; 815 case 0x08: /* SSFIFO */ 816 return stellaris_adc_fifo_read(s, n); 817 case 0x0c: /* SSFSTAT */ 818 return s->fifo[n].state; 819 default: 820 break; 821 } 822 } 823 switch (offset) { 824 case 0x00: /* ACTSS */ 825 return s->actss; 826 case 0x04: /* RIS */ 827 return s->ris; 828 case 0x08: /* IM */ 829 return s->im; 830 case 0x0c: /* ISC */ 831 return s->ris & s->im; 832 case 0x10: /* OSTAT */ 833 return s->ostat; 834 case 0x14: /* EMUX */ 835 return s->emux; 836 case 0x18: /* USTAT */ 837 return s->ustat; 838 case 0x20: /* SSPRI */ 839 return s->sspri; 840 case 0x30: /* SAC */ 841 return s->sac; 842 default: 843 qemu_log_mask(LOG_GUEST_ERROR, 844 "stellaris_adc: read at bad offset 0x%x\n", (int)offset); 845 return 0; 846 } 847 } 848 849 static void stellaris_adc_write(void *opaque, hwaddr offset, 850 uint64_t value, unsigned size) 851 { 852 StellarisADCState *s = opaque; 853 854 /* TODO: Implement this. */ 855 if (offset >= 0x40 && offset < 0xc0) { 856 int n; 857 n = (offset - 0x40) >> 5; 858 switch (offset & 0x1f) { 859 case 0x00: /* SSMUX */ 860 s->ssmux[n] = value & 0x33333333; 861 return; 862 case 0x04: /* SSCTL */ 863 if (value != 6) { 864 qemu_log_mask(LOG_UNIMP, 865 "ADC: Unimplemented sequence %" PRIx64 "\n", 866 value); 867 } 868 s->ssctl[n] = value; 869 return; 870 default: 871 break; 872 } 873 } 874 switch (offset) { 875 case 0x00: /* ACTSS */ 876 s->actss = value & 0xf; 877 break; 878 case 0x08: /* IM */ 879 s->im = value; 880 break; 881 case 0x0c: /* ISC */ 882 s->ris &= ~value; 883 break; 884 case 0x10: /* OSTAT */ 885 s->ostat &= ~value; 886 break; 887 case 0x14: /* EMUX */ 888 s->emux = value; 889 break; 890 case 0x18: /* USTAT */ 891 s->ustat &= ~value; 892 break; 893 case 0x20: /* SSPRI */ 894 s->sspri = value; 895 break; 896 case 0x28: /* PSSI */ 897 qemu_log_mask(LOG_UNIMP, "ADC: sample initiate unimplemented\n"); 898 break; 899 case 0x30: /* SAC */ 900 s->sac = value; 901 break; 902 default: 903 qemu_log_mask(LOG_GUEST_ERROR, 904 "stellaris_adc: write at bad offset 0x%x\n", (int)offset); 905 } 906 stellaris_adc_update(s); 907 } 908 909 static const MemoryRegionOps stellaris_adc_ops = { 910 .read = stellaris_adc_read, 911 .write = stellaris_adc_write, 912 .endianness = DEVICE_NATIVE_ENDIAN, 913 }; 914 915 static const VMStateDescription vmstate_stellaris_adc = { 916 .name = "stellaris_adc", 917 .version_id = 1, 918 .minimum_version_id = 1, 919 .fields = (const VMStateField[]) { 920 VMSTATE_UINT32(actss, StellarisADCState), 921 VMSTATE_UINT32(ris, StellarisADCState), 922 VMSTATE_UINT32(im, StellarisADCState), 923 VMSTATE_UINT32(emux, StellarisADCState), 924 VMSTATE_UINT32(ostat, StellarisADCState), 925 VMSTATE_UINT32(ustat, StellarisADCState), 926 VMSTATE_UINT32(sspri, StellarisADCState), 927 VMSTATE_UINT32(sac, StellarisADCState), 928 VMSTATE_UINT32(fifo[0].state, StellarisADCState), 929 VMSTATE_UINT32_ARRAY(fifo[0].data, StellarisADCState, 16), 930 VMSTATE_UINT32(ssmux[0], StellarisADCState), 931 VMSTATE_UINT32(ssctl[0], StellarisADCState), 932 VMSTATE_UINT32(fifo[1].state, StellarisADCState), 933 VMSTATE_UINT32_ARRAY(fifo[1].data, StellarisADCState, 16), 934 VMSTATE_UINT32(ssmux[1], StellarisADCState), 935 VMSTATE_UINT32(ssctl[1], StellarisADCState), 936 VMSTATE_UINT32(fifo[2].state, StellarisADCState), 937 VMSTATE_UINT32_ARRAY(fifo[2].data, StellarisADCState, 16), 938 VMSTATE_UINT32(ssmux[2], StellarisADCState), 939 VMSTATE_UINT32(ssctl[2], StellarisADCState), 940 VMSTATE_UINT32(fifo[3].state, StellarisADCState), 941 VMSTATE_UINT32_ARRAY(fifo[3].data, StellarisADCState, 16), 942 VMSTATE_UINT32(ssmux[3], StellarisADCState), 943 VMSTATE_UINT32(ssctl[3], StellarisADCState), 944 VMSTATE_UINT32(noise, StellarisADCState), 945 VMSTATE_END_OF_LIST() 946 } 947 }; 948 949 static void stellaris_adc_init(Object *obj) 950 { 951 DeviceState *dev = DEVICE(obj); 952 StellarisADCState *s = STELLARIS_ADC(obj); 953 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 954 int n; 955 956 for (n = 0; n < 4; n++) { 957 sysbus_init_irq(sbd, &s->irq[n]); 958 } 959 960 memory_region_init_io(&s->iomem, obj, &stellaris_adc_ops, s, 961 "adc", 0x1000); 962 sysbus_init_mmio(sbd, &s->iomem); 963 qdev_init_gpio_in(dev, stellaris_adc_trigger, 1); 964 } 965 966 /* Board init. */ 967 static stellaris_board_info stellaris_boards[] = { 968 { "LM3S811EVB", 969 0, 970 0x0032000e, 971 0x001f001f, /* dc0 */ 972 0x001132bf, 973 0x01071013, 974 0x3f0f01ff, 975 0x0000001f, 976 BP_OLED_I2C 977 }, 978 { "LM3S6965EVB", 979 0x10010002, 980 0x1073402e, 981 0x00ff007f, /* dc0 */ 982 0x001133ff, 983 0x030f5317, 984 0x0f0f87ff, 985 0x5000007f, 986 BP_OLED_SSI | BP_GAMEPAD 987 } 988 }; 989 990 static void stellaris_init(MachineState *ms, stellaris_board_info *board) 991 { 992 static const int uart_irq[] = {5, 6, 33, 34}; 993 static const int timer_irq[] = {19, 21, 23, 35}; 994 static const uint32_t gpio_addr[7] = 995 { 0x40004000, 0x40005000, 0x40006000, 0x40007000, 996 0x40024000, 0x40025000, 0x40026000}; 997 static const int gpio_irq[7] = {0, 1, 2, 3, 4, 30, 31}; 998 999 /* Memory map of SoC devices, from 1000 * Stellaris LM3S6965 Microcontroller Data Sheet (rev I) 1001 * http://www.ti.com/lit/ds/symlink/lm3s6965.pdf 1002 * 1003 * 40000000 wdtimer 1004 * 40002000 i2c (unimplemented) 1005 * 40004000 GPIO 1006 * 40005000 GPIO 1007 * 40006000 GPIO 1008 * 40007000 GPIO 1009 * 40008000 SSI 1010 * 4000c000 UART 1011 * 4000d000 UART 1012 * 4000e000 UART 1013 * 40020000 i2c 1014 * 40021000 i2c (unimplemented) 1015 * 40024000 GPIO 1016 * 40025000 GPIO 1017 * 40026000 GPIO 1018 * 40028000 PWM (unimplemented) 1019 * 4002c000 QEI (unimplemented) 1020 * 4002d000 QEI (unimplemented) 1021 * 40030000 gptimer 1022 * 40031000 gptimer 1023 * 40032000 gptimer 1024 * 40033000 gptimer 1025 * 40038000 ADC 1026 * 4003c000 analogue comparator (unimplemented) 1027 * 40048000 ethernet 1028 * 400fc000 hibernation module (unimplemented) 1029 * 400fd000 flash memory control (unimplemented) 1030 * 400fe000 system control 1031 */ 1032 1033 Object *soc_container; 1034 DeviceState *gpio_dev[7], *nvic; 1035 qemu_irq gpio_in[7][8]; 1036 qemu_irq gpio_out[7][8]; 1037 qemu_irq adc; 1038 int sram_size; 1039 int flash_size; 1040 I2CBus *i2c; 1041 DeviceState *dev; 1042 DeviceState *ssys_dev; 1043 int i; 1044 int j; 1045 NICInfo *nd; 1046 MACAddr mac; 1047 1048 MemoryRegion *sram = g_new(MemoryRegion, 1); 1049 MemoryRegion *flash = g_new(MemoryRegion, 1); 1050 MemoryRegion *system_memory = get_system_memory(); 1051 1052 flash_size = (((board->dc0 & 0xffff) + 1) << 1) * 1024; 1053 sram_size = ((board->dc0 >> 18) + 1) * 1024; 1054 1055 soc_container = object_new(TYPE_CONTAINER); 1056 object_property_add_child(OBJECT(ms), "soc", soc_container); 1057 1058 /* Flash programming is done via the SCU, so pretend it is ROM. */ 1059 memory_region_init_rom(flash, NULL, "stellaris.flash", flash_size, 1060 &error_fatal); 1061 memory_region_add_subregion(system_memory, 0, flash); 1062 1063 memory_region_init_ram(sram, NULL, "stellaris.sram", sram_size, 1064 &error_fatal); 1065 memory_region_add_subregion(system_memory, 0x20000000, sram); 1066 1067 /* 1068 * Create the system-registers object early, because we will 1069 * need its sysclk output. 1070 */ 1071 ssys_dev = qdev_new(TYPE_STELLARIS_SYS); 1072 object_property_add_child(soc_container, "sys", OBJECT(ssys_dev)); 1073 1074 /* 1075 * Most devices come preprogrammed with a MAC address in the user data. 1076 * Generate a MAC address now, if there isn't a matching -nic for it. 1077 */ 1078 nd = qemu_find_nic_info("stellaris_enet", true, "stellaris"); 1079 if (nd) { 1080 memcpy(mac.a, nd->macaddr.a, sizeof(mac.a)); 1081 } else { 1082 qemu_macaddr_default_if_unset(&mac); 1083 } 1084 1085 qdev_prop_set_uint32(ssys_dev, "user0", 1086 mac.a[0] | (mac.a[1] << 8) | (mac.a[2] << 16)); 1087 qdev_prop_set_uint32(ssys_dev, "user1", 1088 mac.a[3] | (mac.a[4] << 8) | (mac.a[5] << 16)); 1089 qdev_prop_set_uint32(ssys_dev, "did0", board->did0); 1090 qdev_prop_set_uint32(ssys_dev, "did1", board->did1); 1091 qdev_prop_set_uint32(ssys_dev, "dc0", board->dc0); 1092 qdev_prop_set_uint32(ssys_dev, "dc1", board->dc1); 1093 qdev_prop_set_uint32(ssys_dev, "dc2", board->dc2); 1094 qdev_prop_set_uint32(ssys_dev, "dc3", board->dc3); 1095 qdev_prop_set_uint32(ssys_dev, "dc4", board->dc4); 1096 sysbus_realize_and_unref(SYS_BUS_DEVICE(ssys_dev), &error_fatal); 1097 1098 nvic = qdev_new(TYPE_ARMV7M); 1099 object_property_add_child(soc_container, "v7m", OBJECT(nvic)); 1100 qdev_prop_set_uint32(nvic, "num-irq", NUM_IRQ_LINES); 1101 qdev_prop_set_uint8(nvic, "num-prio-bits", NUM_PRIO_BITS); 1102 qdev_prop_set_string(nvic, "cpu-type", ms->cpu_type); 1103 qdev_prop_set_bit(nvic, "enable-bitband", true); 1104 qdev_connect_clock_in(nvic, "cpuclk", 1105 qdev_get_clock_out(ssys_dev, "SYSCLK")); 1106 /* This SoC does not connect the systick reference clock */ 1107 object_property_set_link(OBJECT(nvic), "memory", 1108 OBJECT(get_system_memory()), &error_abort); 1109 /* This will exit with an error if the user passed us a bad cpu_type */ 1110 sysbus_realize_and_unref(SYS_BUS_DEVICE(nvic), &error_fatal); 1111 1112 /* Now we can wire up the IRQ and MMIO of the system registers */ 1113 sysbus_mmio_map(SYS_BUS_DEVICE(ssys_dev), 0, 0x400fe000); 1114 sysbus_connect_irq(SYS_BUS_DEVICE(ssys_dev), 0, qdev_get_gpio_in(nvic, 28)); 1115 1116 if (board->dc1 & (1 << 16)) { 1117 dev = sysbus_create_varargs(TYPE_STELLARIS_ADC, 0x40038000, 1118 qdev_get_gpio_in(nvic, 14), 1119 qdev_get_gpio_in(nvic, 15), 1120 qdev_get_gpio_in(nvic, 16), 1121 qdev_get_gpio_in(nvic, 17), 1122 NULL); 1123 adc = qdev_get_gpio_in(dev, 0); 1124 } else { 1125 adc = NULL; 1126 } 1127 for (i = 0; i < 4; i++) { 1128 if (board->dc2 & (0x10000 << i)) { 1129 SysBusDevice *sbd; 1130 1131 dev = qdev_new(TYPE_STELLARIS_GPTM); 1132 sbd = SYS_BUS_DEVICE(dev); 1133 object_property_add_child(soc_container, "gptm[*]", OBJECT(dev)); 1134 qdev_connect_clock_in(dev, "clk", 1135 qdev_get_clock_out(ssys_dev, "SYSCLK")); 1136 sysbus_realize_and_unref(sbd, &error_fatal); 1137 sysbus_mmio_map(sbd, 0, 0x40030000 + i * 0x1000); 1138 sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(nvic, timer_irq[i])); 1139 /* TODO: This is incorrect, but we get away with it because 1140 the ADC output is only ever pulsed. */ 1141 qdev_connect_gpio_out(dev, 0, adc); 1142 } 1143 } 1144 1145 if (board->dc1 & (1 << 3)) { /* watchdog present */ 1146 dev = qdev_new(TYPE_LUMINARY_WATCHDOG); 1147 object_property_add_child(soc_container, "wdg", OBJECT(dev)); 1148 qdev_connect_clock_in(dev, "WDOGCLK", 1149 qdev_get_clock_out(ssys_dev, "SYSCLK")); 1150 1151 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1152 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1153 0, 1154 0x40000000u); 1155 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1156 0, 1157 qdev_get_gpio_in(nvic, 18)); 1158 } 1159 1160 1161 for (i = 0; i < 7; i++) { 1162 if (board->dc4 & (1 << i)) { 1163 gpio_dev[i] = sysbus_create_simple("pl061_luminary", gpio_addr[i], 1164 qdev_get_gpio_in(nvic, 1165 gpio_irq[i])); 1166 for (j = 0; j < 8; j++) { 1167 gpio_in[i][j] = qdev_get_gpio_in(gpio_dev[i], j); 1168 gpio_out[i][j] = NULL; 1169 } 1170 } 1171 } 1172 1173 if (board->dc2 & (1 << 12)) { 1174 dev = sysbus_create_simple(TYPE_STELLARIS_I2C, 0x40020000, 1175 qdev_get_gpio_in(nvic, 8)); 1176 i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c"); 1177 if (board->peripherals & BP_OLED_I2C) { 1178 i2c_slave_create_simple(i2c, "ssd0303", 0x3d); 1179 } 1180 } 1181 1182 for (i = 0; i < 4; i++) { 1183 if (board->dc2 & (1 << i)) { 1184 SysBusDevice *sbd; 1185 1186 dev = qdev_new("pl011_luminary"); 1187 object_property_add_child(soc_container, "uart[*]", OBJECT(dev)); 1188 sbd = SYS_BUS_DEVICE(dev); 1189 qdev_prop_set_chr(dev, "chardev", serial_hd(i)); 1190 sysbus_realize_and_unref(sbd, &error_fatal); 1191 sysbus_mmio_map(sbd, 0, 0x4000c000 + i * 0x1000); 1192 sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(nvic, uart_irq[i])); 1193 } 1194 } 1195 if (board->dc2 & (1 << 4)) { 1196 dev = sysbus_create_simple("pl022", 0x40008000, 1197 qdev_get_gpio_in(nvic, 7)); 1198 if (board->peripherals & BP_OLED_SSI) { 1199 void *bus; 1200 DeviceState *sddev; 1201 DeviceState *ssddev; 1202 DriveInfo *dinfo; 1203 DeviceState *carddev; 1204 DeviceState *gpio_d_splitter; 1205 BlockBackend *blk; 1206 1207 /* 1208 * Some boards have both an OLED controller and SD card connected to 1209 * the same SSI port, with the SD card chip select connected to a 1210 * GPIO pin. Technically the OLED chip select is connected to the 1211 * SSI Fss pin. We do not bother emulating that as both devices 1212 * should never be selected simultaneously, and our OLED controller 1213 * ignores stray 0xff commands that occur when deselecting the SD 1214 * card. 1215 * 1216 * The h/w wiring is: 1217 * - GPIO pin D0 is wired to the active-low SD card chip select 1218 * - GPIO pin A3 is wired to the active-low OLED chip select 1219 * - The SoC wiring of the PL061 "auxiliary function" for A3 is 1220 * SSI0Fss ("frame signal"), which is an output from the SoC's 1221 * SSI controller. The SSI controller takes SSI0Fss low when it 1222 * transmits a frame, so it can work as a chip-select signal. 1223 * - GPIO A4 is aux-function SSI0Rx, and wired to the SD card Tx 1224 * (the OLED never sends data to the CPU, so no wiring needed) 1225 * - GPIO A5 is aux-function SSI0Tx, and wired to the SD card Rx 1226 * and the OLED display-data-in 1227 * - GPIO A2 is aux-function SSI0Clk, wired to SD card and OLED 1228 * serial-clock input 1229 * So a guest that wants to use the OLED can configure the PL061 1230 * to make pins A2, A3, A5 aux-function, so they are connected 1231 * directly to the SSI controller. When the SSI controller sends 1232 * data it asserts SSI0Fss which selects the OLED. 1233 * A guest that wants to use the SD card configures A2, A4 and A5 1234 * as aux-function, but leaves A3 as a software-controlled GPIO 1235 * line. It asserts the SD card chip-select by using the PL061 1236 * to control pin D0, and lets the SSI controller handle Clk, Tx 1237 * and Rx. (The SSI controller asserts Fss during tx cycles as 1238 * usual, but because A3 is not set to aux-function this is not 1239 * forwarded to the OLED, and so the OLED stays unselected.) 1240 * 1241 * The QEMU implementation instead is: 1242 * - GPIO pin D0 is wired to the active-low SD card chip select, 1243 * and also to the OLED chip-select which is implemented 1244 * as *active-high* 1245 * - SSI controller signals go to the devices regardless of 1246 * whether the guest programs A2, A4, A5 as aux-function or not 1247 * 1248 * The problem with this implementation is if the guest doesn't 1249 * care about the SD card and only uses the OLED. In that case it 1250 * may choose never to do anything with D0 (leaving it in its 1251 * default floating state, which reliably leaves the card disabled 1252 * because an SD card has a pullup on CS within the card itself), 1253 * and only set up A2, A3, A5. This for us would mean the OLED 1254 * never gets the chip-select assert it needs. We work around 1255 * this with a manual raise of D0 here (despite board creation 1256 * code being the wrong place to raise IRQ lines) to put the OLED 1257 * into an initially selected state. 1258 * 1259 * In theory the right way to model this would be: 1260 * - Implement aux-function support in the PL061, with an 1261 * extra set of AFIN and AFOUT GPIO lines (set up so that 1262 * if a GPIO line is in auxfn mode the main GPIO in and out 1263 * track the AFIN and AFOUT lines) 1264 * - Wire the AFOUT for D0 up to either a line from the 1265 * SSI controller that's pulled low around every transmit, 1266 * or at least to an always-0 line here on the board 1267 * - Make the ssd0323 OLED controller chipselect active-low 1268 */ 1269 bus = qdev_get_child_bus(dev, "ssi"); 1270 sddev = ssi_create_peripheral(bus, "ssi-sd"); 1271 1272 dinfo = drive_get(IF_SD, 0, 0); 1273 blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL; 1274 carddev = qdev_new(TYPE_SD_CARD_SPI); 1275 qdev_prop_set_drive_err(carddev, "drive", blk, &error_fatal); 1276 qdev_realize_and_unref(carddev, 1277 qdev_get_child_bus(sddev, "sd-bus"), 1278 &error_fatal); 1279 1280 ssddev = qdev_new("ssd0323"); 1281 object_property_add_child(OBJECT(ms), "oled", OBJECT(ssddev)); 1282 qdev_prop_set_uint8(ssddev, "cs", 1); 1283 qdev_realize_and_unref(ssddev, bus, &error_fatal); 1284 1285 gpio_d_splitter = qdev_new(TYPE_SPLIT_IRQ); 1286 object_property_add_child(OBJECT(ms), "splitter", 1287 OBJECT(gpio_d_splitter)); 1288 qdev_prop_set_uint32(gpio_d_splitter, "num-lines", 2); 1289 qdev_realize_and_unref(gpio_d_splitter, NULL, &error_fatal); 1290 qdev_connect_gpio_out( 1291 gpio_d_splitter, 0, 1292 qdev_get_gpio_in_named(sddev, SSI_GPIO_CS, 0)); 1293 qdev_connect_gpio_out( 1294 gpio_d_splitter, 1, 1295 qdev_get_gpio_in_named(ssddev, SSI_GPIO_CS, 0)); 1296 gpio_out[GPIO_D][0] = qdev_get_gpio_in(gpio_d_splitter, 0); 1297 1298 gpio_out[GPIO_C][7] = qdev_get_gpio_in(ssddev, 0); 1299 1300 /* Make sure the select pin is high. */ 1301 qemu_irq_raise(gpio_out[GPIO_D][0]); 1302 } 1303 } 1304 if (board->dc4 & (1 << 28)) { 1305 DeviceState *enet; 1306 1307 enet = qdev_new("stellaris_enet"); 1308 object_property_add_child(soc_container, "enet", OBJECT(enet)); 1309 if (nd) { 1310 qdev_set_nic_properties(enet, nd); 1311 } else { 1312 qdev_prop_set_macaddr(enet, "mac", mac.a); 1313 } 1314 1315 sysbus_realize_and_unref(SYS_BUS_DEVICE(enet), &error_fatal); 1316 sysbus_mmio_map(SYS_BUS_DEVICE(enet), 0, 0x40048000); 1317 sysbus_connect_irq(SYS_BUS_DEVICE(enet), 0, qdev_get_gpio_in(nvic, 42)); 1318 } 1319 if (board->peripherals & BP_GAMEPAD) { 1320 QList *gpad_keycode_list = qlist_new(); 1321 static const int gpad_keycode[5] = { 1322 Q_KEY_CODE_UP, Q_KEY_CODE_DOWN, Q_KEY_CODE_LEFT, 1323 Q_KEY_CODE_RIGHT, Q_KEY_CODE_CTRL, 1324 }; 1325 DeviceState *gpad; 1326 1327 gpad = qdev_new(TYPE_STELLARIS_GAMEPAD); 1328 object_property_add_child(OBJECT(ms), "gamepad", OBJECT(gpad)); 1329 for (i = 0; i < ARRAY_SIZE(gpad_keycode); i++) { 1330 qlist_append_int(gpad_keycode_list, gpad_keycode[i]); 1331 } 1332 qdev_prop_set_array(gpad, "keycodes", gpad_keycode_list); 1333 sysbus_realize_and_unref(SYS_BUS_DEVICE(gpad), &error_fatal); 1334 1335 qdev_connect_gpio_out(gpad, 0, 1336 qemu_irq_invert(gpio_in[GPIO_E][0])); /* up */ 1337 qdev_connect_gpio_out(gpad, 1, 1338 qemu_irq_invert(gpio_in[GPIO_E][1])); /* down */ 1339 qdev_connect_gpio_out(gpad, 2, 1340 qemu_irq_invert(gpio_in[GPIO_E][2])); /* left */ 1341 qdev_connect_gpio_out(gpad, 3, 1342 qemu_irq_invert(gpio_in[GPIO_E][3])); /* right */ 1343 qdev_connect_gpio_out(gpad, 4, 1344 qemu_irq_invert(gpio_in[GPIO_F][1])); /* select */ 1345 } 1346 for (i = 0; i < 7; i++) { 1347 if (board->dc4 & (1 << i)) { 1348 for (j = 0; j < 8; j++) { 1349 if (gpio_out[i][j]) { 1350 qdev_connect_gpio_out(gpio_dev[i], j, gpio_out[i][j]); 1351 } 1352 } 1353 } 1354 } 1355 1356 /* Add dummy regions for the devices we don't implement yet, 1357 * so guest accesses don't cause unlogged crashes. 1358 */ 1359 create_unimplemented_device("i2c-0", 0x40002000, 0x1000); 1360 create_unimplemented_device("i2c-2", 0x40021000, 0x1000); 1361 create_unimplemented_device("PWM", 0x40028000, 0x1000); 1362 create_unimplemented_device("QEI-0", 0x4002c000, 0x1000); 1363 create_unimplemented_device("QEI-1", 0x4002d000, 0x1000); 1364 create_unimplemented_device("analogue-comparator", 0x4003c000, 0x1000); 1365 create_unimplemented_device("hibernation", 0x400fc000, 0x1000); 1366 create_unimplemented_device("flash-control", 0x400fd000, 0x1000); 1367 1368 armv7m_load_kernel(ARM_CPU(first_cpu), ms->kernel_filename, 0, flash_size); 1369 } 1370 1371 /* FIXME: Figure out how to generate these from stellaris_boards. */ 1372 static void lm3s811evb_init(MachineState *machine) 1373 { 1374 stellaris_init(machine, &stellaris_boards[0]); 1375 } 1376 1377 static void lm3s6965evb_init(MachineState *machine) 1378 { 1379 stellaris_init(machine, &stellaris_boards[1]); 1380 } 1381 1382 static void lm3s811evb_class_init(ObjectClass *oc, void *data) 1383 { 1384 MachineClass *mc = MACHINE_CLASS(oc); 1385 1386 mc->desc = "Stellaris LM3S811EVB (Cortex-M3)"; 1387 mc->init = lm3s811evb_init; 1388 mc->ignore_memory_transaction_failures = true; 1389 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3"); 1390 } 1391 1392 static const TypeInfo lm3s811evb_type = { 1393 .name = MACHINE_TYPE_NAME("lm3s811evb"), 1394 .parent = TYPE_MACHINE, 1395 .class_init = lm3s811evb_class_init, 1396 }; 1397 1398 static void lm3s6965evb_class_init(ObjectClass *oc, void *data) 1399 { 1400 MachineClass *mc = MACHINE_CLASS(oc); 1401 1402 mc->desc = "Stellaris LM3S6965EVB (Cortex-M3)"; 1403 mc->init = lm3s6965evb_init; 1404 mc->ignore_memory_transaction_failures = true; 1405 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3"); 1406 } 1407 1408 static const TypeInfo lm3s6965evb_type = { 1409 .name = MACHINE_TYPE_NAME("lm3s6965evb"), 1410 .parent = TYPE_MACHINE, 1411 .class_init = lm3s6965evb_class_init, 1412 }; 1413 1414 static void stellaris_machine_init(void) 1415 { 1416 type_register_static(&lm3s811evb_type); 1417 type_register_static(&lm3s6965evb_type); 1418 } 1419 1420 type_init(stellaris_machine_init) 1421 1422 static void stellaris_i2c_class_init(ObjectClass *klass, void *data) 1423 { 1424 DeviceClass *dc = DEVICE_CLASS(klass); 1425 ResettableClass *rc = RESETTABLE_CLASS(klass); 1426 1427 rc->phases.enter = stellaris_i2c_reset_enter; 1428 rc->phases.hold = stellaris_i2c_reset_hold; 1429 rc->phases.exit = stellaris_i2c_reset_exit; 1430 dc->vmsd = &vmstate_stellaris_i2c; 1431 } 1432 1433 static const TypeInfo stellaris_i2c_info = { 1434 .name = TYPE_STELLARIS_I2C, 1435 .parent = TYPE_SYS_BUS_DEVICE, 1436 .instance_size = sizeof(stellaris_i2c_state), 1437 .instance_init = stellaris_i2c_init, 1438 .class_init = stellaris_i2c_class_init, 1439 }; 1440 1441 static void stellaris_adc_class_init(ObjectClass *klass, void *data) 1442 { 1443 DeviceClass *dc = DEVICE_CLASS(klass); 1444 ResettableClass *rc = RESETTABLE_CLASS(klass); 1445 1446 rc->phases.hold = stellaris_adc_reset_hold; 1447 dc->vmsd = &vmstate_stellaris_adc; 1448 } 1449 1450 static const TypeInfo stellaris_adc_info = { 1451 .name = TYPE_STELLARIS_ADC, 1452 .parent = TYPE_SYS_BUS_DEVICE, 1453 .instance_size = sizeof(StellarisADCState), 1454 .instance_init = stellaris_adc_init, 1455 .class_init = stellaris_adc_class_init, 1456 }; 1457 1458 static void stellaris_sys_class_init(ObjectClass *klass, void *data) 1459 { 1460 DeviceClass *dc = DEVICE_CLASS(klass); 1461 ResettableClass *rc = RESETTABLE_CLASS(klass); 1462 1463 dc->vmsd = &vmstate_stellaris_sys; 1464 rc->phases.enter = stellaris_sys_reset_enter; 1465 rc->phases.hold = stellaris_sys_reset_hold; 1466 rc->phases.exit = stellaris_sys_reset_exit; 1467 device_class_set_props(dc, stellaris_sys_properties); 1468 } 1469 1470 static const TypeInfo stellaris_sys_info = { 1471 .name = TYPE_STELLARIS_SYS, 1472 .parent = TYPE_SYS_BUS_DEVICE, 1473 .instance_size = sizeof(ssys_state), 1474 .instance_init = stellaris_sys_instance_init, 1475 .class_init = stellaris_sys_class_init, 1476 }; 1477 1478 static void stellaris_register_types(void) 1479 { 1480 type_register_static(&stellaris_i2c_info); 1481 type_register_static(&stellaris_adc_info); 1482 type_register_static(&stellaris_sys_info); 1483 } 1484 1485 type_init(stellaris_register_types) 1486