1 /* 2 * Luminary Micro Stellaris peripherals 3 * 4 * Copyright (c) 2006 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/bitops.h" 12 #include "qapi/error.h" 13 #include "hw/core/split-irq.h" 14 #include "hw/sysbus.h" 15 #include "hw/sd/sd.h" 16 #include "hw/ssi/ssi.h" 17 #include "hw/arm/boot.h" 18 #include "qemu/timer.h" 19 #include "hw/i2c/i2c.h" 20 #include "net/net.h" 21 #include "hw/boards.h" 22 #include "qemu/log.h" 23 #include "exec/address-spaces.h" 24 #include "system/system.h" 25 #include "hw/arm/armv7m.h" 26 #include "hw/char/pl011.h" 27 #include "hw/input/stellaris_gamepad.h" 28 #include "hw/irq.h" 29 #include "hw/watchdog/cmsdk-apb-watchdog.h" 30 #include "migration/vmstate.h" 31 #include "hw/misc/unimp.h" 32 #include "hw/timer/stellaris-gptm.h" 33 #include "hw/qdev-clock.h" 34 #include "qom/object.h" 35 #include "qapi/qmp/qlist.h" 36 #include "ui/input.h" 37 38 #define GPIO_A 0 39 #define GPIO_B 1 40 #define GPIO_C 2 41 #define GPIO_D 3 42 #define GPIO_E 4 43 #define GPIO_F 5 44 #define GPIO_G 6 45 46 #define BP_OLED_I2C 0x01 47 #define BP_OLED_SSI 0x02 48 #define BP_GAMEPAD 0x04 49 50 #define NUM_IRQ_LINES 64 51 #define NUM_PRIO_BITS 3 52 53 #define NUM_GPIO 7 54 #define NUM_UART 4 55 #define NUM_GPTM 4 56 #define NUM_I2C 2 57 58 /* 59 * See Stellaris Data Sheet chapter 5.2.5 "System Control", 60 * Register 13 .. 17: Device Capabilities 0 .. 4 (DC0 .. DC4). 61 */ 62 #define DC1_WDT 3 63 #define DC1_HIB 6 64 #define DC1_MPU 7 65 #define DC1_ADC 16 66 #define DC1_PWM 20 67 #define DC2_UART(n) (n) 68 #define DC2_SSI 4 69 #define DC2_QEI(n) (8 + n) 70 #define DC2_I2C(n) (12 + 2 * n) 71 #define DC2_GPTM(n) (16 + n) 72 #define DC2_COMP(n) (24 + n) 73 #define DC4_GPIO(n) (n) 74 #define DC4_EMAC 28 75 76 #define DEV_CAP(_dc, _cap) extract32(board->dc##_dc, DC##_dc##_##_cap, 1) 77 78 typedef const struct { 79 const char *name; 80 uint32_t did0; 81 uint32_t did1; 82 uint32_t dc0; 83 uint32_t dc1; 84 uint32_t dc2; 85 uint32_t dc3; 86 uint32_t dc4; 87 uint32_t peripherals; 88 } stellaris_board_info; 89 90 /* System controller. */ 91 92 #define TYPE_STELLARIS_SYS "stellaris-sys" 93 OBJECT_DECLARE_SIMPLE_TYPE(ssys_state, STELLARIS_SYS) 94 95 struct ssys_state { 96 SysBusDevice parent_obj; 97 98 MemoryRegion iomem; 99 uint32_t pborctl; 100 uint32_t ldopctl; 101 uint32_t int_status; 102 uint32_t int_mask; 103 uint32_t resc; 104 uint32_t rcc; 105 uint32_t rcc2; 106 uint32_t rcgc[3]; 107 uint32_t scgc[3]; 108 uint32_t dcgc[3]; 109 uint32_t clkvclr; 110 uint32_t ldoarst; 111 qemu_irq irq; 112 Clock *sysclk; 113 /* Properties (all read-only registers) */ 114 uint32_t user0; 115 uint32_t user1; 116 uint32_t did0; 117 uint32_t did1; 118 uint32_t dc0; 119 uint32_t dc1; 120 uint32_t dc2; 121 uint32_t dc3; 122 uint32_t dc4; 123 }; 124 125 static void ssys_update(ssys_state *s) 126 { 127 qemu_set_irq(s->irq, (s->int_status & s->int_mask) != 0); 128 } 129 130 static const uint32_t pllcfg_sandstorm[16] = { 131 0x31c0, /* 1 Mhz */ 132 0x1ae0, /* 1.8432 Mhz */ 133 0x18c0, /* 2 Mhz */ 134 0xd573, /* 2.4576 Mhz */ 135 0x37a6, /* 3.57954 Mhz */ 136 0x1ae2, /* 3.6864 Mhz */ 137 0x0c40, /* 4 Mhz */ 138 0x98bc, /* 4.906 Mhz */ 139 0x935b, /* 4.9152 Mhz */ 140 0x09c0, /* 5 Mhz */ 141 0x4dee, /* 5.12 Mhz */ 142 0x0c41, /* 6 Mhz */ 143 0x75db, /* 6.144 Mhz */ 144 0x1ae6, /* 7.3728 Mhz */ 145 0x0600, /* 8 Mhz */ 146 0x585b /* 8.192 Mhz */ 147 }; 148 149 static const uint32_t pllcfg_fury[16] = { 150 0x3200, /* 1 Mhz */ 151 0x1b20, /* 1.8432 Mhz */ 152 0x1900, /* 2 Mhz */ 153 0xf42b, /* 2.4576 Mhz */ 154 0x37e3, /* 3.57954 Mhz */ 155 0x1b21, /* 3.6864 Mhz */ 156 0x0c80, /* 4 Mhz */ 157 0x98ee, /* 4.906 Mhz */ 158 0xd5b4, /* 4.9152 Mhz */ 159 0x0a00, /* 5 Mhz */ 160 0x4e27, /* 5.12 Mhz */ 161 0x1902, /* 6 Mhz */ 162 0xec1c, /* 6.144 Mhz */ 163 0x1b23, /* 7.3728 Mhz */ 164 0x0640, /* 8 Mhz */ 165 0xb11c /* 8.192 Mhz */ 166 }; 167 168 #define DID0_VER_MASK 0x70000000 169 #define DID0_VER_0 0x00000000 170 #define DID0_VER_1 0x10000000 171 172 #define DID0_CLASS_MASK 0x00FF0000 173 #define DID0_CLASS_SANDSTORM 0x00000000 174 #define DID0_CLASS_FURY 0x00010000 175 176 static int ssys_board_class(const ssys_state *s) 177 { 178 uint32_t did0 = s->did0; 179 switch (did0 & DID0_VER_MASK) { 180 case DID0_VER_0: 181 return DID0_CLASS_SANDSTORM; 182 case DID0_VER_1: 183 switch (did0 & DID0_CLASS_MASK) { 184 case DID0_CLASS_SANDSTORM: 185 case DID0_CLASS_FURY: 186 return did0 & DID0_CLASS_MASK; 187 } 188 /* for unknown classes, fall through */ 189 default: 190 /* This can only happen if the hardwired constant did0 value 191 * in this board's stellaris_board_info struct is wrong. 192 */ 193 g_assert_not_reached(); 194 } 195 } 196 197 static uint64_t ssys_read(void *opaque, hwaddr offset, 198 unsigned size) 199 { 200 ssys_state *s = (ssys_state *)opaque; 201 202 switch (offset) { 203 case 0x000: /* DID0 */ 204 return s->did0; 205 case 0x004: /* DID1 */ 206 return s->did1; 207 case 0x008: /* DC0 */ 208 return s->dc0; 209 case 0x010: /* DC1 */ 210 return s->dc1; 211 case 0x014: /* DC2 */ 212 return s->dc2; 213 case 0x018: /* DC3 */ 214 return s->dc3; 215 case 0x01c: /* DC4 */ 216 return s->dc4; 217 case 0x030: /* PBORCTL */ 218 return s->pborctl; 219 case 0x034: /* LDOPCTL */ 220 return s->ldopctl; 221 case 0x040: /* SRCR0 */ 222 return 0; 223 case 0x044: /* SRCR1 */ 224 return 0; 225 case 0x048: /* SRCR2 */ 226 return 0; 227 case 0x050: /* RIS */ 228 return s->int_status; 229 case 0x054: /* IMC */ 230 return s->int_mask; 231 case 0x058: /* MISC */ 232 return s->int_status & s->int_mask; 233 case 0x05c: /* RESC */ 234 return s->resc; 235 case 0x060: /* RCC */ 236 return s->rcc; 237 case 0x064: /* PLLCFG */ 238 { 239 int xtal; 240 xtal = (s->rcc >> 6) & 0xf; 241 switch (ssys_board_class(s)) { 242 case DID0_CLASS_FURY: 243 return pllcfg_fury[xtal]; 244 case DID0_CLASS_SANDSTORM: 245 return pllcfg_sandstorm[xtal]; 246 default: 247 g_assert_not_reached(); 248 } 249 } 250 case 0x070: /* RCC2 */ 251 return s->rcc2; 252 case 0x100: /* RCGC0 */ 253 return s->rcgc[0]; 254 case 0x104: /* RCGC1 */ 255 return s->rcgc[1]; 256 case 0x108: /* RCGC2 */ 257 return s->rcgc[2]; 258 case 0x110: /* SCGC0 */ 259 return s->scgc[0]; 260 case 0x114: /* SCGC1 */ 261 return s->scgc[1]; 262 case 0x118: /* SCGC2 */ 263 return s->scgc[2]; 264 case 0x120: /* DCGC0 */ 265 return s->dcgc[0]; 266 case 0x124: /* DCGC1 */ 267 return s->dcgc[1]; 268 case 0x128: /* DCGC2 */ 269 return s->dcgc[2]; 270 case 0x150: /* CLKVCLR */ 271 return s->clkvclr; 272 case 0x160: /* LDOARST */ 273 return s->ldoarst; 274 case 0x1e0: /* USER0 */ 275 return s->user0; 276 case 0x1e4: /* USER1 */ 277 return s->user1; 278 default: 279 qemu_log_mask(LOG_GUEST_ERROR, 280 "SSYS: read at bad offset 0x%x\n", (int)offset); 281 return 0; 282 } 283 } 284 285 static bool ssys_use_rcc2(ssys_state *s) 286 { 287 return (s->rcc2 >> 31) & 0x1; 288 } 289 290 /* 291 * Calculate the system clock period. We only want to propagate 292 * this change to the rest of the system if we're not being called 293 * from migration post-load. 294 */ 295 static void ssys_calculate_system_clock(ssys_state *s, bool propagate_clock) 296 { 297 int period_ns; 298 /* 299 * SYSDIV field specifies divisor: 0 == /1, 1 == /2, etc. Input 300 * clock is 200MHz, which is a period of 5 ns. Dividing the clock 301 * frequency by X is the same as multiplying the period by X. 302 */ 303 if (ssys_use_rcc2(s)) { 304 period_ns = 5 * (((s->rcc2 >> 23) & 0x3f) + 1); 305 } else { 306 period_ns = 5 * (((s->rcc >> 23) & 0xf) + 1); 307 } 308 clock_set_ns(s->sysclk, period_ns); 309 if (propagate_clock) { 310 clock_propagate(s->sysclk); 311 } 312 } 313 314 static void ssys_write(void *opaque, hwaddr offset, 315 uint64_t value, unsigned size) 316 { 317 ssys_state *s = (ssys_state *)opaque; 318 319 switch (offset) { 320 case 0x030: /* PBORCTL */ 321 s->pborctl = value & 0xffff; 322 break; 323 case 0x034: /* LDOPCTL */ 324 s->ldopctl = value & 0x1f; 325 break; 326 case 0x040: /* SRCR0 */ 327 case 0x044: /* SRCR1 */ 328 case 0x048: /* SRCR2 */ 329 qemu_log_mask(LOG_UNIMP, "Peripheral reset not implemented\n"); 330 break; 331 case 0x054: /* IMC */ 332 s->int_mask = value & 0x7f; 333 break; 334 case 0x058: /* MISC */ 335 s->int_status &= ~value; 336 break; 337 case 0x05c: /* RESC */ 338 s->resc = value & 0x3f; 339 break; 340 case 0x060: /* RCC */ 341 if ((s->rcc & (1 << 13)) != 0 && (value & (1 << 13)) == 0) { 342 /* PLL enable. */ 343 s->int_status |= (1 << 6); 344 } 345 s->rcc = value; 346 ssys_calculate_system_clock(s, true); 347 break; 348 case 0x070: /* RCC2 */ 349 if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) { 350 break; 351 } 352 353 if ((s->rcc2 & (1 << 13)) != 0 && (value & (1 << 13)) == 0) { 354 /* PLL enable. */ 355 s->int_status |= (1 << 6); 356 } 357 s->rcc2 = value; 358 ssys_calculate_system_clock(s, true); 359 break; 360 case 0x100: /* RCGC0 */ 361 s->rcgc[0] = value; 362 break; 363 case 0x104: /* RCGC1 */ 364 s->rcgc[1] = value; 365 break; 366 case 0x108: /* RCGC2 */ 367 s->rcgc[2] = value; 368 break; 369 case 0x110: /* SCGC0 */ 370 s->scgc[0] = value; 371 break; 372 case 0x114: /* SCGC1 */ 373 s->scgc[1] = value; 374 break; 375 case 0x118: /* SCGC2 */ 376 s->scgc[2] = value; 377 break; 378 case 0x120: /* DCGC0 */ 379 s->dcgc[0] = value; 380 break; 381 case 0x124: /* DCGC1 */ 382 s->dcgc[1] = value; 383 break; 384 case 0x128: /* DCGC2 */ 385 s->dcgc[2] = value; 386 break; 387 case 0x150: /* CLKVCLR */ 388 s->clkvclr = value; 389 break; 390 case 0x160: /* LDOARST */ 391 s->ldoarst = value; 392 break; 393 default: 394 qemu_log_mask(LOG_GUEST_ERROR, 395 "SSYS: write at bad offset 0x%x\n", (int)offset); 396 } 397 ssys_update(s); 398 } 399 400 static const MemoryRegionOps ssys_ops = { 401 .read = ssys_read, 402 .write = ssys_write, 403 .endianness = DEVICE_NATIVE_ENDIAN, 404 }; 405 406 static void stellaris_sys_reset_enter(Object *obj, ResetType type) 407 { 408 ssys_state *s = STELLARIS_SYS(obj); 409 410 s->pborctl = 0x7ffd; 411 s->rcc = 0x078e3ac0; 412 413 if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) { 414 s->rcc2 = 0; 415 } else { 416 s->rcc2 = 0x07802810; 417 } 418 s->rcgc[0] = 1; 419 s->scgc[0] = 1; 420 s->dcgc[0] = 1; 421 } 422 423 static void stellaris_sys_reset_hold(Object *obj, ResetType type) 424 { 425 ssys_state *s = STELLARIS_SYS(obj); 426 427 /* OK to propagate clocks from the hold phase */ 428 ssys_calculate_system_clock(s, true); 429 } 430 431 static void stellaris_sys_reset_exit(Object *obj, ResetType type) 432 { 433 } 434 435 static int stellaris_sys_post_load(void *opaque, int version_id) 436 { 437 ssys_state *s = opaque; 438 439 ssys_calculate_system_clock(s, false); 440 441 return 0; 442 } 443 444 static const VMStateDescription vmstate_stellaris_sys = { 445 .name = "stellaris_sys", 446 .version_id = 2, 447 .minimum_version_id = 1, 448 .post_load = stellaris_sys_post_load, 449 .fields = (const VMStateField[]) { 450 VMSTATE_UINT32(pborctl, ssys_state), 451 VMSTATE_UINT32(ldopctl, ssys_state), 452 VMSTATE_UINT32(int_mask, ssys_state), 453 VMSTATE_UINT32(int_status, ssys_state), 454 VMSTATE_UINT32(resc, ssys_state), 455 VMSTATE_UINT32(rcc, ssys_state), 456 VMSTATE_UINT32_V(rcc2, ssys_state, 2), 457 VMSTATE_UINT32_ARRAY(rcgc, ssys_state, 3), 458 VMSTATE_UINT32_ARRAY(scgc, ssys_state, 3), 459 VMSTATE_UINT32_ARRAY(dcgc, ssys_state, 3), 460 VMSTATE_UINT32(clkvclr, ssys_state), 461 VMSTATE_UINT32(ldoarst, ssys_state), 462 /* No field for sysclk -- handled in post-load instead */ 463 VMSTATE_END_OF_LIST() 464 } 465 }; 466 467 static const Property stellaris_sys_properties[] = { 468 DEFINE_PROP_UINT32("user0", ssys_state, user0, 0), 469 DEFINE_PROP_UINT32("user1", ssys_state, user1, 0), 470 DEFINE_PROP_UINT32("did0", ssys_state, did0, 0), 471 DEFINE_PROP_UINT32("did1", ssys_state, did1, 0), 472 DEFINE_PROP_UINT32("dc0", ssys_state, dc0, 0), 473 DEFINE_PROP_UINT32("dc1", ssys_state, dc1, 0), 474 DEFINE_PROP_UINT32("dc2", ssys_state, dc2, 0), 475 DEFINE_PROP_UINT32("dc3", ssys_state, dc3, 0), 476 DEFINE_PROP_UINT32("dc4", ssys_state, dc4, 0), 477 }; 478 479 static void stellaris_sys_instance_init(Object *obj) 480 { 481 ssys_state *s = STELLARIS_SYS(obj); 482 SysBusDevice *sbd = SYS_BUS_DEVICE(s); 483 484 memory_region_init_io(&s->iomem, obj, &ssys_ops, s, "ssys", 0x00001000); 485 sysbus_init_mmio(sbd, &s->iomem); 486 sysbus_init_irq(sbd, &s->irq); 487 s->sysclk = qdev_init_clock_out(DEVICE(s), "SYSCLK"); 488 } 489 490 /* 491 * I2C controller. 492 * ??? For now we only implement the master interface. 493 */ 494 495 #define TYPE_STELLARIS_I2C "stellaris-i2c" 496 OBJECT_DECLARE_SIMPLE_TYPE(stellaris_i2c_state, STELLARIS_I2C) 497 498 struct stellaris_i2c_state { 499 SysBusDevice parent_obj; 500 501 I2CBus *bus; 502 qemu_irq irq; 503 MemoryRegion iomem; 504 uint32_t msa; 505 uint32_t mcs; 506 uint32_t mdr; 507 uint32_t mtpr; 508 uint32_t mimr; 509 uint32_t mris; 510 uint32_t mcr; 511 }; 512 513 #define STELLARIS_I2C_MCS_BUSY 0x01 514 #define STELLARIS_I2C_MCS_ERROR 0x02 515 #define STELLARIS_I2C_MCS_ADRACK 0x04 516 #define STELLARIS_I2C_MCS_DATACK 0x08 517 #define STELLARIS_I2C_MCS_ARBLST 0x10 518 #define STELLARIS_I2C_MCS_IDLE 0x20 519 #define STELLARIS_I2C_MCS_BUSBSY 0x40 520 521 static uint64_t stellaris_i2c_read(void *opaque, hwaddr offset, 522 unsigned size) 523 { 524 stellaris_i2c_state *s = (stellaris_i2c_state *)opaque; 525 526 switch (offset) { 527 case 0x00: /* MSA */ 528 return s->msa; 529 case 0x04: /* MCS */ 530 /* We don't emulate timing, so the controller is never busy. */ 531 return s->mcs | STELLARIS_I2C_MCS_IDLE; 532 case 0x08: /* MDR */ 533 return s->mdr; 534 case 0x0c: /* MTPR */ 535 return s->mtpr; 536 case 0x10: /* MIMR */ 537 return s->mimr; 538 case 0x14: /* MRIS */ 539 return s->mris; 540 case 0x18: /* MMIS */ 541 return s->mris & s->mimr; 542 case 0x20: /* MCR */ 543 return s->mcr; 544 default: 545 qemu_log_mask(LOG_GUEST_ERROR, 546 "stellaris_i2c: read at bad offset 0x%x\n", (int)offset); 547 return 0; 548 } 549 } 550 551 static void stellaris_i2c_update(stellaris_i2c_state *s) 552 { 553 int level; 554 555 level = (s->mris & s->mimr) != 0; 556 qemu_set_irq(s->irq, level); 557 } 558 559 static void stellaris_i2c_write(void *opaque, hwaddr offset, 560 uint64_t value, unsigned size) 561 { 562 stellaris_i2c_state *s = (stellaris_i2c_state *)opaque; 563 564 switch (offset) { 565 case 0x00: /* MSA */ 566 s->msa = value & 0xff; 567 break; 568 case 0x04: /* MCS */ 569 if ((s->mcr & 0x10) == 0) { 570 /* Disabled. Do nothing. */ 571 break; 572 } 573 /* Grab the bus if this is starting a transfer. */ 574 if ((value & 2) && (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) { 575 if (i2c_start_transfer(s->bus, s->msa >> 1, s->msa & 1)) { 576 s->mcs |= STELLARIS_I2C_MCS_ARBLST; 577 } else { 578 s->mcs &= ~STELLARIS_I2C_MCS_ARBLST; 579 s->mcs |= STELLARIS_I2C_MCS_BUSBSY; 580 } 581 } 582 /* If we don't have the bus then indicate an error. */ 583 if (!i2c_bus_busy(s->bus) 584 || (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) { 585 s->mcs |= STELLARIS_I2C_MCS_ERROR; 586 break; 587 } 588 s->mcs &= ~STELLARIS_I2C_MCS_ERROR; 589 if (value & 1) { 590 /* Transfer a byte. */ 591 /* TODO: Handle errors. */ 592 if (s->msa & 1) { 593 /* Recv */ 594 s->mdr = i2c_recv(s->bus); 595 } else { 596 /* Send */ 597 i2c_send(s->bus, s->mdr); 598 } 599 /* Raise an interrupt. */ 600 s->mris |= 1; 601 } 602 if (value & 4) { 603 /* Finish transfer. */ 604 i2c_end_transfer(s->bus); 605 s->mcs &= ~STELLARIS_I2C_MCS_BUSBSY; 606 } 607 break; 608 case 0x08: /* MDR */ 609 s->mdr = value & 0xff; 610 break; 611 case 0x0c: /* MTPR */ 612 s->mtpr = value & 0xff; 613 break; 614 case 0x10: /* MIMR */ 615 s->mimr = 1; 616 break; 617 case 0x1c: /* MICR */ 618 s->mris &= ~value; 619 break; 620 case 0x20: /* MCR */ 621 if (value & 1) { 622 qemu_log_mask(LOG_UNIMP, 623 "stellaris_i2c: Loopback not implemented\n"); 624 } 625 if (value & 0x20) { 626 qemu_log_mask(LOG_UNIMP, 627 "stellaris_i2c: Slave mode not implemented\n"); 628 } 629 s->mcr = value & 0x31; 630 break; 631 default: 632 qemu_log_mask(LOG_GUEST_ERROR, 633 "stellaris_i2c: write at bad offset 0x%x\n", (int)offset); 634 } 635 stellaris_i2c_update(s); 636 } 637 638 static void stellaris_i2c_reset_enter(Object *obj, ResetType type) 639 { 640 stellaris_i2c_state *s = STELLARIS_I2C(obj); 641 642 if (s->mcs & STELLARIS_I2C_MCS_BUSBSY) 643 i2c_end_transfer(s->bus); 644 } 645 646 static void stellaris_i2c_reset_hold(Object *obj, ResetType type) 647 { 648 stellaris_i2c_state *s = STELLARIS_I2C(obj); 649 650 s->msa = 0; 651 s->mcs = 0; 652 s->mdr = 0; 653 s->mtpr = 1; 654 s->mimr = 0; 655 s->mris = 0; 656 s->mcr = 0; 657 } 658 659 static void stellaris_i2c_reset_exit(Object *obj, ResetType type) 660 { 661 stellaris_i2c_state *s = STELLARIS_I2C(obj); 662 663 stellaris_i2c_update(s); 664 } 665 666 static const MemoryRegionOps stellaris_i2c_ops = { 667 .read = stellaris_i2c_read, 668 .write = stellaris_i2c_write, 669 .endianness = DEVICE_NATIVE_ENDIAN, 670 }; 671 672 static const VMStateDescription vmstate_stellaris_i2c = { 673 .name = "stellaris_i2c", 674 .version_id = 1, 675 .minimum_version_id = 1, 676 .fields = (const VMStateField[]) { 677 VMSTATE_UINT32(msa, stellaris_i2c_state), 678 VMSTATE_UINT32(mcs, stellaris_i2c_state), 679 VMSTATE_UINT32(mdr, stellaris_i2c_state), 680 VMSTATE_UINT32(mtpr, stellaris_i2c_state), 681 VMSTATE_UINT32(mimr, stellaris_i2c_state), 682 VMSTATE_UINT32(mris, stellaris_i2c_state), 683 VMSTATE_UINT32(mcr, stellaris_i2c_state), 684 VMSTATE_END_OF_LIST() 685 } 686 }; 687 688 static void stellaris_i2c_init(Object *obj) 689 { 690 DeviceState *dev = DEVICE(obj); 691 stellaris_i2c_state *s = STELLARIS_I2C(obj); 692 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 693 I2CBus *bus; 694 695 sysbus_init_irq(sbd, &s->irq); 696 bus = i2c_init_bus(dev, "i2c"); 697 s->bus = bus; 698 699 memory_region_init_io(&s->iomem, obj, &stellaris_i2c_ops, s, 700 "i2c", 0x1000); 701 sysbus_init_mmio(sbd, &s->iomem); 702 } 703 704 /* Analogue to Digital Converter. This is only partially implemented, 705 enough for applications that use a combined ADC and timer tick. */ 706 707 #define STELLARIS_ADC_EM_CONTROLLER 0 708 #define STELLARIS_ADC_EM_COMP 1 709 #define STELLARIS_ADC_EM_EXTERNAL 4 710 #define STELLARIS_ADC_EM_TIMER 5 711 #define STELLARIS_ADC_EM_PWM0 6 712 #define STELLARIS_ADC_EM_PWM1 7 713 #define STELLARIS_ADC_EM_PWM2 8 714 715 #define STELLARIS_ADC_FIFO_EMPTY 0x0100 716 #define STELLARIS_ADC_FIFO_FULL 0x1000 717 718 #define TYPE_STELLARIS_ADC "stellaris-adc" 719 typedef struct StellarisADCState StellarisADCState; 720 DECLARE_INSTANCE_CHECKER(StellarisADCState, STELLARIS_ADC, TYPE_STELLARIS_ADC) 721 722 struct StellarisADCState { 723 SysBusDevice parent_obj; 724 725 MemoryRegion iomem; 726 uint32_t actss; 727 uint32_t ris; 728 uint32_t im; 729 uint32_t emux; 730 uint32_t ostat; 731 uint32_t ustat; 732 uint32_t sspri; 733 uint32_t sac; 734 struct { 735 uint32_t state; 736 uint32_t data[16]; 737 } fifo[4]; 738 uint32_t ssmux[4]; 739 uint32_t ssctl[4]; 740 uint32_t noise; 741 qemu_irq irq[4]; 742 }; 743 744 static uint32_t stellaris_adc_fifo_read(StellarisADCState *s, int n) 745 { 746 int tail; 747 748 tail = s->fifo[n].state & 0xf; 749 if (s->fifo[n].state & STELLARIS_ADC_FIFO_EMPTY) { 750 s->ustat |= 1 << n; 751 } else { 752 s->fifo[n].state = (s->fifo[n].state & ~0xf) | ((tail + 1) & 0xf); 753 s->fifo[n].state &= ~STELLARIS_ADC_FIFO_FULL; 754 if (tail + 1 == ((s->fifo[n].state >> 4) & 0xf)) 755 s->fifo[n].state |= STELLARIS_ADC_FIFO_EMPTY; 756 } 757 return s->fifo[n].data[tail]; 758 } 759 760 static void stellaris_adc_fifo_write(StellarisADCState *s, int n, 761 uint32_t value) 762 { 763 int head; 764 765 /* TODO: Real hardware has limited size FIFOs. We have a full 16 entry 766 FIFO fir each sequencer. */ 767 head = (s->fifo[n].state >> 4) & 0xf; 768 if (s->fifo[n].state & STELLARIS_ADC_FIFO_FULL) { 769 s->ostat |= 1 << n; 770 return; 771 } 772 s->fifo[n].data[head] = value; 773 head = (head + 1) & 0xf; 774 s->fifo[n].state &= ~STELLARIS_ADC_FIFO_EMPTY; 775 s->fifo[n].state = (s->fifo[n].state & ~0xf0) | (head << 4); 776 if ((s->fifo[n].state & 0xf) == head) 777 s->fifo[n].state |= STELLARIS_ADC_FIFO_FULL; 778 } 779 780 static void stellaris_adc_update(StellarisADCState *s) 781 { 782 int level; 783 int n; 784 785 for (n = 0; n < 4; n++) { 786 level = (s->ris & s->im & (1 << n)) != 0; 787 qemu_set_irq(s->irq[n], level); 788 } 789 } 790 791 static void stellaris_adc_trigger(void *opaque, int irq, int level) 792 { 793 StellarisADCState *s = opaque; 794 int n; 795 796 for (n = 0; n < 4; n++) { 797 if ((s->actss & (1 << n)) == 0) { 798 continue; 799 } 800 801 if (((s->emux >> (n * 4)) & 0xff) != 5) { 802 continue; 803 } 804 805 /* Some applications use the ADC as a random number source, so introduce 806 some variation into the signal. */ 807 s->noise = s->noise * 314159 + 1; 808 /* ??? actual inputs not implemented. Return an arbitrary value. */ 809 stellaris_adc_fifo_write(s, n, 0x200 + ((s->noise >> 16) & 7)); 810 s->ris |= (1 << n); 811 stellaris_adc_update(s); 812 } 813 } 814 815 static void stellaris_adc_reset_hold(Object *obj, ResetType type) 816 { 817 StellarisADCState *s = STELLARIS_ADC(obj); 818 int n; 819 820 for (n = 0; n < 4; n++) { 821 s->ssmux[n] = 0; 822 s->ssctl[n] = 0; 823 s->fifo[n].state = STELLARIS_ADC_FIFO_EMPTY; 824 } 825 } 826 827 static uint64_t stellaris_adc_read(void *opaque, hwaddr offset, 828 unsigned size) 829 { 830 StellarisADCState *s = opaque; 831 832 /* TODO: Implement this. */ 833 if (offset >= 0x40 && offset < 0xc0) { 834 int n; 835 n = (offset - 0x40) >> 5; 836 switch (offset & 0x1f) { 837 case 0x00: /* SSMUX */ 838 return s->ssmux[n]; 839 case 0x04: /* SSCTL */ 840 return s->ssctl[n]; 841 case 0x08: /* SSFIFO */ 842 return stellaris_adc_fifo_read(s, n); 843 case 0x0c: /* SSFSTAT */ 844 return s->fifo[n].state; 845 default: 846 break; 847 } 848 } 849 switch (offset) { 850 case 0x00: /* ACTSS */ 851 return s->actss; 852 case 0x04: /* RIS */ 853 return s->ris; 854 case 0x08: /* IM */ 855 return s->im; 856 case 0x0c: /* ISC */ 857 return s->ris & s->im; 858 case 0x10: /* OSTAT */ 859 return s->ostat; 860 case 0x14: /* EMUX */ 861 return s->emux; 862 case 0x18: /* USTAT */ 863 return s->ustat; 864 case 0x20: /* SSPRI */ 865 return s->sspri; 866 case 0x30: /* SAC */ 867 return s->sac; 868 default: 869 qemu_log_mask(LOG_GUEST_ERROR, 870 "stellaris_adc: read at bad offset 0x%x\n", (int)offset); 871 return 0; 872 } 873 } 874 875 static void stellaris_adc_write(void *opaque, hwaddr offset, 876 uint64_t value, unsigned size) 877 { 878 StellarisADCState *s = opaque; 879 880 /* TODO: Implement this. */ 881 if (offset >= 0x40 && offset < 0xc0) { 882 int n; 883 n = (offset - 0x40) >> 5; 884 switch (offset & 0x1f) { 885 case 0x00: /* SSMUX */ 886 s->ssmux[n] = value & 0x33333333; 887 return; 888 case 0x04: /* SSCTL */ 889 if (value != 6) { 890 qemu_log_mask(LOG_UNIMP, 891 "ADC: Unimplemented sequence %" PRIx64 "\n", 892 value); 893 } 894 s->ssctl[n] = value; 895 return; 896 default: 897 break; 898 } 899 } 900 switch (offset) { 901 case 0x00: /* ACTSS */ 902 s->actss = value & 0xf; 903 break; 904 case 0x08: /* IM */ 905 s->im = value; 906 break; 907 case 0x0c: /* ISC */ 908 s->ris &= ~value; 909 break; 910 case 0x10: /* OSTAT */ 911 s->ostat &= ~value; 912 break; 913 case 0x14: /* EMUX */ 914 s->emux = value; 915 break; 916 case 0x18: /* USTAT */ 917 s->ustat &= ~value; 918 break; 919 case 0x20: /* SSPRI */ 920 s->sspri = value; 921 break; 922 case 0x28: /* PSSI */ 923 qemu_log_mask(LOG_UNIMP, "ADC: sample initiate unimplemented\n"); 924 break; 925 case 0x30: /* SAC */ 926 s->sac = value; 927 break; 928 default: 929 qemu_log_mask(LOG_GUEST_ERROR, 930 "stellaris_adc: write at bad offset 0x%x\n", (int)offset); 931 } 932 stellaris_adc_update(s); 933 } 934 935 static const MemoryRegionOps stellaris_adc_ops = { 936 .read = stellaris_adc_read, 937 .write = stellaris_adc_write, 938 .endianness = DEVICE_NATIVE_ENDIAN, 939 }; 940 941 static const VMStateDescription vmstate_stellaris_adc = { 942 .name = "stellaris_adc", 943 .version_id = 1, 944 .minimum_version_id = 1, 945 .fields = (const VMStateField[]) { 946 VMSTATE_UINT32(actss, StellarisADCState), 947 VMSTATE_UINT32(ris, StellarisADCState), 948 VMSTATE_UINT32(im, StellarisADCState), 949 VMSTATE_UINT32(emux, StellarisADCState), 950 VMSTATE_UINT32(ostat, StellarisADCState), 951 VMSTATE_UINT32(ustat, StellarisADCState), 952 VMSTATE_UINT32(sspri, StellarisADCState), 953 VMSTATE_UINT32(sac, StellarisADCState), 954 VMSTATE_UINT32(fifo[0].state, StellarisADCState), 955 VMSTATE_UINT32_ARRAY(fifo[0].data, StellarisADCState, 16), 956 VMSTATE_UINT32(ssmux[0], StellarisADCState), 957 VMSTATE_UINT32(ssctl[0], StellarisADCState), 958 VMSTATE_UINT32(fifo[1].state, StellarisADCState), 959 VMSTATE_UINT32_ARRAY(fifo[1].data, StellarisADCState, 16), 960 VMSTATE_UINT32(ssmux[1], StellarisADCState), 961 VMSTATE_UINT32(ssctl[1], StellarisADCState), 962 VMSTATE_UINT32(fifo[2].state, StellarisADCState), 963 VMSTATE_UINT32_ARRAY(fifo[2].data, StellarisADCState, 16), 964 VMSTATE_UINT32(ssmux[2], StellarisADCState), 965 VMSTATE_UINT32(ssctl[2], StellarisADCState), 966 VMSTATE_UINT32(fifo[3].state, StellarisADCState), 967 VMSTATE_UINT32_ARRAY(fifo[3].data, StellarisADCState, 16), 968 VMSTATE_UINT32(ssmux[3], StellarisADCState), 969 VMSTATE_UINT32(ssctl[3], StellarisADCState), 970 VMSTATE_UINT32(noise, StellarisADCState), 971 VMSTATE_END_OF_LIST() 972 } 973 }; 974 975 static void stellaris_adc_init(Object *obj) 976 { 977 DeviceState *dev = DEVICE(obj); 978 StellarisADCState *s = STELLARIS_ADC(obj); 979 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 980 int n; 981 982 for (n = 0; n < 4; n++) { 983 sysbus_init_irq(sbd, &s->irq[n]); 984 } 985 986 memory_region_init_io(&s->iomem, obj, &stellaris_adc_ops, s, 987 "adc", 0x1000); 988 sysbus_init_mmio(sbd, &s->iomem); 989 qdev_init_gpio_in(dev, stellaris_adc_trigger, 1); 990 } 991 992 /* Board init. */ 993 static const stellaris_board_info stellaris_boards[] = { 994 { "LM3S811EVB", 995 0, 996 0x0032000e, 997 0x001f001f, /* dc0 */ 998 0x001132bf, 999 0x01071013, 1000 0x3f0f01ff, 1001 0x0000001f, 1002 BP_OLED_I2C 1003 }, 1004 { "LM3S6965EVB", 1005 0x10010002, 1006 0x1073402e, 1007 0x00ff007f, /* dc0 */ 1008 0x001133ff, 1009 0x030f5317, 1010 0x0f0f87ff, 1011 0x5000007f, 1012 BP_OLED_SSI | BP_GAMEPAD 1013 } 1014 }; 1015 1016 static void stellaris_init(MachineState *ms, stellaris_board_info *board) 1017 { 1018 static const int uart_irq[NUM_UART] = {5, 6, 33, 34}; 1019 static const int timer_irq[NUM_GPTM] = {19, 21, 23, 35}; 1020 static const uint32_t gpio_addr[NUM_GPIO] = 1021 { 0x40004000, 0x40005000, 0x40006000, 0x40007000, 1022 0x40024000, 0x40025000, 0x40026000}; 1023 static const int gpio_irq[NUM_GPIO] = {0, 1, 2, 3, 4, 30, 31}; 1024 1025 /* Memory map of SoC devices, from 1026 * Stellaris LM3S6965 Microcontroller Data Sheet (rev I) 1027 * http://www.ti.com/lit/ds/symlink/lm3s6965.pdf 1028 * 1029 * 40000000 wdtimer 1030 * 40004000 GPIO 1031 * 40005000 GPIO 1032 * 40006000 GPIO 1033 * 40007000 GPIO 1034 * 40008000 SSI 1035 * 4000c000 UART 1036 * 4000d000 UART 1037 * 4000e000 UART 1038 * 40020000 i2c 1039 * 40021000 i2c (unimplemented) 1040 * 40024000 GPIO 1041 * 40025000 GPIO 1042 * 40026000 GPIO 1043 * 40028000 PWM (unimplemented) 1044 * 4002c000 QEI (unimplemented) 1045 * 4002d000 QEI (unimplemented) 1046 * 40030000 gptimer 1047 * 40031000 gptimer 1048 * 40032000 gptimer 1049 * 40033000 gptimer 1050 * 40038000 ADC 1051 * 4003c000 analogue comparator (unimplemented) 1052 * 40048000 ethernet 1053 * 400fc000 hibernation module (unimplemented) 1054 * 400fd000 flash memory control (unimplemented) 1055 * 400fe000 system control 1056 */ 1057 1058 Object *soc_container; 1059 DeviceState *gpio_dev[NUM_GPIO], *armv7m, *nvic; 1060 qemu_irq gpio_in[NUM_GPIO][8]; 1061 qemu_irq gpio_out[NUM_GPIO][8]; 1062 qemu_irq adc; 1063 int sram_size; 1064 int flash_size; 1065 I2CBus *i2c; 1066 DeviceState *dev; 1067 DeviceState *ssys_dev; 1068 int i; 1069 int j; 1070 NICInfo *nd; 1071 MACAddr mac; 1072 1073 MemoryRegion *sram = g_new(MemoryRegion, 1); 1074 MemoryRegion *flash = g_new(MemoryRegion, 1); 1075 MemoryRegion *system_memory = get_system_memory(); 1076 1077 flash_size = (((board->dc0 & 0xffff) + 1) << 1) * 1024; 1078 sram_size = ((board->dc0 >> 18) + 1) * 1024; 1079 1080 soc_container = object_new(TYPE_CONTAINER); 1081 object_property_add_child(OBJECT(ms), "soc", soc_container); 1082 1083 /* Flash programming is done via the SCU, so pretend it is ROM. */ 1084 memory_region_init_rom(flash, NULL, "stellaris.flash", flash_size, 1085 &error_fatal); 1086 memory_region_add_subregion(system_memory, 0, flash); 1087 1088 memory_region_init_ram(sram, NULL, "stellaris.sram", sram_size, 1089 &error_fatal); 1090 memory_region_add_subregion(system_memory, 0x20000000, sram); 1091 1092 /* 1093 * Create the system-registers object early, because we will 1094 * need its sysclk output. 1095 */ 1096 ssys_dev = qdev_new(TYPE_STELLARIS_SYS); 1097 object_property_add_child(soc_container, "sys", OBJECT(ssys_dev)); 1098 1099 /* 1100 * Most devices come preprogrammed with a MAC address in the user data. 1101 * Generate a MAC address now, if there isn't a matching -nic for it. 1102 */ 1103 nd = qemu_find_nic_info("stellaris_enet", true, "stellaris"); 1104 if (nd) { 1105 memcpy(mac.a, nd->macaddr.a, sizeof(mac.a)); 1106 } else { 1107 qemu_macaddr_default_if_unset(&mac); 1108 } 1109 1110 qdev_prop_set_uint32(ssys_dev, "user0", 1111 mac.a[0] | (mac.a[1] << 8) | (mac.a[2] << 16)); 1112 qdev_prop_set_uint32(ssys_dev, "user1", 1113 mac.a[3] | (mac.a[4] << 8) | (mac.a[5] << 16)); 1114 qdev_prop_set_uint32(ssys_dev, "did0", board->did0); 1115 qdev_prop_set_uint32(ssys_dev, "did1", board->did1); 1116 qdev_prop_set_uint32(ssys_dev, "dc0", board->dc0); 1117 qdev_prop_set_uint32(ssys_dev, "dc1", board->dc1); 1118 qdev_prop_set_uint32(ssys_dev, "dc2", board->dc2); 1119 qdev_prop_set_uint32(ssys_dev, "dc3", board->dc3); 1120 qdev_prop_set_uint32(ssys_dev, "dc4", board->dc4); 1121 sysbus_realize_and_unref(SYS_BUS_DEVICE(ssys_dev), &error_fatal); 1122 1123 armv7m = qdev_new(TYPE_ARMV7M); 1124 object_property_add_child(soc_container, "v7m", OBJECT(armv7m)); 1125 qdev_prop_set_uint32(armv7m, "num-irq", NUM_IRQ_LINES); 1126 qdev_prop_set_uint8(armv7m, "num-prio-bits", NUM_PRIO_BITS); 1127 qdev_prop_set_string(armv7m, "cpu-type", ms->cpu_type); 1128 qdev_prop_set_bit(armv7m, "enable-bitband", true); 1129 qdev_connect_clock_in(armv7m, "cpuclk", 1130 qdev_get_clock_out(ssys_dev, "SYSCLK")); 1131 /* This SoC does not connect the systick reference clock */ 1132 object_property_set_link(OBJECT(armv7m), "memory", 1133 OBJECT(get_system_memory()), &error_abort); 1134 /* This will exit with an error if the user passed us a bad cpu_type */ 1135 sysbus_realize_and_unref(SYS_BUS_DEVICE(armv7m), &error_fatal); 1136 nvic = armv7m; 1137 1138 /* Now we can wire up the IRQ and MMIO of the system registers */ 1139 sysbus_mmio_map(SYS_BUS_DEVICE(ssys_dev), 0, 0x400fe000); 1140 sysbus_connect_irq(SYS_BUS_DEVICE(ssys_dev), 0, qdev_get_gpio_in(nvic, 28)); 1141 1142 if (DEV_CAP(1, ADC)) { 1143 dev = sysbus_create_varargs(TYPE_STELLARIS_ADC, 0x40038000, 1144 qdev_get_gpio_in(nvic, 14), 1145 qdev_get_gpio_in(nvic, 15), 1146 qdev_get_gpio_in(nvic, 16), 1147 qdev_get_gpio_in(nvic, 17), 1148 NULL); 1149 adc = qdev_get_gpio_in(dev, 0); 1150 } else { 1151 adc = NULL; 1152 } 1153 for (i = 0; i < NUM_GPTM; i++) { 1154 if (DEV_CAP(2, GPTM(i))) { 1155 SysBusDevice *sbd; 1156 1157 dev = qdev_new(TYPE_STELLARIS_GPTM); 1158 sbd = SYS_BUS_DEVICE(dev); 1159 object_property_add_child(soc_container, "gptm[*]", OBJECT(dev)); 1160 qdev_connect_clock_in(dev, "clk", 1161 qdev_get_clock_out(ssys_dev, "SYSCLK")); 1162 sysbus_realize_and_unref(sbd, &error_fatal); 1163 sysbus_mmio_map(sbd, 0, 0x40030000 + i * 0x1000); 1164 sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(nvic, timer_irq[i])); 1165 /* TODO: This is incorrect, but we get away with it because 1166 the ADC output is only ever pulsed. */ 1167 qdev_connect_gpio_out(dev, 0, adc); 1168 } 1169 } 1170 1171 if (DEV_CAP(1, WDT)) { 1172 dev = qdev_new(TYPE_LUMINARY_WATCHDOG); 1173 object_property_add_child(soc_container, "wdg", OBJECT(dev)); 1174 qdev_connect_clock_in(dev, "WDOGCLK", 1175 qdev_get_clock_out(ssys_dev, "SYSCLK")); 1176 1177 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1178 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1179 0, 1180 0x40000000u); 1181 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1182 0, 1183 qdev_get_gpio_in(nvic, 18)); 1184 } 1185 1186 1187 for (i = 0; i < NUM_GPIO; i++) { 1188 if (DEV_CAP(4, GPIO(i))) { 1189 gpio_dev[i] = sysbus_create_simple("pl061_luminary", gpio_addr[i], 1190 qdev_get_gpio_in(nvic, 1191 gpio_irq[i])); 1192 for (j = 0; j < 8; j++) { 1193 gpio_in[i][j] = qdev_get_gpio_in(gpio_dev[i], j); 1194 gpio_out[i][j] = NULL; 1195 } 1196 } 1197 } 1198 1199 if (DEV_CAP(2, I2C(0))) { 1200 dev = sysbus_create_simple(TYPE_STELLARIS_I2C, 0x40020000, 1201 qdev_get_gpio_in(nvic, 8)); 1202 i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c"); 1203 if (board->peripherals & BP_OLED_I2C) { 1204 i2c_slave_create_simple(i2c, "ssd0303", 0x3d); 1205 } 1206 } 1207 1208 for (i = 0; i < NUM_UART; i++) { 1209 if (DEV_CAP(2, UART(i))) { 1210 SysBusDevice *sbd; 1211 1212 dev = qdev_new("pl011_luminary"); 1213 object_property_add_child(soc_container, "uart[*]", OBJECT(dev)); 1214 sbd = SYS_BUS_DEVICE(dev); 1215 qdev_prop_set_chr(dev, "chardev", serial_hd(i)); 1216 sysbus_realize_and_unref(sbd, &error_fatal); 1217 sysbus_mmio_map(sbd, 0, 0x4000c000 + i * 0x1000); 1218 sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(nvic, uart_irq[i])); 1219 } 1220 } 1221 if (DEV_CAP(2, SSI)) { 1222 dev = sysbus_create_simple("pl022", 0x40008000, 1223 qdev_get_gpio_in(nvic, 7)); 1224 if (board->peripherals & BP_OLED_SSI) { 1225 void *bus; 1226 DeviceState *sddev; 1227 DeviceState *ssddev; 1228 DriveInfo *dinfo; 1229 DeviceState *carddev; 1230 DeviceState *gpio_d_splitter; 1231 BlockBackend *blk; 1232 1233 /* 1234 * Some boards have both an OLED controller and SD card connected to 1235 * the same SSI port, with the SD card chip select connected to a 1236 * GPIO pin. Technically the OLED chip select is connected to the 1237 * SSI Fss pin. We do not bother emulating that as both devices 1238 * should never be selected simultaneously, and our OLED controller 1239 * ignores stray 0xff commands that occur when deselecting the SD 1240 * card. 1241 * 1242 * The h/w wiring is: 1243 * - GPIO pin D0 is wired to the active-low SD card chip select 1244 * - GPIO pin A3 is wired to the active-low OLED chip select 1245 * - The SoC wiring of the PL061 "auxiliary function" for A3 is 1246 * SSI0Fss ("frame signal"), which is an output from the SoC's 1247 * SSI controller. The SSI controller takes SSI0Fss low when it 1248 * transmits a frame, so it can work as a chip-select signal. 1249 * - GPIO A4 is aux-function SSI0Rx, and wired to the SD card Tx 1250 * (the OLED never sends data to the CPU, so no wiring needed) 1251 * - GPIO A5 is aux-function SSI0Tx, and wired to the SD card Rx 1252 * and the OLED display-data-in 1253 * - GPIO A2 is aux-function SSI0Clk, wired to SD card and OLED 1254 * serial-clock input 1255 * So a guest that wants to use the OLED can configure the PL061 1256 * to make pins A2, A3, A5 aux-function, so they are connected 1257 * directly to the SSI controller. When the SSI controller sends 1258 * data it asserts SSI0Fss which selects the OLED. 1259 * A guest that wants to use the SD card configures A2, A4 and A5 1260 * as aux-function, but leaves A3 as a software-controlled GPIO 1261 * line. It asserts the SD card chip-select by using the PL061 1262 * to control pin D0, and lets the SSI controller handle Clk, Tx 1263 * and Rx. (The SSI controller asserts Fss during tx cycles as 1264 * usual, but because A3 is not set to aux-function this is not 1265 * forwarded to the OLED, and so the OLED stays unselected.) 1266 * 1267 * The QEMU implementation instead is: 1268 * - GPIO pin D0 is wired to the active-low SD card chip select, 1269 * and also to the OLED chip-select which is implemented 1270 * as *active-high* 1271 * - SSI controller signals go to the devices regardless of 1272 * whether the guest programs A2, A4, A5 as aux-function or not 1273 * 1274 * The problem with this implementation is if the guest doesn't 1275 * care about the SD card and only uses the OLED. In that case it 1276 * may choose never to do anything with D0 (leaving it in its 1277 * default floating state, which reliably leaves the card disabled 1278 * because an SD card has a pullup on CS within the card itself), 1279 * and only set up A2, A3, A5. This for us would mean the OLED 1280 * never gets the chip-select assert it needs. We work around 1281 * this with a manual raise of D0 here (despite board creation 1282 * code being the wrong place to raise IRQ lines) to put the OLED 1283 * into an initially selected state. 1284 * 1285 * In theory the right way to model this would be: 1286 * - Implement aux-function support in the PL061, with an 1287 * extra set of AFIN and AFOUT GPIO lines (set up so that 1288 * if a GPIO line is in auxfn mode the main GPIO in and out 1289 * track the AFIN and AFOUT lines) 1290 * - Wire the AFOUT for D0 up to either a line from the 1291 * SSI controller that's pulled low around every transmit, 1292 * or at least to an always-0 line here on the board 1293 * - Make the ssd0323 OLED controller chipselect active-low 1294 */ 1295 bus = qdev_get_child_bus(dev, "ssi"); 1296 sddev = ssi_create_peripheral(bus, "ssi-sd"); 1297 1298 dinfo = drive_get(IF_SD, 0, 0); 1299 blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL; 1300 carddev = qdev_new(TYPE_SD_CARD_SPI); 1301 qdev_prop_set_drive_err(carddev, "drive", blk, &error_fatal); 1302 qdev_realize_and_unref(carddev, 1303 qdev_get_child_bus(sddev, "sd-bus"), 1304 &error_fatal); 1305 1306 ssddev = qdev_new("ssd0323"); 1307 object_property_add_child(OBJECT(ms), "oled", OBJECT(ssddev)); 1308 qdev_prop_set_uint8(ssddev, "cs", 1); 1309 qdev_realize_and_unref(ssddev, bus, &error_fatal); 1310 1311 gpio_d_splitter = qdev_new(TYPE_SPLIT_IRQ); 1312 object_property_add_child(OBJECT(ms), "splitter", 1313 OBJECT(gpio_d_splitter)); 1314 qdev_prop_set_uint32(gpio_d_splitter, "num-lines", 2); 1315 qdev_realize_and_unref(gpio_d_splitter, NULL, &error_fatal); 1316 qdev_connect_gpio_out( 1317 gpio_d_splitter, 0, 1318 qdev_get_gpio_in_named(sddev, SSI_GPIO_CS, 0)); 1319 qdev_connect_gpio_out( 1320 gpio_d_splitter, 1, 1321 qdev_get_gpio_in_named(ssddev, SSI_GPIO_CS, 0)); 1322 gpio_out[GPIO_D][0] = qdev_get_gpio_in(gpio_d_splitter, 0); 1323 1324 gpio_out[GPIO_C][7] = qdev_get_gpio_in(ssddev, 0); 1325 1326 /* Make sure the select pin is high. */ 1327 qemu_irq_raise(gpio_out[GPIO_D][0]); 1328 } 1329 } 1330 if (DEV_CAP(4, EMAC)) { 1331 DeviceState *enet; 1332 1333 enet = qdev_new("stellaris_enet"); 1334 object_property_add_child(soc_container, "enet", OBJECT(enet)); 1335 if (nd) { 1336 qdev_set_nic_properties(enet, nd); 1337 } else { 1338 qdev_prop_set_macaddr(enet, "mac", mac.a); 1339 } 1340 1341 sysbus_realize_and_unref(SYS_BUS_DEVICE(enet), &error_fatal); 1342 sysbus_mmio_map(SYS_BUS_DEVICE(enet), 0, 0x40048000); 1343 sysbus_connect_irq(SYS_BUS_DEVICE(enet), 0, qdev_get_gpio_in(nvic, 42)); 1344 } 1345 if (board->peripherals & BP_GAMEPAD) { 1346 QList *gpad_keycode_list = qlist_new(); 1347 static const int gpad_keycode[5] = { 1348 Q_KEY_CODE_UP, Q_KEY_CODE_DOWN, Q_KEY_CODE_LEFT, 1349 Q_KEY_CODE_RIGHT, Q_KEY_CODE_CTRL, 1350 }; 1351 DeviceState *gpad; 1352 1353 gpad = qdev_new(TYPE_STELLARIS_GAMEPAD); 1354 object_property_add_child(OBJECT(ms), "gamepad", OBJECT(gpad)); 1355 for (i = 0; i < ARRAY_SIZE(gpad_keycode); i++) { 1356 qlist_append_int(gpad_keycode_list, gpad_keycode[i]); 1357 } 1358 qdev_prop_set_array(gpad, "keycodes", gpad_keycode_list); 1359 sysbus_realize_and_unref(SYS_BUS_DEVICE(gpad), &error_fatal); 1360 1361 qdev_connect_gpio_out(gpad, 0, 1362 qemu_irq_invert(gpio_in[GPIO_E][0])); /* up */ 1363 qdev_connect_gpio_out(gpad, 1, 1364 qemu_irq_invert(gpio_in[GPIO_E][1])); /* down */ 1365 qdev_connect_gpio_out(gpad, 2, 1366 qemu_irq_invert(gpio_in[GPIO_E][2])); /* left */ 1367 qdev_connect_gpio_out(gpad, 3, 1368 qemu_irq_invert(gpio_in[GPIO_E][3])); /* right */ 1369 qdev_connect_gpio_out(gpad, 4, 1370 qemu_irq_invert(gpio_in[GPIO_F][1])); /* select */ 1371 } 1372 for (i = 0; i < 7; i++) { 1373 if (board->dc4 & (1 << i)) { 1374 for (j = 0; j < 8; j++) { 1375 if (gpio_out[i][j]) { 1376 qdev_connect_gpio_out(gpio_dev[i], j, gpio_out[i][j]); 1377 } 1378 } 1379 } 1380 } 1381 1382 /* Add dummy regions for the devices we don't implement yet, 1383 * so guest accesses don't cause unlogged crashes. 1384 */ 1385 create_unimplemented_device("i2c-2", 0x40021000, 0x1000); 1386 create_unimplemented_device("PWM", 0x40028000, 0x1000); 1387 create_unimplemented_device("QEI-0", 0x4002c000, 0x1000); 1388 create_unimplemented_device("QEI-1", 0x4002d000, 0x1000); 1389 create_unimplemented_device("analogue-comparator", 0x4003c000, 0x1000); 1390 create_unimplemented_device("hibernation", 0x400fc000, 0x1000); 1391 create_unimplemented_device("flash-control", 0x400fd000, 0x1000); 1392 1393 armv7m_load_kernel(ARMV7M(armv7m)->cpu, ms->kernel_filename, 0, flash_size); 1394 } 1395 1396 /* FIXME: Figure out how to generate these from stellaris_boards. */ 1397 static void lm3s811evb_init(MachineState *machine) 1398 { 1399 stellaris_init(machine, &stellaris_boards[0]); 1400 } 1401 1402 static void lm3s6965evb_init(MachineState *machine) 1403 { 1404 stellaris_init(machine, &stellaris_boards[1]); 1405 } 1406 1407 /* 1408 * Stellaris LM3S811 Evaluation Board Schematics: 1409 * https://www.ti.com/lit/ug/symlink/spmu030.pdf 1410 */ 1411 static void lm3s811evb_class_init(ObjectClass *oc, void *data) 1412 { 1413 MachineClass *mc = MACHINE_CLASS(oc); 1414 1415 mc->desc = "Stellaris LM3S811EVB (Cortex-M3)"; 1416 mc->init = lm3s811evb_init; 1417 mc->ignore_memory_transaction_failures = true; 1418 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3"); 1419 } 1420 1421 static const TypeInfo lm3s811evb_type = { 1422 .name = MACHINE_TYPE_NAME("lm3s811evb"), 1423 .parent = TYPE_MACHINE, 1424 .class_init = lm3s811evb_class_init, 1425 }; 1426 1427 /* 1428 * Stellaris: LM3S6965 Evaluation Board Schematics: 1429 * https://www.ti.com/lit/ug/symlink/spmu029.pdf 1430 */ 1431 static void lm3s6965evb_class_init(ObjectClass *oc, void *data) 1432 { 1433 MachineClass *mc = MACHINE_CLASS(oc); 1434 1435 mc->desc = "Stellaris LM3S6965EVB (Cortex-M3)"; 1436 mc->init = lm3s6965evb_init; 1437 mc->ignore_memory_transaction_failures = true; 1438 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3"); 1439 } 1440 1441 static const TypeInfo lm3s6965evb_type = { 1442 .name = MACHINE_TYPE_NAME("lm3s6965evb"), 1443 .parent = TYPE_MACHINE, 1444 .class_init = lm3s6965evb_class_init, 1445 }; 1446 1447 static void stellaris_machine_init(void) 1448 { 1449 type_register_static(&lm3s811evb_type); 1450 type_register_static(&lm3s6965evb_type); 1451 } 1452 1453 type_init(stellaris_machine_init) 1454 1455 static void stellaris_i2c_class_init(ObjectClass *klass, void *data) 1456 { 1457 DeviceClass *dc = DEVICE_CLASS(klass); 1458 ResettableClass *rc = RESETTABLE_CLASS(klass); 1459 1460 rc->phases.enter = stellaris_i2c_reset_enter; 1461 rc->phases.hold = stellaris_i2c_reset_hold; 1462 rc->phases.exit = stellaris_i2c_reset_exit; 1463 dc->vmsd = &vmstate_stellaris_i2c; 1464 } 1465 1466 static const TypeInfo stellaris_i2c_info = { 1467 .name = TYPE_STELLARIS_I2C, 1468 .parent = TYPE_SYS_BUS_DEVICE, 1469 .instance_size = sizeof(stellaris_i2c_state), 1470 .instance_init = stellaris_i2c_init, 1471 .class_init = stellaris_i2c_class_init, 1472 }; 1473 1474 static void stellaris_adc_class_init(ObjectClass *klass, void *data) 1475 { 1476 DeviceClass *dc = DEVICE_CLASS(klass); 1477 ResettableClass *rc = RESETTABLE_CLASS(klass); 1478 1479 rc->phases.hold = stellaris_adc_reset_hold; 1480 dc->vmsd = &vmstate_stellaris_adc; 1481 } 1482 1483 static const TypeInfo stellaris_adc_info = { 1484 .name = TYPE_STELLARIS_ADC, 1485 .parent = TYPE_SYS_BUS_DEVICE, 1486 .instance_size = sizeof(StellarisADCState), 1487 .instance_init = stellaris_adc_init, 1488 .class_init = stellaris_adc_class_init, 1489 }; 1490 1491 static void stellaris_sys_class_init(ObjectClass *klass, void *data) 1492 { 1493 DeviceClass *dc = DEVICE_CLASS(klass); 1494 ResettableClass *rc = RESETTABLE_CLASS(klass); 1495 1496 dc->vmsd = &vmstate_stellaris_sys; 1497 rc->phases.enter = stellaris_sys_reset_enter; 1498 rc->phases.hold = stellaris_sys_reset_hold; 1499 rc->phases.exit = stellaris_sys_reset_exit; 1500 device_class_set_props(dc, stellaris_sys_properties); 1501 } 1502 1503 static const TypeInfo stellaris_sys_info = { 1504 .name = TYPE_STELLARIS_SYS, 1505 .parent = TYPE_SYS_BUS_DEVICE, 1506 .instance_size = sizeof(ssys_state), 1507 .instance_init = stellaris_sys_instance_init, 1508 .class_init = stellaris_sys_class_init, 1509 }; 1510 1511 static void stellaris_register_types(void) 1512 { 1513 type_register_static(&stellaris_i2c_info); 1514 type_register_static(&stellaris_adc_info); 1515 type_register_static(&stellaris_sys_info); 1516 } 1517 1518 type_init(stellaris_register_types) 1519