1 /* 2 * Luminary Micro Stellaris peripherals 3 * 4 * Copyright (c) 2006 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qapi/error.h" 12 #include "hw/sysbus.h" 13 #include "hw/ssi/ssi.h" 14 #include "hw/arm/boot.h" 15 #include "qemu/timer.h" 16 #include "hw/i2c/i2c.h" 17 #include "net/net.h" 18 #include "hw/boards.h" 19 #include "qemu/log.h" 20 #include "exec/address-spaces.h" 21 #include "sysemu/sysemu.h" 22 #include "hw/arm/armv7m.h" 23 #include "hw/char/pl011.h" 24 #include "hw/input/gamepad.h" 25 #include "hw/irq.h" 26 #include "hw/watchdog/cmsdk-apb-watchdog.h" 27 #include "migration/vmstate.h" 28 #include "hw/misc/unimp.h" 29 #include "hw/qdev-clock.h" 30 #include "qom/object.h" 31 32 #define GPIO_A 0 33 #define GPIO_B 1 34 #define GPIO_C 2 35 #define GPIO_D 3 36 #define GPIO_E 4 37 #define GPIO_F 5 38 #define GPIO_G 6 39 40 #define BP_OLED_I2C 0x01 41 #define BP_OLED_SSI 0x02 42 #define BP_GAMEPAD 0x04 43 44 #define NUM_IRQ_LINES 64 45 46 typedef const struct { 47 const char *name; 48 uint32_t did0; 49 uint32_t did1; 50 uint32_t dc0; 51 uint32_t dc1; 52 uint32_t dc2; 53 uint32_t dc3; 54 uint32_t dc4; 55 uint32_t peripherals; 56 } stellaris_board_info; 57 58 /* General purpose timer module. */ 59 60 #define TYPE_STELLARIS_GPTM "stellaris-gptm" 61 OBJECT_DECLARE_SIMPLE_TYPE(gptm_state, STELLARIS_GPTM) 62 63 struct gptm_state { 64 SysBusDevice parent_obj; 65 66 MemoryRegion iomem; 67 uint32_t config; 68 uint32_t mode[2]; 69 uint32_t control; 70 uint32_t state; 71 uint32_t mask; 72 uint32_t load[2]; 73 uint32_t match[2]; 74 uint32_t prescale[2]; 75 uint32_t match_prescale[2]; 76 uint32_t rtc; 77 int64_t tick[2]; 78 struct gptm_state *opaque[2]; 79 QEMUTimer *timer[2]; 80 /* The timers have an alternate output used to trigger the ADC. */ 81 qemu_irq trigger; 82 qemu_irq irq; 83 }; 84 85 static void gptm_update_irq(gptm_state *s) 86 { 87 int level; 88 level = (s->state & s->mask) != 0; 89 qemu_set_irq(s->irq, level); 90 } 91 92 static void gptm_stop(gptm_state *s, int n) 93 { 94 timer_del(s->timer[n]); 95 } 96 97 static void gptm_reload(gptm_state *s, int n, int reset) 98 { 99 int64_t tick; 100 if (reset) 101 tick = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 102 else 103 tick = s->tick[n]; 104 105 if (s->config == 0) { 106 /* 32-bit CountDown. */ 107 uint32_t count; 108 count = s->load[0] | (s->load[1] << 16); 109 tick += (int64_t)count * system_clock_scale; 110 } else if (s->config == 1) { 111 /* 32-bit RTC. 1Hz tick. */ 112 tick += NANOSECONDS_PER_SECOND; 113 } else if (s->mode[n] == 0xa) { 114 /* PWM mode. Not implemented. */ 115 } else { 116 qemu_log_mask(LOG_UNIMP, 117 "GPTM: 16-bit timer mode unimplemented: 0x%x\n", 118 s->mode[n]); 119 return; 120 } 121 s->tick[n] = tick; 122 timer_mod(s->timer[n], tick); 123 } 124 125 static void gptm_tick(void *opaque) 126 { 127 gptm_state **p = (gptm_state **)opaque; 128 gptm_state *s; 129 int n; 130 131 s = *p; 132 n = p - s->opaque; 133 if (s->config == 0) { 134 s->state |= 1; 135 if ((s->control & 0x20)) { 136 /* Output trigger. */ 137 qemu_irq_pulse(s->trigger); 138 } 139 if (s->mode[0] & 1) { 140 /* One-shot. */ 141 s->control &= ~1; 142 } else { 143 /* Periodic. */ 144 gptm_reload(s, 0, 0); 145 } 146 } else if (s->config == 1) { 147 /* RTC. */ 148 uint32_t match; 149 s->rtc++; 150 match = s->match[0] | (s->match[1] << 16); 151 if (s->rtc > match) 152 s->rtc = 0; 153 if (s->rtc == 0) { 154 s->state |= 8; 155 } 156 gptm_reload(s, 0, 0); 157 } else if (s->mode[n] == 0xa) { 158 /* PWM mode. Not implemented. */ 159 } else { 160 qemu_log_mask(LOG_UNIMP, 161 "GPTM: 16-bit timer mode unimplemented: 0x%x\n", 162 s->mode[n]); 163 } 164 gptm_update_irq(s); 165 } 166 167 static uint64_t gptm_read(void *opaque, hwaddr offset, 168 unsigned size) 169 { 170 gptm_state *s = (gptm_state *)opaque; 171 172 switch (offset) { 173 case 0x00: /* CFG */ 174 return s->config; 175 case 0x04: /* TAMR */ 176 return s->mode[0]; 177 case 0x08: /* TBMR */ 178 return s->mode[1]; 179 case 0x0c: /* CTL */ 180 return s->control; 181 case 0x18: /* IMR */ 182 return s->mask; 183 case 0x1c: /* RIS */ 184 return s->state; 185 case 0x20: /* MIS */ 186 return s->state & s->mask; 187 case 0x24: /* CR */ 188 return 0; 189 case 0x28: /* TAILR */ 190 return s->load[0] | ((s->config < 4) ? (s->load[1] << 16) : 0); 191 case 0x2c: /* TBILR */ 192 return s->load[1]; 193 case 0x30: /* TAMARCHR */ 194 return s->match[0] | ((s->config < 4) ? (s->match[1] << 16) : 0); 195 case 0x34: /* TBMATCHR */ 196 return s->match[1]; 197 case 0x38: /* TAPR */ 198 return s->prescale[0]; 199 case 0x3c: /* TBPR */ 200 return s->prescale[1]; 201 case 0x40: /* TAPMR */ 202 return s->match_prescale[0]; 203 case 0x44: /* TBPMR */ 204 return s->match_prescale[1]; 205 case 0x48: /* TAR */ 206 if (s->config == 1) { 207 return s->rtc; 208 } 209 qemu_log_mask(LOG_UNIMP, 210 "GPTM: read of TAR but timer read not supported\n"); 211 return 0; 212 case 0x4c: /* TBR */ 213 qemu_log_mask(LOG_UNIMP, 214 "GPTM: read of TBR but timer read not supported\n"); 215 return 0; 216 default: 217 qemu_log_mask(LOG_GUEST_ERROR, 218 "GPTM: read at bad offset 0x02%" HWADDR_PRIx "\n", 219 offset); 220 return 0; 221 } 222 } 223 224 static void gptm_write(void *opaque, hwaddr offset, 225 uint64_t value, unsigned size) 226 { 227 gptm_state *s = (gptm_state *)opaque; 228 uint32_t oldval; 229 230 /* The timers should be disabled before changing the configuration. 231 We take advantage of this and defer everything until the timer 232 is enabled. */ 233 switch (offset) { 234 case 0x00: /* CFG */ 235 s->config = value; 236 break; 237 case 0x04: /* TAMR */ 238 s->mode[0] = value; 239 break; 240 case 0x08: /* TBMR */ 241 s->mode[1] = value; 242 break; 243 case 0x0c: /* CTL */ 244 oldval = s->control; 245 s->control = value; 246 /* TODO: Implement pause. */ 247 if ((oldval ^ value) & 1) { 248 if (value & 1) { 249 gptm_reload(s, 0, 1); 250 } else { 251 gptm_stop(s, 0); 252 } 253 } 254 if (((oldval ^ value) & 0x100) && s->config >= 4) { 255 if (value & 0x100) { 256 gptm_reload(s, 1, 1); 257 } else { 258 gptm_stop(s, 1); 259 } 260 } 261 break; 262 case 0x18: /* IMR */ 263 s->mask = value & 0x77; 264 gptm_update_irq(s); 265 break; 266 case 0x24: /* CR */ 267 s->state &= ~value; 268 break; 269 case 0x28: /* TAILR */ 270 s->load[0] = value & 0xffff; 271 if (s->config < 4) { 272 s->load[1] = value >> 16; 273 } 274 break; 275 case 0x2c: /* TBILR */ 276 s->load[1] = value & 0xffff; 277 break; 278 case 0x30: /* TAMARCHR */ 279 s->match[0] = value & 0xffff; 280 if (s->config < 4) { 281 s->match[1] = value >> 16; 282 } 283 break; 284 case 0x34: /* TBMATCHR */ 285 s->match[1] = value >> 16; 286 break; 287 case 0x38: /* TAPR */ 288 s->prescale[0] = value; 289 break; 290 case 0x3c: /* TBPR */ 291 s->prescale[1] = value; 292 break; 293 case 0x40: /* TAPMR */ 294 s->match_prescale[0] = value; 295 break; 296 case 0x44: /* TBPMR */ 297 s->match_prescale[0] = value; 298 break; 299 default: 300 qemu_log_mask(LOG_GUEST_ERROR, 301 "GPTM: write at bad offset 0x02%" HWADDR_PRIx "\n", 302 offset); 303 } 304 gptm_update_irq(s); 305 } 306 307 static const MemoryRegionOps gptm_ops = { 308 .read = gptm_read, 309 .write = gptm_write, 310 .endianness = DEVICE_NATIVE_ENDIAN, 311 }; 312 313 static const VMStateDescription vmstate_stellaris_gptm = { 314 .name = "stellaris_gptm", 315 .version_id = 1, 316 .minimum_version_id = 1, 317 .fields = (VMStateField[]) { 318 VMSTATE_UINT32(config, gptm_state), 319 VMSTATE_UINT32_ARRAY(mode, gptm_state, 2), 320 VMSTATE_UINT32(control, gptm_state), 321 VMSTATE_UINT32(state, gptm_state), 322 VMSTATE_UINT32(mask, gptm_state), 323 VMSTATE_UNUSED(8), 324 VMSTATE_UINT32_ARRAY(load, gptm_state, 2), 325 VMSTATE_UINT32_ARRAY(match, gptm_state, 2), 326 VMSTATE_UINT32_ARRAY(prescale, gptm_state, 2), 327 VMSTATE_UINT32_ARRAY(match_prescale, gptm_state, 2), 328 VMSTATE_UINT32(rtc, gptm_state), 329 VMSTATE_INT64_ARRAY(tick, gptm_state, 2), 330 VMSTATE_TIMER_PTR_ARRAY(timer, gptm_state, 2), 331 VMSTATE_END_OF_LIST() 332 } 333 }; 334 335 static void stellaris_gptm_init(Object *obj) 336 { 337 DeviceState *dev = DEVICE(obj); 338 gptm_state *s = STELLARIS_GPTM(obj); 339 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 340 341 sysbus_init_irq(sbd, &s->irq); 342 qdev_init_gpio_out(dev, &s->trigger, 1); 343 344 memory_region_init_io(&s->iomem, obj, &gptm_ops, s, 345 "gptm", 0x1000); 346 sysbus_init_mmio(sbd, &s->iomem); 347 348 s->opaque[0] = s->opaque[1] = s; 349 } 350 351 static void stellaris_gptm_realize(DeviceState *dev, Error **errp) 352 { 353 gptm_state *s = STELLARIS_GPTM(dev); 354 s->timer[0] = timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque[0]); 355 s->timer[1] = timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque[1]); 356 } 357 358 /* System controller. */ 359 360 #define TYPE_STELLARIS_SYS "stellaris-sys" 361 OBJECT_DECLARE_SIMPLE_TYPE(ssys_state, STELLARIS_SYS) 362 363 struct ssys_state { 364 SysBusDevice parent_obj; 365 366 MemoryRegion iomem; 367 uint32_t pborctl; 368 uint32_t ldopctl; 369 uint32_t int_status; 370 uint32_t int_mask; 371 uint32_t resc; 372 uint32_t rcc; 373 uint32_t rcc2; 374 uint32_t rcgc[3]; 375 uint32_t scgc[3]; 376 uint32_t dcgc[3]; 377 uint32_t clkvclr; 378 uint32_t ldoarst; 379 qemu_irq irq; 380 Clock *sysclk; 381 /* Properties (all read-only registers) */ 382 uint32_t user0; 383 uint32_t user1; 384 uint32_t did0; 385 uint32_t did1; 386 uint32_t dc0; 387 uint32_t dc1; 388 uint32_t dc2; 389 uint32_t dc3; 390 uint32_t dc4; 391 }; 392 393 static void ssys_update(ssys_state *s) 394 { 395 qemu_set_irq(s->irq, (s->int_status & s->int_mask) != 0); 396 } 397 398 static uint32_t pllcfg_sandstorm[16] = { 399 0x31c0, /* 1 Mhz */ 400 0x1ae0, /* 1.8432 Mhz */ 401 0x18c0, /* 2 Mhz */ 402 0xd573, /* 2.4576 Mhz */ 403 0x37a6, /* 3.57954 Mhz */ 404 0x1ae2, /* 3.6864 Mhz */ 405 0x0c40, /* 4 Mhz */ 406 0x98bc, /* 4.906 Mhz */ 407 0x935b, /* 4.9152 Mhz */ 408 0x09c0, /* 5 Mhz */ 409 0x4dee, /* 5.12 Mhz */ 410 0x0c41, /* 6 Mhz */ 411 0x75db, /* 6.144 Mhz */ 412 0x1ae6, /* 7.3728 Mhz */ 413 0x0600, /* 8 Mhz */ 414 0x585b /* 8.192 Mhz */ 415 }; 416 417 static uint32_t pllcfg_fury[16] = { 418 0x3200, /* 1 Mhz */ 419 0x1b20, /* 1.8432 Mhz */ 420 0x1900, /* 2 Mhz */ 421 0xf42b, /* 2.4576 Mhz */ 422 0x37e3, /* 3.57954 Mhz */ 423 0x1b21, /* 3.6864 Mhz */ 424 0x0c80, /* 4 Mhz */ 425 0x98ee, /* 4.906 Mhz */ 426 0xd5b4, /* 4.9152 Mhz */ 427 0x0a00, /* 5 Mhz */ 428 0x4e27, /* 5.12 Mhz */ 429 0x1902, /* 6 Mhz */ 430 0xec1c, /* 6.144 Mhz */ 431 0x1b23, /* 7.3728 Mhz */ 432 0x0640, /* 8 Mhz */ 433 0xb11c /* 8.192 Mhz */ 434 }; 435 436 #define DID0_VER_MASK 0x70000000 437 #define DID0_VER_0 0x00000000 438 #define DID0_VER_1 0x10000000 439 440 #define DID0_CLASS_MASK 0x00FF0000 441 #define DID0_CLASS_SANDSTORM 0x00000000 442 #define DID0_CLASS_FURY 0x00010000 443 444 static int ssys_board_class(const ssys_state *s) 445 { 446 uint32_t did0 = s->did0; 447 switch (did0 & DID0_VER_MASK) { 448 case DID0_VER_0: 449 return DID0_CLASS_SANDSTORM; 450 case DID0_VER_1: 451 switch (did0 & DID0_CLASS_MASK) { 452 case DID0_CLASS_SANDSTORM: 453 case DID0_CLASS_FURY: 454 return did0 & DID0_CLASS_MASK; 455 } 456 /* for unknown classes, fall through */ 457 default: 458 /* This can only happen if the hardwired constant did0 value 459 * in this board's stellaris_board_info struct is wrong. 460 */ 461 g_assert_not_reached(); 462 } 463 } 464 465 static uint64_t ssys_read(void *opaque, hwaddr offset, 466 unsigned size) 467 { 468 ssys_state *s = (ssys_state *)opaque; 469 470 switch (offset) { 471 case 0x000: /* DID0 */ 472 return s->did0; 473 case 0x004: /* DID1 */ 474 return s->did1; 475 case 0x008: /* DC0 */ 476 return s->dc0; 477 case 0x010: /* DC1 */ 478 return s->dc1; 479 case 0x014: /* DC2 */ 480 return s->dc2; 481 case 0x018: /* DC3 */ 482 return s->dc3; 483 case 0x01c: /* DC4 */ 484 return s->dc4; 485 case 0x030: /* PBORCTL */ 486 return s->pborctl; 487 case 0x034: /* LDOPCTL */ 488 return s->ldopctl; 489 case 0x040: /* SRCR0 */ 490 return 0; 491 case 0x044: /* SRCR1 */ 492 return 0; 493 case 0x048: /* SRCR2 */ 494 return 0; 495 case 0x050: /* RIS */ 496 return s->int_status; 497 case 0x054: /* IMC */ 498 return s->int_mask; 499 case 0x058: /* MISC */ 500 return s->int_status & s->int_mask; 501 case 0x05c: /* RESC */ 502 return s->resc; 503 case 0x060: /* RCC */ 504 return s->rcc; 505 case 0x064: /* PLLCFG */ 506 { 507 int xtal; 508 xtal = (s->rcc >> 6) & 0xf; 509 switch (ssys_board_class(s)) { 510 case DID0_CLASS_FURY: 511 return pllcfg_fury[xtal]; 512 case DID0_CLASS_SANDSTORM: 513 return pllcfg_sandstorm[xtal]; 514 default: 515 g_assert_not_reached(); 516 } 517 } 518 case 0x070: /* RCC2 */ 519 return s->rcc2; 520 case 0x100: /* RCGC0 */ 521 return s->rcgc[0]; 522 case 0x104: /* RCGC1 */ 523 return s->rcgc[1]; 524 case 0x108: /* RCGC2 */ 525 return s->rcgc[2]; 526 case 0x110: /* SCGC0 */ 527 return s->scgc[0]; 528 case 0x114: /* SCGC1 */ 529 return s->scgc[1]; 530 case 0x118: /* SCGC2 */ 531 return s->scgc[2]; 532 case 0x120: /* DCGC0 */ 533 return s->dcgc[0]; 534 case 0x124: /* DCGC1 */ 535 return s->dcgc[1]; 536 case 0x128: /* DCGC2 */ 537 return s->dcgc[2]; 538 case 0x150: /* CLKVCLR */ 539 return s->clkvclr; 540 case 0x160: /* LDOARST */ 541 return s->ldoarst; 542 case 0x1e0: /* USER0 */ 543 return s->user0; 544 case 0x1e4: /* USER1 */ 545 return s->user1; 546 default: 547 qemu_log_mask(LOG_GUEST_ERROR, 548 "SSYS: read at bad offset 0x%x\n", (int)offset); 549 return 0; 550 } 551 } 552 553 static bool ssys_use_rcc2(ssys_state *s) 554 { 555 return (s->rcc2 >> 31) & 0x1; 556 } 557 558 /* 559 * Calculate the system clock period. We only want to propagate 560 * this change to the rest of the system if we're not being called 561 * from migration post-load. 562 */ 563 static void ssys_calculate_system_clock(ssys_state *s, bool propagate_clock) 564 { 565 /* 566 * SYSDIV field specifies divisor: 0 == /1, 1 == /2, etc. Input 567 * clock is 200MHz, which is a period of 5 ns. Dividing the clock 568 * frequency by X is the same as multiplying the period by X. 569 */ 570 if (ssys_use_rcc2(s)) { 571 system_clock_scale = 5 * (((s->rcc2 >> 23) & 0x3f) + 1); 572 } else { 573 system_clock_scale = 5 * (((s->rcc >> 23) & 0xf) + 1); 574 } 575 clock_set_ns(s->sysclk, system_clock_scale); 576 if (propagate_clock) { 577 clock_propagate(s->sysclk); 578 } 579 } 580 581 static void ssys_write(void *opaque, hwaddr offset, 582 uint64_t value, unsigned size) 583 { 584 ssys_state *s = (ssys_state *)opaque; 585 586 switch (offset) { 587 case 0x030: /* PBORCTL */ 588 s->pborctl = value & 0xffff; 589 break; 590 case 0x034: /* LDOPCTL */ 591 s->ldopctl = value & 0x1f; 592 break; 593 case 0x040: /* SRCR0 */ 594 case 0x044: /* SRCR1 */ 595 case 0x048: /* SRCR2 */ 596 qemu_log_mask(LOG_UNIMP, "Peripheral reset not implemented\n"); 597 break; 598 case 0x054: /* IMC */ 599 s->int_mask = value & 0x7f; 600 break; 601 case 0x058: /* MISC */ 602 s->int_status &= ~value; 603 break; 604 case 0x05c: /* RESC */ 605 s->resc = value & 0x3f; 606 break; 607 case 0x060: /* RCC */ 608 if ((s->rcc & (1 << 13)) != 0 && (value & (1 << 13)) == 0) { 609 /* PLL enable. */ 610 s->int_status |= (1 << 6); 611 } 612 s->rcc = value; 613 ssys_calculate_system_clock(s, true); 614 break; 615 case 0x070: /* RCC2 */ 616 if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) { 617 break; 618 } 619 620 if ((s->rcc2 & (1 << 13)) != 0 && (value & (1 << 13)) == 0) { 621 /* PLL enable. */ 622 s->int_status |= (1 << 6); 623 } 624 s->rcc2 = value; 625 ssys_calculate_system_clock(s, true); 626 break; 627 case 0x100: /* RCGC0 */ 628 s->rcgc[0] = value; 629 break; 630 case 0x104: /* RCGC1 */ 631 s->rcgc[1] = value; 632 break; 633 case 0x108: /* RCGC2 */ 634 s->rcgc[2] = value; 635 break; 636 case 0x110: /* SCGC0 */ 637 s->scgc[0] = value; 638 break; 639 case 0x114: /* SCGC1 */ 640 s->scgc[1] = value; 641 break; 642 case 0x118: /* SCGC2 */ 643 s->scgc[2] = value; 644 break; 645 case 0x120: /* DCGC0 */ 646 s->dcgc[0] = value; 647 break; 648 case 0x124: /* DCGC1 */ 649 s->dcgc[1] = value; 650 break; 651 case 0x128: /* DCGC2 */ 652 s->dcgc[2] = value; 653 break; 654 case 0x150: /* CLKVCLR */ 655 s->clkvclr = value; 656 break; 657 case 0x160: /* LDOARST */ 658 s->ldoarst = value; 659 break; 660 default: 661 qemu_log_mask(LOG_GUEST_ERROR, 662 "SSYS: write at bad offset 0x%x\n", (int)offset); 663 } 664 ssys_update(s); 665 } 666 667 static const MemoryRegionOps ssys_ops = { 668 .read = ssys_read, 669 .write = ssys_write, 670 .endianness = DEVICE_NATIVE_ENDIAN, 671 }; 672 673 static void stellaris_sys_reset_enter(Object *obj, ResetType type) 674 { 675 ssys_state *s = STELLARIS_SYS(obj); 676 677 s->pborctl = 0x7ffd; 678 s->rcc = 0x078e3ac0; 679 680 if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) { 681 s->rcc2 = 0; 682 } else { 683 s->rcc2 = 0x07802810; 684 } 685 s->rcgc[0] = 1; 686 s->scgc[0] = 1; 687 s->dcgc[0] = 1; 688 } 689 690 static void stellaris_sys_reset_hold(Object *obj) 691 { 692 ssys_state *s = STELLARIS_SYS(obj); 693 694 /* OK to propagate clocks from the hold phase */ 695 ssys_calculate_system_clock(s, true); 696 } 697 698 static void stellaris_sys_reset_exit(Object *obj) 699 { 700 } 701 702 static int stellaris_sys_post_load(void *opaque, int version_id) 703 { 704 ssys_state *s = opaque; 705 706 ssys_calculate_system_clock(s, false); 707 708 return 0; 709 } 710 711 static const VMStateDescription vmstate_stellaris_sys = { 712 .name = "stellaris_sys", 713 .version_id = 2, 714 .minimum_version_id = 1, 715 .post_load = stellaris_sys_post_load, 716 .fields = (VMStateField[]) { 717 VMSTATE_UINT32(pborctl, ssys_state), 718 VMSTATE_UINT32(ldopctl, ssys_state), 719 VMSTATE_UINT32(int_mask, ssys_state), 720 VMSTATE_UINT32(int_status, ssys_state), 721 VMSTATE_UINT32(resc, ssys_state), 722 VMSTATE_UINT32(rcc, ssys_state), 723 VMSTATE_UINT32_V(rcc2, ssys_state, 2), 724 VMSTATE_UINT32_ARRAY(rcgc, ssys_state, 3), 725 VMSTATE_UINT32_ARRAY(scgc, ssys_state, 3), 726 VMSTATE_UINT32_ARRAY(dcgc, ssys_state, 3), 727 VMSTATE_UINT32(clkvclr, ssys_state), 728 VMSTATE_UINT32(ldoarst, ssys_state), 729 /* No field for sysclk -- handled in post-load instead */ 730 VMSTATE_END_OF_LIST() 731 } 732 }; 733 734 static Property stellaris_sys_properties[] = { 735 DEFINE_PROP_UINT32("user0", ssys_state, user0, 0), 736 DEFINE_PROP_UINT32("user1", ssys_state, user1, 0), 737 DEFINE_PROP_UINT32("did0", ssys_state, did0, 0), 738 DEFINE_PROP_UINT32("did1", ssys_state, did1, 0), 739 DEFINE_PROP_UINT32("dc0", ssys_state, dc0, 0), 740 DEFINE_PROP_UINT32("dc1", ssys_state, dc1, 0), 741 DEFINE_PROP_UINT32("dc2", ssys_state, dc2, 0), 742 DEFINE_PROP_UINT32("dc3", ssys_state, dc3, 0), 743 DEFINE_PROP_UINT32("dc4", ssys_state, dc4, 0), 744 DEFINE_PROP_END_OF_LIST() 745 }; 746 747 static void stellaris_sys_instance_init(Object *obj) 748 { 749 ssys_state *s = STELLARIS_SYS(obj); 750 SysBusDevice *sbd = SYS_BUS_DEVICE(s); 751 752 memory_region_init_io(&s->iomem, obj, &ssys_ops, s, "ssys", 0x00001000); 753 sysbus_init_mmio(sbd, &s->iomem); 754 sysbus_init_irq(sbd, &s->irq); 755 s->sysclk = qdev_init_clock_out(DEVICE(s), "SYSCLK"); 756 } 757 758 /* I2C controller. */ 759 760 #define TYPE_STELLARIS_I2C "stellaris-i2c" 761 OBJECT_DECLARE_SIMPLE_TYPE(stellaris_i2c_state, STELLARIS_I2C) 762 763 struct stellaris_i2c_state { 764 SysBusDevice parent_obj; 765 766 I2CBus *bus; 767 qemu_irq irq; 768 MemoryRegion iomem; 769 uint32_t msa; 770 uint32_t mcs; 771 uint32_t mdr; 772 uint32_t mtpr; 773 uint32_t mimr; 774 uint32_t mris; 775 uint32_t mcr; 776 }; 777 778 #define STELLARIS_I2C_MCS_BUSY 0x01 779 #define STELLARIS_I2C_MCS_ERROR 0x02 780 #define STELLARIS_I2C_MCS_ADRACK 0x04 781 #define STELLARIS_I2C_MCS_DATACK 0x08 782 #define STELLARIS_I2C_MCS_ARBLST 0x10 783 #define STELLARIS_I2C_MCS_IDLE 0x20 784 #define STELLARIS_I2C_MCS_BUSBSY 0x40 785 786 static uint64_t stellaris_i2c_read(void *opaque, hwaddr offset, 787 unsigned size) 788 { 789 stellaris_i2c_state *s = (stellaris_i2c_state *)opaque; 790 791 switch (offset) { 792 case 0x00: /* MSA */ 793 return s->msa; 794 case 0x04: /* MCS */ 795 /* We don't emulate timing, so the controller is never busy. */ 796 return s->mcs | STELLARIS_I2C_MCS_IDLE; 797 case 0x08: /* MDR */ 798 return s->mdr; 799 case 0x0c: /* MTPR */ 800 return s->mtpr; 801 case 0x10: /* MIMR */ 802 return s->mimr; 803 case 0x14: /* MRIS */ 804 return s->mris; 805 case 0x18: /* MMIS */ 806 return s->mris & s->mimr; 807 case 0x20: /* MCR */ 808 return s->mcr; 809 default: 810 qemu_log_mask(LOG_GUEST_ERROR, 811 "stellaris_i2c: read at bad offset 0x%x\n", (int)offset); 812 return 0; 813 } 814 } 815 816 static void stellaris_i2c_update(stellaris_i2c_state *s) 817 { 818 int level; 819 820 level = (s->mris & s->mimr) != 0; 821 qemu_set_irq(s->irq, level); 822 } 823 824 static void stellaris_i2c_write(void *opaque, hwaddr offset, 825 uint64_t value, unsigned size) 826 { 827 stellaris_i2c_state *s = (stellaris_i2c_state *)opaque; 828 829 switch (offset) { 830 case 0x00: /* MSA */ 831 s->msa = value & 0xff; 832 break; 833 case 0x04: /* MCS */ 834 if ((s->mcr & 0x10) == 0) { 835 /* Disabled. Do nothing. */ 836 break; 837 } 838 /* Grab the bus if this is starting a transfer. */ 839 if ((value & 2) && (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) { 840 if (i2c_start_transfer(s->bus, s->msa >> 1, s->msa & 1)) { 841 s->mcs |= STELLARIS_I2C_MCS_ARBLST; 842 } else { 843 s->mcs &= ~STELLARIS_I2C_MCS_ARBLST; 844 s->mcs |= STELLARIS_I2C_MCS_BUSBSY; 845 } 846 } 847 /* If we don't have the bus then indicate an error. */ 848 if (!i2c_bus_busy(s->bus) 849 || (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) { 850 s->mcs |= STELLARIS_I2C_MCS_ERROR; 851 break; 852 } 853 s->mcs &= ~STELLARIS_I2C_MCS_ERROR; 854 if (value & 1) { 855 /* Transfer a byte. */ 856 /* TODO: Handle errors. */ 857 if (s->msa & 1) { 858 /* Recv */ 859 s->mdr = i2c_recv(s->bus); 860 } else { 861 /* Send */ 862 i2c_send(s->bus, s->mdr); 863 } 864 /* Raise an interrupt. */ 865 s->mris |= 1; 866 } 867 if (value & 4) { 868 /* Finish transfer. */ 869 i2c_end_transfer(s->bus); 870 s->mcs &= ~STELLARIS_I2C_MCS_BUSBSY; 871 } 872 break; 873 case 0x08: /* MDR */ 874 s->mdr = value & 0xff; 875 break; 876 case 0x0c: /* MTPR */ 877 s->mtpr = value & 0xff; 878 break; 879 case 0x10: /* MIMR */ 880 s->mimr = 1; 881 break; 882 case 0x1c: /* MICR */ 883 s->mris &= ~value; 884 break; 885 case 0x20: /* MCR */ 886 if (value & 1) { 887 qemu_log_mask(LOG_UNIMP, 888 "stellaris_i2c: Loopback not implemented\n"); 889 } 890 if (value & 0x20) { 891 qemu_log_mask(LOG_UNIMP, 892 "stellaris_i2c: Slave mode not implemented\n"); 893 } 894 s->mcr = value & 0x31; 895 break; 896 default: 897 qemu_log_mask(LOG_GUEST_ERROR, 898 "stellaris_i2c: write at bad offset 0x%x\n", (int)offset); 899 } 900 stellaris_i2c_update(s); 901 } 902 903 static void stellaris_i2c_reset(stellaris_i2c_state *s) 904 { 905 if (s->mcs & STELLARIS_I2C_MCS_BUSBSY) 906 i2c_end_transfer(s->bus); 907 908 s->msa = 0; 909 s->mcs = 0; 910 s->mdr = 0; 911 s->mtpr = 1; 912 s->mimr = 0; 913 s->mris = 0; 914 s->mcr = 0; 915 stellaris_i2c_update(s); 916 } 917 918 static const MemoryRegionOps stellaris_i2c_ops = { 919 .read = stellaris_i2c_read, 920 .write = stellaris_i2c_write, 921 .endianness = DEVICE_NATIVE_ENDIAN, 922 }; 923 924 static const VMStateDescription vmstate_stellaris_i2c = { 925 .name = "stellaris_i2c", 926 .version_id = 1, 927 .minimum_version_id = 1, 928 .fields = (VMStateField[]) { 929 VMSTATE_UINT32(msa, stellaris_i2c_state), 930 VMSTATE_UINT32(mcs, stellaris_i2c_state), 931 VMSTATE_UINT32(mdr, stellaris_i2c_state), 932 VMSTATE_UINT32(mtpr, stellaris_i2c_state), 933 VMSTATE_UINT32(mimr, stellaris_i2c_state), 934 VMSTATE_UINT32(mris, stellaris_i2c_state), 935 VMSTATE_UINT32(mcr, stellaris_i2c_state), 936 VMSTATE_END_OF_LIST() 937 } 938 }; 939 940 static void stellaris_i2c_init(Object *obj) 941 { 942 DeviceState *dev = DEVICE(obj); 943 stellaris_i2c_state *s = STELLARIS_I2C(obj); 944 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 945 I2CBus *bus; 946 947 sysbus_init_irq(sbd, &s->irq); 948 bus = i2c_init_bus(dev, "i2c"); 949 s->bus = bus; 950 951 memory_region_init_io(&s->iomem, obj, &stellaris_i2c_ops, s, 952 "i2c", 0x1000); 953 sysbus_init_mmio(sbd, &s->iomem); 954 /* ??? For now we only implement the master interface. */ 955 stellaris_i2c_reset(s); 956 } 957 958 /* Analogue to Digital Converter. This is only partially implemented, 959 enough for applications that use a combined ADC and timer tick. */ 960 961 #define STELLARIS_ADC_EM_CONTROLLER 0 962 #define STELLARIS_ADC_EM_COMP 1 963 #define STELLARIS_ADC_EM_EXTERNAL 4 964 #define STELLARIS_ADC_EM_TIMER 5 965 #define STELLARIS_ADC_EM_PWM0 6 966 #define STELLARIS_ADC_EM_PWM1 7 967 #define STELLARIS_ADC_EM_PWM2 8 968 969 #define STELLARIS_ADC_FIFO_EMPTY 0x0100 970 #define STELLARIS_ADC_FIFO_FULL 0x1000 971 972 #define TYPE_STELLARIS_ADC "stellaris-adc" 973 typedef struct StellarisADCState stellaris_adc_state; 974 DECLARE_INSTANCE_CHECKER(stellaris_adc_state, STELLARIS_ADC, 975 TYPE_STELLARIS_ADC) 976 977 struct StellarisADCState { 978 SysBusDevice parent_obj; 979 980 MemoryRegion iomem; 981 uint32_t actss; 982 uint32_t ris; 983 uint32_t im; 984 uint32_t emux; 985 uint32_t ostat; 986 uint32_t ustat; 987 uint32_t sspri; 988 uint32_t sac; 989 struct { 990 uint32_t state; 991 uint32_t data[16]; 992 } fifo[4]; 993 uint32_t ssmux[4]; 994 uint32_t ssctl[4]; 995 uint32_t noise; 996 qemu_irq irq[4]; 997 }; 998 999 static uint32_t stellaris_adc_fifo_read(stellaris_adc_state *s, int n) 1000 { 1001 int tail; 1002 1003 tail = s->fifo[n].state & 0xf; 1004 if (s->fifo[n].state & STELLARIS_ADC_FIFO_EMPTY) { 1005 s->ustat |= 1 << n; 1006 } else { 1007 s->fifo[n].state = (s->fifo[n].state & ~0xf) | ((tail + 1) & 0xf); 1008 s->fifo[n].state &= ~STELLARIS_ADC_FIFO_FULL; 1009 if (tail + 1 == ((s->fifo[n].state >> 4) & 0xf)) 1010 s->fifo[n].state |= STELLARIS_ADC_FIFO_EMPTY; 1011 } 1012 return s->fifo[n].data[tail]; 1013 } 1014 1015 static void stellaris_adc_fifo_write(stellaris_adc_state *s, int n, 1016 uint32_t value) 1017 { 1018 int head; 1019 1020 /* TODO: Real hardware has limited size FIFOs. We have a full 16 entry 1021 FIFO fir each sequencer. */ 1022 head = (s->fifo[n].state >> 4) & 0xf; 1023 if (s->fifo[n].state & STELLARIS_ADC_FIFO_FULL) { 1024 s->ostat |= 1 << n; 1025 return; 1026 } 1027 s->fifo[n].data[head] = value; 1028 head = (head + 1) & 0xf; 1029 s->fifo[n].state &= ~STELLARIS_ADC_FIFO_EMPTY; 1030 s->fifo[n].state = (s->fifo[n].state & ~0xf0) | (head << 4); 1031 if ((s->fifo[n].state & 0xf) == head) 1032 s->fifo[n].state |= STELLARIS_ADC_FIFO_FULL; 1033 } 1034 1035 static void stellaris_adc_update(stellaris_adc_state *s) 1036 { 1037 int level; 1038 int n; 1039 1040 for (n = 0; n < 4; n++) { 1041 level = (s->ris & s->im & (1 << n)) != 0; 1042 qemu_set_irq(s->irq[n], level); 1043 } 1044 } 1045 1046 static void stellaris_adc_trigger(void *opaque, int irq, int level) 1047 { 1048 stellaris_adc_state *s = (stellaris_adc_state *)opaque; 1049 int n; 1050 1051 for (n = 0; n < 4; n++) { 1052 if ((s->actss & (1 << n)) == 0) { 1053 continue; 1054 } 1055 1056 if (((s->emux >> (n * 4)) & 0xff) != 5) { 1057 continue; 1058 } 1059 1060 /* Some applications use the ADC as a random number source, so introduce 1061 some variation into the signal. */ 1062 s->noise = s->noise * 314159 + 1; 1063 /* ??? actual inputs not implemented. Return an arbitrary value. */ 1064 stellaris_adc_fifo_write(s, n, 0x200 + ((s->noise >> 16) & 7)); 1065 s->ris |= (1 << n); 1066 stellaris_adc_update(s); 1067 } 1068 } 1069 1070 static void stellaris_adc_reset(stellaris_adc_state *s) 1071 { 1072 int n; 1073 1074 for (n = 0; n < 4; n++) { 1075 s->ssmux[n] = 0; 1076 s->ssctl[n] = 0; 1077 s->fifo[n].state = STELLARIS_ADC_FIFO_EMPTY; 1078 } 1079 } 1080 1081 static uint64_t stellaris_adc_read(void *opaque, hwaddr offset, 1082 unsigned size) 1083 { 1084 stellaris_adc_state *s = (stellaris_adc_state *)opaque; 1085 1086 /* TODO: Implement this. */ 1087 if (offset >= 0x40 && offset < 0xc0) { 1088 int n; 1089 n = (offset - 0x40) >> 5; 1090 switch (offset & 0x1f) { 1091 case 0x00: /* SSMUX */ 1092 return s->ssmux[n]; 1093 case 0x04: /* SSCTL */ 1094 return s->ssctl[n]; 1095 case 0x08: /* SSFIFO */ 1096 return stellaris_adc_fifo_read(s, n); 1097 case 0x0c: /* SSFSTAT */ 1098 return s->fifo[n].state; 1099 default: 1100 break; 1101 } 1102 } 1103 switch (offset) { 1104 case 0x00: /* ACTSS */ 1105 return s->actss; 1106 case 0x04: /* RIS */ 1107 return s->ris; 1108 case 0x08: /* IM */ 1109 return s->im; 1110 case 0x0c: /* ISC */ 1111 return s->ris & s->im; 1112 case 0x10: /* OSTAT */ 1113 return s->ostat; 1114 case 0x14: /* EMUX */ 1115 return s->emux; 1116 case 0x18: /* USTAT */ 1117 return s->ustat; 1118 case 0x20: /* SSPRI */ 1119 return s->sspri; 1120 case 0x30: /* SAC */ 1121 return s->sac; 1122 default: 1123 qemu_log_mask(LOG_GUEST_ERROR, 1124 "stellaris_adc: read at bad offset 0x%x\n", (int)offset); 1125 return 0; 1126 } 1127 } 1128 1129 static void stellaris_adc_write(void *opaque, hwaddr offset, 1130 uint64_t value, unsigned size) 1131 { 1132 stellaris_adc_state *s = (stellaris_adc_state *)opaque; 1133 1134 /* TODO: Implement this. */ 1135 if (offset >= 0x40 && offset < 0xc0) { 1136 int n; 1137 n = (offset - 0x40) >> 5; 1138 switch (offset & 0x1f) { 1139 case 0x00: /* SSMUX */ 1140 s->ssmux[n] = value & 0x33333333; 1141 return; 1142 case 0x04: /* SSCTL */ 1143 if (value != 6) { 1144 qemu_log_mask(LOG_UNIMP, 1145 "ADC: Unimplemented sequence %" PRIx64 "\n", 1146 value); 1147 } 1148 s->ssctl[n] = value; 1149 return; 1150 default: 1151 break; 1152 } 1153 } 1154 switch (offset) { 1155 case 0x00: /* ACTSS */ 1156 s->actss = value & 0xf; 1157 break; 1158 case 0x08: /* IM */ 1159 s->im = value; 1160 break; 1161 case 0x0c: /* ISC */ 1162 s->ris &= ~value; 1163 break; 1164 case 0x10: /* OSTAT */ 1165 s->ostat &= ~value; 1166 break; 1167 case 0x14: /* EMUX */ 1168 s->emux = value; 1169 break; 1170 case 0x18: /* USTAT */ 1171 s->ustat &= ~value; 1172 break; 1173 case 0x20: /* SSPRI */ 1174 s->sspri = value; 1175 break; 1176 case 0x28: /* PSSI */ 1177 qemu_log_mask(LOG_UNIMP, "ADC: sample initiate unimplemented\n"); 1178 break; 1179 case 0x30: /* SAC */ 1180 s->sac = value; 1181 break; 1182 default: 1183 qemu_log_mask(LOG_GUEST_ERROR, 1184 "stellaris_adc: write at bad offset 0x%x\n", (int)offset); 1185 } 1186 stellaris_adc_update(s); 1187 } 1188 1189 static const MemoryRegionOps stellaris_adc_ops = { 1190 .read = stellaris_adc_read, 1191 .write = stellaris_adc_write, 1192 .endianness = DEVICE_NATIVE_ENDIAN, 1193 }; 1194 1195 static const VMStateDescription vmstate_stellaris_adc = { 1196 .name = "stellaris_adc", 1197 .version_id = 1, 1198 .minimum_version_id = 1, 1199 .fields = (VMStateField[]) { 1200 VMSTATE_UINT32(actss, stellaris_adc_state), 1201 VMSTATE_UINT32(ris, stellaris_adc_state), 1202 VMSTATE_UINT32(im, stellaris_adc_state), 1203 VMSTATE_UINT32(emux, stellaris_adc_state), 1204 VMSTATE_UINT32(ostat, stellaris_adc_state), 1205 VMSTATE_UINT32(ustat, stellaris_adc_state), 1206 VMSTATE_UINT32(sspri, stellaris_adc_state), 1207 VMSTATE_UINT32(sac, stellaris_adc_state), 1208 VMSTATE_UINT32(fifo[0].state, stellaris_adc_state), 1209 VMSTATE_UINT32_ARRAY(fifo[0].data, stellaris_adc_state, 16), 1210 VMSTATE_UINT32(ssmux[0], stellaris_adc_state), 1211 VMSTATE_UINT32(ssctl[0], stellaris_adc_state), 1212 VMSTATE_UINT32(fifo[1].state, stellaris_adc_state), 1213 VMSTATE_UINT32_ARRAY(fifo[1].data, stellaris_adc_state, 16), 1214 VMSTATE_UINT32(ssmux[1], stellaris_adc_state), 1215 VMSTATE_UINT32(ssctl[1], stellaris_adc_state), 1216 VMSTATE_UINT32(fifo[2].state, stellaris_adc_state), 1217 VMSTATE_UINT32_ARRAY(fifo[2].data, stellaris_adc_state, 16), 1218 VMSTATE_UINT32(ssmux[2], stellaris_adc_state), 1219 VMSTATE_UINT32(ssctl[2], stellaris_adc_state), 1220 VMSTATE_UINT32(fifo[3].state, stellaris_adc_state), 1221 VMSTATE_UINT32_ARRAY(fifo[3].data, stellaris_adc_state, 16), 1222 VMSTATE_UINT32(ssmux[3], stellaris_adc_state), 1223 VMSTATE_UINT32(ssctl[3], stellaris_adc_state), 1224 VMSTATE_UINT32(noise, stellaris_adc_state), 1225 VMSTATE_END_OF_LIST() 1226 } 1227 }; 1228 1229 static void stellaris_adc_init(Object *obj) 1230 { 1231 DeviceState *dev = DEVICE(obj); 1232 stellaris_adc_state *s = STELLARIS_ADC(obj); 1233 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 1234 int n; 1235 1236 for (n = 0; n < 4; n++) { 1237 sysbus_init_irq(sbd, &s->irq[n]); 1238 } 1239 1240 memory_region_init_io(&s->iomem, obj, &stellaris_adc_ops, s, 1241 "adc", 0x1000); 1242 sysbus_init_mmio(sbd, &s->iomem); 1243 stellaris_adc_reset(s); 1244 qdev_init_gpio_in(dev, stellaris_adc_trigger, 1); 1245 } 1246 1247 /* Board init. */ 1248 static stellaris_board_info stellaris_boards[] = { 1249 { "LM3S811EVB", 1250 0, 1251 0x0032000e, 1252 0x001f001f, /* dc0 */ 1253 0x001132bf, 1254 0x01071013, 1255 0x3f0f01ff, 1256 0x0000001f, 1257 BP_OLED_I2C 1258 }, 1259 { "LM3S6965EVB", 1260 0x10010002, 1261 0x1073402e, 1262 0x00ff007f, /* dc0 */ 1263 0x001133ff, 1264 0x030f5317, 1265 0x0f0f87ff, 1266 0x5000007f, 1267 BP_OLED_SSI | BP_GAMEPAD 1268 } 1269 }; 1270 1271 static void stellaris_init(MachineState *ms, stellaris_board_info *board) 1272 { 1273 static const int uart_irq[] = {5, 6, 33, 34}; 1274 static const int timer_irq[] = {19, 21, 23, 35}; 1275 static const uint32_t gpio_addr[7] = 1276 { 0x40004000, 0x40005000, 0x40006000, 0x40007000, 1277 0x40024000, 0x40025000, 0x40026000}; 1278 static const int gpio_irq[7] = {0, 1, 2, 3, 4, 30, 31}; 1279 1280 /* Memory map of SoC devices, from 1281 * Stellaris LM3S6965 Microcontroller Data Sheet (rev I) 1282 * http://www.ti.com/lit/ds/symlink/lm3s6965.pdf 1283 * 1284 * 40000000 wdtimer 1285 * 40002000 i2c (unimplemented) 1286 * 40004000 GPIO 1287 * 40005000 GPIO 1288 * 40006000 GPIO 1289 * 40007000 GPIO 1290 * 40008000 SSI 1291 * 4000c000 UART 1292 * 4000d000 UART 1293 * 4000e000 UART 1294 * 40020000 i2c 1295 * 40021000 i2c (unimplemented) 1296 * 40024000 GPIO 1297 * 40025000 GPIO 1298 * 40026000 GPIO 1299 * 40028000 PWM (unimplemented) 1300 * 4002c000 QEI (unimplemented) 1301 * 4002d000 QEI (unimplemented) 1302 * 40030000 gptimer 1303 * 40031000 gptimer 1304 * 40032000 gptimer 1305 * 40033000 gptimer 1306 * 40038000 ADC 1307 * 4003c000 analogue comparator (unimplemented) 1308 * 40048000 ethernet 1309 * 400fc000 hibernation module (unimplemented) 1310 * 400fd000 flash memory control (unimplemented) 1311 * 400fe000 system control 1312 */ 1313 1314 DeviceState *gpio_dev[7], *nvic; 1315 qemu_irq gpio_in[7][8]; 1316 qemu_irq gpio_out[7][8]; 1317 qemu_irq adc; 1318 int sram_size; 1319 int flash_size; 1320 I2CBus *i2c; 1321 DeviceState *dev; 1322 DeviceState *ssys_dev; 1323 int i; 1324 int j; 1325 uint8_t *macaddr; 1326 1327 MemoryRegion *sram = g_new(MemoryRegion, 1); 1328 MemoryRegion *flash = g_new(MemoryRegion, 1); 1329 MemoryRegion *system_memory = get_system_memory(); 1330 1331 flash_size = (((board->dc0 & 0xffff) + 1) << 1) * 1024; 1332 sram_size = ((board->dc0 >> 18) + 1) * 1024; 1333 1334 /* Flash programming is done via the SCU, so pretend it is ROM. */ 1335 memory_region_init_rom(flash, NULL, "stellaris.flash", flash_size, 1336 &error_fatal); 1337 memory_region_add_subregion(system_memory, 0, flash); 1338 1339 memory_region_init_ram(sram, NULL, "stellaris.sram", sram_size, 1340 &error_fatal); 1341 memory_region_add_subregion(system_memory, 0x20000000, sram); 1342 1343 /* 1344 * Create the system-registers object early, because we will 1345 * need its sysclk output. 1346 */ 1347 ssys_dev = qdev_new(TYPE_STELLARIS_SYS); 1348 /* Most devices come preprogrammed with a MAC address in the user data. */ 1349 macaddr = nd_table[0].macaddr.a; 1350 qdev_prop_set_uint32(ssys_dev, "user0", 1351 macaddr[0] | (macaddr[1] << 8) | (macaddr[2] << 16)); 1352 qdev_prop_set_uint32(ssys_dev, "user1", 1353 macaddr[3] | (macaddr[4] << 8) | (macaddr[5] << 16)); 1354 qdev_prop_set_uint32(ssys_dev, "did0", board->did0); 1355 qdev_prop_set_uint32(ssys_dev, "did1", board->did1); 1356 qdev_prop_set_uint32(ssys_dev, "dc0", board->dc0); 1357 qdev_prop_set_uint32(ssys_dev, "dc1", board->dc1); 1358 qdev_prop_set_uint32(ssys_dev, "dc2", board->dc2); 1359 qdev_prop_set_uint32(ssys_dev, "dc3", board->dc3); 1360 qdev_prop_set_uint32(ssys_dev, "dc4", board->dc4); 1361 sysbus_realize_and_unref(SYS_BUS_DEVICE(ssys_dev), &error_fatal); 1362 1363 nvic = qdev_new(TYPE_ARMV7M); 1364 qdev_prop_set_uint32(nvic, "num-irq", NUM_IRQ_LINES); 1365 qdev_prop_set_string(nvic, "cpu-type", ms->cpu_type); 1366 qdev_prop_set_bit(nvic, "enable-bitband", true); 1367 object_property_set_link(OBJECT(nvic), "memory", 1368 OBJECT(get_system_memory()), &error_abort); 1369 /* This will exit with an error if the user passed us a bad cpu_type */ 1370 sysbus_realize_and_unref(SYS_BUS_DEVICE(nvic), &error_fatal); 1371 1372 /* Now we can wire up the IRQ and MMIO of the system registers */ 1373 sysbus_mmio_map(SYS_BUS_DEVICE(ssys_dev), 0, 0x400fe000); 1374 sysbus_connect_irq(SYS_BUS_DEVICE(ssys_dev), 0, qdev_get_gpio_in(nvic, 28)); 1375 1376 if (board->dc1 & (1 << 16)) { 1377 dev = sysbus_create_varargs(TYPE_STELLARIS_ADC, 0x40038000, 1378 qdev_get_gpio_in(nvic, 14), 1379 qdev_get_gpio_in(nvic, 15), 1380 qdev_get_gpio_in(nvic, 16), 1381 qdev_get_gpio_in(nvic, 17), 1382 NULL); 1383 adc = qdev_get_gpio_in(dev, 0); 1384 } else { 1385 adc = NULL; 1386 } 1387 for (i = 0; i < 4; i++) { 1388 if (board->dc2 & (0x10000 << i)) { 1389 dev = sysbus_create_simple(TYPE_STELLARIS_GPTM, 1390 0x40030000 + i * 0x1000, 1391 qdev_get_gpio_in(nvic, timer_irq[i])); 1392 /* TODO: This is incorrect, but we get away with it because 1393 the ADC output is only ever pulsed. */ 1394 qdev_connect_gpio_out(dev, 0, adc); 1395 } 1396 } 1397 1398 if (board->dc1 & (1 << 3)) { /* watchdog present */ 1399 dev = qdev_new(TYPE_LUMINARY_WATCHDOG); 1400 1401 qdev_connect_clock_in(dev, "WDOGCLK", 1402 qdev_get_clock_out(ssys_dev, "SYSCLK")); 1403 1404 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1405 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1406 0, 1407 0x40000000u); 1408 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1409 0, 1410 qdev_get_gpio_in(nvic, 18)); 1411 } 1412 1413 1414 for (i = 0; i < 7; i++) { 1415 if (board->dc4 & (1 << i)) { 1416 gpio_dev[i] = sysbus_create_simple("pl061_luminary", gpio_addr[i], 1417 qdev_get_gpio_in(nvic, 1418 gpio_irq[i])); 1419 for (j = 0; j < 8; j++) { 1420 gpio_in[i][j] = qdev_get_gpio_in(gpio_dev[i], j); 1421 gpio_out[i][j] = NULL; 1422 } 1423 } 1424 } 1425 1426 if (board->dc2 & (1 << 12)) { 1427 dev = sysbus_create_simple(TYPE_STELLARIS_I2C, 0x40020000, 1428 qdev_get_gpio_in(nvic, 8)); 1429 i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c"); 1430 if (board->peripherals & BP_OLED_I2C) { 1431 i2c_slave_create_simple(i2c, "ssd0303", 0x3d); 1432 } 1433 } 1434 1435 for (i = 0; i < 4; i++) { 1436 if (board->dc2 & (1 << i)) { 1437 pl011_luminary_create(0x4000c000 + i * 0x1000, 1438 qdev_get_gpio_in(nvic, uart_irq[i]), 1439 serial_hd(i)); 1440 } 1441 } 1442 if (board->dc2 & (1 << 4)) { 1443 dev = sysbus_create_simple("pl022", 0x40008000, 1444 qdev_get_gpio_in(nvic, 7)); 1445 if (board->peripherals & BP_OLED_SSI) { 1446 void *bus; 1447 DeviceState *sddev; 1448 DeviceState *ssddev; 1449 1450 /* 1451 * Some boards have both an OLED controller and SD card connected to 1452 * the same SSI port, with the SD card chip select connected to a 1453 * GPIO pin. Technically the OLED chip select is connected to the 1454 * SSI Fss pin. We do not bother emulating that as both devices 1455 * should never be selected simultaneously, and our OLED controller 1456 * ignores stray 0xff commands that occur when deselecting the SD 1457 * card. 1458 * 1459 * The h/w wiring is: 1460 * - GPIO pin D0 is wired to the active-low SD card chip select 1461 * - GPIO pin A3 is wired to the active-low OLED chip select 1462 * - The SoC wiring of the PL061 "auxiliary function" for A3 is 1463 * SSI0Fss ("frame signal"), which is an output from the SoC's 1464 * SSI controller. The SSI controller takes SSI0Fss low when it 1465 * transmits a frame, so it can work as a chip-select signal. 1466 * - GPIO A4 is aux-function SSI0Rx, and wired to the SD card Tx 1467 * (the OLED never sends data to the CPU, so no wiring needed) 1468 * - GPIO A5 is aux-function SSI0Tx, and wired to the SD card Rx 1469 * and the OLED display-data-in 1470 * - GPIO A2 is aux-function SSI0Clk, wired to SD card and OLED 1471 * serial-clock input 1472 * So a guest that wants to use the OLED can configure the PL061 1473 * to make pins A2, A3, A5 aux-function, so they are connected 1474 * directly to the SSI controller. When the SSI controller sends 1475 * data it asserts SSI0Fss which selects the OLED. 1476 * A guest that wants to use the SD card configures A2, A4 and A5 1477 * as aux-function, but leaves A3 as a software-controlled GPIO 1478 * line. It asserts the SD card chip-select by using the PL061 1479 * to control pin D0, and lets the SSI controller handle Clk, Tx 1480 * and Rx. (The SSI controller asserts Fss during tx cycles as 1481 * usual, but because A3 is not set to aux-function this is not 1482 * forwarded to the OLED, and so the OLED stays unselected.) 1483 * 1484 * The QEMU implementation instead is: 1485 * - GPIO pin D0 is wired to the active-low SD card chip select, 1486 * and also to the OLED chip-select which is implemented 1487 * as *active-high* 1488 * - SSI controller signals go to the devices regardless of 1489 * whether the guest programs A2, A4, A5 as aux-function or not 1490 * 1491 * The problem with this implementation is if the guest doesn't 1492 * care about the SD card and only uses the OLED. In that case it 1493 * may choose never to do anything with D0 (leaving it in its 1494 * default floating state, which reliably leaves the card disabled 1495 * because an SD card has a pullup on CS within the card itself), 1496 * and only set up A2, A3, A5. This for us would mean the OLED 1497 * never gets the chip-select assert it needs. We work around 1498 * this with a manual raise of D0 here (despite board creation 1499 * code being the wrong place to raise IRQ lines) to put the OLED 1500 * into an initially selected state. 1501 * 1502 * In theory the right way to model this would be: 1503 * - Implement aux-function support in the PL061, with an 1504 * extra set of AFIN and AFOUT GPIO lines (set up so that 1505 * if a GPIO line is in auxfn mode the main GPIO in and out 1506 * track the AFIN and AFOUT lines) 1507 * - Wire the AFOUT for D0 up to either a line from the 1508 * SSI controller that's pulled low around every transmit, 1509 * or at least to an always-0 line here on the board 1510 * - Make the ssd0323 OLED controller chipselect active-low 1511 */ 1512 bus = qdev_get_child_bus(dev, "ssi"); 1513 1514 sddev = ssi_create_peripheral(bus, "ssi-sd"); 1515 ssddev = ssi_create_peripheral(bus, "ssd0323"); 1516 gpio_out[GPIO_D][0] = qemu_irq_split( 1517 qdev_get_gpio_in_named(sddev, SSI_GPIO_CS, 0), 1518 qdev_get_gpio_in_named(ssddev, SSI_GPIO_CS, 0)); 1519 gpio_out[GPIO_C][7] = qdev_get_gpio_in(ssddev, 0); 1520 1521 /* Make sure the select pin is high. */ 1522 qemu_irq_raise(gpio_out[GPIO_D][0]); 1523 } 1524 } 1525 if (board->dc4 & (1 << 28)) { 1526 DeviceState *enet; 1527 1528 qemu_check_nic_model(&nd_table[0], "stellaris"); 1529 1530 enet = qdev_new("stellaris_enet"); 1531 qdev_set_nic_properties(enet, &nd_table[0]); 1532 sysbus_realize_and_unref(SYS_BUS_DEVICE(enet), &error_fatal); 1533 sysbus_mmio_map(SYS_BUS_DEVICE(enet), 0, 0x40048000); 1534 sysbus_connect_irq(SYS_BUS_DEVICE(enet), 0, qdev_get_gpio_in(nvic, 42)); 1535 } 1536 if (board->peripherals & BP_GAMEPAD) { 1537 qemu_irq gpad_irq[5]; 1538 static const int gpad_keycode[5] = { 0xc8, 0xd0, 0xcb, 0xcd, 0x1d }; 1539 1540 gpad_irq[0] = qemu_irq_invert(gpio_in[GPIO_E][0]); /* up */ 1541 gpad_irq[1] = qemu_irq_invert(gpio_in[GPIO_E][1]); /* down */ 1542 gpad_irq[2] = qemu_irq_invert(gpio_in[GPIO_E][2]); /* left */ 1543 gpad_irq[3] = qemu_irq_invert(gpio_in[GPIO_E][3]); /* right */ 1544 gpad_irq[4] = qemu_irq_invert(gpio_in[GPIO_F][1]); /* select */ 1545 1546 stellaris_gamepad_init(5, gpad_irq, gpad_keycode); 1547 } 1548 for (i = 0; i < 7; i++) { 1549 if (board->dc4 & (1 << i)) { 1550 for (j = 0; j < 8; j++) { 1551 if (gpio_out[i][j]) { 1552 qdev_connect_gpio_out(gpio_dev[i], j, gpio_out[i][j]); 1553 } 1554 } 1555 } 1556 } 1557 1558 /* Add dummy regions for the devices we don't implement yet, 1559 * so guest accesses don't cause unlogged crashes. 1560 */ 1561 create_unimplemented_device("i2c-0", 0x40002000, 0x1000); 1562 create_unimplemented_device("i2c-2", 0x40021000, 0x1000); 1563 create_unimplemented_device("PWM", 0x40028000, 0x1000); 1564 create_unimplemented_device("QEI-0", 0x4002c000, 0x1000); 1565 create_unimplemented_device("QEI-1", 0x4002d000, 0x1000); 1566 create_unimplemented_device("analogue-comparator", 0x4003c000, 0x1000); 1567 create_unimplemented_device("hibernation", 0x400fc000, 0x1000); 1568 create_unimplemented_device("flash-control", 0x400fd000, 0x1000); 1569 1570 armv7m_load_kernel(ARM_CPU(first_cpu), ms->kernel_filename, flash_size); 1571 } 1572 1573 /* FIXME: Figure out how to generate these from stellaris_boards. */ 1574 static void lm3s811evb_init(MachineState *machine) 1575 { 1576 stellaris_init(machine, &stellaris_boards[0]); 1577 } 1578 1579 static void lm3s6965evb_init(MachineState *machine) 1580 { 1581 stellaris_init(machine, &stellaris_boards[1]); 1582 } 1583 1584 static void lm3s811evb_class_init(ObjectClass *oc, void *data) 1585 { 1586 MachineClass *mc = MACHINE_CLASS(oc); 1587 1588 mc->desc = "Stellaris LM3S811EVB (Cortex-M3)"; 1589 mc->init = lm3s811evb_init; 1590 mc->ignore_memory_transaction_failures = true; 1591 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3"); 1592 } 1593 1594 static const TypeInfo lm3s811evb_type = { 1595 .name = MACHINE_TYPE_NAME("lm3s811evb"), 1596 .parent = TYPE_MACHINE, 1597 .class_init = lm3s811evb_class_init, 1598 }; 1599 1600 static void lm3s6965evb_class_init(ObjectClass *oc, void *data) 1601 { 1602 MachineClass *mc = MACHINE_CLASS(oc); 1603 1604 mc->desc = "Stellaris LM3S6965EVB (Cortex-M3)"; 1605 mc->init = lm3s6965evb_init; 1606 mc->ignore_memory_transaction_failures = true; 1607 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3"); 1608 } 1609 1610 static const TypeInfo lm3s6965evb_type = { 1611 .name = MACHINE_TYPE_NAME("lm3s6965evb"), 1612 .parent = TYPE_MACHINE, 1613 .class_init = lm3s6965evb_class_init, 1614 }; 1615 1616 static void stellaris_machine_init(void) 1617 { 1618 type_register_static(&lm3s811evb_type); 1619 type_register_static(&lm3s6965evb_type); 1620 } 1621 1622 type_init(stellaris_machine_init) 1623 1624 static void stellaris_i2c_class_init(ObjectClass *klass, void *data) 1625 { 1626 DeviceClass *dc = DEVICE_CLASS(klass); 1627 1628 dc->vmsd = &vmstate_stellaris_i2c; 1629 } 1630 1631 static const TypeInfo stellaris_i2c_info = { 1632 .name = TYPE_STELLARIS_I2C, 1633 .parent = TYPE_SYS_BUS_DEVICE, 1634 .instance_size = sizeof(stellaris_i2c_state), 1635 .instance_init = stellaris_i2c_init, 1636 .class_init = stellaris_i2c_class_init, 1637 }; 1638 1639 static void stellaris_gptm_class_init(ObjectClass *klass, void *data) 1640 { 1641 DeviceClass *dc = DEVICE_CLASS(klass); 1642 1643 dc->vmsd = &vmstate_stellaris_gptm; 1644 dc->realize = stellaris_gptm_realize; 1645 } 1646 1647 static const TypeInfo stellaris_gptm_info = { 1648 .name = TYPE_STELLARIS_GPTM, 1649 .parent = TYPE_SYS_BUS_DEVICE, 1650 .instance_size = sizeof(gptm_state), 1651 .instance_init = stellaris_gptm_init, 1652 .class_init = stellaris_gptm_class_init, 1653 }; 1654 1655 static void stellaris_adc_class_init(ObjectClass *klass, void *data) 1656 { 1657 DeviceClass *dc = DEVICE_CLASS(klass); 1658 1659 dc->vmsd = &vmstate_stellaris_adc; 1660 } 1661 1662 static const TypeInfo stellaris_adc_info = { 1663 .name = TYPE_STELLARIS_ADC, 1664 .parent = TYPE_SYS_BUS_DEVICE, 1665 .instance_size = sizeof(stellaris_adc_state), 1666 .instance_init = stellaris_adc_init, 1667 .class_init = stellaris_adc_class_init, 1668 }; 1669 1670 static void stellaris_sys_class_init(ObjectClass *klass, void *data) 1671 { 1672 DeviceClass *dc = DEVICE_CLASS(klass); 1673 ResettableClass *rc = RESETTABLE_CLASS(klass); 1674 1675 dc->vmsd = &vmstate_stellaris_sys; 1676 rc->phases.enter = stellaris_sys_reset_enter; 1677 rc->phases.hold = stellaris_sys_reset_hold; 1678 rc->phases.exit = stellaris_sys_reset_exit; 1679 device_class_set_props(dc, stellaris_sys_properties); 1680 } 1681 1682 static const TypeInfo stellaris_sys_info = { 1683 .name = TYPE_STELLARIS_SYS, 1684 .parent = TYPE_SYS_BUS_DEVICE, 1685 .instance_size = sizeof(ssys_state), 1686 .instance_init = stellaris_sys_instance_init, 1687 .class_init = stellaris_sys_class_init, 1688 }; 1689 1690 static void stellaris_register_types(void) 1691 { 1692 type_register_static(&stellaris_i2c_info); 1693 type_register_static(&stellaris_gptm_info); 1694 type_register_static(&stellaris_adc_info); 1695 type_register_static(&stellaris_sys_info); 1696 } 1697 1698 type_init(stellaris_register_types) 1699