1 /* 2 * Luminary Micro Stellaris peripherals 3 * 4 * Copyright (c) 2006 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "hw/sysbus.h" 11 #include "hw/ssi.h" 12 #include "hw/arm/arm.h" 13 #include "hw/devices.h" 14 #include "qemu/timer.h" 15 #include "hw/i2c/i2c.h" 16 #include "net/net.h" 17 #include "hw/boards.h" 18 #include "exec/address-spaces.h" 19 20 #define GPIO_A 0 21 #define GPIO_B 1 22 #define GPIO_C 2 23 #define GPIO_D 3 24 #define GPIO_E 4 25 #define GPIO_F 5 26 #define GPIO_G 6 27 28 #define BP_OLED_I2C 0x01 29 #define BP_OLED_SSI 0x02 30 #define BP_GAMEPAD 0x04 31 32 typedef const struct { 33 const char *name; 34 uint32_t did0; 35 uint32_t did1; 36 uint32_t dc0; 37 uint32_t dc1; 38 uint32_t dc2; 39 uint32_t dc3; 40 uint32_t dc4; 41 uint32_t peripherals; 42 } stellaris_board_info; 43 44 /* General purpose timer module. */ 45 46 #define TYPE_STELLARIS_GPTM "stellaris-gptm" 47 #define STELLARIS_GPTM(obj) \ 48 OBJECT_CHECK(gptm_state, (obj), TYPE_STELLARIS_GPTM) 49 50 typedef struct gptm_state { 51 SysBusDevice parent_obj; 52 53 MemoryRegion iomem; 54 uint32_t config; 55 uint32_t mode[2]; 56 uint32_t control; 57 uint32_t state; 58 uint32_t mask; 59 uint32_t load[2]; 60 uint32_t match[2]; 61 uint32_t prescale[2]; 62 uint32_t match_prescale[2]; 63 uint32_t rtc; 64 int64_t tick[2]; 65 struct gptm_state *opaque[2]; 66 QEMUTimer *timer[2]; 67 /* The timers have an alternate output used to trigger the ADC. */ 68 qemu_irq trigger; 69 qemu_irq irq; 70 } gptm_state; 71 72 static void gptm_update_irq(gptm_state *s) 73 { 74 int level; 75 level = (s->state & s->mask) != 0; 76 qemu_set_irq(s->irq, level); 77 } 78 79 static void gptm_stop(gptm_state *s, int n) 80 { 81 qemu_del_timer(s->timer[n]); 82 } 83 84 static void gptm_reload(gptm_state *s, int n, int reset) 85 { 86 int64_t tick; 87 if (reset) 88 tick = qemu_get_clock_ns(vm_clock); 89 else 90 tick = s->tick[n]; 91 92 if (s->config == 0) { 93 /* 32-bit CountDown. */ 94 uint32_t count; 95 count = s->load[0] | (s->load[1] << 16); 96 tick += (int64_t)count * system_clock_scale; 97 } else if (s->config == 1) { 98 /* 32-bit RTC. 1Hz tick. */ 99 tick += get_ticks_per_sec(); 100 } else if (s->mode[n] == 0xa) { 101 /* PWM mode. Not implemented. */ 102 } else { 103 hw_error("TODO: 16-bit timer mode 0x%x\n", s->mode[n]); 104 } 105 s->tick[n] = tick; 106 qemu_mod_timer(s->timer[n], tick); 107 } 108 109 static void gptm_tick(void *opaque) 110 { 111 gptm_state **p = (gptm_state **)opaque; 112 gptm_state *s; 113 int n; 114 115 s = *p; 116 n = p - s->opaque; 117 if (s->config == 0) { 118 s->state |= 1; 119 if ((s->control & 0x20)) { 120 /* Output trigger. */ 121 qemu_irq_pulse(s->trigger); 122 } 123 if (s->mode[0] & 1) { 124 /* One-shot. */ 125 s->control &= ~1; 126 } else { 127 /* Periodic. */ 128 gptm_reload(s, 0, 0); 129 } 130 } else if (s->config == 1) { 131 /* RTC. */ 132 uint32_t match; 133 s->rtc++; 134 match = s->match[0] | (s->match[1] << 16); 135 if (s->rtc > match) 136 s->rtc = 0; 137 if (s->rtc == 0) { 138 s->state |= 8; 139 } 140 gptm_reload(s, 0, 0); 141 } else if (s->mode[n] == 0xa) { 142 /* PWM mode. Not implemented. */ 143 } else { 144 hw_error("TODO: 16-bit timer mode 0x%x\n", s->mode[n]); 145 } 146 gptm_update_irq(s); 147 } 148 149 static uint64_t gptm_read(void *opaque, hwaddr offset, 150 unsigned size) 151 { 152 gptm_state *s = (gptm_state *)opaque; 153 154 switch (offset) { 155 case 0x00: /* CFG */ 156 return s->config; 157 case 0x04: /* TAMR */ 158 return s->mode[0]; 159 case 0x08: /* TBMR */ 160 return s->mode[1]; 161 case 0x0c: /* CTL */ 162 return s->control; 163 case 0x18: /* IMR */ 164 return s->mask; 165 case 0x1c: /* RIS */ 166 return s->state; 167 case 0x20: /* MIS */ 168 return s->state & s->mask; 169 case 0x24: /* CR */ 170 return 0; 171 case 0x28: /* TAILR */ 172 return s->load[0] | ((s->config < 4) ? (s->load[1] << 16) : 0); 173 case 0x2c: /* TBILR */ 174 return s->load[1]; 175 case 0x30: /* TAMARCHR */ 176 return s->match[0] | ((s->config < 4) ? (s->match[1] << 16) : 0); 177 case 0x34: /* TBMATCHR */ 178 return s->match[1]; 179 case 0x38: /* TAPR */ 180 return s->prescale[0]; 181 case 0x3c: /* TBPR */ 182 return s->prescale[1]; 183 case 0x40: /* TAPMR */ 184 return s->match_prescale[0]; 185 case 0x44: /* TBPMR */ 186 return s->match_prescale[1]; 187 case 0x48: /* TAR */ 188 if (s->control == 1) 189 return s->rtc; 190 case 0x4c: /* TBR */ 191 hw_error("TODO: Timer value read\n"); 192 default: 193 hw_error("gptm_read: Bad offset 0x%x\n", (int)offset); 194 return 0; 195 } 196 } 197 198 static void gptm_write(void *opaque, hwaddr offset, 199 uint64_t value, unsigned size) 200 { 201 gptm_state *s = (gptm_state *)opaque; 202 uint32_t oldval; 203 204 /* The timers should be disabled before changing the configuration. 205 We take advantage of this and defer everything until the timer 206 is enabled. */ 207 switch (offset) { 208 case 0x00: /* CFG */ 209 s->config = value; 210 break; 211 case 0x04: /* TAMR */ 212 s->mode[0] = value; 213 break; 214 case 0x08: /* TBMR */ 215 s->mode[1] = value; 216 break; 217 case 0x0c: /* CTL */ 218 oldval = s->control; 219 s->control = value; 220 /* TODO: Implement pause. */ 221 if ((oldval ^ value) & 1) { 222 if (value & 1) { 223 gptm_reload(s, 0, 1); 224 } else { 225 gptm_stop(s, 0); 226 } 227 } 228 if (((oldval ^ value) & 0x100) && s->config >= 4) { 229 if (value & 0x100) { 230 gptm_reload(s, 1, 1); 231 } else { 232 gptm_stop(s, 1); 233 } 234 } 235 break; 236 case 0x18: /* IMR */ 237 s->mask = value & 0x77; 238 gptm_update_irq(s); 239 break; 240 case 0x24: /* CR */ 241 s->state &= ~value; 242 break; 243 case 0x28: /* TAILR */ 244 s->load[0] = value & 0xffff; 245 if (s->config < 4) { 246 s->load[1] = value >> 16; 247 } 248 break; 249 case 0x2c: /* TBILR */ 250 s->load[1] = value & 0xffff; 251 break; 252 case 0x30: /* TAMARCHR */ 253 s->match[0] = value & 0xffff; 254 if (s->config < 4) { 255 s->match[1] = value >> 16; 256 } 257 break; 258 case 0x34: /* TBMATCHR */ 259 s->match[1] = value >> 16; 260 break; 261 case 0x38: /* TAPR */ 262 s->prescale[0] = value; 263 break; 264 case 0x3c: /* TBPR */ 265 s->prescale[1] = value; 266 break; 267 case 0x40: /* TAPMR */ 268 s->match_prescale[0] = value; 269 break; 270 case 0x44: /* TBPMR */ 271 s->match_prescale[0] = value; 272 break; 273 default: 274 hw_error("gptm_write: Bad offset 0x%x\n", (int)offset); 275 } 276 gptm_update_irq(s); 277 } 278 279 static const MemoryRegionOps gptm_ops = { 280 .read = gptm_read, 281 .write = gptm_write, 282 .endianness = DEVICE_NATIVE_ENDIAN, 283 }; 284 285 static const VMStateDescription vmstate_stellaris_gptm = { 286 .name = "stellaris_gptm", 287 .version_id = 1, 288 .minimum_version_id = 1, 289 .minimum_version_id_old = 1, 290 .fields = (VMStateField[]) { 291 VMSTATE_UINT32(config, gptm_state), 292 VMSTATE_UINT32_ARRAY(mode, gptm_state, 2), 293 VMSTATE_UINT32(control, gptm_state), 294 VMSTATE_UINT32(state, gptm_state), 295 VMSTATE_UINT32(mask, gptm_state), 296 VMSTATE_UNUSED(8), 297 VMSTATE_UINT32_ARRAY(load, gptm_state, 2), 298 VMSTATE_UINT32_ARRAY(match, gptm_state, 2), 299 VMSTATE_UINT32_ARRAY(prescale, gptm_state, 2), 300 VMSTATE_UINT32_ARRAY(match_prescale, gptm_state, 2), 301 VMSTATE_UINT32(rtc, gptm_state), 302 VMSTATE_INT64_ARRAY(tick, gptm_state, 2), 303 VMSTATE_TIMER_ARRAY(timer, gptm_state, 2), 304 VMSTATE_END_OF_LIST() 305 } 306 }; 307 308 static int stellaris_gptm_init(SysBusDevice *sbd) 309 { 310 DeviceState *dev = DEVICE(sbd); 311 gptm_state *s = STELLARIS_GPTM(dev); 312 313 sysbus_init_irq(sbd, &s->irq); 314 qdev_init_gpio_out(dev, &s->trigger, 1); 315 316 memory_region_init_io(&s->iomem, OBJECT(s), &gptm_ops, s, 317 "gptm", 0x1000); 318 sysbus_init_mmio(sbd, &s->iomem); 319 320 s->opaque[0] = s->opaque[1] = s; 321 s->timer[0] = qemu_new_timer_ns(vm_clock, gptm_tick, &s->opaque[0]); 322 s->timer[1] = qemu_new_timer_ns(vm_clock, gptm_tick, &s->opaque[1]); 323 vmstate_register(dev, -1, &vmstate_stellaris_gptm, s); 324 return 0; 325 } 326 327 328 /* System controller. */ 329 330 typedef struct { 331 MemoryRegion iomem; 332 uint32_t pborctl; 333 uint32_t ldopctl; 334 uint32_t int_status; 335 uint32_t int_mask; 336 uint32_t resc; 337 uint32_t rcc; 338 uint32_t rcc2; 339 uint32_t rcgc[3]; 340 uint32_t scgc[3]; 341 uint32_t dcgc[3]; 342 uint32_t clkvclr; 343 uint32_t ldoarst; 344 uint32_t user0; 345 uint32_t user1; 346 qemu_irq irq; 347 stellaris_board_info *board; 348 } ssys_state; 349 350 static void ssys_update(ssys_state *s) 351 { 352 qemu_set_irq(s->irq, (s->int_status & s->int_mask) != 0); 353 } 354 355 static uint32_t pllcfg_sandstorm[16] = { 356 0x31c0, /* 1 Mhz */ 357 0x1ae0, /* 1.8432 Mhz */ 358 0x18c0, /* 2 Mhz */ 359 0xd573, /* 2.4576 Mhz */ 360 0x37a6, /* 3.57954 Mhz */ 361 0x1ae2, /* 3.6864 Mhz */ 362 0x0c40, /* 4 Mhz */ 363 0x98bc, /* 4.906 Mhz */ 364 0x935b, /* 4.9152 Mhz */ 365 0x09c0, /* 5 Mhz */ 366 0x4dee, /* 5.12 Mhz */ 367 0x0c41, /* 6 Mhz */ 368 0x75db, /* 6.144 Mhz */ 369 0x1ae6, /* 7.3728 Mhz */ 370 0x0600, /* 8 Mhz */ 371 0x585b /* 8.192 Mhz */ 372 }; 373 374 static uint32_t pllcfg_fury[16] = { 375 0x3200, /* 1 Mhz */ 376 0x1b20, /* 1.8432 Mhz */ 377 0x1900, /* 2 Mhz */ 378 0xf42b, /* 2.4576 Mhz */ 379 0x37e3, /* 3.57954 Mhz */ 380 0x1b21, /* 3.6864 Mhz */ 381 0x0c80, /* 4 Mhz */ 382 0x98ee, /* 4.906 Mhz */ 383 0xd5b4, /* 4.9152 Mhz */ 384 0x0a00, /* 5 Mhz */ 385 0x4e27, /* 5.12 Mhz */ 386 0x1902, /* 6 Mhz */ 387 0xec1c, /* 6.144 Mhz */ 388 0x1b23, /* 7.3728 Mhz */ 389 0x0640, /* 8 Mhz */ 390 0xb11c /* 8.192 Mhz */ 391 }; 392 393 #define DID0_VER_MASK 0x70000000 394 #define DID0_VER_0 0x00000000 395 #define DID0_VER_1 0x10000000 396 397 #define DID0_CLASS_MASK 0x00FF0000 398 #define DID0_CLASS_SANDSTORM 0x00000000 399 #define DID0_CLASS_FURY 0x00010000 400 401 static int ssys_board_class(const ssys_state *s) 402 { 403 uint32_t did0 = s->board->did0; 404 switch (did0 & DID0_VER_MASK) { 405 case DID0_VER_0: 406 return DID0_CLASS_SANDSTORM; 407 case DID0_VER_1: 408 switch (did0 & DID0_CLASS_MASK) { 409 case DID0_CLASS_SANDSTORM: 410 case DID0_CLASS_FURY: 411 return did0 & DID0_CLASS_MASK; 412 } 413 /* for unknown classes, fall through */ 414 default: 415 hw_error("ssys_board_class: Unknown class 0x%08x\n", did0); 416 } 417 } 418 419 static uint64_t ssys_read(void *opaque, hwaddr offset, 420 unsigned size) 421 { 422 ssys_state *s = (ssys_state *)opaque; 423 424 switch (offset) { 425 case 0x000: /* DID0 */ 426 return s->board->did0; 427 case 0x004: /* DID1 */ 428 return s->board->did1; 429 case 0x008: /* DC0 */ 430 return s->board->dc0; 431 case 0x010: /* DC1 */ 432 return s->board->dc1; 433 case 0x014: /* DC2 */ 434 return s->board->dc2; 435 case 0x018: /* DC3 */ 436 return s->board->dc3; 437 case 0x01c: /* DC4 */ 438 return s->board->dc4; 439 case 0x030: /* PBORCTL */ 440 return s->pborctl; 441 case 0x034: /* LDOPCTL */ 442 return s->ldopctl; 443 case 0x040: /* SRCR0 */ 444 return 0; 445 case 0x044: /* SRCR1 */ 446 return 0; 447 case 0x048: /* SRCR2 */ 448 return 0; 449 case 0x050: /* RIS */ 450 return s->int_status; 451 case 0x054: /* IMC */ 452 return s->int_mask; 453 case 0x058: /* MISC */ 454 return s->int_status & s->int_mask; 455 case 0x05c: /* RESC */ 456 return s->resc; 457 case 0x060: /* RCC */ 458 return s->rcc; 459 case 0x064: /* PLLCFG */ 460 { 461 int xtal; 462 xtal = (s->rcc >> 6) & 0xf; 463 switch (ssys_board_class(s)) { 464 case DID0_CLASS_FURY: 465 return pllcfg_fury[xtal]; 466 case DID0_CLASS_SANDSTORM: 467 return pllcfg_sandstorm[xtal]; 468 default: 469 hw_error("ssys_read: Unhandled class for PLLCFG read.\n"); 470 return 0; 471 } 472 } 473 case 0x070: /* RCC2 */ 474 return s->rcc2; 475 case 0x100: /* RCGC0 */ 476 return s->rcgc[0]; 477 case 0x104: /* RCGC1 */ 478 return s->rcgc[1]; 479 case 0x108: /* RCGC2 */ 480 return s->rcgc[2]; 481 case 0x110: /* SCGC0 */ 482 return s->scgc[0]; 483 case 0x114: /* SCGC1 */ 484 return s->scgc[1]; 485 case 0x118: /* SCGC2 */ 486 return s->scgc[2]; 487 case 0x120: /* DCGC0 */ 488 return s->dcgc[0]; 489 case 0x124: /* DCGC1 */ 490 return s->dcgc[1]; 491 case 0x128: /* DCGC2 */ 492 return s->dcgc[2]; 493 case 0x150: /* CLKVCLR */ 494 return s->clkvclr; 495 case 0x160: /* LDOARST */ 496 return s->ldoarst; 497 case 0x1e0: /* USER0 */ 498 return s->user0; 499 case 0x1e4: /* USER1 */ 500 return s->user1; 501 default: 502 hw_error("ssys_read: Bad offset 0x%x\n", (int)offset); 503 return 0; 504 } 505 } 506 507 static bool ssys_use_rcc2(ssys_state *s) 508 { 509 return (s->rcc2 >> 31) & 0x1; 510 } 511 512 /* 513 * Caculate the sys. clock period in ms. 514 */ 515 static void ssys_calculate_system_clock(ssys_state *s) 516 { 517 if (ssys_use_rcc2(s)) { 518 system_clock_scale = 5 * (((s->rcc2 >> 23) & 0x3f) + 1); 519 } else { 520 system_clock_scale = 5 * (((s->rcc >> 23) & 0xf) + 1); 521 } 522 } 523 524 static void ssys_write(void *opaque, hwaddr offset, 525 uint64_t value, unsigned size) 526 { 527 ssys_state *s = (ssys_state *)opaque; 528 529 switch (offset) { 530 case 0x030: /* PBORCTL */ 531 s->pborctl = value & 0xffff; 532 break; 533 case 0x034: /* LDOPCTL */ 534 s->ldopctl = value & 0x1f; 535 break; 536 case 0x040: /* SRCR0 */ 537 case 0x044: /* SRCR1 */ 538 case 0x048: /* SRCR2 */ 539 fprintf(stderr, "Peripheral reset not implemented\n"); 540 break; 541 case 0x054: /* IMC */ 542 s->int_mask = value & 0x7f; 543 break; 544 case 0x058: /* MISC */ 545 s->int_status &= ~value; 546 break; 547 case 0x05c: /* RESC */ 548 s->resc = value & 0x3f; 549 break; 550 case 0x060: /* RCC */ 551 if ((s->rcc & (1 << 13)) != 0 && (value & (1 << 13)) == 0) { 552 /* PLL enable. */ 553 s->int_status |= (1 << 6); 554 } 555 s->rcc = value; 556 ssys_calculate_system_clock(s); 557 break; 558 case 0x070: /* RCC2 */ 559 if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) { 560 break; 561 } 562 563 if ((s->rcc2 & (1 << 13)) != 0 && (value & (1 << 13)) == 0) { 564 /* PLL enable. */ 565 s->int_status |= (1 << 6); 566 } 567 s->rcc2 = value; 568 ssys_calculate_system_clock(s); 569 break; 570 case 0x100: /* RCGC0 */ 571 s->rcgc[0] = value; 572 break; 573 case 0x104: /* RCGC1 */ 574 s->rcgc[1] = value; 575 break; 576 case 0x108: /* RCGC2 */ 577 s->rcgc[2] = value; 578 break; 579 case 0x110: /* SCGC0 */ 580 s->scgc[0] = value; 581 break; 582 case 0x114: /* SCGC1 */ 583 s->scgc[1] = value; 584 break; 585 case 0x118: /* SCGC2 */ 586 s->scgc[2] = value; 587 break; 588 case 0x120: /* DCGC0 */ 589 s->dcgc[0] = value; 590 break; 591 case 0x124: /* DCGC1 */ 592 s->dcgc[1] = value; 593 break; 594 case 0x128: /* DCGC2 */ 595 s->dcgc[2] = value; 596 break; 597 case 0x150: /* CLKVCLR */ 598 s->clkvclr = value; 599 break; 600 case 0x160: /* LDOARST */ 601 s->ldoarst = value; 602 break; 603 default: 604 hw_error("ssys_write: Bad offset 0x%x\n", (int)offset); 605 } 606 ssys_update(s); 607 } 608 609 static const MemoryRegionOps ssys_ops = { 610 .read = ssys_read, 611 .write = ssys_write, 612 .endianness = DEVICE_NATIVE_ENDIAN, 613 }; 614 615 static void ssys_reset(void *opaque) 616 { 617 ssys_state *s = (ssys_state *)opaque; 618 619 s->pborctl = 0x7ffd; 620 s->rcc = 0x078e3ac0; 621 622 if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) { 623 s->rcc2 = 0; 624 } else { 625 s->rcc2 = 0x07802810; 626 } 627 s->rcgc[0] = 1; 628 s->scgc[0] = 1; 629 s->dcgc[0] = 1; 630 ssys_calculate_system_clock(s); 631 } 632 633 static int stellaris_sys_post_load(void *opaque, int version_id) 634 { 635 ssys_state *s = opaque; 636 637 ssys_calculate_system_clock(s); 638 639 return 0; 640 } 641 642 static const VMStateDescription vmstate_stellaris_sys = { 643 .name = "stellaris_sys", 644 .version_id = 2, 645 .minimum_version_id = 1, 646 .minimum_version_id_old = 1, 647 .post_load = stellaris_sys_post_load, 648 .fields = (VMStateField[]) { 649 VMSTATE_UINT32(pborctl, ssys_state), 650 VMSTATE_UINT32(ldopctl, ssys_state), 651 VMSTATE_UINT32(int_mask, ssys_state), 652 VMSTATE_UINT32(int_status, ssys_state), 653 VMSTATE_UINT32(resc, ssys_state), 654 VMSTATE_UINT32(rcc, ssys_state), 655 VMSTATE_UINT32_V(rcc2, ssys_state, 2), 656 VMSTATE_UINT32_ARRAY(rcgc, ssys_state, 3), 657 VMSTATE_UINT32_ARRAY(scgc, ssys_state, 3), 658 VMSTATE_UINT32_ARRAY(dcgc, ssys_state, 3), 659 VMSTATE_UINT32(clkvclr, ssys_state), 660 VMSTATE_UINT32(ldoarst, ssys_state), 661 VMSTATE_END_OF_LIST() 662 } 663 }; 664 665 static int stellaris_sys_init(uint32_t base, qemu_irq irq, 666 stellaris_board_info * board, 667 uint8_t *macaddr) 668 { 669 ssys_state *s; 670 671 s = (ssys_state *)g_malloc0(sizeof(ssys_state)); 672 s->irq = irq; 673 s->board = board; 674 /* Most devices come preprogrammed with a MAC address in the user data. */ 675 s->user0 = macaddr[0] | (macaddr[1] << 8) | (macaddr[2] << 16); 676 s->user1 = macaddr[3] | (macaddr[4] << 8) | (macaddr[5] << 16); 677 678 memory_region_init_io(&s->iomem, NULL, &ssys_ops, s, "ssys", 0x00001000); 679 memory_region_add_subregion(get_system_memory(), base, &s->iomem); 680 ssys_reset(s); 681 vmstate_register(NULL, -1, &vmstate_stellaris_sys, s); 682 return 0; 683 } 684 685 686 /* I2C controller. */ 687 688 typedef struct { 689 SysBusDevice busdev; 690 i2c_bus *bus; 691 qemu_irq irq; 692 MemoryRegion iomem; 693 uint32_t msa; 694 uint32_t mcs; 695 uint32_t mdr; 696 uint32_t mtpr; 697 uint32_t mimr; 698 uint32_t mris; 699 uint32_t mcr; 700 } stellaris_i2c_state; 701 702 #define STELLARIS_I2C_MCS_BUSY 0x01 703 #define STELLARIS_I2C_MCS_ERROR 0x02 704 #define STELLARIS_I2C_MCS_ADRACK 0x04 705 #define STELLARIS_I2C_MCS_DATACK 0x08 706 #define STELLARIS_I2C_MCS_ARBLST 0x10 707 #define STELLARIS_I2C_MCS_IDLE 0x20 708 #define STELLARIS_I2C_MCS_BUSBSY 0x40 709 710 static uint64_t stellaris_i2c_read(void *opaque, hwaddr offset, 711 unsigned size) 712 { 713 stellaris_i2c_state *s = (stellaris_i2c_state *)opaque; 714 715 switch (offset) { 716 case 0x00: /* MSA */ 717 return s->msa; 718 case 0x04: /* MCS */ 719 /* We don't emulate timing, so the controller is never busy. */ 720 return s->mcs | STELLARIS_I2C_MCS_IDLE; 721 case 0x08: /* MDR */ 722 return s->mdr; 723 case 0x0c: /* MTPR */ 724 return s->mtpr; 725 case 0x10: /* MIMR */ 726 return s->mimr; 727 case 0x14: /* MRIS */ 728 return s->mris; 729 case 0x18: /* MMIS */ 730 return s->mris & s->mimr; 731 case 0x20: /* MCR */ 732 return s->mcr; 733 default: 734 hw_error("strllaris_i2c_read: Bad offset 0x%x\n", (int)offset); 735 return 0; 736 } 737 } 738 739 static void stellaris_i2c_update(stellaris_i2c_state *s) 740 { 741 int level; 742 743 level = (s->mris & s->mimr) != 0; 744 qemu_set_irq(s->irq, level); 745 } 746 747 static void stellaris_i2c_write(void *opaque, hwaddr offset, 748 uint64_t value, unsigned size) 749 { 750 stellaris_i2c_state *s = (stellaris_i2c_state *)opaque; 751 752 switch (offset) { 753 case 0x00: /* MSA */ 754 s->msa = value & 0xff; 755 break; 756 case 0x04: /* MCS */ 757 if ((s->mcr & 0x10) == 0) { 758 /* Disabled. Do nothing. */ 759 break; 760 } 761 /* Grab the bus if this is starting a transfer. */ 762 if ((value & 2) && (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) { 763 if (i2c_start_transfer(s->bus, s->msa >> 1, s->msa & 1)) { 764 s->mcs |= STELLARIS_I2C_MCS_ARBLST; 765 } else { 766 s->mcs &= ~STELLARIS_I2C_MCS_ARBLST; 767 s->mcs |= STELLARIS_I2C_MCS_BUSBSY; 768 } 769 } 770 /* If we don't have the bus then indicate an error. */ 771 if (!i2c_bus_busy(s->bus) 772 || (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) { 773 s->mcs |= STELLARIS_I2C_MCS_ERROR; 774 break; 775 } 776 s->mcs &= ~STELLARIS_I2C_MCS_ERROR; 777 if (value & 1) { 778 /* Transfer a byte. */ 779 /* TODO: Handle errors. */ 780 if (s->msa & 1) { 781 /* Recv */ 782 s->mdr = i2c_recv(s->bus) & 0xff; 783 } else { 784 /* Send */ 785 i2c_send(s->bus, s->mdr); 786 } 787 /* Raise an interrupt. */ 788 s->mris |= 1; 789 } 790 if (value & 4) { 791 /* Finish transfer. */ 792 i2c_end_transfer(s->bus); 793 s->mcs &= ~STELLARIS_I2C_MCS_BUSBSY; 794 } 795 break; 796 case 0x08: /* MDR */ 797 s->mdr = value & 0xff; 798 break; 799 case 0x0c: /* MTPR */ 800 s->mtpr = value & 0xff; 801 break; 802 case 0x10: /* MIMR */ 803 s->mimr = 1; 804 break; 805 case 0x1c: /* MICR */ 806 s->mris &= ~value; 807 break; 808 case 0x20: /* MCR */ 809 if (value & 1) 810 hw_error( 811 "stellaris_i2c_write: Loopback not implemented\n"); 812 if (value & 0x20) 813 hw_error( 814 "stellaris_i2c_write: Slave mode not implemented\n"); 815 s->mcr = value & 0x31; 816 break; 817 default: 818 hw_error("stellaris_i2c_write: Bad offset 0x%x\n", 819 (int)offset); 820 } 821 stellaris_i2c_update(s); 822 } 823 824 static void stellaris_i2c_reset(stellaris_i2c_state *s) 825 { 826 if (s->mcs & STELLARIS_I2C_MCS_BUSBSY) 827 i2c_end_transfer(s->bus); 828 829 s->msa = 0; 830 s->mcs = 0; 831 s->mdr = 0; 832 s->mtpr = 1; 833 s->mimr = 0; 834 s->mris = 0; 835 s->mcr = 0; 836 stellaris_i2c_update(s); 837 } 838 839 static const MemoryRegionOps stellaris_i2c_ops = { 840 .read = stellaris_i2c_read, 841 .write = stellaris_i2c_write, 842 .endianness = DEVICE_NATIVE_ENDIAN, 843 }; 844 845 static const VMStateDescription vmstate_stellaris_i2c = { 846 .name = "stellaris_i2c", 847 .version_id = 1, 848 .minimum_version_id = 1, 849 .minimum_version_id_old = 1, 850 .fields = (VMStateField[]) { 851 VMSTATE_UINT32(msa, stellaris_i2c_state), 852 VMSTATE_UINT32(mcs, stellaris_i2c_state), 853 VMSTATE_UINT32(mdr, stellaris_i2c_state), 854 VMSTATE_UINT32(mtpr, stellaris_i2c_state), 855 VMSTATE_UINT32(mimr, stellaris_i2c_state), 856 VMSTATE_UINT32(mris, stellaris_i2c_state), 857 VMSTATE_UINT32(mcr, stellaris_i2c_state), 858 VMSTATE_END_OF_LIST() 859 } 860 }; 861 862 static int stellaris_i2c_init(SysBusDevice * dev) 863 { 864 stellaris_i2c_state *s = FROM_SYSBUS(stellaris_i2c_state, dev); 865 i2c_bus *bus; 866 867 sysbus_init_irq(dev, &s->irq); 868 bus = i2c_init_bus(&dev->qdev, "i2c"); 869 s->bus = bus; 870 871 memory_region_init_io(&s->iomem, OBJECT(s), &stellaris_i2c_ops, s, 872 "i2c", 0x1000); 873 sysbus_init_mmio(dev, &s->iomem); 874 /* ??? For now we only implement the master interface. */ 875 stellaris_i2c_reset(s); 876 vmstate_register(&dev->qdev, -1, &vmstate_stellaris_i2c, s); 877 return 0; 878 } 879 880 /* Analogue to Digital Converter. This is only partially implemented, 881 enough for applications that use a combined ADC and timer tick. */ 882 883 #define STELLARIS_ADC_EM_CONTROLLER 0 884 #define STELLARIS_ADC_EM_COMP 1 885 #define STELLARIS_ADC_EM_EXTERNAL 4 886 #define STELLARIS_ADC_EM_TIMER 5 887 #define STELLARIS_ADC_EM_PWM0 6 888 #define STELLARIS_ADC_EM_PWM1 7 889 #define STELLARIS_ADC_EM_PWM2 8 890 891 #define STELLARIS_ADC_FIFO_EMPTY 0x0100 892 #define STELLARIS_ADC_FIFO_FULL 0x1000 893 894 typedef struct 895 { 896 SysBusDevice busdev; 897 MemoryRegion iomem; 898 uint32_t actss; 899 uint32_t ris; 900 uint32_t im; 901 uint32_t emux; 902 uint32_t ostat; 903 uint32_t ustat; 904 uint32_t sspri; 905 uint32_t sac; 906 struct { 907 uint32_t state; 908 uint32_t data[16]; 909 } fifo[4]; 910 uint32_t ssmux[4]; 911 uint32_t ssctl[4]; 912 uint32_t noise; 913 qemu_irq irq[4]; 914 } stellaris_adc_state; 915 916 static uint32_t stellaris_adc_fifo_read(stellaris_adc_state *s, int n) 917 { 918 int tail; 919 920 tail = s->fifo[n].state & 0xf; 921 if (s->fifo[n].state & STELLARIS_ADC_FIFO_EMPTY) { 922 s->ustat |= 1 << n; 923 } else { 924 s->fifo[n].state = (s->fifo[n].state & ~0xf) | ((tail + 1) & 0xf); 925 s->fifo[n].state &= ~STELLARIS_ADC_FIFO_FULL; 926 if (tail + 1 == ((s->fifo[n].state >> 4) & 0xf)) 927 s->fifo[n].state |= STELLARIS_ADC_FIFO_EMPTY; 928 } 929 return s->fifo[n].data[tail]; 930 } 931 932 static void stellaris_adc_fifo_write(stellaris_adc_state *s, int n, 933 uint32_t value) 934 { 935 int head; 936 937 /* TODO: Real hardware has limited size FIFOs. We have a full 16 entry 938 FIFO fir each sequencer. */ 939 head = (s->fifo[n].state >> 4) & 0xf; 940 if (s->fifo[n].state & STELLARIS_ADC_FIFO_FULL) { 941 s->ostat |= 1 << n; 942 return; 943 } 944 s->fifo[n].data[head] = value; 945 head = (head + 1) & 0xf; 946 s->fifo[n].state &= ~STELLARIS_ADC_FIFO_EMPTY; 947 s->fifo[n].state = (s->fifo[n].state & ~0xf0) | (head << 4); 948 if ((s->fifo[n].state & 0xf) == head) 949 s->fifo[n].state |= STELLARIS_ADC_FIFO_FULL; 950 } 951 952 static void stellaris_adc_update(stellaris_adc_state *s) 953 { 954 int level; 955 int n; 956 957 for (n = 0; n < 4; n++) { 958 level = (s->ris & s->im & (1 << n)) != 0; 959 qemu_set_irq(s->irq[n], level); 960 } 961 } 962 963 static void stellaris_adc_trigger(void *opaque, int irq, int level) 964 { 965 stellaris_adc_state *s = (stellaris_adc_state *)opaque; 966 int n; 967 968 for (n = 0; n < 4; n++) { 969 if ((s->actss & (1 << n)) == 0) { 970 continue; 971 } 972 973 if (((s->emux >> (n * 4)) & 0xff) != 5) { 974 continue; 975 } 976 977 /* Some applications use the ADC as a random number source, so introduce 978 some variation into the signal. */ 979 s->noise = s->noise * 314159 + 1; 980 /* ??? actual inputs not implemented. Return an arbitrary value. */ 981 stellaris_adc_fifo_write(s, n, 0x200 + ((s->noise >> 16) & 7)); 982 s->ris |= (1 << n); 983 stellaris_adc_update(s); 984 } 985 } 986 987 static void stellaris_adc_reset(stellaris_adc_state *s) 988 { 989 int n; 990 991 for (n = 0; n < 4; n++) { 992 s->ssmux[n] = 0; 993 s->ssctl[n] = 0; 994 s->fifo[n].state = STELLARIS_ADC_FIFO_EMPTY; 995 } 996 } 997 998 static uint64_t stellaris_adc_read(void *opaque, hwaddr offset, 999 unsigned size) 1000 { 1001 stellaris_adc_state *s = (stellaris_adc_state *)opaque; 1002 1003 /* TODO: Implement this. */ 1004 if (offset >= 0x40 && offset < 0xc0) { 1005 int n; 1006 n = (offset - 0x40) >> 5; 1007 switch (offset & 0x1f) { 1008 case 0x00: /* SSMUX */ 1009 return s->ssmux[n]; 1010 case 0x04: /* SSCTL */ 1011 return s->ssctl[n]; 1012 case 0x08: /* SSFIFO */ 1013 return stellaris_adc_fifo_read(s, n); 1014 case 0x0c: /* SSFSTAT */ 1015 return s->fifo[n].state; 1016 default: 1017 break; 1018 } 1019 } 1020 switch (offset) { 1021 case 0x00: /* ACTSS */ 1022 return s->actss; 1023 case 0x04: /* RIS */ 1024 return s->ris; 1025 case 0x08: /* IM */ 1026 return s->im; 1027 case 0x0c: /* ISC */ 1028 return s->ris & s->im; 1029 case 0x10: /* OSTAT */ 1030 return s->ostat; 1031 case 0x14: /* EMUX */ 1032 return s->emux; 1033 case 0x18: /* USTAT */ 1034 return s->ustat; 1035 case 0x20: /* SSPRI */ 1036 return s->sspri; 1037 case 0x30: /* SAC */ 1038 return s->sac; 1039 default: 1040 hw_error("strllaris_adc_read: Bad offset 0x%x\n", 1041 (int)offset); 1042 return 0; 1043 } 1044 } 1045 1046 static void stellaris_adc_write(void *opaque, hwaddr offset, 1047 uint64_t value, unsigned size) 1048 { 1049 stellaris_adc_state *s = (stellaris_adc_state *)opaque; 1050 1051 /* TODO: Implement this. */ 1052 if (offset >= 0x40 && offset < 0xc0) { 1053 int n; 1054 n = (offset - 0x40) >> 5; 1055 switch (offset & 0x1f) { 1056 case 0x00: /* SSMUX */ 1057 s->ssmux[n] = value & 0x33333333; 1058 return; 1059 case 0x04: /* SSCTL */ 1060 if (value != 6) { 1061 hw_error("ADC: Unimplemented sequence %" PRIx64 "\n", 1062 value); 1063 } 1064 s->ssctl[n] = value; 1065 return; 1066 default: 1067 break; 1068 } 1069 } 1070 switch (offset) { 1071 case 0x00: /* ACTSS */ 1072 s->actss = value & 0xf; 1073 break; 1074 case 0x08: /* IM */ 1075 s->im = value; 1076 break; 1077 case 0x0c: /* ISC */ 1078 s->ris &= ~value; 1079 break; 1080 case 0x10: /* OSTAT */ 1081 s->ostat &= ~value; 1082 break; 1083 case 0x14: /* EMUX */ 1084 s->emux = value; 1085 break; 1086 case 0x18: /* USTAT */ 1087 s->ustat &= ~value; 1088 break; 1089 case 0x20: /* SSPRI */ 1090 s->sspri = value; 1091 break; 1092 case 0x28: /* PSSI */ 1093 hw_error("Not implemented: ADC sample initiate\n"); 1094 break; 1095 case 0x30: /* SAC */ 1096 s->sac = value; 1097 break; 1098 default: 1099 hw_error("stellaris_adc_write: Bad offset 0x%x\n", (int)offset); 1100 } 1101 stellaris_adc_update(s); 1102 } 1103 1104 static const MemoryRegionOps stellaris_adc_ops = { 1105 .read = stellaris_adc_read, 1106 .write = stellaris_adc_write, 1107 .endianness = DEVICE_NATIVE_ENDIAN, 1108 }; 1109 1110 static const VMStateDescription vmstate_stellaris_adc = { 1111 .name = "stellaris_adc", 1112 .version_id = 1, 1113 .minimum_version_id = 1, 1114 .minimum_version_id_old = 1, 1115 .fields = (VMStateField[]) { 1116 VMSTATE_UINT32(actss, stellaris_adc_state), 1117 VMSTATE_UINT32(ris, stellaris_adc_state), 1118 VMSTATE_UINT32(im, stellaris_adc_state), 1119 VMSTATE_UINT32(emux, stellaris_adc_state), 1120 VMSTATE_UINT32(ostat, stellaris_adc_state), 1121 VMSTATE_UINT32(ustat, stellaris_adc_state), 1122 VMSTATE_UINT32(sspri, stellaris_adc_state), 1123 VMSTATE_UINT32(sac, stellaris_adc_state), 1124 VMSTATE_UINT32(fifo[0].state, stellaris_adc_state), 1125 VMSTATE_UINT32_ARRAY(fifo[0].data, stellaris_adc_state, 16), 1126 VMSTATE_UINT32(ssmux[0], stellaris_adc_state), 1127 VMSTATE_UINT32(ssctl[0], stellaris_adc_state), 1128 VMSTATE_UINT32(fifo[1].state, stellaris_adc_state), 1129 VMSTATE_UINT32_ARRAY(fifo[1].data, stellaris_adc_state, 16), 1130 VMSTATE_UINT32(ssmux[1], stellaris_adc_state), 1131 VMSTATE_UINT32(ssctl[1], stellaris_adc_state), 1132 VMSTATE_UINT32(fifo[2].state, stellaris_adc_state), 1133 VMSTATE_UINT32_ARRAY(fifo[2].data, stellaris_adc_state, 16), 1134 VMSTATE_UINT32(ssmux[2], stellaris_adc_state), 1135 VMSTATE_UINT32(ssctl[2], stellaris_adc_state), 1136 VMSTATE_UINT32(fifo[3].state, stellaris_adc_state), 1137 VMSTATE_UINT32_ARRAY(fifo[3].data, stellaris_adc_state, 16), 1138 VMSTATE_UINT32(ssmux[3], stellaris_adc_state), 1139 VMSTATE_UINT32(ssctl[3], stellaris_adc_state), 1140 VMSTATE_UINT32(noise, stellaris_adc_state), 1141 VMSTATE_END_OF_LIST() 1142 } 1143 }; 1144 1145 static int stellaris_adc_init(SysBusDevice *dev) 1146 { 1147 stellaris_adc_state *s = FROM_SYSBUS(stellaris_adc_state, dev); 1148 int n; 1149 1150 for (n = 0; n < 4; n++) { 1151 sysbus_init_irq(dev, &s->irq[n]); 1152 } 1153 1154 memory_region_init_io(&s->iomem, OBJECT(s), &stellaris_adc_ops, s, 1155 "adc", 0x1000); 1156 sysbus_init_mmio(dev, &s->iomem); 1157 stellaris_adc_reset(s); 1158 qdev_init_gpio_in(&dev->qdev, stellaris_adc_trigger, 1); 1159 vmstate_register(&dev->qdev, -1, &vmstate_stellaris_adc, s); 1160 return 0; 1161 } 1162 1163 /* Board init. */ 1164 static stellaris_board_info stellaris_boards[] = { 1165 { "LM3S811EVB", 1166 0, 1167 0x0032000e, 1168 0x001f001f, /* dc0 */ 1169 0x001132bf, 1170 0x01071013, 1171 0x3f0f01ff, 1172 0x0000001f, 1173 BP_OLED_I2C 1174 }, 1175 { "LM3S6965EVB", 1176 0x10010002, 1177 0x1073402e, 1178 0x00ff007f, /* dc0 */ 1179 0x001133ff, 1180 0x030f5317, 1181 0x0f0f87ff, 1182 0x5000007f, 1183 BP_OLED_SSI | BP_GAMEPAD 1184 } 1185 }; 1186 1187 static void stellaris_init(const char *kernel_filename, const char *cpu_model, 1188 stellaris_board_info *board) 1189 { 1190 static const int uart_irq[] = {5, 6, 33, 34}; 1191 static const int timer_irq[] = {19, 21, 23, 35}; 1192 static const uint32_t gpio_addr[7] = 1193 { 0x40004000, 0x40005000, 0x40006000, 0x40007000, 1194 0x40024000, 0x40025000, 0x40026000}; 1195 static const int gpio_irq[7] = {0, 1, 2, 3, 4, 30, 31}; 1196 1197 MemoryRegion *address_space_mem = get_system_memory(); 1198 qemu_irq *pic; 1199 DeviceState *gpio_dev[7]; 1200 qemu_irq gpio_in[7][8]; 1201 qemu_irq gpio_out[7][8]; 1202 qemu_irq adc; 1203 int sram_size; 1204 int flash_size; 1205 i2c_bus *i2c; 1206 DeviceState *dev; 1207 int i; 1208 int j; 1209 1210 flash_size = ((board->dc0 & 0xffff) + 1) << 1; 1211 sram_size = (board->dc0 >> 18) + 1; 1212 pic = armv7m_init(address_space_mem, 1213 flash_size, sram_size, kernel_filename, cpu_model); 1214 1215 if (board->dc1 & (1 << 16)) { 1216 dev = sysbus_create_varargs("stellaris-adc", 0x40038000, 1217 pic[14], pic[15], pic[16], pic[17], NULL); 1218 adc = qdev_get_gpio_in(dev, 0); 1219 } else { 1220 adc = NULL; 1221 } 1222 for (i = 0; i < 4; i++) { 1223 if (board->dc2 & (0x10000 << i)) { 1224 dev = sysbus_create_simple(TYPE_STELLARIS_GPTM, 1225 0x40030000 + i * 0x1000, 1226 pic[timer_irq[i]]); 1227 /* TODO: This is incorrect, but we get away with it because 1228 the ADC output is only ever pulsed. */ 1229 qdev_connect_gpio_out(dev, 0, adc); 1230 } 1231 } 1232 1233 stellaris_sys_init(0x400fe000, pic[28], board, nd_table[0].macaddr.a); 1234 1235 for (i = 0; i < 7; i++) { 1236 if (board->dc4 & (1 << i)) { 1237 gpio_dev[i] = sysbus_create_simple("pl061_luminary", gpio_addr[i], 1238 pic[gpio_irq[i]]); 1239 for (j = 0; j < 8; j++) { 1240 gpio_in[i][j] = qdev_get_gpio_in(gpio_dev[i], j); 1241 gpio_out[i][j] = NULL; 1242 } 1243 } 1244 } 1245 1246 if (board->dc2 & (1 << 12)) { 1247 dev = sysbus_create_simple("stellaris-i2c", 0x40020000, pic[8]); 1248 i2c = (i2c_bus *)qdev_get_child_bus(dev, "i2c"); 1249 if (board->peripherals & BP_OLED_I2C) { 1250 i2c_create_slave(i2c, "ssd0303", 0x3d); 1251 } 1252 } 1253 1254 for (i = 0; i < 4; i++) { 1255 if (board->dc2 & (1 << i)) { 1256 sysbus_create_simple("pl011_luminary", 0x4000c000 + i * 0x1000, 1257 pic[uart_irq[i]]); 1258 } 1259 } 1260 if (board->dc2 & (1 << 4)) { 1261 dev = sysbus_create_simple("pl022", 0x40008000, pic[7]); 1262 if (board->peripherals & BP_OLED_SSI) { 1263 void *bus; 1264 DeviceState *sddev; 1265 DeviceState *ssddev; 1266 1267 /* Some boards have both an OLED controller and SD card connected to 1268 * the same SSI port, with the SD card chip select connected to a 1269 * GPIO pin. Technically the OLED chip select is connected to the 1270 * SSI Fss pin. We do not bother emulating that as both devices 1271 * should never be selected simultaneously, and our OLED controller 1272 * ignores stray 0xff commands that occur when deselecting the SD 1273 * card. 1274 */ 1275 bus = qdev_get_child_bus(dev, "ssi"); 1276 1277 sddev = ssi_create_slave(bus, "ssi-sd"); 1278 ssddev = ssi_create_slave(bus, "ssd0323"); 1279 gpio_out[GPIO_D][0] = qemu_irq_split(qdev_get_gpio_in(sddev, 0), 1280 qdev_get_gpio_in(ssddev, 0)); 1281 gpio_out[GPIO_C][7] = qdev_get_gpio_in(ssddev, 1); 1282 1283 /* Make sure the select pin is high. */ 1284 qemu_irq_raise(gpio_out[GPIO_D][0]); 1285 } 1286 } 1287 if (board->dc4 & (1 << 28)) { 1288 DeviceState *enet; 1289 1290 qemu_check_nic_model(&nd_table[0], "stellaris"); 1291 1292 enet = qdev_create(NULL, "stellaris_enet"); 1293 qdev_set_nic_properties(enet, &nd_table[0]); 1294 qdev_init_nofail(enet); 1295 sysbus_mmio_map(SYS_BUS_DEVICE(enet), 0, 0x40048000); 1296 sysbus_connect_irq(SYS_BUS_DEVICE(enet), 0, pic[42]); 1297 } 1298 if (board->peripherals & BP_GAMEPAD) { 1299 qemu_irq gpad_irq[5]; 1300 static const int gpad_keycode[5] = { 0xc8, 0xd0, 0xcb, 0xcd, 0x1d }; 1301 1302 gpad_irq[0] = qemu_irq_invert(gpio_in[GPIO_E][0]); /* up */ 1303 gpad_irq[1] = qemu_irq_invert(gpio_in[GPIO_E][1]); /* down */ 1304 gpad_irq[2] = qemu_irq_invert(gpio_in[GPIO_E][2]); /* left */ 1305 gpad_irq[3] = qemu_irq_invert(gpio_in[GPIO_E][3]); /* right */ 1306 gpad_irq[4] = qemu_irq_invert(gpio_in[GPIO_F][1]); /* select */ 1307 1308 stellaris_gamepad_init(5, gpad_irq, gpad_keycode); 1309 } 1310 for (i = 0; i < 7; i++) { 1311 if (board->dc4 & (1 << i)) { 1312 for (j = 0; j < 8; j++) { 1313 if (gpio_out[i][j]) { 1314 qdev_connect_gpio_out(gpio_dev[i], j, gpio_out[i][j]); 1315 } 1316 } 1317 } 1318 } 1319 } 1320 1321 /* FIXME: Figure out how to generate these from stellaris_boards. */ 1322 static void lm3s811evb_init(QEMUMachineInitArgs *args) 1323 { 1324 const char *cpu_model = args->cpu_model; 1325 const char *kernel_filename = args->kernel_filename; 1326 stellaris_init(kernel_filename, cpu_model, &stellaris_boards[0]); 1327 } 1328 1329 static void lm3s6965evb_init(QEMUMachineInitArgs *args) 1330 { 1331 const char *cpu_model = args->cpu_model; 1332 const char *kernel_filename = args->kernel_filename; 1333 stellaris_init(kernel_filename, cpu_model, &stellaris_boards[1]); 1334 } 1335 1336 static QEMUMachine lm3s811evb_machine = { 1337 .name = "lm3s811evb", 1338 .desc = "Stellaris LM3S811EVB", 1339 .init = lm3s811evb_init, 1340 DEFAULT_MACHINE_OPTIONS, 1341 }; 1342 1343 static QEMUMachine lm3s6965evb_machine = { 1344 .name = "lm3s6965evb", 1345 .desc = "Stellaris LM3S6965EVB", 1346 .init = lm3s6965evb_init, 1347 DEFAULT_MACHINE_OPTIONS, 1348 }; 1349 1350 static void stellaris_machine_init(void) 1351 { 1352 qemu_register_machine(&lm3s811evb_machine); 1353 qemu_register_machine(&lm3s6965evb_machine); 1354 } 1355 1356 machine_init(stellaris_machine_init); 1357 1358 static void stellaris_i2c_class_init(ObjectClass *klass, void *data) 1359 { 1360 SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass); 1361 1362 sdc->init = stellaris_i2c_init; 1363 } 1364 1365 static const TypeInfo stellaris_i2c_info = { 1366 .name = "stellaris-i2c", 1367 .parent = TYPE_SYS_BUS_DEVICE, 1368 .instance_size = sizeof(stellaris_i2c_state), 1369 .class_init = stellaris_i2c_class_init, 1370 }; 1371 1372 static void stellaris_gptm_class_init(ObjectClass *klass, void *data) 1373 { 1374 SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass); 1375 1376 sdc->init = stellaris_gptm_init; 1377 } 1378 1379 static const TypeInfo stellaris_gptm_info = { 1380 .name = TYPE_STELLARIS_GPTM, 1381 .parent = TYPE_SYS_BUS_DEVICE, 1382 .instance_size = sizeof(gptm_state), 1383 .class_init = stellaris_gptm_class_init, 1384 }; 1385 1386 static void stellaris_adc_class_init(ObjectClass *klass, void *data) 1387 { 1388 SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass); 1389 1390 sdc->init = stellaris_adc_init; 1391 } 1392 1393 static const TypeInfo stellaris_adc_info = { 1394 .name = "stellaris-adc", 1395 .parent = TYPE_SYS_BUS_DEVICE, 1396 .instance_size = sizeof(stellaris_adc_state), 1397 .class_init = stellaris_adc_class_init, 1398 }; 1399 1400 static void stellaris_register_types(void) 1401 { 1402 type_register_static(&stellaris_i2c_info); 1403 type_register_static(&stellaris_gptm_info); 1404 type_register_static(&stellaris_adc_info); 1405 } 1406 1407 type_init(stellaris_register_types) 1408