1 /* 2 * Luminary Micro Stellaris peripherals 3 * 4 * Copyright (c) 2006 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qapi/error.h" 12 #include "hw/core/split-irq.h" 13 #include "hw/sysbus.h" 14 #include "hw/sd/sd.h" 15 #include "hw/ssi/ssi.h" 16 #include "hw/arm/boot.h" 17 #include "qemu/timer.h" 18 #include "hw/i2c/i2c.h" 19 #include "net/net.h" 20 #include "hw/boards.h" 21 #include "qemu/log.h" 22 #include "exec/address-spaces.h" 23 #include "system/system.h" 24 #include "hw/arm/armv7m.h" 25 #include "hw/char/pl011.h" 26 #include "hw/input/stellaris_gamepad.h" 27 #include "hw/irq.h" 28 #include "hw/watchdog/cmsdk-apb-watchdog.h" 29 #include "migration/vmstate.h" 30 #include "hw/misc/unimp.h" 31 #include "hw/timer/stellaris-gptm.h" 32 #include "hw/qdev-clock.h" 33 #include "qom/object.h" 34 #include "qapi/qmp/qlist.h" 35 #include "ui/input.h" 36 37 #define GPIO_A 0 38 #define GPIO_B 1 39 #define GPIO_C 2 40 #define GPIO_D 3 41 #define GPIO_E 4 42 #define GPIO_F 5 43 #define GPIO_G 6 44 45 #define BP_OLED_I2C 0x01 46 #define BP_OLED_SSI 0x02 47 #define BP_GAMEPAD 0x04 48 49 #define NUM_IRQ_LINES 64 50 #define NUM_PRIO_BITS 3 51 52 #define NUM_GPIO 7 53 #define NUM_UART 4 54 #define NUM_GPTM 4 55 #define NUM_I2C 2 56 57 typedef const struct { 58 const char *name; 59 uint32_t did0; 60 uint32_t did1; 61 uint32_t dc0; 62 uint32_t dc1; 63 uint32_t dc2; 64 uint32_t dc3; 65 uint32_t dc4; 66 uint32_t peripherals; 67 } stellaris_board_info; 68 69 /* System controller. */ 70 71 #define TYPE_STELLARIS_SYS "stellaris-sys" 72 OBJECT_DECLARE_SIMPLE_TYPE(ssys_state, STELLARIS_SYS) 73 74 struct ssys_state { 75 SysBusDevice parent_obj; 76 77 MemoryRegion iomem; 78 uint32_t pborctl; 79 uint32_t ldopctl; 80 uint32_t int_status; 81 uint32_t int_mask; 82 uint32_t resc; 83 uint32_t rcc; 84 uint32_t rcc2; 85 uint32_t rcgc[3]; 86 uint32_t scgc[3]; 87 uint32_t dcgc[3]; 88 uint32_t clkvclr; 89 uint32_t ldoarst; 90 qemu_irq irq; 91 Clock *sysclk; 92 /* Properties (all read-only registers) */ 93 uint32_t user0; 94 uint32_t user1; 95 uint32_t did0; 96 uint32_t did1; 97 uint32_t dc0; 98 uint32_t dc1; 99 uint32_t dc2; 100 uint32_t dc3; 101 uint32_t dc4; 102 }; 103 104 static void ssys_update(ssys_state *s) 105 { 106 qemu_set_irq(s->irq, (s->int_status & s->int_mask) != 0); 107 } 108 109 static const uint32_t pllcfg_sandstorm[16] = { 110 0x31c0, /* 1 Mhz */ 111 0x1ae0, /* 1.8432 Mhz */ 112 0x18c0, /* 2 Mhz */ 113 0xd573, /* 2.4576 Mhz */ 114 0x37a6, /* 3.57954 Mhz */ 115 0x1ae2, /* 3.6864 Mhz */ 116 0x0c40, /* 4 Mhz */ 117 0x98bc, /* 4.906 Mhz */ 118 0x935b, /* 4.9152 Mhz */ 119 0x09c0, /* 5 Mhz */ 120 0x4dee, /* 5.12 Mhz */ 121 0x0c41, /* 6 Mhz */ 122 0x75db, /* 6.144 Mhz */ 123 0x1ae6, /* 7.3728 Mhz */ 124 0x0600, /* 8 Mhz */ 125 0x585b /* 8.192 Mhz */ 126 }; 127 128 static const uint32_t pllcfg_fury[16] = { 129 0x3200, /* 1 Mhz */ 130 0x1b20, /* 1.8432 Mhz */ 131 0x1900, /* 2 Mhz */ 132 0xf42b, /* 2.4576 Mhz */ 133 0x37e3, /* 3.57954 Mhz */ 134 0x1b21, /* 3.6864 Mhz */ 135 0x0c80, /* 4 Mhz */ 136 0x98ee, /* 4.906 Mhz */ 137 0xd5b4, /* 4.9152 Mhz */ 138 0x0a00, /* 5 Mhz */ 139 0x4e27, /* 5.12 Mhz */ 140 0x1902, /* 6 Mhz */ 141 0xec1c, /* 6.144 Mhz */ 142 0x1b23, /* 7.3728 Mhz */ 143 0x0640, /* 8 Mhz */ 144 0xb11c /* 8.192 Mhz */ 145 }; 146 147 #define DID0_VER_MASK 0x70000000 148 #define DID0_VER_0 0x00000000 149 #define DID0_VER_1 0x10000000 150 151 #define DID0_CLASS_MASK 0x00FF0000 152 #define DID0_CLASS_SANDSTORM 0x00000000 153 #define DID0_CLASS_FURY 0x00010000 154 155 static int ssys_board_class(const ssys_state *s) 156 { 157 uint32_t did0 = s->did0; 158 switch (did0 & DID0_VER_MASK) { 159 case DID0_VER_0: 160 return DID0_CLASS_SANDSTORM; 161 case DID0_VER_1: 162 switch (did0 & DID0_CLASS_MASK) { 163 case DID0_CLASS_SANDSTORM: 164 case DID0_CLASS_FURY: 165 return did0 & DID0_CLASS_MASK; 166 } 167 /* for unknown classes, fall through */ 168 default: 169 /* This can only happen if the hardwired constant did0 value 170 * in this board's stellaris_board_info struct is wrong. 171 */ 172 g_assert_not_reached(); 173 } 174 } 175 176 static uint64_t ssys_read(void *opaque, hwaddr offset, 177 unsigned size) 178 { 179 ssys_state *s = (ssys_state *)opaque; 180 181 switch (offset) { 182 case 0x000: /* DID0 */ 183 return s->did0; 184 case 0x004: /* DID1 */ 185 return s->did1; 186 case 0x008: /* DC0 */ 187 return s->dc0; 188 case 0x010: /* DC1 */ 189 return s->dc1; 190 case 0x014: /* DC2 */ 191 return s->dc2; 192 case 0x018: /* DC3 */ 193 return s->dc3; 194 case 0x01c: /* DC4 */ 195 return s->dc4; 196 case 0x030: /* PBORCTL */ 197 return s->pborctl; 198 case 0x034: /* LDOPCTL */ 199 return s->ldopctl; 200 case 0x040: /* SRCR0 */ 201 return 0; 202 case 0x044: /* SRCR1 */ 203 return 0; 204 case 0x048: /* SRCR2 */ 205 return 0; 206 case 0x050: /* RIS */ 207 return s->int_status; 208 case 0x054: /* IMC */ 209 return s->int_mask; 210 case 0x058: /* MISC */ 211 return s->int_status & s->int_mask; 212 case 0x05c: /* RESC */ 213 return s->resc; 214 case 0x060: /* RCC */ 215 return s->rcc; 216 case 0x064: /* PLLCFG */ 217 { 218 int xtal; 219 xtal = (s->rcc >> 6) & 0xf; 220 switch (ssys_board_class(s)) { 221 case DID0_CLASS_FURY: 222 return pllcfg_fury[xtal]; 223 case DID0_CLASS_SANDSTORM: 224 return pllcfg_sandstorm[xtal]; 225 default: 226 g_assert_not_reached(); 227 } 228 } 229 case 0x070: /* RCC2 */ 230 return s->rcc2; 231 case 0x100: /* RCGC0 */ 232 return s->rcgc[0]; 233 case 0x104: /* RCGC1 */ 234 return s->rcgc[1]; 235 case 0x108: /* RCGC2 */ 236 return s->rcgc[2]; 237 case 0x110: /* SCGC0 */ 238 return s->scgc[0]; 239 case 0x114: /* SCGC1 */ 240 return s->scgc[1]; 241 case 0x118: /* SCGC2 */ 242 return s->scgc[2]; 243 case 0x120: /* DCGC0 */ 244 return s->dcgc[0]; 245 case 0x124: /* DCGC1 */ 246 return s->dcgc[1]; 247 case 0x128: /* DCGC2 */ 248 return s->dcgc[2]; 249 case 0x150: /* CLKVCLR */ 250 return s->clkvclr; 251 case 0x160: /* LDOARST */ 252 return s->ldoarst; 253 case 0x1e0: /* USER0 */ 254 return s->user0; 255 case 0x1e4: /* USER1 */ 256 return s->user1; 257 default: 258 qemu_log_mask(LOG_GUEST_ERROR, 259 "SSYS: read at bad offset 0x%x\n", (int)offset); 260 return 0; 261 } 262 } 263 264 static bool ssys_use_rcc2(ssys_state *s) 265 { 266 return (s->rcc2 >> 31) & 0x1; 267 } 268 269 /* 270 * Calculate the system clock period. We only want to propagate 271 * this change to the rest of the system if we're not being called 272 * from migration post-load. 273 */ 274 static void ssys_calculate_system_clock(ssys_state *s, bool propagate_clock) 275 { 276 int period_ns; 277 /* 278 * SYSDIV field specifies divisor: 0 == /1, 1 == /2, etc. Input 279 * clock is 200MHz, which is a period of 5 ns. Dividing the clock 280 * frequency by X is the same as multiplying the period by X. 281 */ 282 if (ssys_use_rcc2(s)) { 283 period_ns = 5 * (((s->rcc2 >> 23) & 0x3f) + 1); 284 } else { 285 period_ns = 5 * (((s->rcc >> 23) & 0xf) + 1); 286 } 287 clock_set_ns(s->sysclk, period_ns); 288 if (propagate_clock) { 289 clock_propagate(s->sysclk); 290 } 291 } 292 293 static void ssys_write(void *opaque, hwaddr offset, 294 uint64_t value, unsigned size) 295 { 296 ssys_state *s = (ssys_state *)opaque; 297 298 switch (offset) { 299 case 0x030: /* PBORCTL */ 300 s->pborctl = value & 0xffff; 301 break; 302 case 0x034: /* LDOPCTL */ 303 s->ldopctl = value & 0x1f; 304 break; 305 case 0x040: /* SRCR0 */ 306 case 0x044: /* SRCR1 */ 307 case 0x048: /* SRCR2 */ 308 qemu_log_mask(LOG_UNIMP, "Peripheral reset not implemented\n"); 309 break; 310 case 0x054: /* IMC */ 311 s->int_mask = value & 0x7f; 312 break; 313 case 0x058: /* MISC */ 314 s->int_status &= ~value; 315 break; 316 case 0x05c: /* RESC */ 317 s->resc = value & 0x3f; 318 break; 319 case 0x060: /* RCC */ 320 if ((s->rcc & (1 << 13)) != 0 && (value & (1 << 13)) == 0) { 321 /* PLL enable. */ 322 s->int_status |= (1 << 6); 323 } 324 s->rcc = value; 325 ssys_calculate_system_clock(s, true); 326 break; 327 case 0x070: /* RCC2 */ 328 if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) { 329 break; 330 } 331 332 if ((s->rcc2 & (1 << 13)) != 0 && (value & (1 << 13)) == 0) { 333 /* PLL enable. */ 334 s->int_status |= (1 << 6); 335 } 336 s->rcc2 = value; 337 ssys_calculate_system_clock(s, true); 338 break; 339 case 0x100: /* RCGC0 */ 340 s->rcgc[0] = value; 341 break; 342 case 0x104: /* RCGC1 */ 343 s->rcgc[1] = value; 344 break; 345 case 0x108: /* RCGC2 */ 346 s->rcgc[2] = value; 347 break; 348 case 0x110: /* SCGC0 */ 349 s->scgc[0] = value; 350 break; 351 case 0x114: /* SCGC1 */ 352 s->scgc[1] = value; 353 break; 354 case 0x118: /* SCGC2 */ 355 s->scgc[2] = value; 356 break; 357 case 0x120: /* DCGC0 */ 358 s->dcgc[0] = value; 359 break; 360 case 0x124: /* DCGC1 */ 361 s->dcgc[1] = value; 362 break; 363 case 0x128: /* DCGC2 */ 364 s->dcgc[2] = value; 365 break; 366 case 0x150: /* CLKVCLR */ 367 s->clkvclr = value; 368 break; 369 case 0x160: /* LDOARST */ 370 s->ldoarst = value; 371 break; 372 default: 373 qemu_log_mask(LOG_GUEST_ERROR, 374 "SSYS: write at bad offset 0x%x\n", (int)offset); 375 } 376 ssys_update(s); 377 } 378 379 static const MemoryRegionOps ssys_ops = { 380 .read = ssys_read, 381 .write = ssys_write, 382 .endianness = DEVICE_NATIVE_ENDIAN, 383 }; 384 385 static void stellaris_sys_reset_enter(Object *obj, ResetType type) 386 { 387 ssys_state *s = STELLARIS_SYS(obj); 388 389 s->pborctl = 0x7ffd; 390 s->rcc = 0x078e3ac0; 391 392 if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) { 393 s->rcc2 = 0; 394 } else { 395 s->rcc2 = 0x07802810; 396 } 397 s->rcgc[0] = 1; 398 s->scgc[0] = 1; 399 s->dcgc[0] = 1; 400 } 401 402 static void stellaris_sys_reset_hold(Object *obj, ResetType type) 403 { 404 ssys_state *s = STELLARIS_SYS(obj); 405 406 /* OK to propagate clocks from the hold phase */ 407 ssys_calculate_system_clock(s, true); 408 } 409 410 static void stellaris_sys_reset_exit(Object *obj, ResetType type) 411 { 412 } 413 414 static int stellaris_sys_post_load(void *opaque, int version_id) 415 { 416 ssys_state *s = opaque; 417 418 ssys_calculate_system_clock(s, false); 419 420 return 0; 421 } 422 423 static const VMStateDescription vmstate_stellaris_sys = { 424 .name = "stellaris_sys", 425 .version_id = 2, 426 .minimum_version_id = 1, 427 .post_load = stellaris_sys_post_load, 428 .fields = (const VMStateField[]) { 429 VMSTATE_UINT32(pborctl, ssys_state), 430 VMSTATE_UINT32(ldopctl, ssys_state), 431 VMSTATE_UINT32(int_mask, ssys_state), 432 VMSTATE_UINT32(int_status, ssys_state), 433 VMSTATE_UINT32(resc, ssys_state), 434 VMSTATE_UINT32(rcc, ssys_state), 435 VMSTATE_UINT32_V(rcc2, ssys_state, 2), 436 VMSTATE_UINT32_ARRAY(rcgc, ssys_state, 3), 437 VMSTATE_UINT32_ARRAY(scgc, ssys_state, 3), 438 VMSTATE_UINT32_ARRAY(dcgc, ssys_state, 3), 439 VMSTATE_UINT32(clkvclr, ssys_state), 440 VMSTATE_UINT32(ldoarst, ssys_state), 441 /* No field for sysclk -- handled in post-load instead */ 442 VMSTATE_END_OF_LIST() 443 } 444 }; 445 446 static const Property stellaris_sys_properties[] = { 447 DEFINE_PROP_UINT32("user0", ssys_state, user0, 0), 448 DEFINE_PROP_UINT32("user1", ssys_state, user1, 0), 449 DEFINE_PROP_UINT32("did0", ssys_state, did0, 0), 450 DEFINE_PROP_UINT32("did1", ssys_state, did1, 0), 451 DEFINE_PROP_UINT32("dc0", ssys_state, dc0, 0), 452 DEFINE_PROP_UINT32("dc1", ssys_state, dc1, 0), 453 DEFINE_PROP_UINT32("dc2", ssys_state, dc2, 0), 454 DEFINE_PROP_UINT32("dc3", ssys_state, dc3, 0), 455 DEFINE_PROP_UINT32("dc4", ssys_state, dc4, 0), 456 }; 457 458 static void stellaris_sys_instance_init(Object *obj) 459 { 460 ssys_state *s = STELLARIS_SYS(obj); 461 SysBusDevice *sbd = SYS_BUS_DEVICE(s); 462 463 memory_region_init_io(&s->iomem, obj, &ssys_ops, s, "ssys", 0x00001000); 464 sysbus_init_mmio(sbd, &s->iomem); 465 sysbus_init_irq(sbd, &s->irq); 466 s->sysclk = qdev_init_clock_out(DEVICE(s), "SYSCLK"); 467 } 468 469 /* 470 * I2C controller. 471 * ??? For now we only implement the master interface. 472 */ 473 474 #define TYPE_STELLARIS_I2C "stellaris-i2c" 475 OBJECT_DECLARE_SIMPLE_TYPE(stellaris_i2c_state, STELLARIS_I2C) 476 477 struct stellaris_i2c_state { 478 SysBusDevice parent_obj; 479 480 I2CBus *bus; 481 qemu_irq irq; 482 MemoryRegion iomem; 483 uint32_t msa; 484 uint32_t mcs; 485 uint32_t mdr; 486 uint32_t mtpr; 487 uint32_t mimr; 488 uint32_t mris; 489 uint32_t mcr; 490 }; 491 492 #define STELLARIS_I2C_MCS_BUSY 0x01 493 #define STELLARIS_I2C_MCS_ERROR 0x02 494 #define STELLARIS_I2C_MCS_ADRACK 0x04 495 #define STELLARIS_I2C_MCS_DATACK 0x08 496 #define STELLARIS_I2C_MCS_ARBLST 0x10 497 #define STELLARIS_I2C_MCS_IDLE 0x20 498 #define STELLARIS_I2C_MCS_BUSBSY 0x40 499 500 static uint64_t stellaris_i2c_read(void *opaque, hwaddr offset, 501 unsigned size) 502 { 503 stellaris_i2c_state *s = (stellaris_i2c_state *)opaque; 504 505 switch (offset) { 506 case 0x00: /* MSA */ 507 return s->msa; 508 case 0x04: /* MCS */ 509 /* We don't emulate timing, so the controller is never busy. */ 510 return s->mcs | STELLARIS_I2C_MCS_IDLE; 511 case 0x08: /* MDR */ 512 return s->mdr; 513 case 0x0c: /* MTPR */ 514 return s->mtpr; 515 case 0x10: /* MIMR */ 516 return s->mimr; 517 case 0x14: /* MRIS */ 518 return s->mris; 519 case 0x18: /* MMIS */ 520 return s->mris & s->mimr; 521 case 0x20: /* MCR */ 522 return s->mcr; 523 default: 524 qemu_log_mask(LOG_GUEST_ERROR, 525 "stellaris_i2c: read at bad offset 0x%x\n", (int)offset); 526 return 0; 527 } 528 } 529 530 static void stellaris_i2c_update(stellaris_i2c_state *s) 531 { 532 int level; 533 534 level = (s->mris & s->mimr) != 0; 535 qemu_set_irq(s->irq, level); 536 } 537 538 static void stellaris_i2c_write(void *opaque, hwaddr offset, 539 uint64_t value, unsigned size) 540 { 541 stellaris_i2c_state *s = (stellaris_i2c_state *)opaque; 542 543 switch (offset) { 544 case 0x00: /* MSA */ 545 s->msa = value & 0xff; 546 break; 547 case 0x04: /* MCS */ 548 if ((s->mcr & 0x10) == 0) { 549 /* Disabled. Do nothing. */ 550 break; 551 } 552 /* Grab the bus if this is starting a transfer. */ 553 if ((value & 2) && (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) { 554 if (i2c_start_transfer(s->bus, s->msa >> 1, s->msa & 1)) { 555 s->mcs |= STELLARIS_I2C_MCS_ARBLST; 556 } else { 557 s->mcs &= ~STELLARIS_I2C_MCS_ARBLST; 558 s->mcs |= STELLARIS_I2C_MCS_BUSBSY; 559 } 560 } 561 /* If we don't have the bus then indicate an error. */ 562 if (!i2c_bus_busy(s->bus) 563 || (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) { 564 s->mcs |= STELLARIS_I2C_MCS_ERROR; 565 break; 566 } 567 s->mcs &= ~STELLARIS_I2C_MCS_ERROR; 568 if (value & 1) { 569 /* Transfer a byte. */ 570 /* TODO: Handle errors. */ 571 if (s->msa & 1) { 572 /* Recv */ 573 s->mdr = i2c_recv(s->bus); 574 } else { 575 /* Send */ 576 i2c_send(s->bus, s->mdr); 577 } 578 /* Raise an interrupt. */ 579 s->mris |= 1; 580 } 581 if (value & 4) { 582 /* Finish transfer. */ 583 i2c_end_transfer(s->bus); 584 s->mcs &= ~STELLARIS_I2C_MCS_BUSBSY; 585 } 586 break; 587 case 0x08: /* MDR */ 588 s->mdr = value & 0xff; 589 break; 590 case 0x0c: /* MTPR */ 591 s->mtpr = value & 0xff; 592 break; 593 case 0x10: /* MIMR */ 594 s->mimr = 1; 595 break; 596 case 0x1c: /* MICR */ 597 s->mris &= ~value; 598 break; 599 case 0x20: /* MCR */ 600 if (value & 1) { 601 qemu_log_mask(LOG_UNIMP, 602 "stellaris_i2c: Loopback not implemented\n"); 603 } 604 if (value & 0x20) { 605 qemu_log_mask(LOG_UNIMP, 606 "stellaris_i2c: Slave mode not implemented\n"); 607 } 608 s->mcr = value & 0x31; 609 break; 610 default: 611 qemu_log_mask(LOG_GUEST_ERROR, 612 "stellaris_i2c: write at bad offset 0x%x\n", (int)offset); 613 } 614 stellaris_i2c_update(s); 615 } 616 617 static void stellaris_i2c_reset_enter(Object *obj, ResetType type) 618 { 619 stellaris_i2c_state *s = STELLARIS_I2C(obj); 620 621 if (s->mcs & STELLARIS_I2C_MCS_BUSBSY) 622 i2c_end_transfer(s->bus); 623 } 624 625 static void stellaris_i2c_reset_hold(Object *obj, ResetType type) 626 { 627 stellaris_i2c_state *s = STELLARIS_I2C(obj); 628 629 s->msa = 0; 630 s->mcs = 0; 631 s->mdr = 0; 632 s->mtpr = 1; 633 s->mimr = 0; 634 s->mris = 0; 635 s->mcr = 0; 636 } 637 638 static void stellaris_i2c_reset_exit(Object *obj, ResetType type) 639 { 640 stellaris_i2c_state *s = STELLARIS_I2C(obj); 641 642 stellaris_i2c_update(s); 643 } 644 645 static const MemoryRegionOps stellaris_i2c_ops = { 646 .read = stellaris_i2c_read, 647 .write = stellaris_i2c_write, 648 .endianness = DEVICE_NATIVE_ENDIAN, 649 }; 650 651 static const VMStateDescription vmstate_stellaris_i2c = { 652 .name = "stellaris_i2c", 653 .version_id = 1, 654 .minimum_version_id = 1, 655 .fields = (const VMStateField[]) { 656 VMSTATE_UINT32(msa, stellaris_i2c_state), 657 VMSTATE_UINT32(mcs, stellaris_i2c_state), 658 VMSTATE_UINT32(mdr, stellaris_i2c_state), 659 VMSTATE_UINT32(mtpr, stellaris_i2c_state), 660 VMSTATE_UINT32(mimr, stellaris_i2c_state), 661 VMSTATE_UINT32(mris, stellaris_i2c_state), 662 VMSTATE_UINT32(mcr, stellaris_i2c_state), 663 VMSTATE_END_OF_LIST() 664 } 665 }; 666 667 static void stellaris_i2c_init(Object *obj) 668 { 669 DeviceState *dev = DEVICE(obj); 670 stellaris_i2c_state *s = STELLARIS_I2C(obj); 671 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 672 I2CBus *bus; 673 674 sysbus_init_irq(sbd, &s->irq); 675 bus = i2c_init_bus(dev, "i2c"); 676 s->bus = bus; 677 678 memory_region_init_io(&s->iomem, obj, &stellaris_i2c_ops, s, 679 "i2c", 0x1000); 680 sysbus_init_mmio(sbd, &s->iomem); 681 } 682 683 /* Analogue to Digital Converter. This is only partially implemented, 684 enough for applications that use a combined ADC and timer tick. */ 685 686 #define STELLARIS_ADC_EM_CONTROLLER 0 687 #define STELLARIS_ADC_EM_COMP 1 688 #define STELLARIS_ADC_EM_EXTERNAL 4 689 #define STELLARIS_ADC_EM_TIMER 5 690 #define STELLARIS_ADC_EM_PWM0 6 691 #define STELLARIS_ADC_EM_PWM1 7 692 #define STELLARIS_ADC_EM_PWM2 8 693 694 #define STELLARIS_ADC_FIFO_EMPTY 0x0100 695 #define STELLARIS_ADC_FIFO_FULL 0x1000 696 697 #define TYPE_STELLARIS_ADC "stellaris-adc" 698 typedef struct StellarisADCState StellarisADCState; 699 DECLARE_INSTANCE_CHECKER(StellarisADCState, STELLARIS_ADC, TYPE_STELLARIS_ADC) 700 701 struct StellarisADCState { 702 SysBusDevice parent_obj; 703 704 MemoryRegion iomem; 705 uint32_t actss; 706 uint32_t ris; 707 uint32_t im; 708 uint32_t emux; 709 uint32_t ostat; 710 uint32_t ustat; 711 uint32_t sspri; 712 uint32_t sac; 713 struct { 714 uint32_t state; 715 uint32_t data[16]; 716 } fifo[4]; 717 uint32_t ssmux[4]; 718 uint32_t ssctl[4]; 719 uint32_t noise; 720 qemu_irq irq[4]; 721 }; 722 723 static uint32_t stellaris_adc_fifo_read(StellarisADCState *s, int n) 724 { 725 int tail; 726 727 tail = s->fifo[n].state & 0xf; 728 if (s->fifo[n].state & STELLARIS_ADC_FIFO_EMPTY) { 729 s->ustat |= 1 << n; 730 } else { 731 s->fifo[n].state = (s->fifo[n].state & ~0xf) | ((tail + 1) & 0xf); 732 s->fifo[n].state &= ~STELLARIS_ADC_FIFO_FULL; 733 if (tail + 1 == ((s->fifo[n].state >> 4) & 0xf)) 734 s->fifo[n].state |= STELLARIS_ADC_FIFO_EMPTY; 735 } 736 return s->fifo[n].data[tail]; 737 } 738 739 static void stellaris_adc_fifo_write(StellarisADCState *s, int n, 740 uint32_t value) 741 { 742 int head; 743 744 /* TODO: Real hardware has limited size FIFOs. We have a full 16 entry 745 FIFO fir each sequencer. */ 746 head = (s->fifo[n].state >> 4) & 0xf; 747 if (s->fifo[n].state & STELLARIS_ADC_FIFO_FULL) { 748 s->ostat |= 1 << n; 749 return; 750 } 751 s->fifo[n].data[head] = value; 752 head = (head + 1) & 0xf; 753 s->fifo[n].state &= ~STELLARIS_ADC_FIFO_EMPTY; 754 s->fifo[n].state = (s->fifo[n].state & ~0xf0) | (head << 4); 755 if ((s->fifo[n].state & 0xf) == head) 756 s->fifo[n].state |= STELLARIS_ADC_FIFO_FULL; 757 } 758 759 static void stellaris_adc_update(StellarisADCState *s) 760 { 761 int level; 762 int n; 763 764 for (n = 0; n < 4; n++) { 765 level = (s->ris & s->im & (1 << n)) != 0; 766 qemu_set_irq(s->irq[n], level); 767 } 768 } 769 770 static void stellaris_adc_trigger(void *opaque, int irq, int level) 771 { 772 StellarisADCState *s = opaque; 773 int n; 774 775 for (n = 0; n < 4; n++) { 776 if ((s->actss & (1 << n)) == 0) { 777 continue; 778 } 779 780 if (((s->emux >> (n * 4)) & 0xff) != 5) { 781 continue; 782 } 783 784 /* Some applications use the ADC as a random number source, so introduce 785 some variation into the signal. */ 786 s->noise = s->noise * 314159 + 1; 787 /* ??? actual inputs not implemented. Return an arbitrary value. */ 788 stellaris_adc_fifo_write(s, n, 0x200 + ((s->noise >> 16) & 7)); 789 s->ris |= (1 << n); 790 stellaris_adc_update(s); 791 } 792 } 793 794 static void stellaris_adc_reset_hold(Object *obj, ResetType type) 795 { 796 StellarisADCState *s = STELLARIS_ADC(obj); 797 int n; 798 799 for (n = 0; n < 4; n++) { 800 s->ssmux[n] = 0; 801 s->ssctl[n] = 0; 802 s->fifo[n].state = STELLARIS_ADC_FIFO_EMPTY; 803 } 804 } 805 806 static uint64_t stellaris_adc_read(void *opaque, hwaddr offset, 807 unsigned size) 808 { 809 StellarisADCState *s = opaque; 810 811 /* TODO: Implement this. */ 812 if (offset >= 0x40 && offset < 0xc0) { 813 int n; 814 n = (offset - 0x40) >> 5; 815 switch (offset & 0x1f) { 816 case 0x00: /* SSMUX */ 817 return s->ssmux[n]; 818 case 0x04: /* SSCTL */ 819 return s->ssctl[n]; 820 case 0x08: /* SSFIFO */ 821 return stellaris_adc_fifo_read(s, n); 822 case 0x0c: /* SSFSTAT */ 823 return s->fifo[n].state; 824 default: 825 break; 826 } 827 } 828 switch (offset) { 829 case 0x00: /* ACTSS */ 830 return s->actss; 831 case 0x04: /* RIS */ 832 return s->ris; 833 case 0x08: /* IM */ 834 return s->im; 835 case 0x0c: /* ISC */ 836 return s->ris & s->im; 837 case 0x10: /* OSTAT */ 838 return s->ostat; 839 case 0x14: /* EMUX */ 840 return s->emux; 841 case 0x18: /* USTAT */ 842 return s->ustat; 843 case 0x20: /* SSPRI */ 844 return s->sspri; 845 case 0x30: /* SAC */ 846 return s->sac; 847 default: 848 qemu_log_mask(LOG_GUEST_ERROR, 849 "stellaris_adc: read at bad offset 0x%x\n", (int)offset); 850 return 0; 851 } 852 } 853 854 static void stellaris_adc_write(void *opaque, hwaddr offset, 855 uint64_t value, unsigned size) 856 { 857 StellarisADCState *s = opaque; 858 859 /* TODO: Implement this. */ 860 if (offset >= 0x40 && offset < 0xc0) { 861 int n; 862 n = (offset - 0x40) >> 5; 863 switch (offset & 0x1f) { 864 case 0x00: /* SSMUX */ 865 s->ssmux[n] = value & 0x33333333; 866 return; 867 case 0x04: /* SSCTL */ 868 if (value != 6) { 869 qemu_log_mask(LOG_UNIMP, 870 "ADC: Unimplemented sequence %" PRIx64 "\n", 871 value); 872 } 873 s->ssctl[n] = value; 874 return; 875 default: 876 break; 877 } 878 } 879 switch (offset) { 880 case 0x00: /* ACTSS */ 881 s->actss = value & 0xf; 882 break; 883 case 0x08: /* IM */ 884 s->im = value; 885 break; 886 case 0x0c: /* ISC */ 887 s->ris &= ~value; 888 break; 889 case 0x10: /* OSTAT */ 890 s->ostat &= ~value; 891 break; 892 case 0x14: /* EMUX */ 893 s->emux = value; 894 break; 895 case 0x18: /* USTAT */ 896 s->ustat &= ~value; 897 break; 898 case 0x20: /* SSPRI */ 899 s->sspri = value; 900 break; 901 case 0x28: /* PSSI */ 902 qemu_log_mask(LOG_UNIMP, "ADC: sample initiate unimplemented\n"); 903 break; 904 case 0x30: /* SAC */ 905 s->sac = value; 906 break; 907 default: 908 qemu_log_mask(LOG_GUEST_ERROR, 909 "stellaris_adc: write at bad offset 0x%x\n", (int)offset); 910 } 911 stellaris_adc_update(s); 912 } 913 914 static const MemoryRegionOps stellaris_adc_ops = { 915 .read = stellaris_adc_read, 916 .write = stellaris_adc_write, 917 .endianness = DEVICE_NATIVE_ENDIAN, 918 }; 919 920 static const VMStateDescription vmstate_stellaris_adc = { 921 .name = "stellaris_adc", 922 .version_id = 1, 923 .minimum_version_id = 1, 924 .fields = (const VMStateField[]) { 925 VMSTATE_UINT32(actss, StellarisADCState), 926 VMSTATE_UINT32(ris, StellarisADCState), 927 VMSTATE_UINT32(im, StellarisADCState), 928 VMSTATE_UINT32(emux, StellarisADCState), 929 VMSTATE_UINT32(ostat, StellarisADCState), 930 VMSTATE_UINT32(ustat, StellarisADCState), 931 VMSTATE_UINT32(sspri, StellarisADCState), 932 VMSTATE_UINT32(sac, StellarisADCState), 933 VMSTATE_UINT32(fifo[0].state, StellarisADCState), 934 VMSTATE_UINT32_ARRAY(fifo[0].data, StellarisADCState, 16), 935 VMSTATE_UINT32(ssmux[0], StellarisADCState), 936 VMSTATE_UINT32(ssctl[0], StellarisADCState), 937 VMSTATE_UINT32(fifo[1].state, StellarisADCState), 938 VMSTATE_UINT32_ARRAY(fifo[1].data, StellarisADCState, 16), 939 VMSTATE_UINT32(ssmux[1], StellarisADCState), 940 VMSTATE_UINT32(ssctl[1], StellarisADCState), 941 VMSTATE_UINT32(fifo[2].state, StellarisADCState), 942 VMSTATE_UINT32_ARRAY(fifo[2].data, StellarisADCState, 16), 943 VMSTATE_UINT32(ssmux[2], StellarisADCState), 944 VMSTATE_UINT32(ssctl[2], StellarisADCState), 945 VMSTATE_UINT32(fifo[3].state, StellarisADCState), 946 VMSTATE_UINT32_ARRAY(fifo[3].data, StellarisADCState, 16), 947 VMSTATE_UINT32(ssmux[3], StellarisADCState), 948 VMSTATE_UINT32(ssctl[3], StellarisADCState), 949 VMSTATE_UINT32(noise, StellarisADCState), 950 VMSTATE_END_OF_LIST() 951 } 952 }; 953 954 static void stellaris_adc_init(Object *obj) 955 { 956 DeviceState *dev = DEVICE(obj); 957 StellarisADCState *s = STELLARIS_ADC(obj); 958 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 959 int n; 960 961 for (n = 0; n < 4; n++) { 962 sysbus_init_irq(sbd, &s->irq[n]); 963 } 964 965 memory_region_init_io(&s->iomem, obj, &stellaris_adc_ops, s, 966 "adc", 0x1000); 967 sysbus_init_mmio(sbd, &s->iomem); 968 qdev_init_gpio_in(dev, stellaris_adc_trigger, 1); 969 } 970 971 /* Board init. */ 972 static const stellaris_board_info stellaris_boards[] = { 973 { "LM3S811EVB", 974 0, 975 0x0032000e, 976 0x001f001f, /* dc0 */ 977 0x001132bf, 978 0x01071013, 979 0x3f0f01ff, 980 0x0000001f, 981 BP_OLED_I2C 982 }, 983 { "LM3S6965EVB", 984 0x10010002, 985 0x1073402e, 986 0x00ff007f, /* dc0 */ 987 0x001133ff, 988 0x030f5317, 989 0x0f0f87ff, 990 0x5000007f, 991 BP_OLED_SSI | BP_GAMEPAD 992 } 993 }; 994 995 static void stellaris_init(MachineState *ms, stellaris_board_info *board) 996 { 997 static const int uart_irq[NUM_UART] = {5, 6, 33, 34}; 998 static const int timer_irq[NUM_GPTM] = {19, 21, 23, 35}; 999 static const uint32_t gpio_addr[NUM_GPIO] = 1000 { 0x40004000, 0x40005000, 0x40006000, 0x40007000, 1001 0x40024000, 0x40025000, 0x40026000}; 1002 static const int gpio_irq[NUM_GPIO] = {0, 1, 2, 3, 4, 30, 31}; 1003 1004 /* Memory map of SoC devices, from 1005 * Stellaris LM3S6965 Microcontroller Data Sheet (rev I) 1006 * http://www.ti.com/lit/ds/symlink/lm3s6965.pdf 1007 * 1008 * 40000000 wdtimer 1009 * 40004000 GPIO 1010 * 40005000 GPIO 1011 * 40006000 GPIO 1012 * 40007000 GPIO 1013 * 40008000 SSI 1014 * 4000c000 UART 1015 * 4000d000 UART 1016 * 4000e000 UART 1017 * 40020000 i2c 1018 * 40021000 i2c (unimplemented) 1019 * 40024000 GPIO 1020 * 40025000 GPIO 1021 * 40026000 GPIO 1022 * 40028000 PWM (unimplemented) 1023 * 4002c000 QEI (unimplemented) 1024 * 4002d000 QEI (unimplemented) 1025 * 40030000 gptimer 1026 * 40031000 gptimer 1027 * 40032000 gptimer 1028 * 40033000 gptimer 1029 * 40038000 ADC 1030 * 4003c000 analogue comparator (unimplemented) 1031 * 40048000 ethernet 1032 * 400fc000 hibernation module (unimplemented) 1033 * 400fd000 flash memory control (unimplemented) 1034 * 400fe000 system control 1035 */ 1036 1037 Object *soc_container; 1038 DeviceState *gpio_dev[NUM_GPIO], *armv7m, *nvic; 1039 qemu_irq gpio_in[NUM_GPIO][8]; 1040 qemu_irq gpio_out[NUM_GPIO][8]; 1041 qemu_irq adc; 1042 int sram_size; 1043 int flash_size; 1044 I2CBus *i2c; 1045 DeviceState *dev; 1046 DeviceState *ssys_dev; 1047 int i; 1048 int j; 1049 NICInfo *nd; 1050 MACAddr mac; 1051 1052 MemoryRegion *sram = g_new(MemoryRegion, 1); 1053 MemoryRegion *flash = g_new(MemoryRegion, 1); 1054 MemoryRegion *system_memory = get_system_memory(); 1055 1056 flash_size = (((board->dc0 & 0xffff) + 1) << 1) * 1024; 1057 sram_size = ((board->dc0 >> 18) + 1) * 1024; 1058 1059 soc_container = object_new(TYPE_CONTAINER); 1060 object_property_add_child(OBJECT(ms), "soc", soc_container); 1061 1062 /* Flash programming is done via the SCU, so pretend it is ROM. */ 1063 memory_region_init_rom(flash, NULL, "stellaris.flash", flash_size, 1064 &error_fatal); 1065 memory_region_add_subregion(system_memory, 0, flash); 1066 1067 memory_region_init_ram(sram, NULL, "stellaris.sram", sram_size, 1068 &error_fatal); 1069 memory_region_add_subregion(system_memory, 0x20000000, sram); 1070 1071 /* 1072 * Create the system-registers object early, because we will 1073 * need its sysclk output. 1074 */ 1075 ssys_dev = qdev_new(TYPE_STELLARIS_SYS); 1076 object_property_add_child(soc_container, "sys", OBJECT(ssys_dev)); 1077 1078 /* 1079 * Most devices come preprogrammed with a MAC address in the user data. 1080 * Generate a MAC address now, if there isn't a matching -nic for it. 1081 */ 1082 nd = qemu_find_nic_info("stellaris_enet", true, "stellaris"); 1083 if (nd) { 1084 memcpy(mac.a, nd->macaddr.a, sizeof(mac.a)); 1085 } else { 1086 qemu_macaddr_default_if_unset(&mac); 1087 } 1088 1089 qdev_prop_set_uint32(ssys_dev, "user0", 1090 mac.a[0] | (mac.a[1] << 8) | (mac.a[2] << 16)); 1091 qdev_prop_set_uint32(ssys_dev, "user1", 1092 mac.a[3] | (mac.a[4] << 8) | (mac.a[5] << 16)); 1093 qdev_prop_set_uint32(ssys_dev, "did0", board->did0); 1094 qdev_prop_set_uint32(ssys_dev, "did1", board->did1); 1095 qdev_prop_set_uint32(ssys_dev, "dc0", board->dc0); 1096 qdev_prop_set_uint32(ssys_dev, "dc1", board->dc1); 1097 qdev_prop_set_uint32(ssys_dev, "dc2", board->dc2); 1098 qdev_prop_set_uint32(ssys_dev, "dc3", board->dc3); 1099 qdev_prop_set_uint32(ssys_dev, "dc4", board->dc4); 1100 sysbus_realize_and_unref(SYS_BUS_DEVICE(ssys_dev), &error_fatal); 1101 1102 armv7m = qdev_new(TYPE_ARMV7M); 1103 object_property_add_child(soc_container, "v7m", OBJECT(armv7m)); 1104 qdev_prop_set_uint32(armv7m, "num-irq", NUM_IRQ_LINES); 1105 qdev_prop_set_uint8(armv7m, "num-prio-bits", NUM_PRIO_BITS); 1106 qdev_prop_set_string(armv7m, "cpu-type", ms->cpu_type); 1107 qdev_prop_set_bit(armv7m, "enable-bitband", true); 1108 qdev_connect_clock_in(armv7m, "cpuclk", 1109 qdev_get_clock_out(ssys_dev, "SYSCLK")); 1110 /* This SoC does not connect the systick reference clock */ 1111 object_property_set_link(OBJECT(armv7m), "memory", 1112 OBJECT(get_system_memory()), &error_abort); 1113 /* This will exit with an error if the user passed us a bad cpu_type */ 1114 sysbus_realize_and_unref(SYS_BUS_DEVICE(armv7m), &error_fatal); 1115 nvic = armv7m; 1116 1117 /* Now we can wire up the IRQ and MMIO of the system registers */ 1118 sysbus_mmio_map(SYS_BUS_DEVICE(ssys_dev), 0, 0x400fe000); 1119 sysbus_connect_irq(SYS_BUS_DEVICE(ssys_dev), 0, qdev_get_gpio_in(nvic, 28)); 1120 1121 if (board->dc1 & (1 << 16)) { 1122 dev = sysbus_create_varargs(TYPE_STELLARIS_ADC, 0x40038000, 1123 qdev_get_gpio_in(nvic, 14), 1124 qdev_get_gpio_in(nvic, 15), 1125 qdev_get_gpio_in(nvic, 16), 1126 qdev_get_gpio_in(nvic, 17), 1127 NULL); 1128 adc = qdev_get_gpio_in(dev, 0); 1129 } else { 1130 adc = NULL; 1131 } 1132 for (i = 0; i < NUM_GPTM; i++) { 1133 if (board->dc2 & (0x10000 << i)) { 1134 SysBusDevice *sbd; 1135 1136 dev = qdev_new(TYPE_STELLARIS_GPTM); 1137 sbd = SYS_BUS_DEVICE(dev); 1138 object_property_add_child(soc_container, "gptm[*]", OBJECT(dev)); 1139 qdev_connect_clock_in(dev, "clk", 1140 qdev_get_clock_out(ssys_dev, "SYSCLK")); 1141 sysbus_realize_and_unref(sbd, &error_fatal); 1142 sysbus_mmio_map(sbd, 0, 0x40030000 + i * 0x1000); 1143 sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(nvic, timer_irq[i])); 1144 /* TODO: This is incorrect, but we get away with it because 1145 the ADC output is only ever pulsed. */ 1146 qdev_connect_gpio_out(dev, 0, adc); 1147 } 1148 } 1149 1150 if (board->dc1 & (1 << 3)) { /* watchdog present */ 1151 dev = qdev_new(TYPE_LUMINARY_WATCHDOG); 1152 object_property_add_child(soc_container, "wdg", OBJECT(dev)); 1153 qdev_connect_clock_in(dev, "WDOGCLK", 1154 qdev_get_clock_out(ssys_dev, "SYSCLK")); 1155 1156 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1157 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1158 0, 1159 0x40000000u); 1160 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1161 0, 1162 qdev_get_gpio_in(nvic, 18)); 1163 } 1164 1165 1166 for (i = 0; i < NUM_GPIO; i++) { 1167 if (board->dc4 & (1 << i)) { 1168 gpio_dev[i] = sysbus_create_simple("pl061_luminary", gpio_addr[i], 1169 qdev_get_gpio_in(nvic, 1170 gpio_irq[i])); 1171 for (j = 0; j < 8; j++) { 1172 gpio_in[i][j] = qdev_get_gpio_in(gpio_dev[i], j); 1173 gpio_out[i][j] = NULL; 1174 } 1175 } 1176 } 1177 1178 if (board->dc2 & (1 << 12)) { 1179 dev = sysbus_create_simple(TYPE_STELLARIS_I2C, 0x40020000, 1180 qdev_get_gpio_in(nvic, 8)); 1181 i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c"); 1182 if (board->peripherals & BP_OLED_I2C) { 1183 i2c_slave_create_simple(i2c, "ssd0303", 0x3d); 1184 } 1185 } 1186 1187 for (i = 0; i < NUM_UART; i++) { 1188 if (board->dc2 & (1 << i)) { 1189 SysBusDevice *sbd; 1190 1191 dev = qdev_new("pl011_luminary"); 1192 object_property_add_child(soc_container, "uart[*]", OBJECT(dev)); 1193 sbd = SYS_BUS_DEVICE(dev); 1194 qdev_prop_set_chr(dev, "chardev", serial_hd(i)); 1195 sysbus_realize_and_unref(sbd, &error_fatal); 1196 sysbus_mmio_map(sbd, 0, 0x4000c000 + i * 0x1000); 1197 sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(nvic, uart_irq[i])); 1198 } 1199 } 1200 if (board->dc2 & (1 << 4)) { 1201 dev = sysbus_create_simple("pl022", 0x40008000, 1202 qdev_get_gpio_in(nvic, 7)); 1203 if (board->peripherals & BP_OLED_SSI) { 1204 void *bus; 1205 DeviceState *sddev; 1206 DeviceState *ssddev; 1207 DriveInfo *dinfo; 1208 DeviceState *carddev; 1209 DeviceState *gpio_d_splitter; 1210 BlockBackend *blk; 1211 1212 /* 1213 * Some boards have both an OLED controller and SD card connected to 1214 * the same SSI port, with the SD card chip select connected to a 1215 * GPIO pin. Technically the OLED chip select is connected to the 1216 * SSI Fss pin. We do not bother emulating that as both devices 1217 * should never be selected simultaneously, and our OLED controller 1218 * ignores stray 0xff commands that occur when deselecting the SD 1219 * card. 1220 * 1221 * The h/w wiring is: 1222 * - GPIO pin D0 is wired to the active-low SD card chip select 1223 * - GPIO pin A3 is wired to the active-low OLED chip select 1224 * - The SoC wiring of the PL061 "auxiliary function" for A3 is 1225 * SSI0Fss ("frame signal"), which is an output from the SoC's 1226 * SSI controller. The SSI controller takes SSI0Fss low when it 1227 * transmits a frame, so it can work as a chip-select signal. 1228 * - GPIO A4 is aux-function SSI0Rx, and wired to the SD card Tx 1229 * (the OLED never sends data to the CPU, so no wiring needed) 1230 * - GPIO A5 is aux-function SSI0Tx, and wired to the SD card Rx 1231 * and the OLED display-data-in 1232 * - GPIO A2 is aux-function SSI0Clk, wired to SD card and OLED 1233 * serial-clock input 1234 * So a guest that wants to use the OLED can configure the PL061 1235 * to make pins A2, A3, A5 aux-function, so they are connected 1236 * directly to the SSI controller. When the SSI controller sends 1237 * data it asserts SSI0Fss which selects the OLED. 1238 * A guest that wants to use the SD card configures A2, A4 and A5 1239 * as aux-function, but leaves A3 as a software-controlled GPIO 1240 * line. It asserts the SD card chip-select by using the PL061 1241 * to control pin D0, and lets the SSI controller handle Clk, Tx 1242 * and Rx. (The SSI controller asserts Fss during tx cycles as 1243 * usual, but because A3 is not set to aux-function this is not 1244 * forwarded to the OLED, and so the OLED stays unselected.) 1245 * 1246 * The QEMU implementation instead is: 1247 * - GPIO pin D0 is wired to the active-low SD card chip select, 1248 * and also to the OLED chip-select which is implemented 1249 * as *active-high* 1250 * - SSI controller signals go to the devices regardless of 1251 * whether the guest programs A2, A4, A5 as aux-function or not 1252 * 1253 * The problem with this implementation is if the guest doesn't 1254 * care about the SD card and only uses the OLED. In that case it 1255 * may choose never to do anything with D0 (leaving it in its 1256 * default floating state, which reliably leaves the card disabled 1257 * because an SD card has a pullup on CS within the card itself), 1258 * and only set up A2, A3, A5. This for us would mean the OLED 1259 * never gets the chip-select assert it needs. We work around 1260 * this with a manual raise of D0 here (despite board creation 1261 * code being the wrong place to raise IRQ lines) to put the OLED 1262 * into an initially selected state. 1263 * 1264 * In theory the right way to model this would be: 1265 * - Implement aux-function support in the PL061, with an 1266 * extra set of AFIN and AFOUT GPIO lines (set up so that 1267 * if a GPIO line is in auxfn mode the main GPIO in and out 1268 * track the AFIN and AFOUT lines) 1269 * - Wire the AFOUT for D0 up to either a line from the 1270 * SSI controller that's pulled low around every transmit, 1271 * or at least to an always-0 line here on the board 1272 * - Make the ssd0323 OLED controller chipselect active-low 1273 */ 1274 bus = qdev_get_child_bus(dev, "ssi"); 1275 sddev = ssi_create_peripheral(bus, "ssi-sd"); 1276 1277 dinfo = drive_get(IF_SD, 0, 0); 1278 blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL; 1279 carddev = qdev_new(TYPE_SD_CARD_SPI); 1280 qdev_prop_set_drive_err(carddev, "drive", blk, &error_fatal); 1281 qdev_realize_and_unref(carddev, 1282 qdev_get_child_bus(sddev, "sd-bus"), 1283 &error_fatal); 1284 1285 ssddev = qdev_new("ssd0323"); 1286 object_property_add_child(OBJECT(ms), "oled", OBJECT(ssddev)); 1287 qdev_prop_set_uint8(ssddev, "cs", 1); 1288 qdev_realize_and_unref(ssddev, bus, &error_fatal); 1289 1290 gpio_d_splitter = qdev_new(TYPE_SPLIT_IRQ); 1291 object_property_add_child(OBJECT(ms), "splitter", 1292 OBJECT(gpio_d_splitter)); 1293 qdev_prop_set_uint32(gpio_d_splitter, "num-lines", 2); 1294 qdev_realize_and_unref(gpio_d_splitter, NULL, &error_fatal); 1295 qdev_connect_gpio_out( 1296 gpio_d_splitter, 0, 1297 qdev_get_gpio_in_named(sddev, SSI_GPIO_CS, 0)); 1298 qdev_connect_gpio_out( 1299 gpio_d_splitter, 1, 1300 qdev_get_gpio_in_named(ssddev, SSI_GPIO_CS, 0)); 1301 gpio_out[GPIO_D][0] = qdev_get_gpio_in(gpio_d_splitter, 0); 1302 1303 gpio_out[GPIO_C][7] = qdev_get_gpio_in(ssddev, 0); 1304 1305 /* Make sure the select pin is high. */ 1306 qemu_irq_raise(gpio_out[GPIO_D][0]); 1307 } 1308 } 1309 if (board->dc4 & (1 << 28)) { 1310 DeviceState *enet; 1311 1312 enet = qdev_new("stellaris_enet"); 1313 object_property_add_child(soc_container, "enet", OBJECT(enet)); 1314 if (nd) { 1315 qdev_set_nic_properties(enet, nd); 1316 } else { 1317 qdev_prop_set_macaddr(enet, "mac", mac.a); 1318 } 1319 1320 sysbus_realize_and_unref(SYS_BUS_DEVICE(enet), &error_fatal); 1321 sysbus_mmio_map(SYS_BUS_DEVICE(enet), 0, 0x40048000); 1322 sysbus_connect_irq(SYS_BUS_DEVICE(enet), 0, qdev_get_gpio_in(nvic, 42)); 1323 } 1324 if (board->peripherals & BP_GAMEPAD) { 1325 QList *gpad_keycode_list = qlist_new(); 1326 static const int gpad_keycode[5] = { 1327 Q_KEY_CODE_UP, Q_KEY_CODE_DOWN, Q_KEY_CODE_LEFT, 1328 Q_KEY_CODE_RIGHT, Q_KEY_CODE_CTRL, 1329 }; 1330 DeviceState *gpad; 1331 1332 gpad = qdev_new(TYPE_STELLARIS_GAMEPAD); 1333 object_property_add_child(OBJECT(ms), "gamepad", OBJECT(gpad)); 1334 for (i = 0; i < ARRAY_SIZE(gpad_keycode); i++) { 1335 qlist_append_int(gpad_keycode_list, gpad_keycode[i]); 1336 } 1337 qdev_prop_set_array(gpad, "keycodes", gpad_keycode_list); 1338 sysbus_realize_and_unref(SYS_BUS_DEVICE(gpad), &error_fatal); 1339 1340 qdev_connect_gpio_out(gpad, 0, 1341 qemu_irq_invert(gpio_in[GPIO_E][0])); /* up */ 1342 qdev_connect_gpio_out(gpad, 1, 1343 qemu_irq_invert(gpio_in[GPIO_E][1])); /* down */ 1344 qdev_connect_gpio_out(gpad, 2, 1345 qemu_irq_invert(gpio_in[GPIO_E][2])); /* left */ 1346 qdev_connect_gpio_out(gpad, 3, 1347 qemu_irq_invert(gpio_in[GPIO_E][3])); /* right */ 1348 qdev_connect_gpio_out(gpad, 4, 1349 qemu_irq_invert(gpio_in[GPIO_F][1])); /* select */ 1350 } 1351 for (i = 0; i < 7; i++) { 1352 if (board->dc4 & (1 << i)) { 1353 for (j = 0; j < 8; j++) { 1354 if (gpio_out[i][j]) { 1355 qdev_connect_gpio_out(gpio_dev[i], j, gpio_out[i][j]); 1356 } 1357 } 1358 } 1359 } 1360 1361 /* Add dummy regions for the devices we don't implement yet, 1362 * so guest accesses don't cause unlogged crashes. 1363 */ 1364 create_unimplemented_device("i2c-2", 0x40021000, 0x1000); 1365 create_unimplemented_device("PWM", 0x40028000, 0x1000); 1366 create_unimplemented_device("QEI-0", 0x4002c000, 0x1000); 1367 create_unimplemented_device("QEI-1", 0x4002d000, 0x1000); 1368 create_unimplemented_device("analogue-comparator", 0x4003c000, 0x1000); 1369 create_unimplemented_device("hibernation", 0x400fc000, 0x1000); 1370 create_unimplemented_device("flash-control", 0x400fd000, 0x1000); 1371 1372 armv7m_load_kernel(ARMV7M(armv7m)->cpu, ms->kernel_filename, 0, flash_size); 1373 } 1374 1375 /* FIXME: Figure out how to generate these from stellaris_boards. */ 1376 static void lm3s811evb_init(MachineState *machine) 1377 { 1378 stellaris_init(machine, &stellaris_boards[0]); 1379 } 1380 1381 static void lm3s6965evb_init(MachineState *machine) 1382 { 1383 stellaris_init(machine, &stellaris_boards[1]); 1384 } 1385 1386 /* 1387 * Stellaris LM3S811 Evaluation Board Schematics: 1388 * https://www.ti.com/lit/ug/symlink/spmu030.pdf 1389 */ 1390 static void lm3s811evb_class_init(ObjectClass *oc, void *data) 1391 { 1392 MachineClass *mc = MACHINE_CLASS(oc); 1393 1394 mc->desc = "Stellaris LM3S811EVB (Cortex-M3)"; 1395 mc->init = lm3s811evb_init; 1396 mc->ignore_memory_transaction_failures = true; 1397 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3"); 1398 } 1399 1400 static const TypeInfo lm3s811evb_type = { 1401 .name = MACHINE_TYPE_NAME("lm3s811evb"), 1402 .parent = TYPE_MACHINE, 1403 .class_init = lm3s811evb_class_init, 1404 }; 1405 1406 /* 1407 * Stellaris: LM3S6965 Evaluation Board Schematics: 1408 * https://www.ti.com/lit/ug/symlink/spmu029.pdf 1409 */ 1410 static void lm3s6965evb_class_init(ObjectClass *oc, void *data) 1411 { 1412 MachineClass *mc = MACHINE_CLASS(oc); 1413 1414 mc->desc = "Stellaris LM3S6965EVB (Cortex-M3)"; 1415 mc->init = lm3s6965evb_init; 1416 mc->ignore_memory_transaction_failures = true; 1417 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3"); 1418 } 1419 1420 static const TypeInfo lm3s6965evb_type = { 1421 .name = MACHINE_TYPE_NAME("lm3s6965evb"), 1422 .parent = TYPE_MACHINE, 1423 .class_init = lm3s6965evb_class_init, 1424 }; 1425 1426 static void stellaris_machine_init(void) 1427 { 1428 type_register_static(&lm3s811evb_type); 1429 type_register_static(&lm3s6965evb_type); 1430 } 1431 1432 type_init(stellaris_machine_init) 1433 1434 static void stellaris_i2c_class_init(ObjectClass *klass, void *data) 1435 { 1436 DeviceClass *dc = DEVICE_CLASS(klass); 1437 ResettableClass *rc = RESETTABLE_CLASS(klass); 1438 1439 rc->phases.enter = stellaris_i2c_reset_enter; 1440 rc->phases.hold = stellaris_i2c_reset_hold; 1441 rc->phases.exit = stellaris_i2c_reset_exit; 1442 dc->vmsd = &vmstate_stellaris_i2c; 1443 } 1444 1445 static const TypeInfo stellaris_i2c_info = { 1446 .name = TYPE_STELLARIS_I2C, 1447 .parent = TYPE_SYS_BUS_DEVICE, 1448 .instance_size = sizeof(stellaris_i2c_state), 1449 .instance_init = stellaris_i2c_init, 1450 .class_init = stellaris_i2c_class_init, 1451 }; 1452 1453 static void stellaris_adc_class_init(ObjectClass *klass, void *data) 1454 { 1455 DeviceClass *dc = DEVICE_CLASS(klass); 1456 ResettableClass *rc = RESETTABLE_CLASS(klass); 1457 1458 rc->phases.hold = stellaris_adc_reset_hold; 1459 dc->vmsd = &vmstate_stellaris_adc; 1460 } 1461 1462 static const TypeInfo stellaris_adc_info = { 1463 .name = TYPE_STELLARIS_ADC, 1464 .parent = TYPE_SYS_BUS_DEVICE, 1465 .instance_size = sizeof(StellarisADCState), 1466 .instance_init = stellaris_adc_init, 1467 .class_init = stellaris_adc_class_init, 1468 }; 1469 1470 static void stellaris_sys_class_init(ObjectClass *klass, void *data) 1471 { 1472 DeviceClass *dc = DEVICE_CLASS(klass); 1473 ResettableClass *rc = RESETTABLE_CLASS(klass); 1474 1475 dc->vmsd = &vmstate_stellaris_sys; 1476 rc->phases.enter = stellaris_sys_reset_enter; 1477 rc->phases.hold = stellaris_sys_reset_hold; 1478 rc->phases.exit = stellaris_sys_reset_exit; 1479 device_class_set_props(dc, stellaris_sys_properties); 1480 } 1481 1482 static const TypeInfo stellaris_sys_info = { 1483 .name = TYPE_STELLARIS_SYS, 1484 .parent = TYPE_SYS_BUS_DEVICE, 1485 .instance_size = sizeof(ssys_state), 1486 .instance_init = stellaris_sys_instance_init, 1487 .class_init = stellaris_sys_class_init, 1488 }; 1489 1490 static void stellaris_register_types(void) 1491 { 1492 type_register_static(&stellaris_i2c_info); 1493 type_register_static(&stellaris_adc_info); 1494 type_register_static(&stellaris_sys_info); 1495 } 1496 1497 type_init(stellaris_register_types) 1498