1 /* 2 * Luminary Micro Stellaris peripherals 3 * 4 * Copyright (c) 2006 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qapi/error.h" 12 #include "hw/sysbus.h" 13 #include "hw/ssi/ssi.h" 14 #include "hw/arm/boot.h" 15 #include "qemu/timer.h" 16 #include "hw/i2c/i2c.h" 17 #include "net/net.h" 18 #include "hw/boards.h" 19 #include "qemu/log.h" 20 #include "exec/address-spaces.h" 21 #include "sysemu/sysemu.h" 22 #include "hw/arm/armv7m.h" 23 #include "hw/char/pl011.h" 24 #include "hw/input/gamepad.h" 25 #include "hw/irq.h" 26 #include "hw/watchdog/cmsdk-apb-watchdog.h" 27 #include "migration/vmstate.h" 28 #include "hw/misc/unimp.h" 29 #include "hw/qdev-clock.h" 30 #include "qom/object.h" 31 32 #define GPIO_A 0 33 #define GPIO_B 1 34 #define GPIO_C 2 35 #define GPIO_D 3 36 #define GPIO_E 4 37 #define GPIO_F 5 38 #define GPIO_G 6 39 40 #define BP_OLED_I2C 0x01 41 #define BP_OLED_SSI 0x02 42 #define BP_GAMEPAD 0x04 43 44 #define NUM_IRQ_LINES 64 45 46 typedef const struct { 47 const char *name; 48 uint32_t did0; 49 uint32_t did1; 50 uint32_t dc0; 51 uint32_t dc1; 52 uint32_t dc2; 53 uint32_t dc3; 54 uint32_t dc4; 55 uint32_t peripherals; 56 } stellaris_board_info; 57 58 /* General purpose timer module. */ 59 60 #define TYPE_STELLARIS_GPTM "stellaris-gptm" 61 OBJECT_DECLARE_SIMPLE_TYPE(gptm_state, STELLARIS_GPTM) 62 63 struct gptm_state { 64 SysBusDevice parent_obj; 65 66 MemoryRegion iomem; 67 uint32_t config; 68 uint32_t mode[2]; 69 uint32_t control; 70 uint32_t state; 71 uint32_t mask; 72 uint32_t load[2]; 73 uint32_t match[2]; 74 uint32_t prescale[2]; 75 uint32_t match_prescale[2]; 76 uint32_t rtc; 77 int64_t tick[2]; 78 struct gptm_state *opaque[2]; 79 QEMUTimer *timer[2]; 80 /* The timers have an alternate output used to trigger the ADC. */ 81 qemu_irq trigger; 82 qemu_irq irq; 83 }; 84 85 static void gptm_update_irq(gptm_state *s) 86 { 87 int level; 88 level = (s->state & s->mask) != 0; 89 qemu_set_irq(s->irq, level); 90 } 91 92 static void gptm_stop(gptm_state *s, int n) 93 { 94 timer_del(s->timer[n]); 95 } 96 97 static void gptm_reload(gptm_state *s, int n, int reset) 98 { 99 int64_t tick; 100 if (reset) { 101 tick = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 102 } else { 103 tick = s->tick[n]; 104 } 105 106 if (s->config == 0) { 107 /* 32-bit CountDown. */ 108 uint32_t count; 109 count = s->load[0] | (s->load[1] << 16); 110 tick += (int64_t)count * system_clock_scale; 111 } else if (s->config == 1) { 112 /* 32-bit RTC. 1Hz tick. */ 113 tick += NANOSECONDS_PER_SECOND; 114 } else if (s->mode[n] == 0xa) { 115 /* PWM mode. Not implemented. */ 116 } else { 117 qemu_log_mask(LOG_UNIMP, 118 "GPTM: 16-bit timer mode unimplemented: 0x%x\n", 119 s->mode[n]); 120 return; 121 } 122 s->tick[n] = tick; 123 timer_mod(s->timer[n], tick); 124 } 125 126 static void gptm_tick(void *opaque) 127 { 128 gptm_state **p = (gptm_state **)opaque; 129 gptm_state *s; 130 int n; 131 132 s = *p; 133 n = p - s->opaque; 134 if (s->config == 0) { 135 s->state |= 1; 136 if ((s->control & 0x20)) { 137 /* Output trigger. */ 138 qemu_irq_pulse(s->trigger); 139 } 140 if (s->mode[0] & 1) { 141 /* One-shot. */ 142 s->control &= ~1; 143 } else { 144 /* Periodic. */ 145 gptm_reload(s, 0, 0); 146 } 147 } else if (s->config == 1) { 148 /* RTC. */ 149 uint32_t match; 150 s->rtc++; 151 match = s->match[0] | (s->match[1] << 16); 152 if (s->rtc > match) 153 s->rtc = 0; 154 if (s->rtc == 0) { 155 s->state |= 8; 156 } 157 gptm_reload(s, 0, 0); 158 } else if (s->mode[n] == 0xa) { 159 /* PWM mode. Not implemented. */ 160 } else { 161 qemu_log_mask(LOG_UNIMP, 162 "GPTM: 16-bit timer mode unimplemented: 0x%x\n", 163 s->mode[n]); 164 } 165 gptm_update_irq(s); 166 } 167 168 static uint64_t gptm_read(void *opaque, hwaddr offset, 169 unsigned size) 170 { 171 gptm_state *s = (gptm_state *)opaque; 172 173 switch (offset) { 174 case 0x00: /* CFG */ 175 return s->config; 176 case 0x04: /* TAMR */ 177 return s->mode[0]; 178 case 0x08: /* TBMR */ 179 return s->mode[1]; 180 case 0x0c: /* CTL */ 181 return s->control; 182 case 0x18: /* IMR */ 183 return s->mask; 184 case 0x1c: /* RIS */ 185 return s->state; 186 case 0x20: /* MIS */ 187 return s->state & s->mask; 188 case 0x24: /* CR */ 189 return 0; 190 case 0x28: /* TAILR */ 191 return s->load[0] | ((s->config < 4) ? (s->load[1] << 16) : 0); 192 case 0x2c: /* TBILR */ 193 return s->load[1]; 194 case 0x30: /* TAMARCHR */ 195 return s->match[0] | ((s->config < 4) ? (s->match[1] << 16) : 0); 196 case 0x34: /* TBMATCHR */ 197 return s->match[1]; 198 case 0x38: /* TAPR */ 199 return s->prescale[0]; 200 case 0x3c: /* TBPR */ 201 return s->prescale[1]; 202 case 0x40: /* TAPMR */ 203 return s->match_prescale[0]; 204 case 0x44: /* TBPMR */ 205 return s->match_prescale[1]; 206 case 0x48: /* TAR */ 207 if (s->config == 1) { 208 return s->rtc; 209 } 210 qemu_log_mask(LOG_UNIMP, 211 "GPTM: read of TAR but timer read not supported\n"); 212 return 0; 213 case 0x4c: /* TBR */ 214 qemu_log_mask(LOG_UNIMP, 215 "GPTM: read of TBR but timer read not supported\n"); 216 return 0; 217 default: 218 qemu_log_mask(LOG_GUEST_ERROR, 219 "GPTM: read at bad offset 0x02%" HWADDR_PRIx "\n", 220 offset); 221 return 0; 222 } 223 } 224 225 static void gptm_write(void *opaque, hwaddr offset, 226 uint64_t value, unsigned size) 227 { 228 gptm_state *s = (gptm_state *)opaque; 229 uint32_t oldval; 230 231 /* 232 * The timers should be disabled before changing the configuration. 233 * We take advantage of this and defer everything until the timer 234 * is enabled. 235 */ 236 switch (offset) { 237 case 0x00: /* CFG */ 238 s->config = value; 239 break; 240 case 0x04: /* TAMR */ 241 s->mode[0] = value; 242 break; 243 case 0x08: /* TBMR */ 244 s->mode[1] = value; 245 break; 246 case 0x0c: /* CTL */ 247 oldval = s->control; 248 s->control = value; 249 /* TODO: Implement pause. */ 250 if ((oldval ^ value) & 1) { 251 if (value & 1) { 252 gptm_reload(s, 0, 1); 253 } else { 254 gptm_stop(s, 0); 255 } 256 } 257 if (((oldval ^ value) & 0x100) && s->config >= 4) { 258 if (value & 0x100) { 259 gptm_reload(s, 1, 1); 260 } else { 261 gptm_stop(s, 1); 262 } 263 } 264 break; 265 case 0x18: /* IMR */ 266 s->mask = value & 0x77; 267 gptm_update_irq(s); 268 break; 269 case 0x24: /* CR */ 270 s->state &= ~value; 271 break; 272 case 0x28: /* TAILR */ 273 s->load[0] = value & 0xffff; 274 if (s->config < 4) { 275 s->load[1] = value >> 16; 276 } 277 break; 278 case 0x2c: /* TBILR */ 279 s->load[1] = value & 0xffff; 280 break; 281 case 0x30: /* TAMARCHR */ 282 s->match[0] = value & 0xffff; 283 if (s->config < 4) { 284 s->match[1] = value >> 16; 285 } 286 break; 287 case 0x34: /* TBMATCHR */ 288 s->match[1] = value >> 16; 289 break; 290 case 0x38: /* TAPR */ 291 s->prescale[0] = value; 292 break; 293 case 0x3c: /* TBPR */ 294 s->prescale[1] = value; 295 break; 296 case 0x40: /* TAPMR */ 297 s->match_prescale[0] = value; 298 break; 299 case 0x44: /* TBPMR */ 300 s->match_prescale[0] = value; 301 break; 302 default: 303 qemu_log_mask(LOG_GUEST_ERROR, 304 "GPTM: write at bad offset 0x02%" HWADDR_PRIx "\n", 305 offset); 306 } 307 gptm_update_irq(s); 308 } 309 310 static const MemoryRegionOps gptm_ops = { 311 .read = gptm_read, 312 .write = gptm_write, 313 .endianness = DEVICE_NATIVE_ENDIAN, 314 }; 315 316 static const VMStateDescription vmstate_stellaris_gptm = { 317 .name = "stellaris_gptm", 318 .version_id = 1, 319 .minimum_version_id = 1, 320 .fields = (VMStateField[]) { 321 VMSTATE_UINT32(config, gptm_state), 322 VMSTATE_UINT32_ARRAY(mode, gptm_state, 2), 323 VMSTATE_UINT32(control, gptm_state), 324 VMSTATE_UINT32(state, gptm_state), 325 VMSTATE_UINT32(mask, gptm_state), 326 VMSTATE_UNUSED(8), 327 VMSTATE_UINT32_ARRAY(load, gptm_state, 2), 328 VMSTATE_UINT32_ARRAY(match, gptm_state, 2), 329 VMSTATE_UINT32_ARRAY(prescale, gptm_state, 2), 330 VMSTATE_UINT32_ARRAY(match_prescale, gptm_state, 2), 331 VMSTATE_UINT32(rtc, gptm_state), 332 VMSTATE_INT64_ARRAY(tick, gptm_state, 2), 333 VMSTATE_TIMER_PTR_ARRAY(timer, gptm_state, 2), 334 VMSTATE_END_OF_LIST() 335 } 336 }; 337 338 static void stellaris_gptm_init(Object *obj) 339 { 340 DeviceState *dev = DEVICE(obj); 341 gptm_state *s = STELLARIS_GPTM(obj); 342 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 343 344 sysbus_init_irq(sbd, &s->irq); 345 qdev_init_gpio_out(dev, &s->trigger, 1); 346 347 memory_region_init_io(&s->iomem, obj, &gptm_ops, s, 348 "gptm", 0x1000); 349 sysbus_init_mmio(sbd, &s->iomem); 350 351 s->opaque[0] = s->opaque[1] = s; 352 } 353 354 static void stellaris_gptm_realize(DeviceState *dev, Error **errp) 355 { 356 gptm_state *s = STELLARIS_GPTM(dev); 357 s->timer[0] = timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque[0]); 358 s->timer[1] = timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque[1]); 359 } 360 361 /* System controller. */ 362 363 #define TYPE_STELLARIS_SYS "stellaris-sys" 364 OBJECT_DECLARE_SIMPLE_TYPE(ssys_state, STELLARIS_SYS) 365 366 struct ssys_state { 367 SysBusDevice parent_obj; 368 369 MemoryRegion iomem; 370 uint32_t pborctl; 371 uint32_t ldopctl; 372 uint32_t int_status; 373 uint32_t int_mask; 374 uint32_t resc; 375 uint32_t rcc; 376 uint32_t rcc2; 377 uint32_t rcgc[3]; 378 uint32_t scgc[3]; 379 uint32_t dcgc[3]; 380 uint32_t clkvclr; 381 uint32_t ldoarst; 382 qemu_irq irq; 383 Clock *sysclk; 384 /* Properties (all read-only registers) */ 385 uint32_t user0; 386 uint32_t user1; 387 uint32_t did0; 388 uint32_t did1; 389 uint32_t dc0; 390 uint32_t dc1; 391 uint32_t dc2; 392 uint32_t dc3; 393 uint32_t dc4; 394 }; 395 396 static void ssys_update(ssys_state *s) 397 { 398 qemu_set_irq(s->irq, (s->int_status & s->int_mask) != 0); 399 } 400 401 static uint32_t pllcfg_sandstorm[16] = { 402 0x31c0, /* 1 Mhz */ 403 0x1ae0, /* 1.8432 Mhz */ 404 0x18c0, /* 2 Mhz */ 405 0xd573, /* 2.4576 Mhz */ 406 0x37a6, /* 3.57954 Mhz */ 407 0x1ae2, /* 3.6864 Mhz */ 408 0x0c40, /* 4 Mhz */ 409 0x98bc, /* 4.906 Mhz */ 410 0x935b, /* 4.9152 Mhz */ 411 0x09c0, /* 5 Mhz */ 412 0x4dee, /* 5.12 Mhz */ 413 0x0c41, /* 6 Mhz */ 414 0x75db, /* 6.144 Mhz */ 415 0x1ae6, /* 7.3728 Mhz */ 416 0x0600, /* 8 Mhz */ 417 0x585b /* 8.192 Mhz */ 418 }; 419 420 static uint32_t pllcfg_fury[16] = { 421 0x3200, /* 1 Mhz */ 422 0x1b20, /* 1.8432 Mhz */ 423 0x1900, /* 2 Mhz */ 424 0xf42b, /* 2.4576 Mhz */ 425 0x37e3, /* 3.57954 Mhz */ 426 0x1b21, /* 3.6864 Mhz */ 427 0x0c80, /* 4 Mhz */ 428 0x98ee, /* 4.906 Mhz */ 429 0xd5b4, /* 4.9152 Mhz */ 430 0x0a00, /* 5 Mhz */ 431 0x4e27, /* 5.12 Mhz */ 432 0x1902, /* 6 Mhz */ 433 0xec1c, /* 6.144 Mhz */ 434 0x1b23, /* 7.3728 Mhz */ 435 0x0640, /* 8 Mhz */ 436 0xb11c /* 8.192 Mhz */ 437 }; 438 439 #define DID0_VER_MASK 0x70000000 440 #define DID0_VER_0 0x00000000 441 #define DID0_VER_1 0x10000000 442 443 #define DID0_CLASS_MASK 0x00FF0000 444 #define DID0_CLASS_SANDSTORM 0x00000000 445 #define DID0_CLASS_FURY 0x00010000 446 447 static int ssys_board_class(const ssys_state *s) 448 { 449 uint32_t did0 = s->did0; 450 switch (did0 & DID0_VER_MASK) { 451 case DID0_VER_0: 452 return DID0_CLASS_SANDSTORM; 453 case DID0_VER_1: 454 switch (did0 & DID0_CLASS_MASK) { 455 case DID0_CLASS_SANDSTORM: 456 case DID0_CLASS_FURY: 457 return did0 & DID0_CLASS_MASK; 458 } 459 /* for unknown classes, fall through */ 460 default: 461 /* This can only happen if the hardwired constant did0 value 462 * in this board's stellaris_board_info struct is wrong. 463 */ 464 g_assert_not_reached(); 465 } 466 } 467 468 static uint64_t ssys_read(void *opaque, hwaddr offset, 469 unsigned size) 470 { 471 ssys_state *s = (ssys_state *)opaque; 472 473 switch (offset) { 474 case 0x000: /* DID0 */ 475 return s->did0; 476 case 0x004: /* DID1 */ 477 return s->did1; 478 case 0x008: /* DC0 */ 479 return s->dc0; 480 case 0x010: /* DC1 */ 481 return s->dc1; 482 case 0x014: /* DC2 */ 483 return s->dc2; 484 case 0x018: /* DC3 */ 485 return s->dc3; 486 case 0x01c: /* DC4 */ 487 return s->dc4; 488 case 0x030: /* PBORCTL */ 489 return s->pborctl; 490 case 0x034: /* LDOPCTL */ 491 return s->ldopctl; 492 case 0x040: /* SRCR0 */ 493 return 0; 494 case 0x044: /* SRCR1 */ 495 return 0; 496 case 0x048: /* SRCR2 */ 497 return 0; 498 case 0x050: /* RIS */ 499 return s->int_status; 500 case 0x054: /* IMC */ 501 return s->int_mask; 502 case 0x058: /* MISC */ 503 return s->int_status & s->int_mask; 504 case 0x05c: /* RESC */ 505 return s->resc; 506 case 0x060: /* RCC */ 507 return s->rcc; 508 case 0x064: /* PLLCFG */ 509 { 510 int xtal; 511 xtal = (s->rcc >> 6) & 0xf; 512 switch (ssys_board_class(s)) { 513 case DID0_CLASS_FURY: 514 return pllcfg_fury[xtal]; 515 case DID0_CLASS_SANDSTORM: 516 return pllcfg_sandstorm[xtal]; 517 default: 518 g_assert_not_reached(); 519 } 520 } 521 case 0x070: /* RCC2 */ 522 return s->rcc2; 523 case 0x100: /* RCGC0 */ 524 return s->rcgc[0]; 525 case 0x104: /* RCGC1 */ 526 return s->rcgc[1]; 527 case 0x108: /* RCGC2 */ 528 return s->rcgc[2]; 529 case 0x110: /* SCGC0 */ 530 return s->scgc[0]; 531 case 0x114: /* SCGC1 */ 532 return s->scgc[1]; 533 case 0x118: /* SCGC2 */ 534 return s->scgc[2]; 535 case 0x120: /* DCGC0 */ 536 return s->dcgc[0]; 537 case 0x124: /* DCGC1 */ 538 return s->dcgc[1]; 539 case 0x128: /* DCGC2 */ 540 return s->dcgc[2]; 541 case 0x150: /* CLKVCLR */ 542 return s->clkvclr; 543 case 0x160: /* LDOARST */ 544 return s->ldoarst; 545 case 0x1e0: /* USER0 */ 546 return s->user0; 547 case 0x1e4: /* USER1 */ 548 return s->user1; 549 default: 550 qemu_log_mask(LOG_GUEST_ERROR, 551 "SSYS: read at bad offset 0x%x\n", (int)offset); 552 return 0; 553 } 554 } 555 556 static bool ssys_use_rcc2(ssys_state *s) 557 { 558 return (s->rcc2 >> 31) & 0x1; 559 } 560 561 /* 562 * Calculate the system clock period. We only want to propagate 563 * this change to the rest of the system if we're not being called 564 * from migration post-load. 565 */ 566 static void ssys_calculate_system_clock(ssys_state *s, bool propagate_clock) 567 { 568 /* 569 * SYSDIV field specifies divisor: 0 == /1, 1 == /2, etc. Input 570 * clock is 200MHz, which is a period of 5 ns. Dividing the clock 571 * frequency by X is the same as multiplying the period by X. 572 */ 573 if (ssys_use_rcc2(s)) { 574 system_clock_scale = 5 * (((s->rcc2 >> 23) & 0x3f) + 1); 575 } else { 576 system_clock_scale = 5 * (((s->rcc >> 23) & 0xf) + 1); 577 } 578 clock_set_ns(s->sysclk, system_clock_scale); 579 if (propagate_clock) { 580 clock_propagate(s->sysclk); 581 } 582 } 583 584 static void ssys_write(void *opaque, hwaddr offset, 585 uint64_t value, unsigned size) 586 { 587 ssys_state *s = (ssys_state *)opaque; 588 589 switch (offset) { 590 case 0x030: /* PBORCTL */ 591 s->pborctl = value & 0xffff; 592 break; 593 case 0x034: /* LDOPCTL */ 594 s->ldopctl = value & 0x1f; 595 break; 596 case 0x040: /* SRCR0 */ 597 case 0x044: /* SRCR1 */ 598 case 0x048: /* SRCR2 */ 599 qemu_log_mask(LOG_UNIMP, "Peripheral reset not implemented\n"); 600 break; 601 case 0x054: /* IMC */ 602 s->int_mask = value & 0x7f; 603 break; 604 case 0x058: /* MISC */ 605 s->int_status &= ~value; 606 break; 607 case 0x05c: /* RESC */ 608 s->resc = value & 0x3f; 609 break; 610 case 0x060: /* RCC */ 611 if ((s->rcc & (1 << 13)) != 0 && (value & (1 << 13)) == 0) { 612 /* PLL enable. */ 613 s->int_status |= (1 << 6); 614 } 615 s->rcc = value; 616 ssys_calculate_system_clock(s, true); 617 break; 618 case 0x070: /* RCC2 */ 619 if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) { 620 break; 621 } 622 623 if ((s->rcc2 & (1 << 13)) != 0 && (value & (1 << 13)) == 0) { 624 /* PLL enable. */ 625 s->int_status |= (1 << 6); 626 } 627 s->rcc2 = value; 628 ssys_calculate_system_clock(s, true); 629 break; 630 case 0x100: /* RCGC0 */ 631 s->rcgc[0] = value; 632 break; 633 case 0x104: /* RCGC1 */ 634 s->rcgc[1] = value; 635 break; 636 case 0x108: /* RCGC2 */ 637 s->rcgc[2] = value; 638 break; 639 case 0x110: /* SCGC0 */ 640 s->scgc[0] = value; 641 break; 642 case 0x114: /* SCGC1 */ 643 s->scgc[1] = value; 644 break; 645 case 0x118: /* SCGC2 */ 646 s->scgc[2] = value; 647 break; 648 case 0x120: /* DCGC0 */ 649 s->dcgc[0] = value; 650 break; 651 case 0x124: /* DCGC1 */ 652 s->dcgc[1] = value; 653 break; 654 case 0x128: /* DCGC2 */ 655 s->dcgc[2] = value; 656 break; 657 case 0x150: /* CLKVCLR */ 658 s->clkvclr = value; 659 break; 660 case 0x160: /* LDOARST */ 661 s->ldoarst = value; 662 break; 663 default: 664 qemu_log_mask(LOG_GUEST_ERROR, 665 "SSYS: write at bad offset 0x%x\n", (int)offset); 666 } 667 ssys_update(s); 668 } 669 670 static const MemoryRegionOps ssys_ops = { 671 .read = ssys_read, 672 .write = ssys_write, 673 .endianness = DEVICE_NATIVE_ENDIAN, 674 }; 675 676 static void stellaris_sys_reset_enter(Object *obj, ResetType type) 677 { 678 ssys_state *s = STELLARIS_SYS(obj); 679 680 s->pborctl = 0x7ffd; 681 s->rcc = 0x078e3ac0; 682 683 if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) { 684 s->rcc2 = 0; 685 } else { 686 s->rcc2 = 0x07802810; 687 } 688 s->rcgc[0] = 1; 689 s->scgc[0] = 1; 690 s->dcgc[0] = 1; 691 } 692 693 static void stellaris_sys_reset_hold(Object *obj) 694 { 695 ssys_state *s = STELLARIS_SYS(obj); 696 697 /* OK to propagate clocks from the hold phase */ 698 ssys_calculate_system_clock(s, true); 699 } 700 701 static void stellaris_sys_reset_exit(Object *obj) 702 { 703 } 704 705 static int stellaris_sys_post_load(void *opaque, int version_id) 706 { 707 ssys_state *s = opaque; 708 709 ssys_calculate_system_clock(s, false); 710 711 return 0; 712 } 713 714 static const VMStateDescription vmstate_stellaris_sys = { 715 .name = "stellaris_sys", 716 .version_id = 2, 717 .minimum_version_id = 1, 718 .post_load = stellaris_sys_post_load, 719 .fields = (VMStateField[]) { 720 VMSTATE_UINT32(pborctl, ssys_state), 721 VMSTATE_UINT32(ldopctl, ssys_state), 722 VMSTATE_UINT32(int_mask, ssys_state), 723 VMSTATE_UINT32(int_status, ssys_state), 724 VMSTATE_UINT32(resc, ssys_state), 725 VMSTATE_UINT32(rcc, ssys_state), 726 VMSTATE_UINT32_V(rcc2, ssys_state, 2), 727 VMSTATE_UINT32_ARRAY(rcgc, ssys_state, 3), 728 VMSTATE_UINT32_ARRAY(scgc, ssys_state, 3), 729 VMSTATE_UINT32_ARRAY(dcgc, ssys_state, 3), 730 VMSTATE_UINT32(clkvclr, ssys_state), 731 VMSTATE_UINT32(ldoarst, ssys_state), 732 /* No field for sysclk -- handled in post-load instead */ 733 VMSTATE_END_OF_LIST() 734 } 735 }; 736 737 static Property stellaris_sys_properties[] = { 738 DEFINE_PROP_UINT32("user0", ssys_state, user0, 0), 739 DEFINE_PROP_UINT32("user1", ssys_state, user1, 0), 740 DEFINE_PROP_UINT32("did0", ssys_state, did0, 0), 741 DEFINE_PROP_UINT32("did1", ssys_state, did1, 0), 742 DEFINE_PROP_UINT32("dc0", ssys_state, dc0, 0), 743 DEFINE_PROP_UINT32("dc1", ssys_state, dc1, 0), 744 DEFINE_PROP_UINT32("dc2", ssys_state, dc2, 0), 745 DEFINE_PROP_UINT32("dc3", ssys_state, dc3, 0), 746 DEFINE_PROP_UINT32("dc4", ssys_state, dc4, 0), 747 DEFINE_PROP_END_OF_LIST() 748 }; 749 750 static void stellaris_sys_instance_init(Object *obj) 751 { 752 ssys_state *s = STELLARIS_SYS(obj); 753 SysBusDevice *sbd = SYS_BUS_DEVICE(s); 754 755 memory_region_init_io(&s->iomem, obj, &ssys_ops, s, "ssys", 0x00001000); 756 sysbus_init_mmio(sbd, &s->iomem); 757 sysbus_init_irq(sbd, &s->irq); 758 s->sysclk = qdev_init_clock_out(DEVICE(s), "SYSCLK"); 759 } 760 761 /* I2C controller. */ 762 763 #define TYPE_STELLARIS_I2C "stellaris-i2c" 764 OBJECT_DECLARE_SIMPLE_TYPE(stellaris_i2c_state, STELLARIS_I2C) 765 766 struct stellaris_i2c_state { 767 SysBusDevice parent_obj; 768 769 I2CBus *bus; 770 qemu_irq irq; 771 MemoryRegion iomem; 772 uint32_t msa; 773 uint32_t mcs; 774 uint32_t mdr; 775 uint32_t mtpr; 776 uint32_t mimr; 777 uint32_t mris; 778 uint32_t mcr; 779 }; 780 781 #define STELLARIS_I2C_MCS_BUSY 0x01 782 #define STELLARIS_I2C_MCS_ERROR 0x02 783 #define STELLARIS_I2C_MCS_ADRACK 0x04 784 #define STELLARIS_I2C_MCS_DATACK 0x08 785 #define STELLARIS_I2C_MCS_ARBLST 0x10 786 #define STELLARIS_I2C_MCS_IDLE 0x20 787 #define STELLARIS_I2C_MCS_BUSBSY 0x40 788 789 static uint64_t stellaris_i2c_read(void *opaque, hwaddr offset, 790 unsigned size) 791 { 792 stellaris_i2c_state *s = (stellaris_i2c_state *)opaque; 793 794 switch (offset) { 795 case 0x00: /* MSA */ 796 return s->msa; 797 case 0x04: /* MCS */ 798 /* We don't emulate timing, so the controller is never busy. */ 799 return s->mcs | STELLARIS_I2C_MCS_IDLE; 800 case 0x08: /* MDR */ 801 return s->mdr; 802 case 0x0c: /* MTPR */ 803 return s->mtpr; 804 case 0x10: /* MIMR */ 805 return s->mimr; 806 case 0x14: /* MRIS */ 807 return s->mris; 808 case 0x18: /* MMIS */ 809 return s->mris & s->mimr; 810 case 0x20: /* MCR */ 811 return s->mcr; 812 default: 813 qemu_log_mask(LOG_GUEST_ERROR, 814 "stellaris_i2c: read at bad offset 0x%x\n", (int)offset); 815 return 0; 816 } 817 } 818 819 static void stellaris_i2c_update(stellaris_i2c_state *s) 820 { 821 int level; 822 823 level = (s->mris & s->mimr) != 0; 824 qemu_set_irq(s->irq, level); 825 } 826 827 static void stellaris_i2c_write(void *opaque, hwaddr offset, 828 uint64_t value, unsigned size) 829 { 830 stellaris_i2c_state *s = (stellaris_i2c_state *)opaque; 831 832 switch (offset) { 833 case 0x00: /* MSA */ 834 s->msa = value & 0xff; 835 break; 836 case 0x04: /* MCS */ 837 if ((s->mcr & 0x10) == 0) { 838 /* Disabled. Do nothing. */ 839 break; 840 } 841 /* Grab the bus if this is starting a transfer. */ 842 if ((value & 2) && (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) { 843 if (i2c_start_transfer(s->bus, s->msa >> 1, s->msa & 1)) { 844 s->mcs |= STELLARIS_I2C_MCS_ARBLST; 845 } else { 846 s->mcs &= ~STELLARIS_I2C_MCS_ARBLST; 847 s->mcs |= STELLARIS_I2C_MCS_BUSBSY; 848 } 849 } 850 /* If we don't have the bus then indicate an error. */ 851 if (!i2c_bus_busy(s->bus) 852 || (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) { 853 s->mcs |= STELLARIS_I2C_MCS_ERROR; 854 break; 855 } 856 s->mcs &= ~STELLARIS_I2C_MCS_ERROR; 857 if (value & 1) { 858 /* Transfer a byte. */ 859 /* TODO: Handle errors. */ 860 if (s->msa & 1) { 861 /* Recv */ 862 s->mdr = i2c_recv(s->bus); 863 } else { 864 /* Send */ 865 i2c_send(s->bus, s->mdr); 866 } 867 /* Raise an interrupt. */ 868 s->mris |= 1; 869 } 870 if (value & 4) { 871 /* Finish transfer. */ 872 i2c_end_transfer(s->bus); 873 s->mcs &= ~STELLARIS_I2C_MCS_BUSBSY; 874 } 875 break; 876 case 0x08: /* MDR */ 877 s->mdr = value & 0xff; 878 break; 879 case 0x0c: /* MTPR */ 880 s->mtpr = value & 0xff; 881 break; 882 case 0x10: /* MIMR */ 883 s->mimr = 1; 884 break; 885 case 0x1c: /* MICR */ 886 s->mris &= ~value; 887 break; 888 case 0x20: /* MCR */ 889 if (value & 1) { 890 qemu_log_mask(LOG_UNIMP, 891 "stellaris_i2c: Loopback not implemented\n"); 892 } 893 if (value & 0x20) { 894 qemu_log_mask(LOG_UNIMP, 895 "stellaris_i2c: Slave mode not implemented\n"); 896 } 897 s->mcr = value & 0x31; 898 break; 899 default: 900 qemu_log_mask(LOG_GUEST_ERROR, 901 "stellaris_i2c: write at bad offset 0x%x\n", (int)offset); 902 } 903 stellaris_i2c_update(s); 904 } 905 906 static void stellaris_i2c_reset(stellaris_i2c_state *s) 907 { 908 if (s->mcs & STELLARIS_I2C_MCS_BUSBSY) 909 i2c_end_transfer(s->bus); 910 911 s->msa = 0; 912 s->mcs = 0; 913 s->mdr = 0; 914 s->mtpr = 1; 915 s->mimr = 0; 916 s->mris = 0; 917 s->mcr = 0; 918 stellaris_i2c_update(s); 919 } 920 921 static const MemoryRegionOps stellaris_i2c_ops = { 922 .read = stellaris_i2c_read, 923 .write = stellaris_i2c_write, 924 .endianness = DEVICE_NATIVE_ENDIAN, 925 }; 926 927 static const VMStateDescription vmstate_stellaris_i2c = { 928 .name = "stellaris_i2c", 929 .version_id = 1, 930 .minimum_version_id = 1, 931 .fields = (VMStateField[]) { 932 VMSTATE_UINT32(msa, stellaris_i2c_state), 933 VMSTATE_UINT32(mcs, stellaris_i2c_state), 934 VMSTATE_UINT32(mdr, stellaris_i2c_state), 935 VMSTATE_UINT32(mtpr, stellaris_i2c_state), 936 VMSTATE_UINT32(mimr, stellaris_i2c_state), 937 VMSTATE_UINT32(mris, stellaris_i2c_state), 938 VMSTATE_UINT32(mcr, stellaris_i2c_state), 939 VMSTATE_END_OF_LIST() 940 } 941 }; 942 943 static void stellaris_i2c_init(Object *obj) 944 { 945 DeviceState *dev = DEVICE(obj); 946 stellaris_i2c_state *s = STELLARIS_I2C(obj); 947 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 948 I2CBus *bus; 949 950 sysbus_init_irq(sbd, &s->irq); 951 bus = i2c_init_bus(dev, "i2c"); 952 s->bus = bus; 953 954 memory_region_init_io(&s->iomem, obj, &stellaris_i2c_ops, s, 955 "i2c", 0x1000); 956 sysbus_init_mmio(sbd, &s->iomem); 957 /* ??? For now we only implement the master interface. */ 958 stellaris_i2c_reset(s); 959 } 960 961 /* Analogue to Digital Converter. This is only partially implemented, 962 enough for applications that use a combined ADC and timer tick. */ 963 964 #define STELLARIS_ADC_EM_CONTROLLER 0 965 #define STELLARIS_ADC_EM_COMP 1 966 #define STELLARIS_ADC_EM_EXTERNAL 4 967 #define STELLARIS_ADC_EM_TIMER 5 968 #define STELLARIS_ADC_EM_PWM0 6 969 #define STELLARIS_ADC_EM_PWM1 7 970 #define STELLARIS_ADC_EM_PWM2 8 971 972 #define STELLARIS_ADC_FIFO_EMPTY 0x0100 973 #define STELLARIS_ADC_FIFO_FULL 0x1000 974 975 #define TYPE_STELLARIS_ADC "stellaris-adc" 976 typedef struct StellarisADCState stellaris_adc_state; 977 DECLARE_INSTANCE_CHECKER(stellaris_adc_state, STELLARIS_ADC, 978 TYPE_STELLARIS_ADC) 979 980 struct StellarisADCState { 981 SysBusDevice parent_obj; 982 983 MemoryRegion iomem; 984 uint32_t actss; 985 uint32_t ris; 986 uint32_t im; 987 uint32_t emux; 988 uint32_t ostat; 989 uint32_t ustat; 990 uint32_t sspri; 991 uint32_t sac; 992 struct { 993 uint32_t state; 994 uint32_t data[16]; 995 } fifo[4]; 996 uint32_t ssmux[4]; 997 uint32_t ssctl[4]; 998 uint32_t noise; 999 qemu_irq irq[4]; 1000 }; 1001 1002 static uint32_t stellaris_adc_fifo_read(stellaris_adc_state *s, int n) 1003 { 1004 int tail; 1005 1006 tail = s->fifo[n].state & 0xf; 1007 if (s->fifo[n].state & STELLARIS_ADC_FIFO_EMPTY) { 1008 s->ustat |= 1 << n; 1009 } else { 1010 s->fifo[n].state = (s->fifo[n].state & ~0xf) | ((tail + 1) & 0xf); 1011 s->fifo[n].state &= ~STELLARIS_ADC_FIFO_FULL; 1012 if (tail + 1 == ((s->fifo[n].state >> 4) & 0xf)) 1013 s->fifo[n].state |= STELLARIS_ADC_FIFO_EMPTY; 1014 } 1015 return s->fifo[n].data[tail]; 1016 } 1017 1018 static void stellaris_adc_fifo_write(stellaris_adc_state *s, int n, 1019 uint32_t value) 1020 { 1021 int head; 1022 1023 /* TODO: Real hardware has limited size FIFOs. We have a full 16 entry 1024 FIFO fir each sequencer. */ 1025 head = (s->fifo[n].state >> 4) & 0xf; 1026 if (s->fifo[n].state & STELLARIS_ADC_FIFO_FULL) { 1027 s->ostat |= 1 << n; 1028 return; 1029 } 1030 s->fifo[n].data[head] = value; 1031 head = (head + 1) & 0xf; 1032 s->fifo[n].state &= ~STELLARIS_ADC_FIFO_EMPTY; 1033 s->fifo[n].state = (s->fifo[n].state & ~0xf0) | (head << 4); 1034 if ((s->fifo[n].state & 0xf) == head) 1035 s->fifo[n].state |= STELLARIS_ADC_FIFO_FULL; 1036 } 1037 1038 static void stellaris_adc_update(stellaris_adc_state *s) 1039 { 1040 int level; 1041 int n; 1042 1043 for (n = 0; n < 4; n++) { 1044 level = (s->ris & s->im & (1 << n)) != 0; 1045 qemu_set_irq(s->irq[n], level); 1046 } 1047 } 1048 1049 static void stellaris_adc_trigger(void *opaque, int irq, int level) 1050 { 1051 stellaris_adc_state *s = (stellaris_adc_state *)opaque; 1052 int n; 1053 1054 for (n = 0; n < 4; n++) { 1055 if ((s->actss & (1 << n)) == 0) { 1056 continue; 1057 } 1058 1059 if (((s->emux >> (n * 4)) & 0xff) != 5) { 1060 continue; 1061 } 1062 1063 /* Some applications use the ADC as a random number source, so introduce 1064 some variation into the signal. */ 1065 s->noise = s->noise * 314159 + 1; 1066 /* ??? actual inputs not implemented. Return an arbitrary value. */ 1067 stellaris_adc_fifo_write(s, n, 0x200 + ((s->noise >> 16) & 7)); 1068 s->ris |= (1 << n); 1069 stellaris_adc_update(s); 1070 } 1071 } 1072 1073 static void stellaris_adc_reset(stellaris_adc_state *s) 1074 { 1075 int n; 1076 1077 for (n = 0; n < 4; n++) { 1078 s->ssmux[n] = 0; 1079 s->ssctl[n] = 0; 1080 s->fifo[n].state = STELLARIS_ADC_FIFO_EMPTY; 1081 } 1082 } 1083 1084 static uint64_t stellaris_adc_read(void *opaque, hwaddr offset, 1085 unsigned size) 1086 { 1087 stellaris_adc_state *s = (stellaris_adc_state *)opaque; 1088 1089 /* TODO: Implement this. */ 1090 if (offset >= 0x40 && offset < 0xc0) { 1091 int n; 1092 n = (offset - 0x40) >> 5; 1093 switch (offset & 0x1f) { 1094 case 0x00: /* SSMUX */ 1095 return s->ssmux[n]; 1096 case 0x04: /* SSCTL */ 1097 return s->ssctl[n]; 1098 case 0x08: /* SSFIFO */ 1099 return stellaris_adc_fifo_read(s, n); 1100 case 0x0c: /* SSFSTAT */ 1101 return s->fifo[n].state; 1102 default: 1103 break; 1104 } 1105 } 1106 switch (offset) { 1107 case 0x00: /* ACTSS */ 1108 return s->actss; 1109 case 0x04: /* RIS */ 1110 return s->ris; 1111 case 0x08: /* IM */ 1112 return s->im; 1113 case 0x0c: /* ISC */ 1114 return s->ris & s->im; 1115 case 0x10: /* OSTAT */ 1116 return s->ostat; 1117 case 0x14: /* EMUX */ 1118 return s->emux; 1119 case 0x18: /* USTAT */ 1120 return s->ustat; 1121 case 0x20: /* SSPRI */ 1122 return s->sspri; 1123 case 0x30: /* SAC */ 1124 return s->sac; 1125 default: 1126 qemu_log_mask(LOG_GUEST_ERROR, 1127 "stellaris_adc: read at bad offset 0x%x\n", (int)offset); 1128 return 0; 1129 } 1130 } 1131 1132 static void stellaris_adc_write(void *opaque, hwaddr offset, 1133 uint64_t value, unsigned size) 1134 { 1135 stellaris_adc_state *s = (stellaris_adc_state *)opaque; 1136 1137 /* TODO: Implement this. */ 1138 if (offset >= 0x40 && offset < 0xc0) { 1139 int n; 1140 n = (offset - 0x40) >> 5; 1141 switch (offset & 0x1f) { 1142 case 0x00: /* SSMUX */ 1143 s->ssmux[n] = value & 0x33333333; 1144 return; 1145 case 0x04: /* SSCTL */ 1146 if (value != 6) { 1147 qemu_log_mask(LOG_UNIMP, 1148 "ADC: Unimplemented sequence %" PRIx64 "\n", 1149 value); 1150 } 1151 s->ssctl[n] = value; 1152 return; 1153 default: 1154 break; 1155 } 1156 } 1157 switch (offset) { 1158 case 0x00: /* ACTSS */ 1159 s->actss = value & 0xf; 1160 break; 1161 case 0x08: /* IM */ 1162 s->im = value; 1163 break; 1164 case 0x0c: /* ISC */ 1165 s->ris &= ~value; 1166 break; 1167 case 0x10: /* OSTAT */ 1168 s->ostat &= ~value; 1169 break; 1170 case 0x14: /* EMUX */ 1171 s->emux = value; 1172 break; 1173 case 0x18: /* USTAT */ 1174 s->ustat &= ~value; 1175 break; 1176 case 0x20: /* SSPRI */ 1177 s->sspri = value; 1178 break; 1179 case 0x28: /* PSSI */ 1180 qemu_log_mask(LOG_UNIMP, "ADC: sample initiate unimplemented\n"); 1181 break; 1182 case 0x30: /* SAC */ 1183 s->sac = value; 1184 break; 1185 default: 1186 qemu_log_mask(LOG_GUEST_ERROR, 1187 "stellaris_adc: write at bad offset 0x%x\n", (int)offset); 1188 } 1189 stellaris_adc_update(s); 1190 } 1191 1192 static const MemoryRegionOps stellaris_adc_ops = { 1193 .read = stellaris_adc_read, 1194 .write = stellaris_adc_write, 1195 .endianness = DEVICE_NATIVE_ENDIAN, 1196 }; 1197 1198 static const VMStateDescription vmstate_stellaris_adc = { 1199 .name = "stellaris_adc", 1200 .version_id = 1, 1201 .minimum_version_id = 1, 1202 .fields = (VMStateField[]) { 1203 VMSTATE_UINT32(actss, stellaris_adc_state), 1204 VMSTATE_UINT32(ris, stellaris_adc_state), 1205 VMSTATE_UINT32(im, stellaris_adc_state), 1206 VMSTATE_UINT32(emux, stellaris_adc_state), 1207 VMSTATE_UINT32(ostat, stellaris_adc_state), 1208 VMSTATE_UINT32(ustat, stellaris_adc_state), 1209 VMSTATE_UINT32(sspri, stellaris_adc_state), 1210 VMSTATE_UINT32(sac, stellaris_adc_state), 1211 VMSTATE_UINT32(fifo[0].state, stellaris_adc_state), 1212 VMSTATE_UINT32_ARRAY(fifo[0].data, stellaris_adc_state, 16), 1213 VMSTATE_UINT32(ssmux[0], stellaris_adc_state), 1214 VMSTATE_UINT32(ssctl[0], stellaris_adc_state), 1215 VMSTATE_UINT32(fifo[1].state, stellaris_adc_state), 1216 VMSTATE_UINT32_ARRAY(fifo[1].data, stellaris_adc_state, 16), 1217 VMSTATE_UINT32(ssmux[1], stellaris_adc_state), 1218 VMSTATE_UINT32(ssctl[1], stellaris_adc_state), 1219 VMSTATE_UINT32(fifo[2].state, stellaris_adc_state), 1220 VMSTATE_UINT32_ARRAY(fifo[2].data, stellaris_adc_state, 16), 1221 VMSTATE_UINT32(ssmux[2], stellaris_adc_state), 1222 VMSTATE_UINT32(ssctl[2], stellaris_adc_state), 1223 VMSTATE_UINT32(fifo[3].state, stellaris_adc_state), 1224 VMSTATE_UINT32_ARRAY(fifo[3].data, stellaris_adc_state, 16), 1225 VMSTATE_UINT32(ssmux[3], stellaris_adc_state), 1226 VMSTATE_UINT32(ssctl[3], stellaris_adc_state), 1227 VMSTATE_UINT32(noise, stellaris_adc_state), 1228 VMSTATE_END_OF_LIST() 1229 } 1230 }; 1231 1232 static void stellaris_adc_init(Object *obj) 1233 { 1234 DeviceState *dev = DEVICE(obj); 1235 stellaris_adc_state *s = STELLARIS_ADC(obj); 1236 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 1237 int n; 1238 1239 for (n = 0; n < 4; n++) { 1240 sysbus_init_irq(sbd, &s->irq[n]); 1241 } 1242 1243 memory_region_init_io(&s->iomem, obj, &stellaris_adc_ops, s, 1244 "adc", 0x1000); 1245 sysbus_init_mmio(sbd, &s->iomem); 1246 stellaris_adc_reset(s); 1247 qdev_init_gpio_in(dev, stellaris_adc_trigger, 1); 1248 } 1249 1250 /* Board init. */ 1251 static stellaris_board_info stellaris_boards[] = { 1252 { "LM3S811EVB", 1253 0, 1254 0x0032000e, 1255 0x001f001f, /* dc0 */ 1256 0x001132bf, 1257 0x01071013, 1258 0x3f0f01ff, 1259 0x0000001f, 1260 BP_OLED_I2C 1261 }, 1262 { "LM3S6965EVB", 1263 0x10010002, 1264 0x1073402e, 1265 0x00ff007f, /* dc0 */ 1266 0x001133ff, 1267 0x030f5317, 1268 0x0f0f87ff, 1269 0x5000007f, 1270 BP_OLED_SSI | BP_GAMEPAD 1271 } 1272 }; 1273 1274 static void stellaris_init(MachineState *ms, stellaris_board_info *board) 1275 { 1276 static const int uart_irq[] = {5, 6, 33, 34}; 1277 static const int timer_irq[] = {19, 21, 23, 35}; 1278 static const uint32_t gpio_addr[7] = 1279 { 0x40004000, 0x40005000, 0x40006000, 0x40007000, 1280 0x40024000, 0x40025000, 0x40026000}; 1281 static const int gpio_irq[7] = {0, 1, 2, 3, 4, 30, 31}; 1282 1283 /* Memory map of SoC devices, from 1284 * Stellaris LM3S6965 Microcontroller Data Sheet (rev I) 1285 * http://www.ti.com/lit/ds/symlink/lm3s6965.pdf 1286 * 1287 * 40000000 wdtimer 1288 * 40002000 i2c (unimplemented) 1289 * 40004000 GPIO 1290 * 40005000 GPIO 1291 * 40006000 GPIO 1292 * 40007000 GPIO 1293 * 40008000 SSI 1294 * 4000c000 UART 1295 * 4000d000 UART 1296 * 4000e000 UART 1297 * 40020000 i2c 1298 * 40021000 i2c (unimplemented) 1299 * 40024000 GPIO 1300 * 40025000 GPIO 1301 * 40026000 GPIO 1302 * 40028000 PWM (unimplemented) 1303 * 4002c000 QEI (unimplemented) 1304 * 4002d000 QEI (unimplemented) 1305 * 40030000 gptimer 1306 * 40031000 gptimer 1307 * 40032000 gptimer 1308 * 40033000 gptimer 1309 * 40038000 ADC 1310 * 4003c000 analogue comparator (unimplemented) 1311 * 40048000 ethernet 1312 * 400fc000 hibernation module (unimplemented) 1313 * 400fd000 flash memory control (unimplemented) 1314 * 400fe000 system control 1315 */ 1316 1317 DeviceState *gpio_dev[7], *nvic; 1318 qemu_irq gpio_in[7][8]; 1319 qemu_irq gpio_out[7][8]; 1320 qemu_irq adc; 1321 int sram_size; 1322 int flash_size; 1323 I2CBus *i2c; 1324 DeviceState *dev; 1325 DeviceState *ssys_dev; 1326 int i; 1327 int j; 1328 const uint8_t *macaddr; 1329 1330 MemoryRegion *sram = g_new(MemoryRegion, 1); 1331 MemoryRegion *flash = g_new(MemoryRegion, 1); 1332 MemoryRegion *system_memory = get_system_memory(); 1333 1334 flash_size = (((board->dc0 & 0xffff) + 1) << 1) * 1024; 1335 sram_size = ((board->dc0 >> 18) + 1) * 1024; 1336 1337 /* Flash programming is done via the SCU, so pretend it is ROM. */ 1338 memory_region_init_rom(flash, NULL, "stellaris.flash", flash_size, 1339 &error_fatal); 1340 memory_region_add_subregion(system_memory, 0, flash); 1341 1342 memory_region_init_ram(sram, NULL, "stellaris.sram", sram_size, 1343 &error_fatal); 1344 memory_region_add_subregion(system_memory, 0x20000000, sram); 1345 1346 /* 1347 * Create the system-registers object early, because we will 1348 * need its sysclk output. 1349 */ 1350 ssys_dev = qdev_new(TYPE_STELLARIS_SYS); 1351 /* Most devices come preprogrammed with a MAC address in the user data. */ 1352 macaddr = nd_table[0].macaddr.a; 1353 qdev_prop_set_uint32(ssys_dev, "user0", 1354 macaddr[0] | (macaddr[1] << 8) | (macaddr[2] << 16)); 1355 qdev_prop_set_uint32(ssys_dev, "user1", 1356 macaddr[3] | (macaddr[4] << 8) | (macaddr[5] << 16)); 1357 qdev_prop_set_uint32(ssys_dev, "did0", board->did0); 1358 qdev_prop_set_uint32(ssys_dev, "did1", board->did1); 1359 qdev_prop_set_uint32(ssys_dev, "dc0", board->dc0); 1360 qdev_prop_set_uint32(ssys_dev, "dc1", board->dc1); 1361 qdev_prop_set_uint32(ssys_dev, "dc2", board->dc2); 1362 qdev_prop_set_uint32(ssys_dev, "dc3", board->dc3); 1363 qdev_prop_set_uint32(ssys_dev, "dc4", board->dc4); 1364 sysbus_realize_and_unref(SYS_BUS_DEVICE(ssys_dev), &error_fatal); 1365 1366 nvic = qdev_new(TYPE_ARMV7M); 1367 qdev_prop_set_uint32(nvic, "num-irq", NUM_IRQ_LINES); 1368 qdev_prop_set_string(nvic, "cpu-type", ms->cpu_type); 1369 qdev_prop_set_bit(nvic, "enable-bitband", true); 1370 qdev_connect_clock_in(nvic, "cpuclk", 1371 qdev_get_clock_out(ssys_dev, "SYSCLK")); 1372 /* This SoC does not connect the systick reference clock */ 1373 object_property_set_link(OBJECT(nvic), "memory", 1374 OBJECT(get_system_memory()), &error_abort); 1375 /* This will exit with an error if the user passed us a bad cpu_type */ 1376 sysbus_realize_and_unref(SYS_BUS_DEVICE(nvic), &error_fatal); 1377 1378 /* Now we can wire up the IRQ and MMIO of the system registers */ 1379 sysbus_mmio_map(SYS_BUS_DEVICE(ssys_dev), 0, 0x400fe000); 1380 sysbus_connect_irq(SYS_BUS_DEVICE(ssys_dev), 0, qdev_get_gpio_in(nvic, 28)); 1381 1382 if (board->dc1 & (1 << 16)) { 1383 dev = sysbus_create_varargs(TYPE_STELLARIS_ADC, 0x40038000, 1384 qdev_get_gpio_in(nvic, 14), 1385 qdev_get_gpio_in(nvic, 15), 1386 qdev_get_gpio_in(nvic, 16), 1387 qdev_get_gpio_in(nvic, 17), 1388 NULL); 1389 adc = qdev_get_gpio_in(dev, 0); 1390 } else { 1391 adc = NULL; 1392 } 1393 for (i = 0; i < 4; i++) { 1394 if (board->dc2 & (0x10000 << i)) { 1395 dev = sysbus_create_simple(TYPE_STELLARIS_GPTM, 1396 0x40030000 + i * 0x1000, 1397 qdev_get_gpio_in(nvic, timer_irq[i])); 1398 /* TODO: This is incorrect, but we get away with it because 1399 the ADC output is only ever pulsed. */ 1400 qdev_connect_gpio_out(dev, 0, adc); 1401 } 1402 } 1403 1404 if (board->dc1 & (1 << 3)) { /* watchdog present */ 1405 dev = qdev_new(TYPE_LUMINARY_WATCHDOG); 1406 1407 qdev_connect_clock_in(dev, "WDOGCLK", 1408 qdev_get_clock_out(ssys_dev, "SYSCLK")); 1409 1410 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1411 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1412 0, 1413 0x40000000u); 1414 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1415 0, 1416 qdev_get_gpio_in(nvic, 18)); 1417 } 1418 1419 1420 for (i = 0; i < 7; i++) { 1421 if (board->dc4 & (1 << i)) { 1422 gpio_dev[i] = sysbus_create_simple("pl061_luminary", gpio_addr[i], 1423 qdev_get_gpio_in(nvic, 1424 gpio_irq[i])); 1425 for (j = 0; j < 8; j++) { 1426 gpio_in[i][j] = qdev_get_gpio_in(gpio_dev[i], j); 1427 gpio_out[i][j] = NULL; 1428 } 1429 } 1430 } 1431 1432 if (board->dc2 & (1 << 12)) { 1433 dev = sysbus_create_simple(TYPE_STELLARIS_I2C, 0x40020000, 1434 qdev_get_gpio_in(nvic, 8)); 1435 i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c"); 1436 if (board->peripherals & BP_OLED_I2C) { 1437 i2c_slave_create_simple(i2c, "ssd0303", 0x3d); 1438 } 1439 } 1440 1441 for (i = 0; i < 4; i++) { 1442 if (board->dc2 & (1 << i)) { 1443 pl011_luminary_create(0x4000c000 + i * 0x1000, 1444 qdev_get_gpio_in(nvic, uart_irq[i]), 1445 serial_hd(i)); 1446 } 1447 } 1448 if (board->dc2 & (1 << 4)) { 1449 dev = sysbus_create_simple("pl022", 0x40008000, 1450 qdev_get_gpio_in(nvic, 7)); 1451 if (board->peripherals & BP_OLED_SSI) { 1452 void *bus; 1453 DeviceState *sddev; 1454 DeviceState *ssddev; 1455 1456 /* 1457 * Some boards have both an OLED controller and SD card connected to 1458 * the same SSI port, with the SD card chip select connected to a 1459 * GPIO pin. Technically the OLED chip select is connected to the 1460 * SSI Fss pin. We do not bother emulating that as both devices 1461 * should never be selected simultaneously, and our OLED controller 1462 * ignores stray 0xff commands that occur when deselecting the SD 1463 * card. 1464 * 1465 * The h/w wiring is: 1466 * - GPIO pin D0 is wired to the active-low SD card chip select 1467 * - GPIO pin A3 is wired to the active-low OLED chip select 1468 * - The SoC wiring of the PL061 "auxiliary function" for A3 is 1469 * SSI0Fss ("frame signal"), which is an output from the SoC's 1470 * SSI controller. The SSI controller takes SSI0Fss low when it 1471 * transmits a frame, so it can work as a chip-select signal. 1472 * - GPIO A4 is aux-function SSI0Rx, and wired to the SD card Tx 1473 * (the OLED never sends data to the CPU, so no wiring needed) 1474 * - GPIO A5 is aux-function SSI0Tx, and wired to the SD card Rx 1475 * and the OLED display-data-in 1476 * - GPIO A2 is aux-function SSI0Clk, wired to SD card and OLED 1477 * serial-clock input 1478 * So a guest that wants to use the OLED can configure the PL061 1479 * to make pins A2, A3, A5 aux-function, so they are connected 1480 * directly to the SSI controller. When the SSI controller sends 1481 * data it asserts SSI0Fss which selects the OLED. 1482 * A guest that wants to use the SD card configures A2, A4 and A5 1483 * as aux-function, but leaves A3 as a software-controlled GPIO 1484 * line. It asserts the SD card chip-select by using the PL061 1485 * to control pin D0, and lets the SSI controller handle Clk, Tx 1486 * and Rx. (The SSI controller asserts Fss during tx cycles as 1487 * usual, but because A3 is not set to aux-function this is not 1488 * forwarded to the OLED, and so the OLED stays unselected.) 1489 * 1490 * The QEMU implementation instead is: 1491 * - GPIO pin D0 is wired to the active-low SD card chip select, 1492 * and also to the OLED chip-select which is implemented 1493 * as *active-high* 1494 * - SSI controller signals go to the devices regardless of 1495 * whether the guest programs A2, A4, A5 as aux-function or not 1496 * 1497 * The problem with this implementation is if the guest doesn't 1498 * care about the SD card and only uses the OLED. In that case it 1499 * may choose never to do anything with D0 (leaving it in its 1500 * default floating state, which reliably leaves the card disabled 1501 * because an SD card has a pullup on CS within the card itself), 1502 * and only set up A2, A3, A5. This for us would mean the OLED 1503 * never gets the chip-select assert it needs. We work around 1504 * this with a manual raise of D0 here (despite board creation 1505 * code being the wrong place to raise IRQ lines) to put the OLED 1506 * into an initially selected state. 1507 * 1508 * In theory the right way to model this would be: 1509 * - Implement aux-function support in the PL061, with an 1510 * extra set of AFIN and AFOUT GPIO lines (set up so that 1511 * if a GPIO line is in auxfn mode the main GPIO in and out 1512 * track the AFIN and AFOUT lines) 1513 * - Wire the AFOUT for D0 up to either a line from the 1514 * SSI controller that's pulled low around every transmit, 1515 * or at least to an always-0 line here on the board 1516 * - Make the ssd0323 OLED controller chipselect active-low 1517 */ 1518 bus = qdev_get_child_bus(dev, "ssi"); 1519 1520 sddev = ssi_create_peripheral(bus, "ssi-sd"); 1521 ssddev = ssi_create_peripheral(bus, "ssd0323"); 1522 gpio_out[GPIO_D][0] = qemu_irq_split( 1523 qdev_get_gpio_in_named(sddev, SSI_GPIO_CS, 0), 1524 qdev_get_gpio_in_named(ssddev, SSI_GPIO_CS, 0)); 1525 gpio_out[GPIO_C][7] = qdev_get_gpio_in(ssddev, 0); 1526 1527 /* Make sure the select pin is high. */ 1528 qemu_irq_raise(gpio_out[GPIO_D][0]); 1529 } 1530 } 1531 if (board->dc4 & (1 << 28)) { 1532 DeviceState *enet; 1533 1534 qemu_check_nic_model(&nd_table[0], "stellaris"); 1535 1536 enet = qdev_new("stellaris_enet"); 1537 qdev_set_nic_properties(enet, &nd_table[0]); 1538 sysbus_realize_and_unref(SYS_BUS_DEVICE(enet), &error_fatal); 1539 sysbus_mmio_map(SYS_BUS_DEVICE(enet), 0, 0x40048000); 1540 sysbus_connect_irq(SYS_BUS_DEVICE(enet), 0, qdev_get_gpio_in(nvic, 42)); 1541 } 1542 if (board->peripherals & BP_GAMEPAD) { 1543 qemu_irq gpad_irq[5]; 1544 static const int gpad_keycode[5] = { 0xc8, 0xd0, 0xcb, 0xcd, 0x1d }; 1545 1546 gpad_irq[0] = qemu_irq_invert(gpio_in[GPIO_E][0]); /* up */ 1547 gpad_irq[1] = qemu_irq_invert(gpio_in[GPIO_E][1]); /* down */ 1548 gpad_irq[2] = qemu_irq_invert(gpio_in[GPIO_E][2]); /* left */ 1549 gpad_irq[3] = qemu_irq_invert(gpio_in[GPIO_E][3]); /* right */ 1550 gpad_irq[4] = qemu_irq_invert(gpio_in[GPIO_F][1]); /* select */ 1551 1552 stellaris_gamepad_init(5, gpad_irq, gpad_keycode); 1553 } 1554 for (i = 0; i < 7; i++) { 1555 if (board->dc4 & (1 << i)) { 1556 for (j = 0; j < 8; j++) { 1557 if (gpio_out[i][j]) { 1558 qdev_connect_gpio_out(gpio_dev[i], j, gpio_out[i][j]); 1559 } 1560 } 1561 } 1562 } 1563 1564 /* Add dummy regions for the devices we don't implement yet, 1565 * so guest accesses don't cause unlogged crashes. 1566 */ 1567 create_unimplemented_device("i2c-0", 0x40002000, 0x1000); 1568 create_unimplemented_device("i2c-2", 0x40021000, 0x1000); 1569 create_unimplemented_device("PWM", 0x40028000, 0x1000); 1570 create_unimplemented_device("QEI-0", 0x4002c000, 0x1000); 1571 create_unimplemented_device("QEI-1", 0x4002d000, 0x1000); 1572 create_unimplemented_device("analogue-comparator", 0x4003c000, 0x1000); 1573 create_unimplemented_device("hibernation", 0x400fc000, 0x1000); 1574 create_unimplemented_device("flash-control", 0x400fd000, 0x1000); 1575 1576 armv7m_load_kernel(ARM_CPU(first_cpu), ms->kernel_filename, flash_size); 1577 } 1578 1579 /* FIXME: Figure out how to generate these from stellaris_boards. */ 1580 static void lm3s811evb_init(MachineState *machine) 1581 { 1582 stellaris_init(machine, &stellaris_boards[0]); 1583 } 1584 1585 static void lm3s6965evb_init(MachineState *machine) 1586 { 1587 stellaris_init(machine, &stellaris_boards[1]); 1588 } 1589 1590 static void lm3s811evb_class_init(ObjectClass *oc, void *data) 1591 { 1592 MachineClass *mc = MACHINE_CLASS(oc); 1593 1594 mc->desc = "Stellaris LM3S811EVB (Cortex-M3)"; 1595 mc->init = lm3s811evb_init; 1596 mc->ignore_memory_transaction_failures = true; 1597 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3"); 1598 } 1599 1600 static const TypeInfo lm3s811evb_type = { 1601 .name = MACHINE_TYPE_NAME("lm3s811evb"), 1602 .parent = TYPE_MACHINE, 1603 .class_init = lm3s811evb_class_init, 1604 }; 1605 1606 static void lm3s6965evb_class_init(ObjectClass *oc, void *data) 1607 { 1608 MachineClass *mc = MACHINE_CLASS(oc); 1609 1610 mc->desc = "Stellaris LM3S6965EVB (Cortex-M3)"; 1611 mc->init = lm3s6965evb_init; 1612 mc->ignore_memory_transaction_failures = true; 1613 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3"); 1614 } 1615 1616 static const TypeInfo lm3s6965evb_type = { 1617 .name = MACHINE_TYPE_NAME("lm3s6965evb"), 1618 .parent = TYPE_MACHINE, 1619 .class_init = lm3s6965evb_class_init, 1620 }; 1621 1622 static void stellaris_machine_init(void) 1623 { 1624 type_register_static(&lm3s811evb_type); 1625 type_register_static(&lm3s6965evb_type); 1626 } 1627 1628 type_init(stellaris_machine_init) 1629 1630 static void stellaris_i2c_class_init(ObjectClass *klass, void *data) 1631 { 1632 DeviceClass *dc = DEVICE_CLASS(klass); 1633 1634 dc->vmsd = &vmstate_stellaris_i2c; 1635 } 1636 1637 static const TypeInfo stellaris_i2c_info = { 1638 .name = TYPE_STELLARIS_I2C, 1639 .parent = TYPE_SYS_BUS_DEVICE, 1640 .instance_size = sizeof(stellaris_i2c_state), 1641 .instance_init = stellaris_i2c_init, 1642 .class_init = stellaris_i2c_class_init, 1643 }; 1644 1645 static void stellaris_gptm_class_init(ObjectClass *klass, void *data) 1646 { 1647 DeviceClass *dc = DEVICE_CLASS(klass); 1648 1649 dc->vmsd = &vmstate_stellaris_gptm; 1650 dc->realize = stellaris_gptm_realize; 1651 } 1652 1653 static const TypeInfo stellaris_gptm_info = { 1654 .name = TYPE_STELLARIS_GPTM, 1655 .parent = TYPE_SYS_BUS_DEVICE, 1656 .instance_size = sizeof(gptm_state), 1657 .instance_init = stellaris_gptm_init, 1658 .class_init = stellaris_gptm_class_init, 1659 }; 1660 1661 static void stellaris_adc_class_init(ObjectClass *klass, void *data) 1662 { 1663 DeviceClass *dc = DEVICE_CLASS(klass); 1664 1665 dc->vmsd = &vmstate_stellaris_adc; 1666 } 1667 1668 static const TypeInfo stellaris_adc_info = { 1669 .name = TYPE_STELLARIS_ADC, 1670 .parent = TYPE_SYS_BUS_DEVICE, 1671 .instance_size = sizeof(stellaris_adc_state), 1672 .instance_init = stellaris_adc_init, 1673 .class_init = stellaris_adc_class_init, 1674 }; 1675 1676 static void stellaris_sys_class_init(ObjectClass *klass, void *data) 1677 { 1678 DeviceClass *dc = DEVICE_CLASS(klass); 1679 ResettableClass *rc = RESETTABLE_CLASS(klass); 1680 1681 dc->vmsd = &vmstate_stellaris_sys; 1682 rc->phases.enter = stellaris_sys_reset_enter; 1683 rc->phases.hold = stellaris_sys_reset_hold; 1684 rc->phases.exit = stellaris_sys_reset_exit; 1685 device_class_set_props(dc, stellaris_sys_properties); 1686 } 1687 1688 static const TypeInfo stellaris_sys_info = { 1689 .name = TYPE_STELLARIS_SYS, 1690 .parent = TYPE_SYS_BUS_DEVICE, 1691 .instance_size = sizeof(ssys_state), 1692 .instance_init = stellaris_sys_instance_init, 1693 .class_init = stellaris_sys_class_init, 1694 }; 1695 1696 static void stellaris_register_types(void) 1697 { 1698 type_register_static(&stellaris_i2c_info); 1699 type_register_static(&stellaris_gptm_info); 1700 type_register_static(&stellaris_adc_info); 1701 type_register_static(&stellaris_sys_info); 1702 } 1703 1704 type_init(stellaris_register_types) 1705