1 /* 2 * ARM SBSA Reference Platform emulation 3 * 4 * Copyright (c) 2018 Linaro Limited 5 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 6 * Written by Hongbo Zhang <hongbo.zhang@linaro.org> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2 or later, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/datadir.h" 23 #include "qapi/error.h" 24 #include "qemu/error-report.h" 25 #include "qemu/units.h" 26 #include "sysemu/device_tree.h" 27 #include "sysemu/kvm.h" 28 #include "sysemu/numa.h" 29 #include "sysemu/runstate.h" 30 #include "sysemu/sysemu.h" 31 #include "exec/hwaddr.h" 32 #include "kvm_arm.h" 33 #include "hw/arm/boot.h" 34 #include "hw/arm/bsa.h" 35 #include "hw/arm/fdt.h" 36 #include "hw/arm/smmuv3.h" 37 #include "hw/block/flash.h" 38 #include "hw/boards.h" 39 #include "hw/ide/internal.h" 40 #include "hw/ide/ahci_internal.h" 41 #include "hw/intc/arm_gicv3_common.h" 42 #include "hw/intc/arm_gicv3_its_common.h" 43 #include "hw/loader.h" 44 #include "hw/pci-host/gpex.h" 45 #include "hw/qdev-properties.h" 46 #include "hw/usb.h" 47 #include "hw/usb/xhci.h" 48 #include "hw/char/pl011.h" 49 #include "hw/watchdog/sbsa_gwdt.h" 50 #include "net/net.h" 51 #include "qapi/qmp/qlist.h" 52 #include "qom/object.h" 53 #include "target/arm/cpu-qom.h" 54 55 #define RAMLIMIT_GB 8192 56 #define RAMLIMIT_BYTES (RAMLIMIT_GB * GiB) 57 58 #define NUM_IRQS 256 59 #define NUM_SMMU_IRQS 4 60 #define NUM_SATA_PORTS 6 61 62 enum { 63 SBSA_FLASH, 64 SBSA_MEM, 65 SBSA_CPUPERIPHS, 66 SBSA_GIC_DIST, 67 SBSA_GIC_REDIST, 68 SBSA_GIC_ITS, 69 SBSA_SECURE_EC, 70 SBSA_GWDT_WS0, 71 SBSA_GWDT_REFRESH, 72 SBSA_GWDT_CONTROL, 73 SBSA_SMMU, 74 SBSA_UART, 75 SBSA_RTC, 76 SBSA_PCIE, 77 SBSA_PCIE_MMIO, 78 SBSA_PCIE_MMIO_HIGH, 79 SBSA_PCIE_PIO, 80 SBSA_PCIE_ECAM, 81 SBSA_GPIO, 82 SBSA_SECURE_UART, 83 SBSA_SECURE_UART_MM, 84 SBSA_SECURE_MEM, 85 SBSA_AHCI, 86 SBSA_XHCI, 87 }; 88 89 struct SBSAMachineState { 90 MachineState parent; 91 struct arm_boot_info bootinfo; 92 int smp_cpus; 93 void *fdt; 94 int fdt_size; 95 int psci_conduit; 96 DeviceState *gic; 97 PFlashCFI01 *flash[2]; 98 }; 99 100 #define TYPE_SBSA_MACHINE MACHINE_TYPE_NAME("sbsa-ref") 101 OBJECT_DECLARE_SIMPLE_TYPE(SBSAMachineState, SBSA_MACHINE) 102 103 static const MemMapEntry sbsa_ref_memmap[] = { 104 /* 512M boot ROM */ 105 [SBSA_FLASH] = { 0, 0x20000000 }, 106 /* 512M secure memory */ 107 [SBSA_SECURE_MEM] = { 0x20000000, 0x20000000 }, 108 /* Space reserved for CPU peripheral devices */ 109 [SBSA_CPUPERIPHS] = { 0x40000000, 0x00040000 }, 110 [SBSA_GIC_DIST] = { 0x40060000, 0x00010000 }, 111 [SBSA_GIC_REDIST] = { 0x40080000, 0x04000000 }, 112 [SBSA_GIC_ITS] = { 0x44081000, 0x00020000 }, 113 [SBSA_SECURE_EC] = { 0x50000000, 0x00001000 }, 114 [SBSA_GWDT_REFRESH] = { 0x50010000, 0x00001000 }, 115 [SBSA_GWDT_CONTROL] = { 0x50011000, 0x00001000 }, 116 [SBSA_UART] = { 0x60000000, 0x00001000 }, 117 [SBSA_RTC] = { 0x60010000, 0x00001000 }, 118 [SBSA_GPIO] = { 0x60020000, 0x00001000 }, 119 [SBSA_SECURE_UART] = { 0x60030000, 0x00001000 }, 120 [SBSA_SECURE_UART_MM] = { 0x60040000, 0x00001000 }, 121 [SBSA_SMMU] = { 0x60050000, 0x00020000 }, 122 /* Space here reserved for more SMMUs */ 123 [SBSA_AHCI] = { 0x60100000, 0x00010000 }, 124 [SBSA_XHCI] = { 0x60110000, 0x00010000 }, 125 /* Space here reserved for other devices */ 126 [SBSA_PCIE_PIO] = { 0x7fff0000, 0x00010000 }, 127 /* 32-bit address PCIE MMIO space */ 128 [SBSA_PCIE_MMIO] = { 0x80000000, 0x70000000 }, 129 /* 256M PCIE ECAM space */ 130 [SBSA_PCIE_ECAM] = { 0xf0000000, 0x10000000 }, 131 /* ~1TB PCIE MMIO space (4GB to 1024GB boundary) */ 132 [SBSA_PCIE_MMIO_HIGH] = { 0x100000000ULL, 0xFF00000000ULL }, 133 [SBSA_MEM] = { 0x10000000000ULL, RAMLIMIT_BYTES }, 134 }; 135 136 static const int sbsa_ref_irqmap[] = { 137 [SBSA_UART] = 1, 138 [SBSA_RTC] = 2, 139 [SBSA_PCIE] = 3, /* ... to 6 */ 140 [SBSA_GPIO] = 7, 141 [SBSA_SECURE_UART] = 8, 142 [SBSA_SECURE_UART_MM] = 9, 143 [SBSA_AHCI] = 10, 144 [SBSA_XHCI] = 11, 145 [SBSA_SMMU] = 12, /* ... to 15 */ 146 [SBSA_GWDT_WS0] = 16, 147 }; 148 149 static uint64_t sbsa_ref_cpu_mp_affinity(SBSAMachineState *sms, int idx) 150 { 151 uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER; 152 return arm_build_mp_affinity(idx, clustersz); 153 } 154 155 static void sbsa_fdt_add_gic_node(SBSAMachineState *sms) 156 { 157 char *nodename; 158 159 nodename = g_strdup_printf("/intc"); 160 qemu_fdt_add_subnode(sms->fdt, nodename); 161 qemu_fdt_setprop_sized_cells(sms->fdt, nodename, "reg", 162 2, sbsa_ref_memmap[SBSA_GIC_DIST].base, 163 2, sbsa_ref_memmap[SBSA_GIC_DIST].size, 164 2, sbsa_ref_memmap[SBSA_GIC_REDIST].base, 165 2, sbsa_ref_memmap[SBSA_GIC_REDIST].size); 166 167 nodename = g_strdup_printf("/intc/its"); 168 qemu_fdt_add_subnode(sms->fdt, nodename); 169 qemu_fdt_setprop_sized_cells(sms->fdt, nodename, "reg", 170 2, sbsa_ref_memmap[SBSA_GIC_ITS].base, 171 2, sbsa_ref_memmap[SBSA_GIC_ITS].size); 172 173 g_free(nodename); 174 } 175 176 /* 177 * Firmware on this machine only uses ACPI table to load OS, these limited 178 * device tree nodes are just to let firmware know the info which varies from 179 * command line parameters, so it is not necessary to be fully compatible 180 * with the kernel CPU and NUMA binding rules. 181 */ 182 static void create_fdt(SBSAMachineState *sms) 183 { 184 void *fdt = create_device_tree(&sms->fdt_size); 185 const MachineState *ms = MACHINE(sms); 186 int nb_numa_nodes = ms->numa_state->num_nodes; 187 int cpu; 188 189 if (!fdt) { 190 error_report("create_device_tree() failed"); 191 exit(1); 192 } 193 194 sms->fdt = fdt; 195 196 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,sbsa-ref"); 197 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 198 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 199 200 /* 201 * This versioning scheme is for informing platform fw only. It is neither: 202 * - A QEMU versioned machine type; a given version of QEMU will emulate 203 * a given version of the platform. 204 * - A reflection of level of SBSA (now SystemReady SR) support provided. 205 * 206 * machine-version-major: updated when changes breaking fw compatibility 207 * are introduced. 208 * machine-version-minor: updated when features are added that don't break 209 * fw compatibility. 210 */ 211 qemu_fdt_setprop_cell(fdt, "/", "machine-version-major", 0); 212 qemu_fdt_setprop_cell(fdt, "/", "machine-version-minor", 3); 213 214 if (ms->numa_state->have_numa_distance) { 215 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); 216 uint32_t *matrix = g_malloc0(size); 217 int idx, i, j; 218 219 for (i = 0; i < nb_numa_nodes; i++) { 220 for (j = 0; j < nb_numa_nodes; j++) { 221 idx = (i * nb_numa_nodes + j) * 3; 222 matrix[idx + 0] = cpu_to_be32(i); 223 matrix[idx + 1] = cpu_to_be32(j); 224 matrix[idx + 2] = 225 cpu_to_be32(ms->numa_state->nodes[i].distance[j]); 226 } 227 } 228 229 qemu_fdt_add_subnode(fdt, "/distance-map"); 230 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", 231 matrix, size); 232 g_free(matrix); 233 } 234 235 /* 236 * From Documentation/devicetree/bindings/arm/cpus.yaml 237 * On ARM v8 64-bit systems this property is required 238 * and matches the MPIDR_EL1 register affinity bits. 239 * 240 * * If cpus node's #address-cells property is set to 2 241 * 242 * The first reg cell bits [7:0] must be set to 243 * bits [39:32] of MPIDR_EL1. 244 * 245 * The second reg cell bits [23:0] must be set to 246 * bits [23:0] of MPIDR_EL1. 247 */ 248 qemu_fdt_add_subnode(sms->fdt, "/cpus"); 249 qemu_fdt_setprop_cell(sms->fdt, "/cpus", "#address-cells", 2); 250 qemu_fdt_setprop_cell(sms->fdt, "/cpus", "#size-cells", 0x0); 251 252 for (cpu = sms->smp_cpus - 1; cpu >= 0; cpu--) { 253 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 254 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 255 CPUState *cs = CPU(armcpu); 256 uint64_t mpidr = sbsa_ref_cpu_mp_affinity(sms, cpu); 257 258 qemu_fdt_add_subnode(sms->fdt, nodename); 259 qemu_fdt_setprop_u64(sms->fdt, nodename, "reg", mpidr); 260 261 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { 262 qemu_fdt_setprop_cell(sms->fdt, nodename, "numa-node-id", 263 ms->possible_cpus->cpus[cs->cpu_index].props.node_id); 264 } 265 266 g_free(nodename); 267 } 268 269 sbsa_fdt_add_gic_node(sms); 270 } 271 272 #define SBSA_FLASH_SECTOR_SIZE (256 * KiB) 273 274 static PFlashCFI01 *sbsa_flash_create1(SBSAMachineState *sms, 275 const char *name, 276 const char *alias_prop_name) 277 { 278 /* 279 * Create a single flash device. We use the same parameters as 280 * the flash devices on the Versatile Express board. 281 */ 282 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 283 284 qdev_prop_set_uint64(dev, "sector-length", SBSA_FLASH_SECTOR_SIZE); 285 qdev_prop_set_uint8(dev, "width", 4); 286 qdev_prop_set_uint8(dev, "device-width", 2); 287 qdev_prop_set_bit(dev, "big-endian", false); 288 qdev_prop_set_uint16(dev, "id0", 0x89); 289 qdev_prop_set_uint16(dev, "id1", 0x18); 290 qdev_prop_set_uint16(dev, "id2", 0x00); 291 qdev_prop_set_uint16(dev, "id3", 0x00); 292 qdev_prop_set_string(dev, "name", name); 293 object_property_add_child(OBJECT(sms), name, OBJECT(dev)); 294 object_property_add_alias(OBJECT(sms), alias_prop_name, 295 OBJECT(dev), "drive"); 296 return PFLASH_CFI01(dev); 297 } 298 299 static void sbsa_flash_create(SBSAMachineState *sms) 300 { 301 sms->flash[0] = sbsa_flash_create1(sms, "sbsa.flash0", "pflash0"); 302 sms->flash[1] = sbsa_flash_create1(sms, "sbsa.flash1", "pflash1"); 303 } 304 305 static void sbsa_flash_map1(PFlashCFI01 *flash, 306 hwaddr base, hwaddr size, 307 MemoryRegion *sysmem) 308 { 309 DeviceState *dev = DEVICE(flash); 310 311 assert(QEMU_IS_ALIGNED(size, SBSA_FLASH_SECTOR_SIZE)); 312 assert(size / SBSA_FLASH_SECTOR_SIZE <= UINT32_MAX); 313 qdev_prop_set_uint32(dev, "num-blocks", size / SBSA_FLASH_SECTOR_SIZE); 314 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 315 316 memory_region_add_subregion(sysmem, base, 317 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 318 0)); 319 } 320 321 static void sbsa_flash_map(SBSAMachineState *sms, 322 MemoryRegion *sysmem, 323 MemoryRegion *secure_sysmem) 324 { 325 /* 326 * Map two flash devices to fill the SBSA_FLASH space in the memmap. 327 * sysmem is the system memory space. secure_sysmem is the secure view 328 * of the system, and the first flash device should be made visible only 329 * there. The second flash device is visible to both secure and nonsecure. 330 */ 331 hwaddr flashsize = sbsa_ref_memmap[SBSA_FLASH].size / 2; 332 hwaddr flashbase = sbsa_ref_memmap[SBSA_FLASH].base; 333 334 sbsa_flash_map1(sms->flash[0], flashbase, flashsize, 335 secure_sysmem); 336 sbsa_flash_map1(sms->flash[1], flashbase + flashsize, flashsize, 337 sysmem); 338 } 339 340 static bool sbsa_firmware_init(SBSAMachineState *sms, 341 MemoryRegion *sysmem, 342 MemoryRegion *secure_sysmem) 343 { 344 const char *bios_name; 345 int i; 346 BlockBackend *pflash_blk0; 347 348 /* Map legacy -drive if=pflash to machine properties */ 349 for (i = 0; i < ARRAY_SIZE(sms->flash); i++) { 350 pflash_cfi01_legacy_drive(sms->flash[i], 351 drive_get(IF_PFLASH, 0, i)); 352 } 353 354 sbsa_flash_map(sms, sysmem, secure_sysmem); 355 356 pflash_blk0 = pflash_cfi01_get_blk(sms->flash[0]); 357 358 bios_name = MACHINE(sms)->firmware; 359 if (bios_name) { 360 char *fname; 361 MemoryRegion *mr; 362 int image_size; 363 364 if (pflash_blk0) { 365 error_report("The contents of the first flash device may be " 366 "specified with -bios or with -drive if=pflash... " 367 "but you cannot use both options at once"); 368 exit(1); 369 } 370 371 /* Fall back to -bios */ 372 373 fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 374 if (!fname) { 375 error_report("Could not find ROM image '%s'", bios_name); 376 exit(1); 377 } 378 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(sms->flash[0]), 0); 379 image_size = load_image_mr(fname, mr); 380 g_free(fname); 381 if (image_size < 0) { 382 error_report("Could not load ROM image '%s'", bios_name); 383 exit(1); 384 } 385 } 386 387 return pflash_blk0 || bios_name; 388 } 389 390 static void create_secure_ram(SBSAMachineState *sms, 391 MemoryRegion *secure_sysmem) 392 { 393 MemoryRegion *secram = g_new(MemoryRegion, 1); 394 hwaddr base = sbsa_ref_memmap[SBSA_SECURE_MEM].base; 395 hwaddr size = sbsa_ref_memmap[SBSA_SECURE_MEM].size; 396 397 memory_region_init_ram(secram, NULL, "sbsa-ref.secure-ram", size, 398 &error_fatal); 399 memory_region_add_subregion(secure_sysmem, base, secram); 400 } 401 402 static void create_its(SBSAMachineState *sms) 403 { 404 const char *itsclass = its_class_name(); 405 DeviceState *dev; 406 407 dev = qdev_new(itsclass); 408 409 object_property_set_link(OBJECT(dev), "parent-gicv3", OBJECT(sms->gic), 410 &error_abort); 411 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 412 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, sbsa_ref_memmap[SBSA_GIC_ITS].base); 413 } 414 415 static void create_gic(SBSAMachineState *sms, MemoryRegion *mem) 416 { 417 unsigned int smp_cpus = MACHINE(sms)->smp.cpus; 418 SysBusDevice *gicbusdev; 419 const char *gictype; 420 uint32_t redist0_capacity, redist0_count; 421 QList *redist_region_count; 422 int i; 423 424 gictype = gicv3_class_name(); 425 426 sms->gic = qdev_new(gictype); 427 qdev_prop_set_uint32(sms->gic, "revision", 3); 428 qdev_prop_set_uint32(sms->gic, "num-cpu", smp_cpus); 429 /* 430 * Note that the num-irq property counts both internal and external 431 * interrupts; there are always 32 of the former (mandated by GIC spec). 432 */ 433 qdev_prop_set_uint32(sms->gic, "num-irq", NUM_IRQS + 32); 434 qdev_prop_set_bit(sms->gic, "has-security-extensions", true); 435 436 redist0_capacity = 437 sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE; 438 redist0_count = MIN(smp_cpus, redist0_capacity); 439 440 redist_region_count = qlist_new(); 441 qlist_append_int(redist_region_count, redist0_count); 442 qdev_prop_set_array(sms->gic, "redist-region-count", redist_region_count); 443 444 object_property_set_link(OBJECT(sms->gic), "sysmem", 445 OBJECT(mem), &error_fatal); 446 qdev_prop_set_bit(sms->gic, "has-lpi", true); 447 448 gicbusdev = SYS_BUS_DEVICE(sms->gic); 449 sysbus_realize_and_unref(gicbusdev, &error_fatal); 450 sysbus_mmio_map(gicbusdev, 0, sbsa_ref_memmap[SBSA_GIC_DIST].base); 451 sysbus_mmio_map(gicbusdev, 1, sbsa_ref_memmap[SBSA_GIC_REDIST].base); 452 453 /* 454 * Wire the outputs from each CPU's generic timer and the GICv3 455 * maintenance interrupt signal to the appropriate GIC PPI inputs, 456 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. 457 */ 458 for (i = 0; i < smp_cpus; i++) { 459 DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); 460 int intidbase = NUM_IRQS + i * GIC_INTERNAL; 461 int irq; 462 /* 463 * Mapping from the output timer irq lines from the CPU to the 464 * GIC PPI inputs used for this board. 465 */ 466 const int timer_irq[] = { 467 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 468 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 469 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 470 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 471 [GTIMER_HYPVIRT] = ARCH_TIMER_NS_EL2_VIRT_IRQ, 472 }; 473 474 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { 475 qdev_connect_gpio_out(cpudev, irq, 476 qdev_get_gpio_in(sms->gic, 477 intidbase + timer_irq[irq])); 478 } 479 480 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0, 481 qdev_get_gpio_in(sms->gic, 482 intidbase 483 + ARCH_GIC_MAINT_IRQ)); 484 485 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, 486 qdev_get_gpio_in(sms->gic, 487 intidbase 488 + VIRTUAL_PMU_IRQ)); 489 490 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 491 sysbus_connect_irq(gicbusdev, i + smp_cpus, 492 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 493 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus, 494 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 495 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, 496 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 497 } 498 create_its(sms); 499 } 500 501 static void create_uart(const SBSAMachineState *sms, int uart, 502 MemoryRegion *mem, Chardev *chr) 503 { 504 hwaddr base = sbsa_ref_memmap[uart].base; 505 int irq = sbsa_ref_irqmap[uart]; 506 DeviceState *dev = qdev_new(TYPE_PL011); 507 SysBusDevice *s = SYS_BUS_DEVICE(dev); 508 509 qdev_prop_set_chr(dev, "chardev", chr); 510 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 511 memory_region_add_subregion(mem, base, 512 sysbus_mmio_get_region(s, 0)); 513 sysbus_connect_irq(s, 0, qdev_get_gpio_in(sms->gic, irq)); 514 } 515 516 static void create_rtc(const SBSAMachineState *sms) 517 { 518 hwaddr base = sbsa_ref_memmap[SBSA_RTC].base; 519 int irq = sbsa_ref_irqmap[SBSA_RTC]; 520 521 sysbus_create_simple("pl031", base, qdev_get_gpio_in(sms->gic, irq)); 522 } 523 524 static void create_wdt(const SBSAMachineState *sms) 525 { 526 hwaddr rbase = sbsa_ref_memmap[SBSA_GWDT_REFRESH].base; 527 hwaddr cbase = sbsa_ref_memmap[SBSA_GWDT_CONTROL].base; 528 DeviceState *dev = qdev_new(TYPE_WDT_SBSA); 529 SysBusDevice *s = SYS_BUS_DEVICE(dev); 530 int irq = sbsa_ref_irqmap[SBSA_GWDT_WS0]; 531 532 sysbus_realize_and_unref(s, &error_fatal); 533 sysbus_mmio_map(s, 0, rbase); 534 sysbus_mmio_map(s, 1, cbase); 535 sysbus_connect_irq(s, 0, qdev_get_gpio_in(sms->gic, irq)); 536 } 537 538 static DeviceState *gpio_key_dev; 539 static void sbsa_ref_powerdown_req(Notifier *n, void *opaque) 540 { 541 /* use gpio Pin 3 for power button event */ 542 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); 543 } 544 545 static Notifier sbsa_ref_powerdown_notifier = { 546 .notify = sbsa_ref_powerdown_req 547 }; 548 549 static void create_gpio(const SBSAMachineState *sms) 550 { 551 DeviceState *pl061_dev; 552 hwaddr base = sbsa_ref_memmap[SBSA_GPIO].base; 553 int irq = sbsa_ref_irqmap[SBSA_GPIO]; 554 555 pl061_dev = sysbus_create_simple("pl061", base, 556 qdev_get_gpio_in(sms->gic, irq)); 557 558 gpio_key_dev = sysbus_create_simple("gpio-key", -1, 559 qdev_get_gpio_in(pl061_dev, 3)); 560 561 /* connect powerdown request */ 562 qemu_register_powerdown_notifier(&sbsa_ref_powerdown_notifier); 563 } 564 565 static void create_ahci(const SBSAMachineState *sms) 566 { 567 hwaddr base = sbsa_ref_memmap[SBSA_AHCI].base; 568 int irq = sbsa_ref_irqmap[SBSA_AHCI]; 569 DeviceState *dev; 570 DriveInfo *hd[NUM_SATA_PORTS]; 571 SysbusAHCIState *sysahci; 572 AHCIState *ahci; 573 int i; 574 575 dev = qdev_new("sysbus-ahci"); 576 qdev_prop_set_uint32(dev, "num-ports", NUM_SATA_PORTS); 577 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 578 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 579 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(sms->gic, irq)); 580 581 sysahci = SYSBUS_AHCI(dev); 582 ahci = &sysahci->ahci; 583 ide_drive_get(hd, ARRAY_SIZE(hd)); 584 for (i = 0; i < ahci->ports; i++) { 585 if (hd[i] == NULL) { 586 continue; 587 } 588 ide_bus_create_drive(&ahci->dev[i].port, 0, hd[i]); 589 } 590 } 591 592 static void create_xhci(const SBSAMachineState *sms) 593 { 594 hwaddr base = sbsa_ref_memmap[SBSA_XHCI].base; 595 int irq = sbsa_ref_irqmap[SBSA_XHCI]; 596 DeviceState *dev = qdev_new(TYPE_XHCI_SYSBUS); 597 qdev_prop_set_uint32(dev, "slots", XHCI_MAXSLOTS); 598 599 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 600 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 601 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(sms->gic, irq)); 602 } 603 604 static void create_smmu(const SBSAMachineState *sms, PCIBus *bus) 605 { 606 hwaddr base = sbsa_ref_memmap[SBSA_SMMU].base; 607 int irq = sbsa_ref_irqmap[SBSA_SMMU]; 608 DeviceState *dev; 609 int i; 610 611 dev = qdev_new(TYPE_ARM_SMMUV3); 612 613 object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus), 614 &error_abort); 615 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 616 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 617 for (i = 0; i < NUM_SMMU_IRQS; i++) { 618 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 619 qdev_get_gpio_in(sms->gic, irq + i)); 620 } 621 } 622 623 static void create_pcie(SBSAMachineState *sms) 624 { 625 hwaddr base_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].base; 626 hwaddr size_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].size; 627 hwaddr base_mmio = sbsa_ref_memmap[SBSA_PCIE_MMIO].base; 628 hwaddr size_mmio = sbsa_ref_memmap[SBSA_PCIE_MMIO].size; 629 hwaddr base_mmio_high = sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].base; 630 hwaddr size_mmio_high = sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].size; 631 hwaddr base_pio = sbsa_ref_memmap[SBSA_PCIE_PIO].base; 632 int irq = sbsa_ref_irqmap[SBSA_PCIE]; 633 MachineClass *mc = MACHINE_GET_CLASS(sms); 634 MemoryRegion *mmio_alias, *mmio_alias_high, *mmio_reg; 635 MemoryRegion *ecam_alias, *ecam_reg; 636 DeviceState *dev; 637 PCIHostState *pci; 638 int i; 639 640 dev = qdev_new(TYPE_GPEX_HOST); 641 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 642 643 /* Map ECAM space */ 644 ecam_alias = g_new0(MemoryRegion, 1); 645 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 646 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 647 ecam_reg, 0, size_ecam); 648 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias); 649 650 /* Map the MMIO space */ 651 mmio_alias = g_new0(MemoryRegion, 1); 652 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 653 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 654 mmio_reg, base_mmio, size_mmio); 655 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); 656 657 /* Map the MMIO_HIGH space */ 658 mmio_alias_high = g_new0(MemoryRegion, 1); 659 memory_region_init_alias(mmio_alias_high, OBJECT(dev), "pcie-mmio-high", 660 mmio_reg, base_mmio_high, size_mmio_high); 661 memory_region_add_subregion(get_system_memory(), base_mmio_high, 662 mmio_alias_high); 663 664 /* Map IO port space */ 665 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); 666 667 for (i = 0; i < GPEX_NUM_IRQS; i++) { 668 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 669 qdev_get_gpio_in(sms->gic, irq + i)); 670 gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); 671 } 672 673 pci = PCI_HOST_BRIDGE(dev); 674 if (pci->bus) { 675 for (i = 0; i < nb_nics; i++) { 676 pci_nic_init_nofail(&nd_table[i], pci->bus, mc->default_nic, NULL); 677 } 678 } 679 680 pci_create_simple(pci->bus, -1, "bochs-display"); 681 682 create_smmu(sms, pci->bus); 683 } 684 685 static void *sbsa_ref_dtb(const struct arm_boot_info *binfo, int *fdt_size) 686 { 687 const SBSAMachineState *board = container_of(binfo, SBSAMachineState, 688 bootinfo); 689 690 *fdt_size = board->fdt_size; 691 return board->fdt; 692 } 693 694 static void create_secure_ec(MemoryRegion *mem) 695 { 696 hwaddr base = sbsa_ref_memmap[SBSA_SECURE_EC].base; 697 DeviceState *dev = qdev_new("sbsa-ec"); 698 SysBusDevice *s = SYS_BUS_DEVICE(dev); 699 700 memory_region_add_subregion(mem, base, 701 sysbus_mmio_get_region(s, 0)); 702 } 703 704 static void sbsa_ref_init(MachineState *machine) 705 { 706 unsigned int smp_cpus = machine->smp.cpus; 707 unsigned int max_cpus = machine->smp.max_cpus; 708 SBSAMachineState *sms = SBSA_MACHINE(machine); 709 MachineClass *mc = MACHINE_GET_CLASS(machine); 710 MemoryRegion *sysmem = get_system_memory(); 711 MemoryRegion *secure_sysmem = g_new(MemoryRegion, 1); 712 bool firmware_loaded; 713 const CPUArchIdList *possible_cpus; 714 int n, sbsa_max_cpus; 715 716 if (kvm_enabled()) { 717 error_report("sbsa-ref: KVM is not supported for this machine"); 718 exit(1); 719 } 720 721 /* 722 * The Secure view of the world is the same as the NonSecure, 723 * but with a few extra devices. Create it as a container region 724 * containing the system memory at low priority; any secure-only 725 * devices go in at higher priority and take precedence. 726 */ 727 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", 728 UINT64_MAX); 729 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); 730 731 firmware_loaded = sbsa_firmware_init(sms, sysmem, secure_sysmem); 732 733 /* 734 * This machine has EL3 enabled, external firmware should supply PSCI 735 * implementation, so the QEMU's internal PSCI is disabled. 736 */ 737 sms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; 738 739 sbsa_max_cpus = sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE; 740 741 if (max_cpus > sbsa_max_cpus) { 742 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " 743 "supported by machine 'sbsa-ref' (%d)", 744 max_cpus, sbsa_max_cpus); 745 exit(1); 746 } 747 748 sms->smp_cpus = smp_cpus; 749 750 if (machine->ram_size > sbsa_ref_memmap[SBSA_MEM].size) { 751 error_report("sbsa-ref: cannot model more than %dGB RAM", RAMLIMIT_GB); 752 exit(1); 753 } 754 755 possible_cpus = mc->possible_cpu_arch_ids(machine); 756 for (n = 0; n < possible_cpus->len; n++) { 757 Object *cpuobj; 758 CPUState *cs; 759 760 if (n >= smp_cpus) { 761 break; 762 } 763 764 cpuobj = object_new(possible_cpus->cpus[n].type); 765 object_property_set_int(cpuobj, "mp-affinity", 766 possible_cpus->cpus[n].arch_id, NULL); 767 768 cs = CPU(cpuobj); 769 cs->cpu_index = n; 770 771 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj), 772 &error_fatal); 773 774 if (object_property_find(cpuobj, "reset-cbar")) { 775 object_property_set_int(cpuobj, "reset-cbar", 776 sbsa_ref_memmap[SBSA_CPUPERIPHS].base, 777 &error_abort); 778 } 779 780 object_property_set_link(cpuobj, "memory", OBJECT(sysmem), 781 &error_abort); 782 783 object_property_set_link(cpuobj, "secure-memory", 784 OBJECT(secure_sysmem), &error_abort); 785 786 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); 787 object_unref(cpuobj); 788 } 789 790 memory_region_add_subregion(sysmem, sbsa_ref_memmap[SBSA_MEM].base, 791 machine->ram); 792 793 create_fdt(sms); 794 795 create_secure_ram(sms, secure_sysmem); 796 797 create_gic(sms, sysmem); 798 799 create_uart(sms, SBSA_UART, sysmem, serial_hd(0)); 800 create_uart(sms, SBSA_SECURE_UART, secure_sysmem, serial_hd(1)); 801 /* Second secure UART for RAS and MM from EL0 */ 802 create_uart(sms, SBSA_SECURE_UART_MM, secure_sysmem, serial_hd(2)); 803 804 create_rtc(sms); 805 806 create_wdt(sms); 807 808 create_gpio(sms); 809 810 create_ahci(sms); 811 812 create_xhci(sms); 813 814 create_pcie(sms); 815 816 create_secure_ec(secure_sysmem); 817 818 sms->bootinfo.ram_size = machine->ram_size; 819 sms->bootinfo.board_id = -1; 820 sms->bootinfo.loader_start = sbsa_ref_memmap[SBSA_MEM].base; 821 sms->bootinfo.get_dtb = sbsa_ref_dtb; 822 sms->bootinfo.firmware_loaded = firmware_loaded; 823 arm_load_kernel(ARM_CPU(first_cpu), machine, &sms->bootinfo); 824 } 825 826 static const CPUArchIdList *sbsa_ref_possible_cpu_arch_ids(MachineState *ms) 827 { 828 unsigned int max_cpus = ms->smp.max_cpus; 829 SBSAMachineState *sms = SBSA_MACHINE(ms); 830 int n; 831 832 if (ms->possible_cpus) { 833 assert(ms->possible_cpus->len == max_cpus); 834 return ms->possible_cpus; 835 } 836 837 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 838 sizeof(CPUArchId) * max_cpus); 839 ms->possible_cpus->len = max_cpus; 840 for (n = 0; n < ms->possible_cpus->len; n++) { 841 ms->possible_cpus->cpus[n].type = ms->cpu_type; 842 ms->possible_cpus->cpus[n].arch_id = 843 sbsa_ref_cpu_mp_affinity(sms, n); 844 ms->possible_cpus->cpus[n].props.has_thread_id = true; 845 ms->possible_cpus->cpus[n].props.thread_id = n; 846 } 847 return ms->possible_cpus; 848 } 849 850 static CpuInstanceProperties 851 sbsa_ref_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 852 { 853 MachineClass *mc = MACHINE_GET_CLASS(ms); 854 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 855 856 assert(cpu_index < possible_cpus->len); 857 return possible_cpus->cpus[cpu_index].props; 858 } 859 860 static int64_t 861 sbsa_ref_get_default_cpu_node_id(const MachineState *ms, int idx) 862 { 863 return idx % ms->numa_state->num_nodes; 864 } 865 866 static void sbsa_ref_instance_init(Object *obj) 867 { 868 SBSAMachineState *sms = SBSA_MACHINE(obj); 869 870 sbsa_flash_create(sms); 871 } 872 873 static void sbsa_ref_class_init(ObjectClass *oc, void *data) 874 { 875 MachineClass *mc = MACHINE_CLASS(oc); 876 static const char * const valid_cpu_types[] = { 877 ARM_CPU_TYPE_NAME("cortex-a57"), 878 ARM_CPU_TYPE_NAME("cortex-a72"), 879 ARM_CPU_TYPE_NAME("neoverse-n1"), 880 ARM_CPU_TYPE_NAME("neoverse-v1"), 881 ARM_CPU_TYPE_NAME("neoverse-n2"), 882 ARM_CPU_TYPE_NAME("max"), 883 NULL, 884 }; 885 886 mc->init = sbsa_ref_init; 887 mc->desc = "QEMU 'SBSA Reference' ARM Virtual Machine"; 888 mc->default_cpu_type = ARM_CPU_TYPE_NAME("neoverse-n1"); 889 mc->valid_cpu_types = valid_cpu_types; 890 mc->max_cpus = 512; 891 mc->pci_allow_0_address = true; 892 mc->minimum_page_bits = 12; 893 mc->block_default_type = IF_IDE; 894 mc->no_cdrom = 1; 895 mc->default_nic = "e1000e"; 896 mc->default_ram_size = 1 * GiB; 897 mc->default_ram_id = "sbsa-ref.ram"; 898 mc->default_cpus = 4; 899 mc->possible_cpu_arch_ids = sbsa_ref_possible_cpu_arch_ids; 900 mc->cpu_index_to_instance_props = sbsa_ref_cpu_index_to_props; 901 mc->get_default_cpu_node_id = sbsa_ref_get_default_cpu_node_id; 902 /* platform instead of architectural choice */ 903 mc->cpu_cluster_has_numa_boundary = true; 904 } 905 906 static const TypeInfo sbsa_ref_info = { 907 .name = TYPE_SBSA_MACHINE, 908 .parent = TYPE_MACHINE, 909 .instance_init = sbsa_ref_instance_init, 910 .class_init = sbsa_ref_class_init, 911 .instance_size = sizeof(SBSAMachineState), 912 }; 913 914 static void sbsa_ref_machine_init(void) 915 { 916 type_register_static(&sbsa_ref_info); 917 } 918 919 type_init(sbsa_ref_machine_init); 920