1 /* 2 * ARM SBSA Reference Platform emulation 3 * 4 * Copyright (c) 2018 Linaro Limited 5 * Written by Hongbo Zhang <hongbo.zhang@linaro.org> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu-common.h" 22 #include "qapi/error.h" 23 #include "qemu/error-report.h" 24 #include "qemu/units.h" 25 #include "sysemu/device_tree.h" 26 #include "sysemu/numa.h" 27 #include "sysemu/runstate.h" 28 #include "sysemu/sysemu.h" 29 #include "exec/address-spaces.h" 30 #include "exec/hwaddr.h" 31 #include "kvm_arm.h" 32 #include "hw/arm/boot.h" 33 #include "hw/block/flash.h" 34 #include "hw/boards.h" 35 #include "hw/ide/internal.h" 36 #include "hw/ide/ahci_internal.h" 37 #include "hw/intc/arm_gicv3_common.h" 38 #include "hw/loader.h" 39 #include "hw/pci-host/gpex.h" 40 #include "hw/qdev-properties.h" 41 #include "hw/usb.h" 42 #include "net/net.h" 43 44 #define RAMLIMIT_GB 8192 45 #define RAMLIMIT_BYTES (RAMLIMIT_GB * GiB) 46 47 #define NUM_IRQS 256 48 #define NUM_SMMU_IRQS 4 49 #define NUM_SATA_PORTS 6 50 51 #define VIRTUAL_PMU_IRQ 7 52 #define ARCH_GIC_MAINT_IRQ 9 53 #define ARCH_TIMER_VIRT_IRQ 11 54 #define ARCH_TIMER_S_EL1_IRQ 13 55 #define ARCH_TIMER_NS_EL1_IRQ 14 56 #define ARCH_TIMER_NS_EL2_IRQ 10 57 58 enum { 59 SBSA_FLASH, 60 SBSA_MEM, 61 SBSA_CPUPERIPHS, 62 SBSA_GIC_DIST, 63 SBSA_GIC_REDIST, 64 SBSA_SMMU, 65 SBSA_UART, 66 SBSA_RTC, 67 SBSA_PCIE, 68 SBSA_PCIE_MMIO, 69 SBSA_PCIE_MMIO_HIGH, 70 SBSA_PCIE_PIO, 71 SBSA_PCIE_ECAM, 72 SBSA_GPIO, 73 SBSA_SECURE_UART, 74 SBSA_SECURE_UART_MM, 75 SBSA_SECURE_MEM, 76 SBSA_AHCI, 77 SBSA_EHCI, 78 }; 79 80 typedef struct MemMapEntry { 81 hwaddr base; 82 hwaddr size; 83 } MemMapEntry; 84 85 typedef struct { 86 MachineState parent; 87 struct arm_boot_info bootinfo; 88 int smp_cpus; 89 void *fdt; 90 int fdt_size; 91 int psci_conduit; 92 PFlashCFI01 *flash[2]; 93 } SBSAMachineState; 94 95 #define TYPE_SBSA_MACHINE MACHINE_TYPE_NAME("sbsa-ref") 96 #define SBSA_MACHINE(obj) \ 97 OBJECT_CHECK(SBSAMachineState, (obj), TYPE_SBSA_MACHINE) 98 99 static const MemMapEntry sbsa_ref_memmap[] = { 100 /* 512M boot ROM */ 101 [SBSA_FLASH] = { 0, 0x20000000 }, 102 /* 512M secure memory */ 103 [SBSA_SECURE_MEM] = { 0x20000000, 0x20000000 }, 104 /* Space reserved for CPU peripheral devices */ 105 [SBSA_CPUPERIPHS] = { 0x40000000, 0x00040000 }, 106 [SBSA_GIC_DIST] = { 0x40060000, 0x00010000 }, 107 [SBSA_GIC_REDIST] = { 0x40080000, 0x04000000 }, 108 [SBSA_UART] = { 0x60000000, 0x00001000 }, 109 [SBSA_RTC] = { 0x60010000, 0x00001000 }, 110 [SBSA_GPIO] = { 0x60020000, 0x00001000 }, 111 [SBSA_SECURE_UART] = { 0x60030000, 0x00001000 }, 112 [SBSA_SECURE_UART_MM] = { 0x60040000, 0x00001000 }, 113 [SBSA_SMMU] = { 0x60050000, 0x00020000 }, 114 /* Space here reserved for more SMMUs */ 115 [SBSA_AHCI] = { 0x60100000, 0x00010000 }, 116 [SBSA_EHCI] = { 0x60110000, 0x00010000 }, 117 /* Space here reserved for other devices */ 118 [SBSA_PCIE_PIO] = { 0x7fff0000, 0x00010000 }, 119 /* 32-bit address PCIE MMIO space */ 120 [SBSA_PCIE_MMIO] = { 0x80000000, 0x70000000 }, 121 /* 256M PCIE ECAM space */ 122 [SBSA_PCIE_ECAM] = { 0xf0000000, 0x10000000 }, 123 /* ~1TB PCIE MMIO space (4GB to 1024GB boundary) */ 124 [SBSA_PCIE_MMIO_HIGH] = { 0x100000000ULL, 0xFF00000000ULL }, 125 [SBSA_MEM] = { 0x10000000000ULL, RAMLIMIT_BYTES }, 126 }; 127 128 static const int sbsa_ref_irqmap[] = { 129 [SBSA_UART] = 1, 130 [SBSA_RTC] = 2, 131 [SBSA_PCIE] = 3, /* ... to 6 */ 132 [SBSA_GPIO] = 7, 133 [SBSA_SECURE_UART] = 8, 134 [SBSA_SECURE_UART_MM] = 9, 135 [SBSA_AHCI] = 10, 136 [SBSA_EHCI] = 11, 137 }; 138 139 /* 140 * Firmware on this machine only uses ACPI table to load OS, these limited 141 * device tree nodes are just to let firmware know the info which varies from 142 * command line parameters, so it is not necessary to be fully compatible 143 * with the kernel CPU and NUMA binding rules. 144 */ 145 static void create_fdt(SBSAMachineState *sms) 146 { 147 void *fdt = create_device_tree(&sms->fdt_size); 148 const MachineState *ms = MACHINE(sms); 149 int nb_numa_nodes = ms->numa_state->num_nodes; 150 int cpu; 151 152 if (!fdt) { 153 error_report("create_device_tree() failed"); 154 exit(1); 155 } 156 157 sms->fdt = fdt; 158 159 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,sbsa-ref"); 160 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 161 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 162 163 if (have_numa_distance) { 164 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); 165 uint32_t *matrix = g_malloc0(size); 166 int idx, i, j; 167 168 for (i = 0; i < nb_numa_nodes; i++) { 169 for (j = 0; j < nb_numa_nodes; j++) { 170 idx = (i * nb_numa_nodes + j) * 3; 171 matrix[idx + 0] = cpu_to_be32(i); 172 matrix[idx + 1] = cpu_to_be32(j); 173 matrix[idx + 2] = cpu_to_be32(numa_info[i].distance[j]); 174 } 175 } 176 177 qemu_fdt_add_subnode(fdt, "/distance-map"); 178 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", 179 matrix, size); 180 g_free(matrix); 181 } 182 183 qemu_fdt_add_subnode(sms->fdt, "/cpus"); 184 185 for (cpu = sms->smp_cpus - 1; cpu >= 0; cpu--) { 186 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 187 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 188 CPUState *cs = CPU(armcpu); 189 190 qemu_fdt_add_subnode(sms->fdt, nodename); 191 192 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { 193 qemu_fdt_setprop_cell(sms->fdt, nodename, "numa-node-id", 194 ms->possible_cpus->cpus[cs->cpu_index].props.node_id); 195 } 196 197 g_free(nodename); 198 } 199 } 200 201 #define SBSA_FLASH_SECTOR_SIZE (256 * KiB) 202 203 static PFlashCFI01 *sbsa_flash_create1(SBSAMachineState *sms, 204 const char *name, 205 const char *alias_prop_name) 206 { 207 /* 208 * Create a single flash device. We use the same parameters as 209 * the flash devices on the Versatile Express board. 210 */ 211 DeviceState *dev = qdev_create(NULL, TYPE_PFLASH_CFI01); 212 213 qdev_prop_set_uint64(dev, "sector-length", SBSA_FLASH_SECTOR_SIZE); 214 qdev_prop_set_uint8(dev, "width", 4); 215 qdev_prop_set_uint8(dev, "device-width", 2); 216 qdev_prop_set_bit(dev, "big-endian", false); 217 qdev_prop_set_uint16(dev, "id0", 0x89); 218 qdev_prop_set_uint16(dev, "id1", 0x18); 219 qdev_prop_set_uint16(dev, "id2", 0x00); 220 qdev_prop_set_uint16(dev, "id3", 0x00); 221 qdev_prop_set_string(dev, "name", name); 222 object_property_add_child(OBJECT(sms), name, OBJECT(dev), 223 &error_abort); 224 object_property_add_alias(OBJECT(sms), alias_prop_name, 225 OBJECT(dev), "drive", &error_abort); 226 return PFLASH_CFI01(dev); 227 } 228 229 static void sbsa_flash_create(SBSAMachineState *sms) 230 { 231 sms->flash[0] = sbsa_flash_create1(sms, "sbsa.flash0", "pflash0"); 232 sms->flash[1] = sbsa_flash_create1(sms, "sbsa.flash1", "pflash1"); 233 } 234 235 static void sbsa_flash_map1(PFlashCFI01 *flash, 236 hwaddr base, hwaddr size, 237 MemoryRegion *sysmem) 238 { 239 DeviceState *dev = DEVICE(flash); 240 241 assert(size % SBSA_FLASH_SECTOR_SIZE == 0); 242 assert(size / SBSA_FLASH_SECTOR_SIZE <= UINT32_MAX); 243 qdev_prop_set_uint32(dev, "num-blocks", size / SBSA_FLASH_SECTOR_SIZE); 244 qdev_init_nofail(dev); 245 246 memory_region_add_subregion(sysmem, base, 247 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 248 0)); 249 } 250 251 static void sbsa_flash_map(SBSAMachineState *sms, 252 MemoryRegion *sysmem, 253 MemoryRegion *secure_sysmem) 254 { 255 /* 256 * Map two flash devices to fill the SBSA_FLASH space in the memmap. 257 * sysmem is the system memory space. secure_sysmem is the secure view 258 * of the system, and the first flash device should be made visible only 259 * there. The second flash device is visible to both secure and nonsecure. 260 */ 261 hwaddr flashsize = sbsa_ref_memmap[SBSA_FLASH].size / 2; 262 hwaddr flashbase = sbsa_ref_memmap[SBSA_FLASH].base; 263 264 sbsa_flash_map1(sms->flash[0], flashbase, flashsize, 265 secure_sysmem); 266 sbsa_flash_map1(sms->flash[1], flashbase + flashsize, flashsize, 267 sysmem); 268 } 269 270 static bool sbsa_firmware_init(SBSAMachineState *sms, 271 MemoryRegion *sysmem, 272 MemoryRegion *secure_sysmem) 273 { 274 int i; 275 BlockBackend *pflash_blk0; 276 277 /* Map legacy -drive if=pflash to machine properties */ 278 for (i = 0; i < ARRAY_SIZE(sms->flash); i++) { 279 pflash_cfi01_legacy_drive(sms->flash[i], 280 drive_get(IF_PFLASH, 0, i)); 281 } 282 283 sbsa_flash_map(sms, sysmem, secure_sysmem); 284 285 pflash_blk0 = pflash_cfi01_get_blk(sms->flash[0]); 286 287 if (bios_name) { 288 char *fname; 289 MemoryRegion *mr; 290 int image_size; 291 292 if (pflash_blk0) { 293 error_report("The contents of the first flash device may be " 294 "specified with -bios or with -drive if=pflash... " 295 "but you cannot use both options at once"); 296 exit(1); 297 } 298 299 /* Fall back to -bios */ 300 301 fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 302 if (!fname) { 303 error_report("Could not find ROM image '%s'", bios_name); 304 exit(1); 305 } 306 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(sms->flash[0]), 0); 307 image_size = load_image_mr(fname, mr); 308 g_free(fname); 309 if (image_size < 0) { 310 error_report("Could not load ROM image '%s'", bios_name); 311 exit(1); 312 } 313 } 314 315 return pflash_blk0 || bios_name; 316 } 317 318 static void create_secure_ram(SBSAMachineState *sms, 319 MemoryRegion *secure_sysmem) 320 { 321 MemoryRegion *secram = g_new(MemoryRegion, 1); 322 hwaddr base = sbsa_ref_memmap[SBSA_SECURE_MEM].base; 323 hwaddr size = sbsa_ref_memmap[SBSA_SECURE_MEM].size; 324 325 memory_region_init_ram(secram, NULL, "sbsa-ref.secure-ram", size, 326 &error_fatal); 327 memory_region_add_subregion(secure_sysmem, base, secram); 328 } 329 330 static void create_gic(SBSAMachineState *sms, qemu_irq *pic) 331 { 332 unsigned int smp_cpus = MACHINE(sms)->smp.cpus; 333 DeviceState *gicdev; 334 SysBusDevice *gicbusdev; 335 const char *gictype; 336 uint32_t redist0_capacity, redist0_count; 337 int i; 338 339 gictype = gicv3_class_name(); 340 341 gicdev = qdev_create(NULL, gictype); 342 qdev_prop_set_uint32(gicdev, "revision", 3); 343 qdev_prop_set_uint32(gicdev, "num-cpu", smp_cpus); 344 /* 345 * Note that the num-irq property counts both internal and external 346 * interrupts; there are always 32 of the former (mandated by GIC spec). 347 */ 348 qdev_prop_set_uint32(gicdev, "num-irq", NUM_IRQS + 32); 349 qdev_prop_set_bit(gicdev, "has-security-extensions", true); 350 351 redist0_capacity = 352 sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE; 353 redist0_count = MIN(smp_cpus, redist0_capacity); 354 355 qdev_prop_set_uint32(gicdev, "len-redist-region-count", 1); 356 qdev_prop_set_uint32(gicdev, "redist-region-count[0]", redist0_count); 357 358 qdev_init_nofail(gicdev); 359 gicbusdev = SYS_BUS_DEVICE(gicdev); 360 sysbus_mmio_map(gicbusdev, 0, sbsa_ref_memmap[SBSA_GIC_DIST].base); 361 sysbus_mmio_map(gicbusdev, 1, sbsa_ref_memmap[SBSA_GIC_REDIST].base); 362 363 /* 364 * Wire the outputs from each CPU's generic timer and the GICv3 365 * maintenance interrupt signal to the appropriate GIC PPI inputs, 366 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. 367 */ 368 for (i = 0; i < smp_cpus; i++) { 369 DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); 370 int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; 371 int irq; 372 /* 373 * Mapping from the output timer irq lines from the CPU to the 374 * GIC PPI inputs used for this board. 375 */ 376 const int timer_irq[] = { 377 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 378 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 379 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 380 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 381 }; 382 383 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { 384 qdev_connect_gpio_out(cpudev, irq, 385 qdev_get_gpio_in(gicdev, 386 ppibase + timer_irq[irq])); 387 } 388 389 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0, 390 qdev_get_gpio_in(gicdev, ppibase 391 + ARCH_GIC_MAINT_IRQ)); 392 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, 393 qdev_get_gpio_in(gicdev, ppibase 394 + VIRTUAL_PMU_IRQ)); 395 396 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 397 sysbus_connect_irq(gicbusdev, i + smp_cpus, 398 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 399 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus, 400 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 401 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, 402 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 403 } 404 405 for (i = 0; i < NUM_IRQS; i++) { 406 pic[i] = qdev_get_gpio_in(gicdev, i); 407 } 408 } 409 410 static void create_uart(const SBSAMachineState *sms, qemu_irq *pic, int uart, 411 MemoryRegion *mem, Chardev *chr) 412 { 413 hwaddr base = sbsa_ref_memmap[uart].base; 414 int irq = sbsa_ref_irqmap[uart]; 415 DeviceState *dev = qdev_create(NULL, "pl011"); 416 SysBusDevice *s = SYS_BUS_DEVICE(dev); 417 418 qdev_prop_set_chr(dev, "chardev", chr); 419 qdev_init_nofail(dev); 420 memory_region_add_subregion(mem, base, 421 sysbus_mmio_get_region(s, 0)); 422 sysbus_connect_irq(s, 0, pic[irq]); 423 } 424 425 static void create_rtc(const SBSAMachineState *sms, qemu_irq *pic) 426 { 427 hwaddr base = sbsa_ref_memmap[SBSA_RTC].base; 428 int irq = sbsa_ref_irqmap[SBSA_RTC]; 429 430 sysbus_create_simple("pl031", base, pic[irq]); 431 } 432 433 static DeviceState *gpio_key_dev; 434 static void sbsa_ref_powerdown_req(Notifier *n, void *opaque) 435 { 436 /* use gpio Pin 3 for power button event */ 437 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); 438 } 439 440 static Notifier sbsa_ref_powerdown_notifier = { 441 .notify = sbsa_ref_powerdown_req 442 }; 443 444 static void create_gpio(const SBSAMachineState *sms, qemu_irq *pic) 445 { 446 DeviceState *pl061_dev; 447 hwaddr base = sbsa_ref_memmap[SBSA_GPIO].base; 448 int irq = sbsa_ref_irqmap[SBSA_GPIO]; 449 450 pl061_dev = sysbus_create_simple("pl061", base, pic[irq]); 451 452 gpio_key_dev = sysbus_create_simple("gpio-key", -1, 453 qdev_get_gpio_in(pl061_dev, 3)); 454 455 /* connect powerdown request */ 456 qemu_register_powerdown_notifier(&sbsa_ref_powerdown_notifier); 457 } 458 459 static void create_ahci(const SBSAMachineState *sms, qemu_irq *pic) 460 { 461 hwaddr base = sbsa_ref_memmap[SBSA_AHCI].base; 462 int irq = sbsa_ref_irqmap[SBSA_AHCI]; 463 DeviceState *dev; 464 DriveInfo *hd[NUM_SATA_PORTS]; 465 SysbusAHCIState *sysahci; 466 AHCIState *ahci; 467 int i; 468 469 dev = qdev_create(NULL, "sysbus-ahci"); 470 qdev_prop_set_uint32(dev, "num-ports", NUM_SATA_PORTS); 471 qdev_init_nofail(dev); 472 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 473 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[irq]); 474 475 sysahci = SYSBUS_AHCI(dev); 476 ahci = &sysahci->ahci; 477 ide_drive_get(hd, ARRAY_SIZE(hd)); 478 for (i = 0; i < ahci->ports; i++) { 479 if (hd[i] == NULL) { 480 continue; 481 } 482 ide_create_drive(&ahci->dev[i].port, 0, hd[i]); 483 } 484 } 485 486 static void create_ehci(const SBSAMachineState *sms, qemu_irq *pic) 487 { 488 hwaddr base = sbsa_ref_memmap[SBSA_EHCI].base; 489 int irq = sbsa_ref_irqmap[SBSA_EHCI]; 490 491 sysbus_create_simple("platform-ehci-usb", base, pic[irq]); 492 } 493 494 static void create_smmu(const SBSAMachineState *sms, qemu_irq *pic, 495 PCIBus *bus) 496 { 497 hwaddr base = sbsa_ref_memmap[SBSA_SMMU].base; 498 int irq = sbsa_ref_irqmap[SBSA_SMMU]; 499 DeviceState *dev; 500 int i; 501 502 dev = qdev_create(NULL, "arm-smmuv3"); 503 504 object_property_set_link(OBJECT(dev), OBJECT(bus), "primary-bus", 505 &error_abort); 506 qdev_init_nofail(dev); 507 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 508 for (i = 0; i < NUM_SMMU_IRQS; i++) { 509 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); 510 } 511 } 512 513 static void create_pcie(SBSAMachineState *sms, qemu_irq *pic) 514 { 515 hwaddr base_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].base; 516 hwaddr size_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].size; 517 hwaddr base_mmio = sbsa_ref_memmap[SBSA_PCIE_MMIO].base; 518 hwaddr size_mmio = sbsa_ref_memmap[SBSA_PCIE_MMIO].size; 519 hwaddr base_mmio_high = sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].base; 520 hwaddr size_mmio_high = sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].size; 521 hwaddr base_pio = sbsa_ref_memmap[SBSA_PCIE_PIO].base; 522 int irq = sbsa_ref_irqmap[SBSA_PCIE]; 523 MemoryRegion *mmio_alias, *mmio_alias_high, *mmio_reg; 524 MemoryRegion *ecam_alias, *ecam_reg; 525 DeviceState *dev; 526 PCIHostState *pci; 527 int i; 528 529 dev = qdev_create(NULL, TYPE_GPEX_HOST); 530 qdev_init_nofail(dev); 531 532 /* Map ECAM space */ 533 ecam_alias = g_new0(MemoryRegion, 1); 534 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 535 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 536 ecam_reg, 0, size_ecam); 537 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias); 538 539 /* Map the MMIO space */ 540 mmio_alias = g_new0(MemoryRegion, 1); 541 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 542 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 543 mmio_reg, base_mmio, size_mmio); 544 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); 545 546 /* Map the MMIO_HIGH space */ 547 mmio_alias_high = g_new0(MemoryRegion, 1); 548 memory_region_init_alias(mmio_alias_high, OBJECT(dev), "pcie-mmio-high", 549 mmio_reg, base_mmio_high, size_mmio_high); 550 memory_region_add_subregion(get_system_memory(), base_mmio_high, 551 mmio_alias_high); 552 553 /* Map IO port space */ 554 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); 555 556 for (i = 0; i < GPEX_NUM_IRQS; i++) { 557 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); 558 gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); 559 } 560 561 pci = PCI_HOST_BRIDGE(dev); 562 if (pci->bus) { 563 for (i = 0; i < nb_nics; i++) { 564 NICInfo *nd = &nd_table[i]; 565 566 if (!nd->model) { 567 nd->model = g_strdup("e1000e"); 568 } 569 570 pci_nic_init_nofail(nd, pci->bus, nd->model, NULL); 571 } 572 } 573 574 pci_create_simple(pci->bus, -1, "VGA"); 575 576 create_smmu(sms, pic, pci->bus); 577 } 578 579 static void *sbsa_ref_dtb(const struct arm_boot_info *binfo, int *fdt_size) 580 { 581 const SBSAMachineState *board = container_of(binfo, SBSAMachineState, 582 bootinfo); 583 584 *fdt_size = board->fdt_size; 585 return board->fdt; 586 } 587 588 static void sbsa_ref_init(MachineState *machine) 589 { 590 unsigned int smp_cpus = machine->smp.cpus; 591 unsigned int max_cpus = machine->smp.max_cpus; 592 SBSAMachineState *sms = SBSA_MACHINE(machine); 593 MachineClass *mc = MACHINE_GET_CLASS(machine); 594 MemoryRegion *sysmem = get_system_memory(); 595 MemoryRegion *secure_sysmem = g_new(MemoryRegion, 1); 596 MemoryRegion *ram = g_new(MemoryRegion, 1); 597 bool firmware_loaded; 598 const CPUArchIdList *possible_cpus; 599 int n, sbsa_max_cpus; 600 qemu_irq pic[NUM_IRQS]; 601 602 if (strcmp(machine->cpu_type, ARM_CPU_TYPE_NAME("cortex-a57"))) { 603 error_report("sbsa-ref: CPU type other than the built-in " 604 "cortex-a57 not supported"); 605 exit(1); 606 } 607 608 if (kvm_enabled()) { 609 error_report("sbsa-ref: KVM is not supported for this machine"); 610 exit(1); 611 } 612 613 /* 614 * The Secure view of the world is the same as the NonSecure, 615 * but with a few extra devices. Create it as a container region 616 * containing the system memory at low priority; any secure-only 617 * devices go in at higher priority and take precedence. 618 */ 619 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", 620 UINT64_MAX); 621 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); 622 623 firmware_loaded = sbsa_firmware_init(sms, sysmem, secure_sysmem); 624 625 if (machine->kernel_filename && firmware_loaded) { 626 error_report("sbsa-ref: No fw_cfg device on this machine, " 627 "so -kernel option is not supported when firmware loaded, " 628 "please load OS from hard disk instead"); 629 exit(1); 630 } 631 632 /* 633 * This machine has EL3 enabled, external firmware should supply PSCI 634 * implementation, so the QEMU's internal PSCI is disabled. 635 */ 636 sms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; 637 638 sbsa_max_cpus = sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE; 639 640 if (max_cpus > sbsa_max_cpus) { 641 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " 642 "supported by machine 'sbsa-ref' (%d)", 643 max_cpus, sbsa_max_cpus); 644 exit(1); 645 } 646 647 sms->smp_cpus = smp_cpus; 648 649 if (machine->ram_size > sbsa_ref_memmap[SBSA_MEM].size) { 650 error_report("sbsa-ref: cannot model more than %dGB RAM", RAMLIMIT_GB); 651 exit(1); 652 } 653 654 possible_cpus = mc->possible_cpu_arch_ids(machine); 655 for (n = 0; n < possible_cpus->len; n++) { 656 Object *cpuobj; 657 CPUState *cs; 658 659 if (n >= smp_cpus) { 660 break; 661 } 662 663 cpuobj = object_new(possible_cpus->cpus[n].type); 664 object_property_set_int(cpuobj, possible_cpus->cpus[n].arch_id, 665 "mp-affinity", NULL); 666 667 cs = CPU(cpuobj); 668 cs->cpu_index = n; 669 670 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj), 671 &error_fatal); 672 673 if (object_property_find(cpuobj, "reset-cbar", NULL)) { 674 object_property_set_int(cpuobj, 675 sbsa_ref_memmap[SBSA_CPUPERIPHS].base, 676 "reset-cbar", &error_abort); 677 } 678 679 object_property_set_link(cpuobj, OBJECT(sysmem), "memory", 680 &error_abort); 681 682 object_property_set_link(cpuobj, OBJECT(secure_sysmem), 683 "secure-memory", &error_abort); 684 685 object_property_set_bool(cpuobj, true, "realized", &error_fatal); 686 object_unref(cpuobj); 687 } 688 689 memory_region_allocate_system_memory(ram, NULL, "sbsa-ref.ram", 690 machine->ram_size); 691 memory_region_add_subregion(sysmem, sbsa_ref_memmap[SBSA_MEM].base, ram); 692 693 create_fdt(sms); 694 695 create_secure_ram(sms, secure_sysmem); 696 697 create_gic(sms, pic); 698 699 create_uart(sms, pic, SBSA_UART, sysmem, serial_hd(0)); 700 create_uart(sms, pic, SBSA_SECURE_UART, secure_sysmem, serial_hd(1)); 701 /* Second secure UART for RAS and MM from EL0 */ 702 create_uart(sms, pic, SBSA_SECURE_UART_MM, secure_sysmem, serial_hd(2)); 703 704 create_rtc(sms, pic); 705 706 create_gpio(sms, pic); 707 708 create_ahci(sms, pic); 709 710 create_ehci(sms, pic); 711 712 create_pcie(sms, pic); 713 714 sms->bootinfo.ram_size = machine->ram_size; 715 sms->bootinfo.nb_cpus = smp_cpus; 716 sms->bootinfo.board_id = -1; 717 sms->bootinfo.loader_start = sbsa_ref_memmap[SBSA_MEM].base; 718 sms->bootinfo.get_dtb = sbsa_ref_dtb; 719 sms->bootinfo.firmware_loaded = firmware_loaded; 720 arm_load_kernel(ARM_CPU(first_cpu), machine, &sms->bootinfo); 721 } 722 723 static uint64_t sbsa_ref_cpu_mp_affinity(SBSAMachineState *sms, int idx) 724 { 725 uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER; 726 return arm_cpu_mp_affinity(idx, clustersz); 727 } 728 729 static const CPUArchIdList *sbsa_ref_possible_cpu_arch_ids(MachineState *ms) 730 { 731 unsigned int max_cpus = ms->smp.max_cpus; 732 SBSAMachineState *sms = SBSA_MACHINE(ms); 733 int n; 734 735 if (ms->possible_cpus) { 736 assert(ms->possible_cpus->len == max_cpus); 737 return ms->possible_cpus; 738 } 739 740 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 741 sizeof(CPUArchId) * max_cpus); 742 ms->possible_cpus->len = max_cpus; 743 for (n = 0; n < ms->possible_cpus->len; n++) { 744 ms->possible_cpus->cpus[n].type = ms->cpu_type; 745 ms->possible_cpus->cpus[n].arch_id = 746 sbsa_ref_cpu_mp_affinity(sms, n); 747 ms->possible_cpus->cpus[n].props.has_thread_id = true; 748 ms->possible_cpus->cpus[n].props.thread_id = n; 749 } 750 return ms->possible_cpus; 751 } 752 753 static CpuInstanceProperties 754 sbsa_ref_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 755 { 756 MachineClass *mc = MACHINE_GET_CLASS(ms); 757 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 758 759 assert(cpu_index < possible_cpus->len); 760 return possible_cpus->cpus[cpu_index].props; 761 } 762 763 static int64_t 764 sbsa_ref_get_default_cpu_node_id(const MachineState *ms, int idx) 765 { 766 return idx % ms->numa_state->num_nodes; 767 } 768 769 static void sbsa_ref_instance_init(Object *obj) 770 { 771 SBSAMachineState *sms = SBSA_MACHINE(obj); 772 773 sbsa_flash_create(sms); 774 } 775 776 static void sbsa_ref_class_init(ObjectClass *oc, void *data) 777 { 778 MachineClass *mc = MACHINE_CLASS(oc); 779 780 mc->init = sbsa_ref_init; 781 mc->desc = "QEMU 'SBSA Reference' ARM Virtual Machine"; 782 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a57"); 783 mc->max_cpus = 512; 784 mc->pci_allow_0_address = true; 785 mc->minimum_page_bits = 12; 786 mc->block_default_type = IF_IDE; 787 mc->no_cdrom = 1; 788 mc->default_ram_size = 1 * GiB; 789 mc->default_cpus = 4; 790 mc->possible_cpu_arch_ids = sbsa_ref_possible_cpu_arch_ids; 791 mc->cpu_index_to_instance_props = sbsa_ref_cpu_index_to_props; 792 mc->get_default_cpu_node_id = sbsa_ref_get_default_cpu_node_id; 793 mc->numa_mem_supported = true; 794 } 795 796 static const TypeInfo sbsa_ref_info = { 797 .name = TYPE_SBSA_MACHINE, 798 .parent = TYPE_MACHINE, 799 .instance_init = sbsa_ref_instance_init, 800 .class_init = sbsa_ref_class_init, 801 .instance_size = sizeof(SBSAMachineState), 802 }; 803 804 static void sbsa_ref_machine_init(void) 805 { 806 type_register_static(&sbsa_ref_info); 807 } 808 809 type_init(sbsa_ref_machine_init); 810