1 /* 2 * ARM SBSA Reference Platform emulation 3 * 4 * Copyright (c) 2018 Linaro Limited 5 * Written by Hongbo Zhang <hongbo.zhang@linaro.org> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu-common.h" 22 #include "qapi/error.h" 23 #include "qemu/error-report.h" 24 #include "qemu/units.h" 25 #include "sysemu/device_tree.h" 26 #include "sysemu/numa.h" 27 #include "sysemu/sysemu.h" 28 #include "exec/address-spaces.h" 29 #include "exec/hwaddr.h" 30 #include "kvm_arm.h" 31 #include "hw/arm/boot.h" 32 #include "hw/block/flash.h" 33 #include "hw/boards.h" 34 #include "hw/ide/internal.h" 35 #include "hw/ide/ahci_internal.h" 36 #include "hw/intc/arm_gicv3_common.h" 37 #include "hw/loader.h" 38 #include "hw/pci-host/gpex.h" 39 #include "hw/usb.h" 40 #include "net/net.h" 41 42 #define RAMLIMIT_GB 8192 43 #define RAMLIMIT_BYTES (RAMLIMIT_GB * GiB) 44 45 #define NUM_IRQS 256 46 #define NUM_SMMU_IRQS 4 47 #define NUM_SATA_PORTS 6 48 49 #define VIRTUAL_PMU_IRQ 7 50 #define ARCH_GIC_MAINT_IRQ 9 51 #define ARCH_TIMER_VIRT_IRQ 11 52 #define ARCH_TIMER_S_EL1_IRQ 13 53 #define ARCH_TIMER_NS_EL1_IRQ 14 54 #define ARCH_TIMER_NS_EL2_IRQ 10 55 56 enum { 57 SBSA_FLASH, 58 SBSA_MEM, 59 SBSA_CPUPERIPHS, 60 SBSA_GIC_DIST, 61 SBSA_GIC_REDIST, 62 SBSA_SMMU, 63 SBSA_UART, 64 SBSA_RTC, 65 SBSA_PCIE, 66 SBSA_PCIE_MMIO, 67 SBSA_PCIE_MMIO_HIGH, 68 SBSA_PCIE_PIO, 69 SBSA_PCIE_ECAM, 70 SBSA_GPIO, 71 SBSA_SECURE_UART, 72 SBSA_SECURE_UART_MM, 73 SBSA_SECURE_MEM, 74 SBSA_AHCI, 75 SBSA_EHCI, 76 }; 77 78 typedef struct MemMapEntry { 79 hwaddr base; 80 hwaddr size; 81 } MemMapEntry; 82 83 typedef struct { 84 MachineState parent; 85 struct arm_boot_info bootinfo; 86 int smp_cpus; 87 void *fdt; 88 int fdt_size; 89 int psci_conduit; 90 PFlashCFI01 *flash[2]; 91 } SBSAMachineState; 92 93 #define TYPE_SBSA_MACHINE MACHINE_TYPE_NAME("sbsa-ref") 94 #define SBSA_MACHINE(obj) \ 95 OBJECT_CHECK(SBSAMachineState, (obj), TYPE_SBSA_MACHINE) 96 97 static const MemMapEntry sbsa_ref_memmap[] = { 98 /* 512M boot ROM */ 99 [SBSA_FLASH] = { 0, 0x20000000 }, 100 /* 512M secure memory */ 101 [SBSA_SECURE_MEM] = { 0x20000000, 0x20000000 }, 102 /* Space reserved for CPU peripheral devices */ 103 [SBSA_CPUPERIPHS] = { 0x40000000, 0x00040000 }, 104 [SBSA_GIC_DIST] = { 0x40060000, 0x00010000 }, 105 [SBSA_GIC_REDIST] = { 0x40080000, 0x04000000 }, 106 [SBSA_UART] = { 0x60000000, 0x00001000 }, 107 [SBSA_RTC] = { 0x60010000, 0x00001000 }, 108 [SBSA_GPIO] = { 0x60020000, 0x00001000 }, 109 [SBSA_SECURE_UART] = { 0x60030000, 0x00001000 }, 110 [SBSA_SECURE_UART_MM] = { 0x60040000, 0x00001000 }, 111 [SBSA_SMMU] = { 0x60050000, 0x00020000 }, 112 /* Space here reserved for more SMMUs */ 113 [SBSA_AHCI] = { 0x60100000, 0x00010000 }, 114 [SBSA_EHCI] = { 0x60110000, 0x00010000 }, 115 /* Space here reserved for other devices */ 116 [SBSA_PCIE_PIO] = { 0x7fff0000, 0x00010000 }, 117 /* 32-bit address PCIE MMIO space */ 118 [SBSA_PCIE_MMIO] = { 0x80000000, 0x70000000 }, 119 /* 256M PCIE ECAM space */ 120 [SBSA_PCIE_ECAM] = { 0xf0000000, 0x10000000 }, 121 /* ~1TB PCIE MMIO space (4GB to 1024GB boundary) */ 122 [SBSA_PCIE_MMIO_HIGH] = { 0x100000000ULL, 0xFF00000000ULL }, 123 [SBSA_MEM] = { 0x10000000000ULL, RAMLIMIT_BYTES }, 124 }; 125 126 static const int sbsa_ref_irqmap[] = { 127 [SBSA_UART] = 1, 128 [SBSA_RTC] = 2, 129 [SBSA_PCIE] = 3, /* ... to 6 */ 130 [SBSA_GPIO] = 7, 131 [SBSA_SECURE_UART] = 8, 132 [SBSA_SECURE_UART_MM] = 9, 133 [SBSA_AHCI] = 10, 134 [SBSA_EHCI] = 11, 135 }; 136 137 /* 138 * Firmware on this machine only uses ACPI table to load OS, these limited 139 * device tree nodes are just to let firmware know the info which varies from 140 * command line parameters, so it is not necessary to be fully compatible 141 * with the kernel CPU and NUMA binding rules. 142 */ 143 static void create_fdt(SBSAMachineState *sms) 144 { 145 void *fdt = create_device_tree(&sms->fdt_size); 146 const MachineState *ms = MACHINE(sms); 147 int cpu; 148 149 if (!fdt) { 150 error_report("create_device_tree() failed"); 151 exit(1); 152 } 153 154 sms->fdt = fdt; 155 156 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,sbsa-ref"); 157 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 158 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 159 160 if (have_numa_distance) { 161 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); 162 uint32_t *matrix = g_malloc0(size); 163 int idx, i, j; 164 165 for (i = 0; i < nb_numa_nodes; i++) { 166 for (j = 0; j < nb_numa_nodes; j++) { 167 idx = (i * nb_numa_nodes + j) * 3; 168 matrix[idx + 0] = cpu_to_be32(i); 169 matrix[idx + 1] = cpu_to_be32(j); 170 matrix[idx + 2] = cpu_to_be32(numa_info[i].distance[j]); 171 } 172 } 173 174 qemu_fdt_add_subnode(fdt, "/distance-map"); 175 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", 176 matrix, size); 177 g_free(matrix); 178 } 179 180 qemu_fdt_add_subnode(sms->fdt, "/cpus"); 181 182 for (cpu = sms->smp_cpus - 1; cpu >= 0; cpu--) { 183 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 184 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 185 CPUState *cs = CPU(armcpu); 186 187 qemu_fdt_add_subnode(sms->fdt, nodename); 188 189 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { 190 qemu_fdt_setprop_cell(sms->fdt, nodename, "numa-node-id", 191 ms->possible_cpus->cpus[cs->cpu_index].props.node_id); 192 } 193 194 g_free(nodename); 195 } 196 } 197 198 #define SBSA_FLASH_SECTOR_SIZE (256 * KiB) 199 200 static PFlashCFI01 *sbsa_flash_create1(SBSAMachineState *sms, 201 const char *name, 202 const char *alias_prop_name) 203 { 204 /* 205 * Create a single flash device. We use the same parameters as 206 * the flash devices on the Versatile Express board. 207 */ 208 DeviceState *dev = qdev_create(NULL, TYPE_PFLASH_CFI01); 209 210 qdev_prop_set_uint64(dev, "sector-length", SBSA_FLASH_SECTOR_SIZE); 211 qdev_prop_set_uint8(dev, "width", 4); 212 qdev_prop_set_uint8(dev, "device-width", 2); 213 qdev_prop_set_bit(dev, "big-endian", false); 214 qdev_prop_set_uint16(dev, "id0", 0x89); 215 qdev_prop_set_uint16(dev, "id1", 0x18); 216 qdev_prop_set_uint16(dev, "id2", 0x00); 217 qdev_prop_set_uint16(dev, "id3", 0x00); 218 qdev_prop_set_string(dev, "name", name); 219 object_property_add_child(OBJECT(sms), name, OBJECT(dev), 220 &error_abort); 221 object_property_add_alias(OBJECT(sms), alias_prop_name, 222 OBJECT(dev), "drive", &error_abort); 223 return PFLASH_CFI01(dev); 224 } 225 226 static void sbsa_flash_create(SBSAMachineState *sms) 227 { 228 sms->flash[0] = sbsa_flash_create1(sms, "sbsa.flash0", "pflash0"); 229 sms->flash[1] = sbsa_flash_create1(sms, "sbsa.flash1", "pflash1"); 230 } 231 232 static void sbsa_flash_map1(PFlashCFI01 *flash, 233 hwaddr base, hwaddr size, 234 MemoryRegion *sysmem) 235 { 236 DeviceState *dev = DEVICE(flash); 237 238 assert(size % SBSA_FLASH_SECTOR_SIZE == 0); 239 assert(size / SBSA_FLASH_SECTOR_SIZE <= UINT32_MAX); 240 qdev_prop_set_uint32(dev, "num-blocks", size / SBSA_FLASH_SECTOR_SIZE); 241 qdev_init_nofail(dev); 242 243 memory_region_add_subregion(sysmem, base, 244 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 245 0)); 246 } 247 248 static void sbsa_flash_map(SBSAMachineState *sms, 249 MemoryRegion *sysmem, 250 MemoryRegion *secure_sysmem) 251 { 252 /* 253 * Map two flash devices to fill the SBSA_FLASH space in the memmap. 254 * sysmem is the system memory space. secure_sysmem is the secure view 255 * of the system, and the first flash device should be made visible only 256 * there. The second flash device is visible to both secure and nonsecure. 257 * If sysmem == secure_sysmem this means there is no separate Secure 258 * address space and both flash devices are generally visible. 259 */ 260 hwaddr flashsize = sbsa_ref_memmap[SBSA_FLASH].size / 2; 261 hwaddr flashbase = sbsa_ref_memmap[SBSA_FLASH].base; 262 263 sbsa_flash_map1(sms->flash[0], flashbase, flashsize, 264 secure_sysmem); 265 sbsa_flash_map1(sms->flash[1], flashbase + flashsize, flashsize, 266 sysmem); 267 } 268 269 static bool sbsa_firmware_init(SBSAMachineState *sms, 270 MemoryRegion *sysmem, 271 MemoryRegion *secure_sysmem) 272 { 273 int i; 274 BlockBackend *pflash_blk0; 275 276 /* Map legacy -drive if=pflash to machine properties */ 277 for (i = 0; i < ARRAY_SIZE(sms->flash); i++) { 278 pflash_cfi01_legacy_drive(sms->flash[i], 279 drive_get(IF_PFLASH, 0, i)); 280 } 281 282 sbsa_flash_map(sms, sysmem, secure_sysmem); 283 284 pflash_blk0 = pflash_cfi01_get_blk(sms->flash[0]); 285 286 if (bios_name) { 287 char *fname; 288 MemoryRegion *mr; 289 int image_size; 290 291 if (pflash_blk0) { 292 error_report("The contents of the first flash device may be " 293 "specified with -bios or with -drive if=pflash... " 294 "but you cannot use both options at once"); 295 exit(1); 296 } 297 298 /* Fall back to -bios */ 299 300 fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 301 if (!fname) { 302 error_report("Could not find ROM image '%s'", bios_name); 303 exit(1); 304 } 305 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(sms->flash[0]), 0); 306 image_size = load_image_mr(fname, mr); 307 g_free(fname); 308 if (image_size < 0) { 309 error_report("Could not load ROM image '%s'", bios_name); 310 exit(1); 311 } 312 } 313 314 return pflash_blk0 || bios_name; 315 } 316 317 static void create_secure_ram(SBSAMachineState *sms, 318 MemoryRegion *secure_sysmem) 319 { 320 MemoryRegion *secram = g_new(MemoryRegion, 1); 321 hwaddr base = sbsa_ref_memmap[SBSA_SECURE_MEM].base; 322 hwaddr size = sbsa_ref_memmap[SBSA_SECURE_MEM].size; 323 324 memory_region_init_ram(secram, NULL, "sbsa-ref.secure-ram", size, 325 &error_fatal); 326 memory_region_add_subregion(secure_sysmem, base, secram); 327 } 328 329 static void create_gic(SBSAMachineState *sms, qemu_irq *pic) 330 { 331 DeviceState *gicdev; 332 SysBusDevice *gicbusdev; 333 const char *gictype; 334 uint32_t redist0_capacity, redist0_count; 335 int i; 336 337 gictype = gicv3_class_name(); 338 339 gicdev = qdev_create(NULL, gictype); 340 qdev_prop_set_uint32(gicdev, "revision", 3); 341 qdev_prop_set_uint32(gicdev, "num-cpu", smp_cpus); 342 /* 343 * Note that the num-irq property counts both internal and external 344 * interrupts; there are always 32 of the former (mandated by GIC spec). 345 */ 346 qdev_prop_set_uint32(gicdev, "num-irq", NUM_IRQS + 32); 347 qdev_prop_set_bit(gicdev, "has-security-extensions", true); 348 349 redist0_capacity = 350 sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE; 351 redist0_count = MIN(smp_cpus, redist0_capacity); 352 353 qdev_prop_set_uint32(gicdev, "len-redist-region-count", 1); 354 qdev_prop_set_uint32(gicdev, "redist-region-count[0]", redist0_count); 355 356 qdev_init_nofail(gicdev); 357 gicbusdev = SYS_BUS_DEVICE(gicdev); 358 sysbus_mmio_map(gicbusdev, 0, sbsa_ref_memmap[SBSA_GIC_DIST].base); 359 sysbus_mmio_map(gicbusdev, 1, sbsa_ref_memmap[SBSA_GIC_REDIST].base); 360 361 /* 362 * Wire the outputs from each CPU's generic timer and the GICv3 363 * maintenance interrupt signal to the appropriate GIC PPI inputs, 364 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. 365 */ 366 for (i = 0; i < smp_cpus; i++) { 367 DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); 368 int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; 369 int irq; 370 /* 371 * Mapping from the output timer irq lines from the CPU to the 372 * GIC PPI inputs used for this board. 373 */ 374 const int timer_irq[] = { 375 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 376 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 377 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 378 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 379 }; 380 381 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { 382 qdev_connect_gpio_out(cpudev, irq, 383 qdev_get_gpio_in(gicdev, 384 ppibase + timer_irq[irq])); 385 } 386 387 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0, 388 qdev_get_gpio_in(gicdev, ppibase 389 + ARCH_GIC_MAINT_IRQ)); 390 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, 391 qdev_get_gpio_in(gicdev, ppibase 392 + VIRTUAL_PMU_IRQ)); 393 394 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 395 sysbus_connect_irq(gicbusdev, i + smp_cpus, 396 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 397 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus, 398 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 399 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, 400 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 401 } 402 403 for (i = 0; i < NUM_IRQS; i++) { 404 pic[i] = qdev_get_gpio_in(gicdev, i); 405 } 406 } 407 408 static void create_uart(const SBSAMachineState *sms, qemu_irq *pic, int uart, 409 MemoryRegion *mem, Chardev *chr) 410 { 411 hwaddr base = sbsa_ref_memmap[uart].base; 412 int irq = sbsa_ref_irqmap[uart]; 413 DeviceState *dev = qdev_create(NULL, "pl011"); 414 SysBusDevice *s = SYS_BUS_DEVICE(dev); 415 416 qdev_prop_set_chr(dev, "chardev", chr); 417 qdev_init_nofail(dev); 418 memory_region_add_subregion(mem, base, 419 sysbus_mmio_get_region(s, 0)); 420 sysbus_connect_irq(s, 0, pic[irq]); 421 } 422 423 static void create_rtc(const SBSAMachineState *sms, qemu_irq *pic) 424 { 425 hwaddr base = sbsa_ref_memmap[SBSA_RTC].base; 426 int irq = sbsa_ref_irqmap[SBSA_RTC]; 427 428 sysbus_create_simple("pl031", base, pic[irq]); 429 } 430 431 static DeviceState *gpio_key_dev; 432 static void sbsa_ref_powerdown_req(Notifier *n, void *opaque) 433 { 434 /* use gpio Pin 3 for power button event */ 435 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); 436 } 437 438 static Notifier sbsa_ref_powerdown_notifier = { 439 .notify = sbsa_ref_powerdown_req 440 }; 441 442 static void create_gpio(const SBSAMachineState *sms, qemu_irq *pic) 443 { 444 DeviceState *pl061_dev; 445 hwaddr base = sbsa_ref_memmap[SBSA_GPIO].base; 446 int irq = sbsa_ref_irqmap[SBSA_GPIO]; 447 448 pl061_dev = sysbus_create_simple("pl061", base, pic[irq]); 449 450 gpio_key_dev = sysbus_create_simple("gpio-key", -1, 451 qdev_get_gpio_in(pl061_dev, 3)); 452 453 /* connect powerdown request */ 454 qemu_register_powerdown_notifier(&sbsa_ref_powerdown_notifier); 455 } 456 457 static void create_ahci(const SBSAMachineState *sms, qemu_irq *pic) 458 { 459 hwaddr base = sbsa_ref_memmap[SBSA_AHCI].base; 460 int irq = sbsa_ref_irqmap[SBSA_AHCI]; 461 DeviceState *dev; 462 DriveInfo *hd[NUM_SATA_PORTS]; 463 SysbusAHCIState *sysahci; 464 AHCIState *ahci; 465 int i; 466 467 dev = qdev_create(NULL, "sysbus-ahci"); 468 qdev_prop_set_uint32(dev, "num-ports", NUM_SATA_PORTS); 469 qdev_init_nofail(dev); 470 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 471 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[irq]); 472 473 sysahci = SYSBUS_AHCI(dev); 474 ahci = &sysahci->ahci; 475 ide_drive_get(hd, ARRAY_SIZE(hd)); 476 for (i = 0; i < ahci->ports; i++) { 477 if (hd[i] == NULL) { 478 continue; 479 } 480 ide_create_drive(&ahci->dev[i].port, 0, hd[i]); 481 } 482 } 483 484 static void create_ehci(const SBSAMachineState *sms, qemu_irq *pic) 485 { 486 hwaddr base = sbsa_ref_memmap[SBSA_EHCI].base; 487 int irq = sbsa_ref_irqmap[SBSA_EHCI]; 488 489 sysbus_create_simple("platform-ehci-usb", base, pic[irq]); 490 } 491 492 static void create_smmu(const SBSAMachineState *sms, qemu_irq *pic, 493 PCIBus *bus) 494 { 495 hwaddr base = sbsa_ref_memmap[SBSA_SMMU].base; 496 int irq = sbsa_ref_irqmap[SBSA_SMMU]; 497 DeviceState *dev; 498 int i; 499 500 dev = qdev_create(NULL, "arm-smmuv3"); 501 502 object_property_set_link(OBJECT(dev), OBJECT(bus), "primary-bus", 503 &error_abort); 504 qdev_init_nofail(dev); 505 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 506 for (i = 0; i < NUM_SMMU_IRQS; i++) { 507 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); 508 } 509 } 510 511 static void create_pcie(SBSAMachineState *sms, qemu_irq *pic) 512 { 513 hwaddr base_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].base; 514 hwaddr size_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].size; 515 hwaddr base_mmio = sbsa_ref_memmap[SBSA_PCIE_MMIO].base; 516 hwaddr size_mmio = sbsa_ref_memmap[SBSA_PCIE_MMIO].size; 517 hwaddr base_mmio_high = sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].base; 518 hwaddr size_mmio_high = sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].size; 519 hwaddr base_pio = sbsa_ref_memmap[SBSA_PCIE_PIO].base; 520 int irq = sbsa_ref_irqmap[SBSA_PCIE]; 521 MemoryRegion *mmio_alias, *mmio_alias_high, *mmio_reg; 522 MemoryRegion *ecam_alias, *ecam_reg; 523 DeviceState *dev; 524 PCIHostState *pci; 525 int i; 526 527 dev = qdev_create(NULL, TYPE_GPEX_HOST); 528 qdev_init_nofail(dev); 529 530 /* Map ECAM space */ 531 ecam_alias = g_new0(MemoryRegion, 1); 532 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 533 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 534 ecam_reg, 0, size_ecam); 535 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias); 536 537 /* Map the MMIO space */ 538 mmio_alias = g_new0(MemoryRegion, 1); 539 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 540 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 541 mmio_reg, base_mmio, size_mmio); 542 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); 543 544 /* Map the MMIO_HIGH space */ 545 mmio_alias_high = g_new0(MemoryRegion, 1); 546 memory_region_init_alias(mmio_alias_high, OBJECT(dev), "pcie-mmio-high", 547 mmio_reg, base_mmio_high, size_mmio_high); 548 memory_region_add_subregion(get_system_memory(), base_mmio_high, 549 mmio_alias_high); 550 551 /* Map IO port space */ 552 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); 553 554 for (i = 0; i < GPEX_NUM_IRQS; i++) { 555 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); 556 gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); 557 } 558 559 pci = PCI_HOST_BRIDGE(dev); 560 if (pci->bus) { 561 for (i = 0; i < nb_nics; i++) { 562 NICInfo *nd = &nd_table[i]; 563 564 if (!nd->model) { 565 nd->model = g_strdup("e1000e"); 566 } 567 568 pci_nic_init_nofail(nd, pci->bus, nd->model, NULL); 569 } 570 } 571 572 pci_create_simple(pci->bus, -1, "VGA"); 573 574 create_smmu(sms, pic, pci->bus); 575 } 576 577 static void *sbsa_ref_dtb(const struct arm_boot_info *binfo, int *fdt_size) 578 { 579 const SBSAMachineState *board = container_of(binfo, SBSAMachineState, 580 bootinfo); 581 582 *fdt_size = board->fdt_size; 583 return board->fdt; 584 } 585 586 static void sbsa_ref_init(MachineState *machine) 587 { 588 SBSAMachineState *sms = SBSA_MACHINE(machine); 589 MachineClass *mc = MACHINE_GET_CLASS(machine); 590 MemoryRegion *sysmem = get_system_memory(); 591 MemoryRegion *secure_sysmem = NULL; 592 MemoryRegion *ram = g_new(MemoryRegion, 1); 593 bool firmware_loaded; 594 const CPUArchIdList *possible_cpus; 595 int n, sbsa_max_cpus; 596 qemu_irq pic[NUM_IRQS]; 597 598 if (strcmp(machine->cpu_type, ARM_CPU_TYPE_NAME("cortex-a57"))) { 599 error_report("sbsa-ref: CPU type other than the built-in " 600 "cortex-a57 not supported"); 601 exit(1); 602 } 603 604 if (kvm_enabled()) { 605 error_report("sbsa-ref: KVM is not supported for this machine"); 606 exit(1); 607 } 608 609 /* 610 * The Secure view of the world is the same as the NonSecure, 611 * but with a few extra devices. Create it as a container region 612 * containing the system memory at low priority; any secure-only 613 * devices go in at higher priority and take precedence. 614 */ 615 secure_sysmem = g_new(MemoryRegion, 1); 616 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", 617 UINT64_MAX); 618 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); 619 620 firmware_loaded = sbsa_firmware_init(sms, sysmem, 621 secure_sysmem ?: sysmem); 622 623 if (machine->kernel_filename && firmware_loaded) { 624 error_report("sbsa-ref: No fw_cfg device on this machine, " 625 "so -kernel option is not supported when firmware loaded, " 626 "please load OS from hard disk instead"); 627 exit(1); 628 } 629 630 /* 631 * This machine has EL3 enabled, external firmware should supply PSCI 632 * implementation, so the QEMU's internal PSCI is disabled. 633 */ 634 sms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; 635 636 sbsa_max_cpus = sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE; 637 638 if (max_cpus > sbsa_max_cpus) { 639 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " 640 "supported by machine 'sbsa-ref' (%d)", 641 max_cpus, sbsa_max_cpus); 642 exit(1); 643 } 644 645 sms->smp_cpus = smp_cpus; 646 647 if (machine->ram_size > sbsa_ref_memmap[SBSA_MEM].size) { 648 error_report("sbsa-ref: cannot model more than %dGB RAM", RAMLIMIT_GB); 649 exit(1); 650 } 651 652 possible_cpus = mc->possible_cpu_arch_ids(machine); 653 for (n = 0; n < possible_cpus->len; n++) { 654 Object *cpuobj; 655 CPUState *cs; 656 657 if (n >= smp_cpus) { 658 break; 659 } 660 661 cpuobj = object_new(possible_cpus->cpus[n].type); 662 object_property_set_int(cpuobj, possible_cpus->cpus[n].arch_id, 663 "mp-affinity", NULL); 664 665 cs = CPU(cpuobj); 666 cs->cpu_index = n; 667 668 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj), 669 &error_fatal); 670 671 if (object_property_find(cpuobj, "reset-cbar", NULL)) { 672 object_property_set_int(cpuobj, 673 sbsa_ref_memmap[SBSA_CPUPERIPHS].base, 674 "reset-cbar", &error_abort); 675 } 676 677 object_property_set_link(cpuobj, OBJECT(sysmem), "memory", 678 &error_abort); 679 680 object_property_set_link(cpuobj, OBJECT(secure_sysmem), 681 "secure-memory", &error_abort); 682 683 object_property_set_bool(cpuobj, true, "realized", &error_fatal); 684 object_unref(cpuobj); 685 } 686 687 memory_region_allocate_system_memory(ram, NULL, "sbsa-ref.ram", 688 machine->ram_size); 689 memory_region_add_subregion(sysmem, sbsa_ref_memmap[SBSA_MEM].base, ram); 690 691 create_fdt(sms); 692 693 create_secure_ram(sms, secure_sysmem); 694 695 create_gic(sms, pic); 696 697 create_uart(sms, pic, SBSA_UART, sysmem, serial_hd(0)); 698 create_uart(sms, pic, SBSA_SECURE_UART, secure_sysmem, serial_hd(1)); 699 /* Second secure UART for RAS and MM from EL0 */ 700 create_uart(sms, pic, SBSA_SECURE_UART_MM, secure_sysmem, serial_hd(2)); 701 702 create_rtc(sms, pic); 703 704 create_gpio(sms, pic); 705 706 create_ahci(sms, pic); 707 708 create_ehci(sms, pic); 709 710 create_pcie(sms, pic); 711 712 sms->bootinfo.ram_size = machine->ram_size; 713 sms->bootinfo.kernel_filename = machine->kernel_filename; 714 sms->bootinfo.nb_cpus = smp_cpus; 715 sms->bootinfo.board_id = -1; 716 sms->bootinfo.loader_start = sbsa_ref_memmap[SBSA_MEM].base; 717 sms->bootinfo.get_dtb = sbsa_ref_dtb; 718 sms->bootinfo.firmware_loaded = firmware_loaded; 719 arm_load_kernel(ARM_CPU(first_cpu), &sms->bootinfo); 720 } 721 722 static uint64_t sbsa_ref_cpu_mp_affinity(SBSAMachineState *sms, int idx) 723 { 724 uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER; 725 return arm_cpu_mp_affinity(idx, clustersz); 726 } 727 728 static const CPUArchIdList *sbsa_ref_possible_cpu_arch_ids(MachineState *ms) 729 { 730 SBSAMachineState *sms = SBSA_MACHINE(ms); 731 int n; 732 733 if (ms->possible_cpus) { 734 assert(ms->possible_cpus->len == max_cpus); 735 return ms->possible_cpus; 736 } 737 738 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 739 sizeof(CPUArchId) * max_cpus); 740 ms->possible_cpus->len = max_cpus; 741 for (n = 0; n < ms->possible_cpus->len; n++) { 742 ms->possible_cpus->cpus[n].type = ms->cpu_type; 743 ms->possible_cpus->cpus[n].arch_id = 744 sbsa_ref_cpu_mp_affinity(sms, n); 745 ms->possible_cpus->cpus[n].props.has_thread_id = true; 746 ms->possible_cpus->cpus[n].props.thread_id = n; 747 } 748 return ms->possible_cpus; 749 } 750 751 static CpuInstanceProperties 752 sbsa_ref_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 753 { 754 MachineClass *mc = MACHINE_GET_CLASS(ms); 755 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 756 757 assert(cpu_index < possible_cpus->len); 758 return possible_cpus->cpus[cpu_index].props; 759 } 760 761 static int64_t 762 sbsa_ref_get_default_cpu_node_id(const MachineState *ms, int idx) 763 { 764 return idx % nb_numa_nodes; 765 } 766 767 static void sbsa_ref_instance_init(Object *obj) 768 { 769 SBSAMachineState *sms = SBSA_MACHINE(obj); 770 771 sbsa_flash_create(sms); 772 } 773 774 static void sbsa_ref_class_init(ObjectClass *oc, void *data) 775 { 776 MachineClass *mc = MACHINE_CLASS(oc); 777 778 mc->init = sbsa_ref_init; 779 mc->desc = "QEMU 'SBSA Reference' ARM Virtual Machine"; 780 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a57"); 781 mc->max_cpus = 512; 782 mc->pci_allow_0_address = true; 783 mc->minimum_page_bits = 12; 784 mc->block_default_type = IF_IDE; 785 mc->no_cdrom = 1; 786 mc->default_ram_size = 1 * GiB; 787 mc->default_cpus = 4; 788 mc->possible_cpu_arch_ids = sbsa_ref_possible_cpu_arch_ids; 789 mc->cpu_index_to_instance_props = sbsa_ref_cpu_index_to_props; 790 mc->get_default_cpu_node_id = sbsa_ref_get_default_cpu_node_id; 791 } 792 793 static const TypeInfo sbsa_ref_info = { 794 .name = TYPE_SBSA_MACHINE, 795 .parent = TYPE_MACHINE, 796 .instance_init = sbsa_ref_instance_init, 797 .class_init = sbsa_ref_class_init, 798 .instance_size = sizeof(SBSAMachineState), 799 }; 800 801 static void sbsa_ref_machine_init(void) 802 { 803 type_register_static(&sbsa_ref_info); 804 } 805 806 type_init(sbsa_ref_machine_init); 807