1 /* 2 * ARM RealView Baseboard System emulation. 3 * 4 * Copyright (c) 2006-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "sysbus.h" 11 #include "arm-misc.h" 12 #include "primecell.h" 13 #include "devices.h" 14 #include "pci.h" 15 #include "net.h" 16 #include "sysemu.h" 17 #include "boards.h" 18 #include "bitbang_i2c.h" 19 #include "blockdev.h" 20 #include "exec-memory.h" 21 22 #define SMP_BOOT_ADDR 0xe0000000 23 #define SMP_BOOTREG_ADDR 0x10000030 24 25 typedef struct { 26 SysBusDevice busdev; 27 MemoryRegion iomem; 28 bitbang_i2c_interface *bitbang; 29 int out; 30 int in; 31 } RealViewI2CState; 32 33 static uint64_t realview_i2c_read(void *opaque, target_phys_addr_t offset, 34 unsigned size) 35 { 36 RealViewI2CState *s = (RealViewI2CState *)opaque; 37 38 if (offset == 0) { 39 return (s->out & 1) | (s->in << 1); 40 } else { 41 hw_error("realview_i2c_read: Bad offset 0x%x\n", (int)offset); 42 return -1; 43 } 44 } 45 46 static void realview_i2c_write(void *opaque, target_phys_addr_t offset, 47 uint64_t value, unsigned size) 48 { 49 RealViewI2CState *s = (RealViewI2CState *)opaque; 50 51 switch (offset) { 52 case 0: 53 s->out |= value & 3; 54 break; 55 case 4: 56 s->out &= ~value; 57 break; 58 default: 59 hw_error("realview_i2c_write: Bad offset 0x%x\n", (int)offset); 60 } 61 bitbang_i2c_set(s->bitbang, BITBANG_I2C_SCL, (s->out & 1) != 0); 62 s->in = bitbang_i2c_set(s->bitbang, BITBANG_I2C_SDA, (s->out & 2) != 0); 63 } 64 65 static const MemoryRegionOps realview_i2c_ops = { 66 .read = realview_i2c_read, 67 .write = realview_i2c_write, 68 .endianness = DEVICE_NATIVE_ENDIAN, 69 }; 70 71 static int realview_i2c_init(SysBusDevice *dev) 72 { 73 RealViewI2CState *s = FROM_SYSBUS(RealViewI2CState, dev); 74 i2c_bus *bus; 75 76 bus = i2c_init_bus(&dev->qdev, "i2c"); 77 s->bitbang = bitbang_i2c_init(bus); 78 memory_region_init_io(&s->iomem, &realview_i2c_ops, s, 79 "realview-i2c", 0x1000); 80 sysbus_init_mmio(dev, &s->iomem); 81 return 0; 82 } 83 84 static void realview_i2c_class_init(ObjectClass *klass, void *data) 85 { 86 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 87 88 k->init = realview_i2c_init; 89 } 90 91 static TypeInfo realview_i2c_info = { 92 .name = "realview_i2c", 93 .parent = TYPE_SYS_BUS_DEVICE, 94 .instance_size = sizeof(RealViewI2CState), 95 .class_init = realview_i2c_class_init, 96 }; 97 98 static void realview_register_types(void) 99 { 100 type_register_static(&realview_i2c_info); 101 } 102 103 /* Board init. */ 104 105 static struct arm_boot_info realview_binfo = { 106 .smp_loader_start = SMP_BOOT_ADDR, 107 .smp_bootreg_addr = SMP_BOOTREG_ADDR, 108 }; 109 110 /* The following two lists must be consistent. */ 111 enum realview_board_type { 112 BOARD_EB, 113 BOARD_EB_MPCORE, 114 BOARD_PB_A8, 115 BOARD_PBX_A9, 116 }; 117 118 static const int realview_board_id[] = { 119 0x33b, 120 0x33b, 121 0x769, 122 0x76d 123 }; 124 125 static void realview_init(ram_addr_t ram_size, 126 const char *boot_device, 127 const char *kernel_filename, const char *kernel_cmdline, 128 const char *initrd_filename, const char *cpu_model, 129 enum realview_board_type board_type) 130 { 131 CPUState *env = NULL; 132 MemoryRegion *sysmem = get_system_memory(); 133 MemoryRegion *ram_lo = g_new(MemoryRegion, 1); 134 MemoryRegion *ram_hi = g_new(MemoryRegion, 1); 135 MemoryRegion *ram_alias = g_new(MemoryRegion, 1); 136 MemoryRegion *ram_hack = g_new(MemoryRegion, 1); 137 DeviceState *dev, *sysctl, *gpio2, *pl041; 138 SysBusDevice *busdev; 139 qemu_irq *irqp; 140 qemu_irq pic[64]; 141 qemu_irq mmc_irq[2]; 142 PCIBus *pci_bus; 143 NICInfo *nd; 144 i2c_bus *i2c; 145 int n; 146 int done_nic = 0; 147 qemu_irq cpu_irq[4]; 148 int is_mpcore = 0; 149 int is_pb = 0; 150 uint32_t proc_id = 0; 151 uint32_t sys_id; 152 ram_addr_t low_ram_size; 153 154 switch (board_type) { 155 case BOARD_EB: 156 break; 157 case BOARD_EB_MPCORE: 158 is_mpcore = 1; 159 break; 160 case BOARD_PB_A8: 161 is_pb = 1; 162 break; 163 case BOARD_PBX_A9: 164 is_mpcore = 1; 165 is_pb = 1; 166 break; 167 } 168 for (n = 0; n < smp_cpus; n++) { 169 env = cpu_init(cpu_model); 170 if (!env) { 171 fprintf(stderr, "Unable to find CPU definition\n"); 172 exit(1); 173 } 174 irqp = arm_pic_init_cpu(env); 175 cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ]; 176 } 177 if (arm_feature(env, ARM_FEATURE_V7)) { 178 if (is_mpcore) { 179 proc_id = 0x0c000000; 180 } else { 181 proc_id = 0x0e000000; 182 } 183 } else if (arm_feature(env, ARM_FEATURE_V6K)) { 184 proc_id = 0x06000000; 185 } else if (arm_feature(env, ARM_FEATURE_V6)) { 186 proc_id = 0x04000000; 187 } else { 188 proc_id = 0x02000000; 189 } 190 191 if (is_pb && ram_size > 0x20000000) { 192 /* Core tile RAM. */ 193 low_ram_size = ram_size - 0x20000000; 194 ram_size = 0x20000000; 195 memory_region_init_ram(ram_lo, "realview.lowmem", low_ram_size); 196 vmstate_register_ram_global(ram_lo); 197 memory_region_add_subregion(sysmem, 0x20000000, ram_lo); 198 } 199 200 memory_region_init_ram(ram_hi, "realview.highmem", ram_size); 201 vmstate_register_ram_global(ram_hi); 202 low_ram_size = ram_size; 203 if (low_ram_size > 0x10000000) 204 low_ram_size = 0x10000000; 205 /* SDRAM at address zero. */ 206 memory_region_init_alias(ram_alias, "realview.alias", 207 ram_hi, 0, low_ram_size); 208 memory_region_add_subregion(sysmem, 0, ram_alias); 209 if (is_pb) { 210 /* And again at a high address. */ 211 memory_region_add_subregion(sysmem, 0x70000000, ram_hi); 212 } else { 213 ram_size = low_ram_size; 214 } 215 216 sys_id = is_pb ? 0x01780500 : 0xc1400400; 217 sysctl = qdev_create(NULL, "realview_sysctl"); 218 qdev_prop_set_uint32(sysctl, "sys_id", sys_id); 219 qdev_prop_set_uint32(sysctl, "proc_id", proc_id); 220 qdev_init_nofail(sysctl); 221 sysbus_mmio_map(sysbus_from_qdev(sysctl), 0, 0x10000000); 222 223 if (is_mpcore) { 224 target_phys_addr_t periphbase; 225 dev = qdev_create(NULL, is_pb ? "a9mpcore_priv": "realview_mpcore"); 226 qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); 227 qdev_init_nofail(dev); 228 busdev = sysbus_from_qdev(dev); 229 if (is_pb) { 230 periphbase = 0x1f000000; 231 } else { 232 periphbase = 0x10100000; 233 } 234 sysbus_mmio_map(busdev, 0, periphbase); 235 for (n = 0; n < smp_cpus; n++) { 236 sysbus_connect_irq(busdev, n, cpu_irq[n]); 237 } 238 sysbus_create_varargs("l2x0", periphbase + 0x2000, NULL); 239 /* Both A9 and 11MPCore put the GIC CPU i/f at base + 0x100 */ 240 realview_binfo.gic_cpu_if_addr = periphbase + 0x100; 241 } else { 242 uint32_t gic_addr = is_pb ? 0x1e000000 : 0x10040000; 243 /* For now just create the nIRQ GIC, and ignore the others. */ 244 dev = sysbus_create_simple("realview_gic", gic_addr, cpu_irq[0]); 245 } 246 for (n = 0; n < 64; n++) { 247 pic[n] = qdev_get_gpio_in(dev, n); 248 } 249 250 pl041 = qdev_create(NULL, "pl041"); 251 qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512); 252 qdev_init_nofail(pl041); 253 sysbus_mmio_map(sysbus_from_qdev(pl041), 0, 0x10004000); 254 sysbus_connect_irq(sysbus_from_qdev(pl041), 0, pic[19]); 255 256 sysbus_create_simple("pl050_keyboard", 0x10006000, pic[20]); 257 sysbus_create_simple("pl050_mouse", 0x10007000, pic[21]); 258 259 sysbus_create_simple("pl011", 0x10009000, pic[12]); 260 sysbus_create_simple("pl011", 0x1000a000, pic[13]); 261 sysbus_create_simple("pl011", 0x1000b000, pic[14]); 262 sysbus_create_simple("pl011", 0x1000c000, pic[15]); 263 264 /* DMA controller is optional, apparently. */ 265 sysbus_create_simple("pl081", 0x10030000, pic[24]); 266 267 sysbus_create_simple("sp804", 0x10011000, pic[4]); 268 sysbus_create_simple("sp804", 0x10012000, pic[5]); 269 270 sysbus_create_simple("pl061", 0x10013000, pic[6]); 271 sysbus_create_simple("pl061", 0x10014000, pic[7]); 272 gpio2 = sysbus_create_simple("pl061", 0x10015000, pic[8]); 273 274 sysbus_create_simple("pl111", 0x10020000, pic[23]); 275 276 dev = sysbus_create_varargs("pl181", 0x10005000, pic[17], pic[18], NULL); 277 /* Wire up MMC card detect and read-only signals. These have 278 * to go to both the PL061 GPIO and the sysctl register. 279 * Note that the PL181 orders these lines (readonly,inserted) 280 * and the PL061 has them the other way about. Also the card 281 * detect line is inverted. 282 */ 283 mmc_irq[0] = qemu_irq_split( 284 qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT), 285 qdev_get_gpio_in(gpio2, 1)); 286 mmc_irq[1] = qemu_irq_split( 287 qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN), 288 qemu_irq_invert(qdev_get_gpio_in(gpio2, 0))); 289 qdev_connect_gpio_out(dev, 0, mmc_irq[0]); 290 qdev_connect_gpio_out(dev, 1, mmc_irq[1]); 291 292 sysbus_create_simple("pl031", 0x10017000, pic[10]); 293 294 if (!is_pb) { 295 dev = qdev_create(NULL, "realview_pci"); 296 busdev = sysbus_from_qdev(dev); 297 qdev_init_nofail(dev); 298 sysbus_mmio_map(busdev, 0, 0x61000000); /* PCI self-config */ 299 sysbus_mmio_map(busdev, 1, 0x62000000); /* PCI config */ 300 sysbus_mmio_map(busdev, 2, 0x63000000); /* PCI I/O */ 301 sysbus_connect_irq(busdev, 0, pic[48]); 302 sysbus_connect_irq(busdev, 1, pic[49]); 303 sysbus_connect_irq(busdev, 2, pic[50]); 304 sysbus_connect_irq(busdev, 3, pic[51]); 305 pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci"); 306 if (usb_enabled) { 307 pci_create_simple(pci_bus, -1, "pci-ohci"); 308 } 309 n = drive_get_max_bus(IF_SCSI); 310 while (n >= 0) { 311 pci_create_simple(pci_bus, -1, "lsi53c895a"); 312 n--; 313 } 314 } 315 for(n = 0; n < nb_nics; n++) { 316 nd = &nd_table[n]; 317 318 if (!done_nic && (!nd->model || 319 strcmp(nd->model, is_pb ? "lan9118" : "smc91c111") == 0)) { 320 if (is_pb) { 321 lan9118_init(nd, 0x4e000000, pic[28]); 322 } else { 323 smc91c111_init(nd, 0x4e000000, pic[28]); 324 } 325 done_nic = 1; 326 } else { 327 pci_nic_init_nofail(nd, "rtl8139", NULL); 328 } 329 } 330 331 dev = sysbus_create_simple("realview_i2c", 0x10002000, NULL); 332 i2c = (i2c_bus *)qdev_get_child_bus(dev, "i2c"); 333 i2c_create_slave(i2c, "ds1338", 0x68); 334 335 /* Memory map for RealView Emulation Baseboard: */ 336 /* 0x10000000 System registers. */ 337 /* 0x10001000 System controller. */ 338 /* 0x10002000 Two-Wire Serial Bus. */ 339 /* 0x10003000 Reserved. */ 340 /* 0x10004000 AACI. */ 341 /* 0x10005000 MCI. */ 342 /* 0x10006000 KMI0. */ 343 /* 0x10007000 KMI1. */ 344 /* 0x10008000 Character LCD. (EB) */ 345 /* 0x10009000 UART0. */ 346 /* 0x1000a000 UART1. */ 347 /* 0x1000b000 UART2. */ 348 /* 0x1000c000 UART3. */ 349 /* 0x1000d000 SSPI. */ 350 /* 0x1000e000 SCI. */ 351 /* 0x1000f000 Reserved. */ 352 /* 0x10010000 Watchdog. */ 353 /* 0x10011000 Timer 0+1. */ 354 /* 0x10012000 Timer 2+3. */ 355 /* 0x10013000 GPIO 0. */ 356 /* 0x10014000 GPIO 1. */ 357 /* 0x10015000 GPIO 2. */ 358 /* 0x10002000 Two-Wire Serial Bus - DVI. (PB) */ 359 /* 0x10017000 RTC. */ 360 /* 0x10018000 DMC. */ 361 /* 0x10019000 PCI controller config. */ 362 /* 0x10020000 CLCD. */ 363 /* 0x10030000 DMA Controller. */ 364 /* 0x10040000 GIC1. (EB) */ 365 /* 0x10050000 GIC2. (EB) */ 366 /* 0x10060000 GIC3. (EB) */ 367 /* 0x10070000 GIC4. (EB) */ 368 /* 0x10080000 SMC. */ 369 /* 0x1e000000 GIC1. (PB) */ 370 /* 0x1e001000 GIC2. (PB) */ 371 /* 0x1e002000 GIC3. (PB) */ 372 /* 0x1e003000 GIC4. (PB) */ 373 /* 0x40000000 NOR flash. */ 374 /* 0x44000000 DoC flash. */ 375 /* 0x48000000 SRAM. */ 376 /* 0x4c000000 Configuration flash. */ 377 /* 0x4e000000 Ethernet. */ 378 /* 0x4f000000 USB. */ 379 /* 0x50000000 PISMO. */ 380 /* 0x54000000 PISMO. */ 381 /* 0x58000000 PISMO. */ 382 /* 0x5c000000 PISMO. */ 383 /* 0x60000000 PCI. */ 384 /* 0x61000000 PCI Self Config. */ 385 /* 0x62000000 PCI Config. */ 386 /* 0x63000000 PCI IO. */ 387 /* 0x64000000 PCI mem 0. */ 388 /* 0x68000000 PCI mem 1. */ 389 /* 0x6c000000 PCI mem 2. */ 390 391 /* ??? Hack to map an additional page of ram for the secondary CPU 392 startup code. I guess this works on real hardware because the 393 BootROM happens to be in ROM/flash or in memory that isn't clobbered 394 until after Linux boots the secondary CPUs. */ 395 memory_region_init_ram(ram_hack, "realview.hack", 0x1000); 396 vmstate_register_ram_global(ram_hack); 397 memory_region_add_subregion(sysmem, SMP_BOOT_ADDR, ram_hack); 398 399 realview_binfo.ram_size = ram_size; 400 realview_binfo.kernel_filename = kernel_filename; 401 realview_binfo.kernel_cmdline = kernel_cmdline; 402 realview_binfo.initrd_filename = initrd_filename; 403 realview_binfo.nb_cpus = smp_cpus; 404 realview_binfo.board_id = realview_board_id[board_type]; 405 realview_binfo.loader_start = (board_type == BOARD_PB_A8 ? 0x70000000 : 0); 406 arm_load_kernel(first_cpu, &realview_binfo); 407 } 408 409 static void realview_eb_init(ram_addr_t ram_size, 410 const char *boot_device, 411 const char *kernel_filename, const char *kernel_cmdline, 412 const char *initrd_filename, const char *cpu_model) 413 { 414 if (!cpu_model) { 415 cpu_model = "arm926"; 416 } 417 realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline, 418 initrd_filename, cpu_model, BOARD_EB); 419 } 420 421 static void realview_eb_mpcore_init(ram_addr_t ram_size, 422 const char *boot_device, 423 const char *kernel_filename, const char *kernel_cmdline, 424 const char *initrd_filename, const char *cpu_model) 425 { 426 if (!cpu_model) { 427 cpu_model = "arm11mpcore"; 428 } 429 realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline, 430 initrd_filename, cpu_model, BOARD_EB_MPCORE); 431 } 432 433 static void realview_pb_a8_init(ram_addr_t ram_size, 434 const char *boot_device, 435 const char *kernel_filename, const char *kernel_cmdline, 436 const char *initrd_filename, const char *cpu_model) 437 { 438 if (!cpu_model) { 439 cpu_model = "cortex-a8"; 440 } 441 realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline, 442 initrd_filename, cpu_model, BOARD_PB_A8); 443 } 444 445 static void realview_pbx_a9_init(ram_addr_t ram_size, 446 const char *boot_device, 447 const char *kernel_filename, const char *kernel_cmdline, 448 const char *initrd_filename, const char *cpu_model) 449 { 450 if (!cpu_model) { 451 cpu_model = "cortex-a9"; 452 } 453 realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline, 454 initrd_filename, cpu_model, BOARD_PBX_A9); 455 } 456 457 static QEMUMachine realview_eb_machine = { 458 .name = "realview-eb", 459 .desc = "ARM RealView Emulation Baseboard (ARM926EJ-S)", 460 .init = realview_eb_init, 461 .use_scsi = 1, 462 }; 463 464 static QEMUMachine realview_eb_mpcore_machine = { 465 .name = "realview-eb-mpcore", 466 .desc = "ARM RealView Emulation Baseboard (ARM11MPCore)", 467 .init = realview_eb_mpcore_init, 468 .use_scsi = 1, 469 .max_cpus = 4, 470 }; 471 472 static QEMUMachine realview_pb_a8_machine = { 473 .name = "realview-pb-a8", 474 .desc = "ARM RealView Platform Baseboard for Cortex-A8", 475 .init = realview_pb_a8_init, 476 }; 477 478 static QEMUMachine realview_pbx_a9_machine = { 479 .name = "realview-pbx-a9", 480 .desc = "ARM RealView Platform Baseboard Explore for Cortex-A9", 481 .init = realview_pbx_a9_init, 482 .use_scsi = 1, 483 .max_cpus = 4, 484 }; 485 486 static void realview_machine_init(void) 487 { 488 qemu_register_machine(&realview_eb_machine); 489 qemu_register_machine(&realview_eb_mpcore_machine); 490 qemu_register_machine(&realview_pb_a8_machine); 491 qemu_register_machine(&realview_pbx_a9_machine); 492 } 493 494 machine_init(realview_machine_init); 495 type_init(realview_register_types) 496