1 /* 2 * Raspberry Pi emulation (c) 2012 Gregory Estrade 3 * Upstreaming code cleanup [including bcm2835_*] (c) 2013 Jan Petrous 4 * 5 * Rasperry Pi 2 emulation Copyright (c) 2015, Microsoft 6 * Written by Andrew Baumann 7 * 8 * Raspberry Pi 3 emulation Copyright (c) 2018 Zoltán Baldaszti 9 * Upstream code cleanup (c) 2018 Pekka Enberg 10 * 11 * This work is licensed under the terms of the GNU GPL, version 2 or later. 12 * See the COPYING file in the top-level directory. 13 */ 14 15 #include "qemu/osdep.h" 16 #include "qemu/units.h" 17 #include "qemu/cutils.h" 18 #include "qapi/error.h" 19 #include "cpu.h" 20 #include "hw/arm/bcm2836.h" 21 #include "hw/registerfields.h" 22 #include "qemu/error-report.h" 23 #include "hw/boards.h" 24 #include "hw/loader.h" 25 #include "hw/arm/boot.h" 26 #include "qom/object.h" 27 28 #define SMPBOOT_ADDR 0x300 /* this should leave enough space for ATAGS */ 29 #define MVBAR_ADDR 0x400 /* secure vectors */ 30 #define BOARDSETUP_ADDR (MVBAR_ADDR + 0x20) /* board setup code */ 31 #define FIRMWARE_ADDR_2 0x8000 /* Pi 2 loads kernel.img here by default */ 32 #define FIRMWARE_ADDR_3 0x80000 /* Pi 3 loads kernel.img here by default */ 33 #define SPINTABLE_ADDR 0xd8 /* Pi 3 bootloader spintable */ 34 35 /* Registered machine type (matches RPi Foundation bootloader and U-Boot) */ 36 #define MACH_TYPE_BCM2708 3138 37 38 struct RaspiMachineState { 39 /*< private >*/ 40 MachineState parent_obj; 41 /*< public >*/ 42 BCM283XState soc; 43 struct arm_boot_info binfo; 44 }; 45 typedef struct RaspiMachineState RaspiMachineState; 46 47 struct RaspiMachineClass { 48 /*< private >*/ 49 MachineClass parent_obj; 50 /*< public >*/ 51 uint32_t board_rev; 52 }; 53 typedef struct RaspiMachineClass RaspiMachineClass; 54 55 #define TYPE_RASPI_MACHINE MACHINE_TYPE_NAME("raspi-common") 56 DECLARE_OBJ_CHECKERS(RaspiMachineState, RaspiMachineClass, 57 RASPI_MACHINE, TYPE_RASPI_MACHINE) 58 59 60 /* 61 * Board revision codes: 62 * www.raspberrypi.org/documentation/hardware/raspberrypi/revision-codes/ 63 */ 64 FIELD(REV_CODE, REVISION, 0, 4); 65 FIELD(REV_CODE, TYPE, 4, 8); 66 FIELD(REV_CODE, PROCESSOR, 12, 4); 67 FIELD(REV_CODE, MANUFACTURER, 16, 4); 68 FIELD(REV_CODE, MEMORY_SIZE, 20, 3); 69 FIELD(REV_CODE, STYLE, 23, 1); 70 71 typedef enum RaspiProcessorId { 72 PROCESSOR_ID_BCM2835 = 0, 73 PROCESSOR_ID_BCM2836 = 1, 74 PROCESSOR_ID_BCM2837 = 2, 75 } RaspiProcessorId; 76 77 static const struct { 78 const char *type; 79 int cores_count; 80 } soc_property[] = { 81 [PROCESSOR_ID_BCM2835] = {TYPE_BCM2835, 1}, 82 [PROCESSOR_ID_BCM2836] = {TYPE_BCM2836, BCM283X_NCPUS}, 83 [PROCESSOR_ID_BCM2837] = {TYPE_BCM2837, BCM283X_NCPUS}, 84 }; 85 86 static uint64_t board_ram_size(uint32_t board_rev) 87 { 88 assert(FIELD_EX32(board_rev, REV_CODE, STYLE)); /* Only new style */ 89 return 256 * MiB << FIELD_EX32(board_rev, REV_CODE, MEMORY_SIZE); 90 } 91 92 static RaspiProcessorId board_processor_id(uint32_t board_rev) 93 { 94 int proc_id = FIELD_EX32(board_rev, REV_CODE, PROCESSOR); 95 96 assert(FIELD_EX32(board_rev, REV_CODE, STYLE)); /* Only new style */ 97 assert(proc_id < ARRAY_SIZE(soc_property) && soc_property[proc_id].type); 98 99 return proc_id; 100 } 101 102 static const char *board_soc_type(uint32_t board_rev) 103 { 104 return soc_property[board_processor_id(board_rev)].type; 105 } 106 107 static int cores_count(uint32_t board_rev) 108 { 109 return soc_property[board_processor_id(board_rev)].cores_count; 110 } 111 112 static const char *board_type(uint32_t board_rev) 113 { 114 static const char *types[] = { 115 "A", "B", "A+", "B+", "2B", "Alpha", "CM1", NULL, "3B", "Zero", 116 "CM3", NULL, "Zero W", "3B+", "3A+", NULL, "CM3+", "4B", 117 }; 118 assert(FIELD_EX32(board_rev, REV_CODE, STYLE)); /* Only new style */ 119 int bt = FIELD_EX32(board_rev, REV_CODE, TYPE); 120 if (bt >= ARRAY_SIZE(types) || !types[bt]) { 121 return "Unknown"; 122 } 123 return types[bt]; 124 } 125 126 static void write_smpboot(ARMCPU *cpu, const struct arm_boot_info *info) 127 { 128 static const uint32_t smpboot[] = { 129 0xe1a0e00f, /* mov lr, pc */ 130 0xe3a0fe00 + (BOARDSETUP_ADDR >> 4), /* mov pc, BOARDSETUP_ADDR */ 131 0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5;get core ID */ 132 0xe7e10050, /* ubfx r0, r0, #0, #2 ;extract LSB */ 133 0xe59f5014, /* ldr r5, =0x400000CC ;load mbox base */ 134 0xe320f001, /* 1: yield */ 135 0xe7953200, /* ldr r3, [r5, r0, lsl #4] ;read mbox for our core*/ 136 0xe3530000, /* cmp r3, #0 ;spin while zero */ 137 0x0afffffb, /* beq 1b */ 138 0xe7853200, /* str r3, [r5, r0, lsl #4] ;clear mbox */ 139 0xe12fff13, /* bx r3 ;jump to target */ 140 0x400000cc, /* (constant: mailbox 3 read/clear base) */ 141 }; 142 143 /* check that we don't overrun board setup vectors */ 144 QEMU_BUILD_BUG_ON(SMPBOOT_ADDR + sizeof(smpboot) > MVBAR_ADDR); 145 /* check that board setup address is correctly relocated */ 146 QEMU_BUILD_BUG_ON((BOARDSETUP_ADDR & 0xf) != 0 147 || (BOARDSETUP_ADDR >> 4) >= 0x100); 148 149 rom_add_blob_fixed_as("raspi_smpboot", smpboot, sizeof(smpboot), 150 info->smp_loader_start, 151 arm_boot_address_space(cpu, info)); 152 } 153 154 static void write_smpboot64(ARMCPU *cpu, const struct arm_boot_info *info) 155 { 156 AddressSpace *as = arm_boot_address_space(cpu, info); 157 /* Unlike the AArch32 version we don't need to call the board setup hook. 158 * The mechanism for doing the spin-table is also entirely different. 159 * We must have four 64-bit fields at absolute addresses 160 * 0xd8, 0xe0, 0xe8, 0xf0 in RAM, which are the flag variables for 161 * our CPUs, and which we must ensure are zero initialized before 162 * the primary CPU goes into the kernel. We put these variables inside 163 * a rom blob, so that the reset for ROM contents zeroes them for us. 164 */ 165 static const uint32_t smpboot[] = { 166 0xd2801b05, /* mov x5, 0xd8 */ 167 0xd53800a6, /* mrs x6, mpidr_el1 */ 168 0x924004c6, /* and x6, x6, #0x3 */ 169 0xd503205f, /* spin: wfe */ 170 0xf86678a4, /* ldr x4, [x5,x6,lsl #3] */ 171 0xb4ffffc4, /* cbz x4, spin */ 172 0xd2800000, /* mov x0, #0x0 */ 173 0xd2800001, /* mov x1, #0x0 */ 174 0xd2800002, /* mov x2, #0x0 */ 175 0xd2800003, /* mov x3, #0x0 */ 176 0xd61f0080, /* br x4 */ 177 }; 178 179 static const uint64_t spintables[] = { 180 0, 0, 0, 0 181 }; 182 183 rom_add_blob_fixed_as("raspi_smpboot", smpboot, sizeof(smpboot), 184 info->smp_loader_start, as); 185 rom_add_blob_fixed_as("raspi_spintables", spintables, sizeof(spintables), 186 SPINTABLE_ADDR, as); 187 } 188 189 static void write_board_setup(ARMCPU *cpu, const struct arm_boot_info *info) 190 { 191 arm_write_secure_board_setup_dummy_smc(cpu, info, MVBAR_ADDR); 192 } 193 194 static void reset_secondary(ARMCPU *cpu, const struct arm_boot_info *info) 195 { 196 CPUState *cs = CPU(cpu); 197 cpu_set_pc(cs, info->smp_loader_start); 198 } 199 200 static void setup_boot(MachineState *machine, RaspiProcessorId processor_id, 201 size_t ram_size) 202 { 203 RaspiMachineState *s = RASPI_MACHINE(machine); 204 int r; 205 206 s->binfo.board_id = MACH_TYPE_BCM2708; 207 s->binfo.ram_size = ram_size; 208 s->binfo.nb_cpus = machine->smp.cpus; 209 210 if (processor_id <= PROCESSOR_ID_BCM2836) { 211 /* 212 * The BCM2835 and BCM2836 require some custom setup code to run 213 * in Secure mode before booting a kernel (to set up the SMC vectors 214 * so that we get a no-op SMC; this is used by Linux to call the 215 * firmware for some cache maintenance operations. 216 * The BCM2837 doesn't need this. 217 */ 218 s->binfo.board_setup_addr = BOARDSETUP_ADDR; 219 s->binfo.write_board_setup = write_board_setup; 220 s->binfo.secure_board_setup = true; 221 s->binfo.secure_boot = true; 222 } 223 224 /* BCM2836 and BCM2837 requires SMP setup */ 225 if (processor_id >= PROCESSOR_ID_BCM2836) { 226 s->binfo.smp_loader_start = SMPBOOT_ADDR; 227 if (processor_id == PROCESSOR_ID_BCM2836) { 228 s->binfo.write_secondary_boot = write_smpboot; 229 } else { 230 s->binfo.write_secondary_boot = write_smpboot64; 231 } 232 s->binfo.secondary_cpu_reset_hook = reset_secondary; 233 } 234 235 /* If the user specified a "firmware" image (e.g. UEFI), we bypass 236 * the normal Linux boot process 237 */ 238 if (machine->firmware) { 239 hwaddr firmware_addr = processor_id <= PROCESSOR_ID_BCM2836 240 ? FIRMWARE_ADDR_2 : FIRMWARE_ADDR_3; 241 /* load the firmware image (typically kernel.img) */ 242 r = load_image_targphys(machine->firmware, firmware_addr, 243 ram_size - firmware_addr); 244 if (r < 0) { 245 error_report("Failed to load firmware from %s", machine->firmware); 246 exit(1); 247 } 248 249 s->binfo.entry = firmware_addr; 250 s->binfo.firmware_loaded = true; 251 } 252 253 arm_load_kernel(&s->soc.cpu[0].core, machine, &s->binfo); 254 } 255 256 static void raspi_machine_init(MachineState *machine) 257 { 258 RaspiMachineClass *mc = RASPI_MACHINE_GET_CLASS(machine); 259 RaspiMachineState *s = RASPI_MACHINE(machine); 260 uint32_t board_rev = mc->board_rev; 261 uint64_t ram_size = board_ram_size(board_rev); 262 uint32_t vcram_size; 263 DriveInfo *di; 264 BlockBackend *blk; 265 BusState *bus; 266 DeviceState *carddev; 267 268 if (machine->ram_size != ram_size) { 269 char *size_str = size_to_str(ram_size); 270 error_report("Invalid RAM size, should be %s", size_str); 271 g_free(size_str); 272 exit(1); 273 } 274 275 /* FIXME: Remove when we have custom CPU address space support */ 276 memory_region_add_subregion_overlap(get_system_memory(), 0, 277 machine->ram, 0); 278 279 /* Setup the SOC */ 280 object_initialize_child(OBJECT(machine), "soc", &s->soc, 281 board_soc_type(board_rev)); 282 object_property_add_const_link(OBJECT(&s->soc), "ram", OBJECT(machine->ram)); 283 object_property_set_int(OBJECT(&s->soc), "board-rev", board_rev, 284 &error_abort); 285 qdev_realize(DEVICE(&s->soc), NULL, &error_abort); 286 287 /* Create and plug in the SD cards */ 288 di = drive_get_next(IF_SD); 289 blk = di ? blk_by_legacy_dinfo(di) : NULL; 290 bus = qdev_get_child_bus(DEVICE(&s->soc), "sd-bus"); 291 if (bus == NULL) { 292 error_report("No SD bus found in SOC object"); 293 exit(1); 294 } 295 carddev = qdev_new(TYPE_SD_CARD); 296 qdev_prop_set_drive_err(carddev, "drive", blk, &error_fatal); 297 qdev_realize_and_unref(carddev, bus, &error_fatal); 298 299 vcram_size = object_property_get_uint(OBJECT(&s->soc), "vcram-size", 300 &error_abort); 301 setup_boot(machine, board_processor_id(mc->board_rev), 302 machine->ram_size - vcram_size); 303 } 304 305 static void raspi_machine_class_common_init(MachineClass *mc, 306 uint32_t board_rev) 307 { 308 mc->desc = g_strdup_printf("Raspberry Pi %s (revision 1.%u)", 309 board_type(board_rev), 310 FIELD_EX32(board_rev, REV_CODE, REVISION)); 311 mc->init = raspi_machine_init; 312 mc->block_default_type = IF_SD; 313 mc->no_parallel = 1; 314 mc->no_floppy = 1; 315 mc->no_cdrom = 1; 316 mc->default_cpus = mc->min_cpus = mc->max_cpus = cores_count(board_rev); 317 mc->default_ram_size = board_ram_size(board_rev); 318 mc->default_ram_id = "ram"; 319 }; 320 321 static void raspi0_machine_class_init(ObjectClass *oc, void *data) 322 { 323 MachineClass *mc = MACHINE_CLASS(oc); 324 RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc); 325 326 rmc->board_rev = 0x920092; /* Revision 1.2 */ 327 raspi_machine_class_common_init(mc, rmc->board_rev); 328 }; 329 330 static void raspi1ap_machine_class_init(ObjectClass *oc, void *data) 331 { 332 MachineClass *mc = MACHINE_CLASS(oc); 333 RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc); 334 335 rmc->board_rev = 0x900021; /* Revision 1.1 */ 336 raspi_machine_class_common_init(mc, rmc->board_rev); 337 }; 338 339 static void raspi2b_machine_class_init(ObjectClass *oc, void *data) 340 { 341 MachineClass *mc = MACHINE_CLASS(oc); 342 RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc); 343 344 mc->alias = "raspi2"; 345 rmc->board_rev = 0xa21041; 346 raspi_machine_class_common_init(mc, rmc->board_rev); 347 }; 348 349 #ifdef TARGET_AARCH64 350 static void raspi3ap_machine_class_init(ObjectClass *oc, void *data) 351 { 352 MachineClass *mc = MACHINE_CLASS(oc); 353 RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc); 354 355 rmc->board_rev = 0x9020e0; /* Revision 1.0 */ 356 raspi_machine_class_common_init(mc, rmc->board_rev); 357 }; 358 359 static void raspi3b_machine_class_init(ObjectClass *oc, void *data) 360 { 361 MachineClass *mc = MACHINE_CLASS(oc); 362 RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc); 363 364 mc->alias = "raspi3"; 365 rmc->board_rev = 0xa02082; 366 raspi_machine_class_common_init(mc, rmc->board_rev); 367 }; 368 #endif /* TARGET_AARCH64 */ 369 370 static const TypeInfo raspi_machine_types[] = { 371 { 372 .name = MACHINE_TYPE_NAME("raspi0"), 373 .parent = TYPE_RASPI_MACHINE, 374 .class_init = raspi0_machine_class_init, 375 }, { 376 .name = MACHINE_TYPE_NAME("raspi1ap"), 377 .parent = TYPE_RASPI_MACHINE, 378 .class_init = raspi1ap_machine_class_init, 379 }, { 380 .name = MACHINE_TYPE_NAME("raspi2b"), 381 .parent = TYPE_RASPI_MACHINE, 382 .class_init = raspi2b_machine_class_init, 383 #ifdef TARGET_AARCH64 384 }, { 385 .name = MACHINE_TYPE_NAME("raspi3ap"), 386 .parent = TYPE_RASPI_MACHINE, 387 .class_init = raspi3ap_machine_class_init, 388 }, { 389 .name = MACHINE_TYPE_NAME("raspi3b"), 390 .parent = TYPE_RASPI_MACHINE, 391 .class_init = raspi3b_machine_class_init, 392 #endif 393 }, { 394 .name = TYPE_RASPI_MACHINE, 395 .parent = TYPE_MACHINE, 396 .instance_size = sizeof(RaspiMachineState), 397 .class_size = sizeof(RaspiMachineClass), 398 .abstract = true, 399 } 400 }; 401 402 DEFINE_TYPES(raspi_machine_types) 403