1 /* omap_sx1.c Support for the Siemens SX1 smartphone emulation. 2 * 3 * Copyright (C) 2008 4 * Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> 5 * Copyright (C) 2007 Vladimir Ananiev <vovan888@gmail.com> 6 * 7 * based on PalmOne's (TM) PDAs support (palm.c) 8 */ 9 10 /* 11 * PalmOne's (TM) PDAs. 12 * 13 * Copyright (C) 2006-2007 Andrzej Zaborowski <balrog@zabor.org> 14 * 15 * This program is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License as 17 * published by the Free Software Foundation; either version 2 of 18 * the License, or (at your option) any later version. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * You should have received a copy of the GNU General Public License along 26 * with this program; if not, write to the Free Software Foundation, Inc., 27 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 28 */ 29 #include "hw.h" 30 #include "sysemu.h" 31 #include "console.h" 32 #include "omap.h" 33 #include "boards.h" 34 #include "arm-misc.h" 35 #include "flash.h" 36 37 /*****************************************************************************/ 38 /* Siemens SX1 Cellphone V1 */ 39 /* - ARM OMAP310 processor 40 * - SRAM 192 kB 41 * - SDRAM 32 MB at 0x10000000 42 * - Boot flash 16 MB at 0x00000000 43 * - Application flash 8 MB at 0x04000000 44 * - 3 serial ports 45 * - 1 SecureDigital 46 * - 1 LCD display 47 * - 1 RTC 48 */ 49 50 /*****************************************************************************/ 51 /* Siemens SX1 Cellphone V2 */ 52 /* - ARM OMAP310 processor 53 * - SRAM 192 kB 54 * - SDRAM 32 MB at 0x10000000 55 * - Boot flash 32 MB at 0x00000000 56 * - 3 serial ports 57 * - 1 SecureDigital 58 * - 1 LCD display 59 * - 1 RTC 60 */ 61 62 static uint32_t static_readb(void *opaque, target_phys_addr_t offset) 63 { 64 uint32_t *val = (uint32_t *) opaque; 65 66 return *val >> ((offset & 3) << 3); 67 } 68 69 static uint32_t static_readh(void *opaque, target_phys_addr_t offset) 70 { 71 uint32_t *val = (uint32_t *) opaque; 72 73 return *val >> ((offset & 1) << 3); 74 } 75 76 static uint32_t static_readw(void *opaque, target_phys_addr_t offset) 77 { 78 uint32_t *val = (uint32_t *) opaque; 79 80 return *val >> ((offset & 0) << 3); 81 } 82 83 static void static_write(void *opaque, target_phys_addr_t offset, 84 uint32_t value) 85 { 86 #ifdef SPY 87 printf("%s: value %08lx written at " PA_FMT "\n", 88 __FUNCTION__, value, offset); 89 #endif 90 } 91 92 static CPUReadMemoryFunc *static_readfn[] = { 93 static_readb, 94 static_readh, 95 static_readw, 96 }; 97 98 static CPUWriteMemoryFunc *static_writefn[] = { 99 static_write, 100 static_write, 101 static_write, 102 }; 103 104 #define sdram_size 0x02000000 105 #define sector_size (128 * 1024) 106 #define flash0_size (16 * 1024 * 1024) 107 #define flash1_size ( 8 * 1024 * 1024) 108 #define flash2_size (32 * 1024 * 1024) 109 #define total_ram_v1 (sdram_size + flash0_size + flash1_size + OMAP15XX_SRAM_SIZE) 110 #define total_ram_v2 (sdram_size + flash2_size + OMAP15XX_SRAM_SIZE) 111 112 static struct arm_boot_info sx1_binfo = { 113 .loader_start = OMAP_EMIFF_BASE, 114 .ram_size = sdram_size, 115 .board_id = 0x265, 116 }; 117 118 static void sx1_init(ram_addr_t ram_size, int vga_ram_size, 119 const char *boot_device, 120 const char *kernel_filename, const char *kernel_cmdline, 121 const char *initrd_filename, const char *cpu_model, 122 const int version) 123 { 124 struct omap_mpu_state_s *cpu; 125 int io; 126 static uint32_t cs0val = 0x00213090; 127 static uint32_t cs1val = 0x00215070; 128 static uint32_t cs2val = 0x00001139; 129 static uint32_t cs3val = 0x00001139; 130 ram_addr_t phys_flash; 131 int index; 132 int fl_idx; 133 uint32_t flash_size = flash0_size; 134 135 if (version == 2) { 136 flash_size = flash2_size; 137 } 138 139 cpu = omap310_mpu_init(sx1_binfo.ram_size, cpu_model); 140 141 /* External Flash (EMIFS) */ 142 cpu_register_physical_memory(OMAP_CS0_BASE, flash_size, 143 (phys_flash = qemu_ram_alloc(flash_size)) | IO_MEM_ROM); 144 145 io = cpu_register_io_memory(0, static_readfn, static_writefn, &cs0val); 146 cpu_register_physical_memory(OMAP_CS0_BASE + flash_size, 147 OMAP_CS0_SIZE - flash_size, io); 148 io = cpu_register_io_memory(0, static_readfn, static_writefn, &cs2val); 149 cpu_register_physical_memory(OMAP_CS2_BASE, OMAP_CS2_SIZE, io); 150 io = cpu_register_io_memory(0, static_readfn, static_writefn, &cs3val); 151 cpu_register_physical_memory(OMAP_CS3_BASE, OMAP_CS3_SIZE, io); 152 153 fl_idx = 0; 154 155 if ((index = drive_get_index(IF_PFLASH, 0, fl_idx)) > -1) { 156 if (!pflash_cfi01_register(OMAP_CS0_BASE, qemu_ram_alloc(flash_size), 157 drives_table[index].bdrv, sector_size, flash_size / sector_size, 158 4, 0, 0, 0, 0)) { 159 fprintf(stderr, "qemu: Error registering flash memory %d.\n", 160 fl_idx); 161 } 162 fl_idx++; 163 } 164 165 if ((version == 1) && 166 (index = drive_get_index(IF_PFLASH, 0, fl_idx)) > -1) { 167 cpu_register_physical_memory(OMAP_CS1_BASE, flash1_size, 168 (phys_flash = qemu_ram_alloc(flash1_size)) | 169 IO_MEM_ROM); 170 io = cpu_register_io_memory(0, static_readfn, static_writefn, &cs1val); 171 cpu_register_physical_memory(OMAP_CS1_BASE + flash1_size, 172 OMAP_CS1_SIZE - flash1_size, io); 173 174 if (!pflash_cfi01_register(OMAP_CS1_BASE, qemu_ram_alloc(flash1_size), 175 drives_table[index].bdrv, sector_size, flash1_size / sector_size, 176 4, 0, 0, 0, 0)) { 177 fprintf(stderr, "qemu: Error registering flash memory %d.\n", 178 fl_idx); 179 } 180 fl_idx++; 181 } else { 182 io = cpu_register_io_memory(0, static_readfn, static_writefn, &cs1val); 183 cpu_register_physical_memory(OMAP_CS1_BASE, OMAP_CS1_SIZE, io); 184 } 185 186 if (!kernel_filename && !fl_idx) { 187 fprintf(stderr, "Kernel or Flash image must be specified\n"); 188 exit(1); 189 } 190 191 /* Load the kernel. */ 192 if (kernel_filename) { 193 /* Start at bootloader. */ 194 cpu->env->regs[15] = sx1_binfo.loader_start; 195 196 sx1_binfo.kernel_filename = kernel_filename; 197 sx1_binfo.kernel_cmdline = kernel_cmdline; 198 sx1_binfo.initrd_filename = initrd_filename; 199 arm_load_kernel(cpu->env, &sx1_binfo); 200 } else { 201 cpu->env->regs[15] = 0x00000000; 202 } 203 204 /* TODO: fix next line */ 205 //~ qemu_console_resize(ds, 640, 480); 206 } 207 208 static void sx1_init_v1(ram_addr_t ram_size, int vga_ram_size, 209 const char *boot_device, 210 const char *kernel_filename, const char *kernel_cmdline, 211 const char *initrd_filename, const char *cpu_model) 212 { 213 sx1_init(ram_size, vga_ram_size, boot_device, kernel_filename, 214 kernel_cmdline, initrd_filename, cpu_model, 1); 215 } 216 217 static void sx1_init_v2(ram_addr_t ram_size, int vga_ram_size, 218 const char *boot_device, 219 const char *kernel_filename, const char *kernel_cmdline, 220 const char *initrd_filename, const char *cpu_model) 221 { 222 sx1_init(ram_size, vga_ram_size, boot_device, kernel_filename, 223 kernel_cmdline, initrd_filename, cpu_model, 2); 224 } 225 226 QEMUMachine sx1_machine_v2 = { 227 .name = "sx1", 228 .desc = "Siemens SX1 (OMAP310) V2", 229 .init = sx1_init_v2, 230 .ram_require = total_ram_v2 | RAMSIZE_FIXED, 231 }; 232 233 QEMUMachine sx1_machine_v1 = { 234 .name = "sx1-v1", 235 .desc = "Siemens SX1 (OMAP310) V1", 236 .init = sx1_init_v1, 237 .ram_require = total_ram_v1 | RAMSIZE_FIXED, 238 }; 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