1 /* 2 * TI OMAP processors emulation. 3 * 4 * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 or 9 * (at your option) version 3 of the License. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/log.h" 22 #include "qemu/error-report.h" 23 #include "qemu/main-loop.h" 24 #include "qapi/error.h" 25 #include "cpu.h" 26 #include "exec/address-spaces.h" 27 #include "hw/hw.h" 28 #include "hw/irq.h" 29 #include "hw/qdev-properties.h" 30 #include "hw/arm/boot.h" 31 #include "hw/arm/omap.h" 32 #include "hw/sd/sd.h" 33 #include "system/blockdev.h" 34 #include "system/system.h" 35 #include "hw/arm/soc_dma.h" 36 #include "system/qtest.h" 37 #include "system/reset.h" 38 #include "system/runstate.h" 39 #include "system/rtc.h" 40 #include "qemu/range.h" 41 #include "hw/sysbus.h" 42 #include "qemu/cutils.h" 43 #include "qemu/bcd.h" 44 #include "target/arm/cpu-qom.h" 45 46 static inline void omap_log_badwidth(const char *funcname, hwaddr addr, int sz) 47 { 48 qemu_log_mask(LOG_GUEST_ERROR, "%s: %d-bit register %#08" HWADDR_PRIx "\n", 49 funcname, 8 * sz, addr); 50 } 51 52 /* Should signal the TCMI/GPMC */ 53 uint32_t omap_badwidth_read8(void *opaque, hwaddr addr) 54 { 55 uint8_t ret; 56 57 omap_log_badwidth(__func__, addr, 1); 58 cpu_physical_memory_read(addr, &ret, 1); 59 return ret; 60 } 61 62 void omap_badwidth_write8(void *opaque, hwaddr addr, 63 uint32_t value) 64 { 65 uint8_t val8 = value; 66 67 omap_log_badwidth(__func__, addr, 1); 68 cpu_physical_memory_write(addr, &val8, 1); 69 } 70 71 uint32_t omap_badwidth_read16(void *opaque, hwaddr addr) 72 { 73 uint16_t ret; 74 75 omap_log_badwidth(__func__, addr, 2); 76 cpu_physical_memory_read(addr, &ret, 2); 77 return ret; 78 } 79 80 void omap_badwidth_write16(void *opaque, hwaddr addr, 81 uint32_t value) 82 { 83 uint16_t val16 = value; 84 85 omap_log_badwidth(__func__, addr, 2); 86 cpu_physical_memory_write(addr, &val16, 2); 87 } 88 89 uint32_t omap_badwidth_read32(void *opaque, hwaddr addr) 90 { 91 uint32_t ret; 92 93 omap_log_badwidth(__func__, addr, 4); 94 cpu_physical_memory_read(addr, &ret, 4); 95 return ret; 96 } 97 98 void omap_badwidth_write32(void *opaque, hwaddr addr, 99 uint32_t value) 100 { 101 omap_log_badwidth(__func__, addr, 4); 102 cpu_physical_memory_write(addr, &value, 4); 103 } 104 105 /* MPU OS timers */ 106 struct omap_mpu_timer_s { 107 MemoryRegion iomem; 108 qemu_irq irq; 109 omap_clk clk; 110 uint32_t val; 111 int64_t time; 112 QEMUTimer *timer; 113 QEMUBH *tick; 114 int64_t rate; 115 int it_ena; 116 117 int enable; 118 int ptv; 119 int ar; 120 int st; 121 uint32_t reset_val; 122 }; 123 124 static inline uint32_t omap_timer_read(struct omap_mpu_timer_s *timer) 125 { 126 uint64_t distance = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - timer->time; 127 128 if (timer->st && timer->enable && timer->rate) 129 return timer->val - muldiv64(distance >> (timer->ptv + 1), 130 timer->rate, NANOSECONDS_PER_SECOND); 131 else 132 return timer->val; 133 } 134 135 static inline void omap_timer_sync(struct omap_mpu_timer_s *timer) 136 { 137 timer->val = omap_timer_read(timer); 138 timer->time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 139 } 140 141 static inline void omap_timer_update(struct omap_mpu_timer_s *timer) 142 { 143 int64_t expires; 144 145 if (timer->enable && timer->st && timer->rate) { 146 timer->val = timer->reset_val; /* Should skip this on clk enable */ 147 expires = muldiv64((uint64_t) timer->val << (timer->ptv + 1), 148 NANOSECONDS_PER_SECOND, timer->rate); 149 150 /* If timer expiry would be sooner than in about 1 ms and 151 * auto-reload isn't set, then fire immediately. This is a hack 152 * to make systems like PalmOS run in acceptable time. PalmOS 153 * sets the interval to a very low value and polls the status bit 154 * in a busy loop when it wants to sleep just a couple of CPU 155 * ticks. */ 156 if (expires > (NANOSECONDS_PER_SECOND >> 10) || timer->ar) { 157 timer_mod(timer->timer, timer->time + expires); 158 } else { 159 qemu_bh_schedule(timer->tick); 160 } 161 } else 162 timer_del(timer->timer); 163 } 164 165 static void omap_timer_fire(void *opaque) 166 { 167 struct omap_mpu_timer_s *timer = opaque; 168 169 if (!timer->ar) { 170 timer->val = 0; 171 timer->st = 0; 172 } 173 174 if (timer->it_ena) 175 /* Edge-triggered irq */ 176 qemu_irq_pulse(timer->irq); 177 } 178 179 static void omap_timer_tick(void *opaque) 180 { 181 struct omap_mpu_timer_s *timer = opaque; 182 183 omap_timer_sync(timer); 184 omap_timer_fire(timer); 185 omap_timer_update(timer); 186 } 187 188 static void omap_timer_clk_update(void *opaque, int line, int on) 189 { 190 struct omap_mpu_timer_s *timer = opaque; 191 192 omap_timer_sync(timer); 193 timer->rate = on ? omap_clk_getrate(timer->clk) : 0; 194 omap_timer_update(timer); 195 } 196 197 static void omap_timer_clk_setup(struct omap_mpu_timer_s *timer) 198 { 199 omap_clk_adduser(timer->clk, 200 qemu_allocate_irq(omap_timer_clk_update, timer, 0)); 201 timer->rate = omap_clk_getrate(timer->clk); 202 } 203 204 static uint64_t omap_mpu_timer_read(void *opaque, hwaddr addr, 205 unsigned size) 206 { 207 struct omap_mpu_timer_s *s = opaque; 208 209 if (size != 4) { 210 return omap_badwidth_read32(opaque, addr); 211 } 212 213 switch (addr) { 214 case 0x00: /* CNTL_TIMER */ 215 return (s->enable << 5) | (s->ptv << 2) | (s->ar << 1) | s->st; 216 217 case 0x04: /* LOAD_TIM */ 218 break; 219 220 case 0x08: /* READ_TIM */ 221 return omap_timer_read(s); 222 } 223 224 OMAP_BAD_REG(addr); 225 return 0; 226 } 227 228 static void omap_mpu_timer_write(void *opaque, hwaddr addr, 229 uint64_t value, unsigned size) 230 { 231 struct omap_mpu_timer_s *s = opaque; 232 233 if (size != 4) { 234 omap_badwidth_write32(opaque, addr, value); 235 return; 236 } 237 238 switch (addr) { 239 case 0x00: /* CNTL_TIMER */ 240 omap_timer_sync(s); 241 s->enable = (value >> 5) & 1; 242 s->ptv = (value >> 2) & 7; 243 s->ar = (value >> 1) & 1; 244 s->st = value & 1; 245 omap_timer_update(s); 246 return; 247 248 case 0x04: /* LOAD_TIM */ 249 s->reset_val = value; 250 return; 251 252 case 0x08: /* READ_TIM */ 253 OMAP_RO_REG(addr); 254 break; 255 256 default: 257 OMAP_BAD_REG(addr); 258 } 259 } 260 261 static const MemoryRegionOps omap_mpu_timer_ops = { 262 .read = omap_mpu_timer_read, 263 .write = omap_mpu_timer_write, 264 .endianness = DEVICE_LITTLE_ENDIAN, 265 }; 266 267 static void omap_mpu_timer_reset(struct omap_mpu_timer_s *s) 268 { 269 timer_del(s->timer); 270 s->enable = 0; 271 s->reset_val = 31337; 272 s->val = 0; 273 s->ptv = 0; 274 s->ar = 0; 275 s->st = 0; 276 s->it_ena = 1; 277 } 278 279 static struct omap_mpu_timer_s *omap_mpu_timer_init(MemoryRegion *system_memory, 280 hwaddr base, 281 qemu_irq irq, omap_clk clk) 282 { 283 struct omap_mpu_timer_s *s = g_new0(struct omap_mpu_timer_s, 1); 284 285 s->irq = irq; 286 s->clk = clk; 287 s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_timer_tick, s); 288 s->tick = qemu_bh_new(omap_timer_fire, s); 289 omap_mpu_timer_reset(s); 290 omap_timer_clk_setup(s); 291 292 memory_region_init_io(&s->iomem, NULL, &omap_mpu_timer_ops, s, 293 "omap-mpu-timer", 0x100); 294 295 memory_region_add_subregion(system_memory, base, &s->iomem); 296 297 return s; 298 } 299 300 /* Watchdog timer */ 301 struct omap_watchdog_timer_s { 302 struct omap_mpu_timer_s timer; 303 MemoryRegion iomem; 304 uint8_t last_wr; 305 int mode; 306 int free; 307 int reset; 308 }; 309 310 static uint64_t omap_wd_timer_read(void *opaque, hwaddr addr, 311 unsigned size) 312 { 313 struct omap_watchdog_timer_s *s = opaque; 314 315 if (size != 2) { 316 return omap_badwidth_read16(opaque, addr); 317 } 318 319 switch (addr) { 320 case 0x00: /* CNTL_TIMER */ 321 return (s->timer.ptv << 9) | (s->timer.ar << 8) | 322 (s->timer.st << 7) | (s->free << 1); 323 324 case 0x04: /* READ_TIMER */ 325 return omap_timer_read(&s->timer); 326 327 case 0x08: /* TIMER_MODE */ 328 return s->mode << 15; 329 } 330 331 OMAP_BAD_REG(addr); 332 return 0; 333 } 334 335 static void omap_wd_timer_write(void *opaque, hwaddr addr, 336 uint64_t value, unsigned size) 337 { 338 struct omap_watchdog_timer_s *s = opaque; 339 340 if (size != 2) { 341 omap_badwidth_write16(opaque, addr, value); 342 return; 343 } 344 345 switch (addr) { 346 case 0x00: /* CNTL_TIMER */ 347 omap_timer_sync(&s->timer); 348 s->timer.ptv = (value >> 9) & 7; 349 s->timer.ar = (value >> 8) & 1; 350 s->timer.st = (value >> 7) & 1; 351 s->free = (value >> 1) & 1; 352 omap_timer_update(&s->timer); 353 break; 354 355 case 0x04: /* LOAD_TIMER */ 356 s->timer.reset_val = value & 0xffff; 357 break; 358 359 case 0x08: /* TIMER_MODE */ 360 if (!s->mode && ((value >> 15) & 1)) 361 omap_clk_get(s->timer.clk); 362 s->mode |= (value >> 15) & 1; 363 if (s->last_wr == 0xf5) { 364 if ((value & 0xff) == 0xa0) { 365 if (s->mode) { 366 s->mode = 0; 367 omap_clk_put(s->timer.clk); 368 } 369 } else { 370 /* XXX: on T|E hardware somehow this has no effect, 371 * on Zire 71 it works as specified. */ 372 s->reset = 1; 373 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 374 } 375 } 376 s->last_wr = value & 0xff; 377 break; 378 379 default: 380 OMAP_BAD_REG(addr); 381 } 382 } 383 384 static const MemoryRegionOps omap_wd_timer_ops = { 385 .read = omap_wd_timer_read, 386 .write = omap_wd_timer_write, 387 .endianness = DEVICE_NATIVE_ENDIAN, 388 }; 389 390 static void omap_wd_timer_reset(struct omap_watchdog_timer_s *s) 391 { 392 timer_del(s->timer.timer); 393 if (!s->mode) 394 omap_clk_get(s->timer.clk); 395 s->mode = 1; 396 s->free = 1; 397 s->reset = 0; 398 s->timer.enable = 1; 399 s->timer.it_ena = 1; 400 s->timer.reset_val = 0xffff; 401 s->timer.val = 0; 402 s->timer.st = 0; 403 s->timer.ptv = 0; 404 s->timer.ar = 0; 405 omap_timer_update(&s->timer); 406 } 407 408 static struct omap_watchdog_timer_s *omap_wd_timer_init(MemoryRegion *memory, 409 hwaddr base, 410 qemu_irq irq, omap_clk clk) 411 { 412 struct omap_watchdog_timer_s *s = g_new0(struct omap_watchdog_timer_s, 1); 413 414 s->timer.irq = irq; 415 s->timer.clk = clk; 416 s->timer.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_timer_tick, &s->timer); 417 omap_wd_timer_reset(s); 418 omap_timer_clk_setup(&s->timer); 419 420 memory_region_init_io(&s->iomem, NULL, &omap_wd_timer_ops, s, 421 "omap-wd-timer", 0x100); 422 memory_region_add_subregion(memory, base, &s->iomem); 423 424 return s; 425 } 426 427 /* 32-kHz timer */ 428 struct omap_32khz_timer_s { 429 struct omap_mpu_timer_s timer; 430 MemoryRegion iomem; 431 }; 432 433 static uint64_t omap_os_timer_read(void *opaque, hwaddr addr, 434 unsigned size) 435 { 436 struct omap_32khz_timer_s *s = opaque; 437 int offset = addr & OMAP_MPUI_REG_MASK; 438 439 if (size != 4) { 440 return omap_badwidth_read32(opaque, addr); 441 } 442 443 switch (offset) { 444 case 0x00: /* TVR */ 445 return s->timer.reset_val; 446 447 case 0x04: /* TCR */ 448 return omap_timer_read(&s->timer); 449 450 case 0x08: /* CR */ 451 return (s->timer.ar << 3) | (s->timer.it_ena << 2) | s->timer.st; 452 453 default: 454 break; 455 } 456 OMAP_BAD_REG(addr); 457 return 0; 458 } 459 460 static void omap_os_timer_write(void *opaque, hwaddr addr, 461 uint64_t value, unsigned size) 462 { 463 struct omap_32khz_timer_s *s = opaque; 464 int offset = addr & OMAP_MPUI_REG_MASK; 465 466 if (size != 4) { 467 omap_badwidth_write32(opaque, addr, value); 468 return; 469 } 470 471 switch (offset) { 472 case 0x00: /* TVR */ 473 s->timer.reset_val = value & 0x00ffffff; 474 break; 475 476 case 0x04: /* TCR */ 477 OMAP_RO_REG(addr); 478 break; 479 480 case 0x08: /* CR */ 481 s->timer.ar = (value >> 3) & 1; 482 s->timer.it_ena = (value >> 2) & 1; 483 if (s->timer.st != (value & 1) || (value & 2)) { 484 omap_timer_sync(&s->timer); 485 s->timer.enable = value & 1; 486 s->timer.st = value & 1; 487 omap_timer_update(&s->timer); 488 } 489 break; 490 491 default: 492 OMAP_BAD_REG(addr); 493 } 494 } 495 496 static const MemoryRegionOps omap_os_timer_ops = { 497 .read = omap_os_timer_read, 498 .write = omap_os_timer_write, 499 .endianness = DEVICE_NATIVE_ENDIAN, 500 }; 501 502 static void omap_os_timer_reset(struct omap_32khz_timer_s *s) 503 { 504 timer_del(s->timer.timer); 505 s->timer.enable = 0; 506 s->timer.it_ena = 0; 507 s->timer.reset_val = 0x00ffffff; 508 s->timer.val = 0; 509 s->timer.st = 0; 510 s->timer.ptv = 0; 511 s->timer.ar = 1; 512 } 513 514 static struct omap_32khz_timer_s *omap_os_timer_init(MemoryRegion *memory, 515 hwaddr base, 516 qemu_irq irq, omap_clk clk) 517 { 518 struct omap_32khz_timer_s *s = g_new0(struct omap_32khz_timer_s, 1); 519 520 s->timer.irq = irq; 521 s->timer.clk = clk; 522 s->timer.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_timer_tick, &s->timer); 523 omap_os_timer_reset(s); 524 omap_timer_clk_setup(&s->timer); 525 526 memory_region_init_io(&s->iomem, NULL, &omap_os_timer_ops, s, 527 "omap-os-timer", 0x800); 528 memory_region_add_subregion(memory, base, &s->iomem); 529 530 return s; 531 } 532 533 /* Ultra Low-Power Device Module */ 534 static uint64_t omap_ulpd_pm_read(void *opaque, hwaddr addr, 535 unsigned size) 536 { 537 struct omap_mpu_state_s *s = opaque; 538 uint16_t ret; 539 540 if (size != 2) { 541 return omap_badwidth_read16(opaque, addr); 542 } 543 544 switch (addr) { 545 case 0x14: /* IT_STATUS */ 546 ret = s->ulpd_pm_regs[addr >> 2]; 547 s->ulpd_pm_regs[addr >> 2] = 0; 548 qemu_irq_lower(qdev_get_gpio_in(s->ih[1], OMAP_INT_GAUGE_32K)); 549 return ret; 550 551 case 0x18: /* Reserved */ 552 case 0x1c: /* Reserved */ 553 case 0x20: /* Reserved */ 554 case 0x28: /* Reserved */ 555 case 0x2c: /* Reserved */ 556 OMAP_BAD_REG(addr); 557 /* fall through */ 558 case 0x00: /* COUNTER_32_LSB */ 559 case 0x04: /* COUNTER_32_MSB */ 560 case 0x08: /* COUNTER_HIGH_FREQ_LSB */ 561 case 0x0c: /* COUNTER_HIGH_FREQ_MSB */ 562 case 0x10: /* GAUGING_CTRL */ 563 case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */ 564 case 0x30: /* CLOCK_CTRL */ 565 case 0x34: /* SOFT_REQ */ 566 case 0x38: /* COUNTER_32_FIQ */ 567 case 0x3c: /* DPLL_CTRL */ 568 case 0x40: /* STATUS_REQ */ 569 /* XXX: check clk::usecount state for every clock */ 570 case 0x48: /* LOCL_TIME */ 571 case 0x4c: /* APLL_CTRL */ 572 case 0x50: /* POWER_CTRL */ 573 return s->ulpd_pm_regs[addr >> 2]; 574 } 575 576 OMAP_BAD_REG(addr); 577 return 0; 578 } 579 580 static inline void omap_ulpd_clk_update(struct omap_mpu_state_s *s, 581 uint16_t diff, uint16_t value) 582 { 583 if (diff & (1 << 4)) /* USB_MCLK_EN */ 584 omap_clk_onoff(omap_findclk(s, "usb_clk0"), (value >> 4) & 1); 585 if (diff & (1 << 5)) /* DIS_USB_PVCI_CLK */ 586 omap_clk_onoff(omap_findclk(s, "usb_w2fc_ck"), (~value >> 5) & 1); 587 } 588 589 static inline void omap_ulpd_req_update(struct omap_mpu_state_s *s, 590 uint16_t diff, uint16_t value) 591 { 592 if (diff & (1 << 0)) /* SOFT_DPLL_REQ */ 593 omap_clk_canidle(omap_findclk(s, "dpll4"), (~value >> 0) & 1); 594 if (diff & (1 << 1)) /* SOFT_COM_REQ */ 595 omap_clk_canidle(omap_findclk(s, "com_mclk_out"), (~value >> 1) & 1); 596 if (diff & (1 << 2)) /* SOFT_SDW_REQ */ 597 omap_clk_canidle(omap_findclk(s, "bt_mclk_out"), (~value >> 2) & 1); 598 if (diff & (1 << 3)) /* SOFT_USB_REQ */ 599 omap_clk_canidle(omap_findclk(s, "usb_clk0"), (~value >> 3) & 1); 600 } 601 602 static void omap_ulpd_pm_write(void *opaque, hwaddr addr, 603 uint64_t value, unsigned size) 604 { 605 struct omap_mpu_state_s *s = opaque; 606 int64_t now, ticks; 607 int div, mult; 608 static const int bypass_div[4] = { 1, 2, 4, 4 }; 609 uint16_t diff; 610 611 if (size != 2) { 612 omap_badwidth_write16(opaque, addr, value); 613 return; 614 } 615 616 switch (addr) { 617 case 0x00: /* COUNTER_32_LSB */ 618 case 0x04: /* COUNTER_32_MSB */ 619 case 0x08: /* COUNTER_HIGH_FREQ_LSB */ 620 case 0x0c: /* COUNTER_HIGH_FREQ_MSB */ 621 case 0x14: /* IT_STATUS */ 622 case 0x40: /* STATUS_REQ */ 623 OMAP_RO_REG(addr); 624 break; 625 626 case 0x10: /* GAUGING_CTRL */ 627 /* Bits 0 and 1 seem to be confused in the OMAP 310 TRM */ 628 if ((s->ulpd_pm_regs[addr >> 2] ^ value) & 1) { 629 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 630 631 if (value & 1) 632 s->ulpd_gauge_start = now; 633 else { 634 now -= s->ulpd_gauge_start; 635 636 /* 32-kHz ticks */ 637 ticks = muldiv64(now, 32768, NANOSECONDS_PER_SECOND); 638 s->ulpd_pm_regs[0x00 >> 2] = (ticks >> 0) & 0xffff; 639 s->ulpd_pm_regs[0x04 >> 2] = (ticks >> 16) & 0xffff; 640 if (ticks >> 32) /* OVERFLOW_32K */ 641 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 2; 642 643 /* High frequency ticks */ 644 ticks = muldiv64(now, 12000000, NANOSECONDS_PER_SECOND); 645 s->ulpd_pm_regs[0x08 >> 2] = (ticks >> 0) & 0xffff; 646 s->ulpd_pm_regs[0x0c >> 2] = (ticks >> 16) & 0xffff; 647 if (ticks >> 32) /* OVERFLOW_HI_FREQ */ 648 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 1; 649 650 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 0; /* IT_GAUGING */ 651 qemu_irq_raise(qdev_get_gpio_in(s->ih[1], OMAP_INT_GAUGE_32K)); 652 } 653 } 654 s->ulpd_pm_regs[addr >> 2] = value; 655 break; 656 657 case 0x18: /* Reserved */ 658 case 0x1c: /* Reserved */ 659 case 0x20: /* Reserved */ 660 case 0x28: /* Reserved */ 661 case 0x2c: /* Reserved */ 662 OMAP_BAD_REG(addr); 663 /* fall through */ 664 case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */ 665 case 0x38: /* COUNTER_32_FIQ */ 666 case 0x48: /* LOCL_TIME */ 667 case 0x50: /* POWER_CTRL */ 668 s->ulpd_pm_regs[addr >> 2] = value; 669 break; 670 671 case 0x30: /* CLOCK_CTRL */ 672 diff = s->ulpd_pm_regs[addr >> 2] ^ value; 673 s->ulpd_pm_regs[addr >> 2] = value & 0x3f; 674 omap_ulpd_clk_update(s, diff, value); 675 break; 676 677 case 0x34: /* SOFT_REQ */ 678 diff = s->ulpd_pm_regs[addr >> 2] ^ value; 679 s->ulpd_pm_regs[addr >> 2] = value & 0x1f; 680 omap_ulpd_req_update(s, diff, value); 681 break; 682 683 case 0x3c: /* DPLL_CTRL */ 684 /* XXX: OMAP310 TRM claims bit 3 is PLL_ENABLE, and bit 4 is 685 * omitted altogether, probably a typo. */ 686 /* This register has identical semantics with DPLL(1:3) control 687 * registers, see omap_dpll_write() */ 688 diff = s->ulpd_pm_regs[addr >> 2] & value; 689 s->ulpd_pm_regs[addr >> 2] = value & 0x2fff; 690 if (diff & (0x3ff << 2)) { 691 if (value & (1 << 4)) { /* PLL_ENABLE */ 692 div = ((value >> 5) & 3) + 1; /* PLL_DIV */ 693 mult = MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */ 694 } else { 695 div = bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */ 696 mult = 1; 697 } 698 omap_clk_setrate(omap_findclk(s, "dpll4"), div, mult); 699 } 700 701 /* Enter the desired mode. */ 702 s->ulpd_pm_regs[addr >> 2] = 703 (s->ulpd_pm_regs[addr >> 2] & 0xfffe) | 704 ((s->ulpd_pm_regs[addr >> 2] >> 4) & 1); 705 706 /* Act as if the lock is restored. */ 707 s->ulpd_pm_regs[addr >> 2] |= 2; 708 break; 709 710 case 0x4c: /* APLL_CTRL */ 711 diff = s->ulpd_pm_regs[addr >> 2] & value; 712 s->ulpd_pm_regs[addr >> 2] = value & 0xf; 713 if (diff & (1 << 0)) /* APLL_NDPLL_SWITCH */ 714 omap_clk_reparent(omap_findclk(s, "ck_48m"), omap_findclk(s, 715 (value & (1 << 0)) ? "apll" : "dpll4")); 716 break; 717 718 default: 719 OMAP_BAD_REG(addr); 720 } 721 } 722 723 static const MemoryRegionOps omap_ulpd_pm_ops = { 724 .read = omap_ulpd_pm_read, 725 .write = omap_ulpd_pm_write, 726 .endianness = DEVICE_NATIVE_ENDIAN, 727 }; 728 729 static void omap_ulpd_pm_reset(struct omap_mpu_state_s *mpu) 730 { 731 mpu->ulpd_pm_regs[0x00 >> 2] = 0x0001; 732 mpu->ulpd_pm_regs[0x04 >> 2] = 0x0000; 733 mpu->ulpd_pm_regs[0x08 >> 2] = 0x0001; 734 mpu->ulpd_pm_regs[0x0c >> 2] = 0x0000; 735 mpu->ulpd_pm_regs[0x10 >> 2] = 0x0000; 736 mpu->ulpd_pm_regs[0x18 >> 2] = 0x01; 737 mpu->ulpd_pm_regs[0x1c >> 2] = 0x01; 738 mpu->ulpd_pm_regs[0x20 >> 2] = 0x01; 739 mpu->ulpd_pm_regs[0x24 >> 2] = 0x03ff; 740 mpu->ulpd_pm_regs[0x28 >> 2] = 0x01; 741 mpu->ulpd_pm_regs[0x2c >> 2] = 0x01; 742 omap_ulpd_clk_update(mpu, mpu->ulpd_pm_regs[0x30 >> 2], 0x0000); 743 mpu->ulpd_pm_regs[0x30 >> 2] = 0x0000; 744 omap_ulpd_req_update(mpu, mpu->ulpd_pm_regs[0x34 >> 2], 0x0000); 745 mpu->ulpd_pm_regs[0x34 >> 2] = 0x0000; 746 mpu->ulpd_pm_regs[0x38 >> 2] = 0x0001; 747 mpu->ulpd_pm_regs[0x3c >> 2] = 0x2211; 748 mpu->ulpd_pm_regs[0x40 >> 2] = 0x0000; /* FIXME: dump a real STATUS_REQ */ 749 mpu->ulpd_pm_regs[0x48 >> 2] = 0x960; 750 mpu->ulpd_pm_regs[0x4c >> 2] = 0x08; 751 mpu->ulpd_pm_regs[0x50 >> 2] = 0x08; 752 omap_clk_setrate(omap_findclk(mpu, "dpll4"), 1, 4); 753 omap_clk_reparent(omap_findclk(mpu, "ck_48m"), omap_findclk(mpu, "dpll4")); 754 } 755 756 static void omap_ulpd_pm_init(MemoryRegion *system_memory, 757 hwaddr base, 758 struct omap_mpu_state_s *mpu) 759 { 760 memory_region_init_io(&mpu->ulpd_pm_iomem, NULL, &omap_ulpd_pm_ops, mpu, 761 "omap-ulpd-pm", 0x800); 762 memory_region_add_subregion(system_memory, base, &mpu->ulpd_pm_iomem); 763 omap_ulpd_pm_reset(mpu); 764 } 765 766 /* OMAP Pin Configuration */ 767 static uint64_t omap_pin_cfg_read(void *opaque, hwaddr addr, 768 unsigned size) 769 { 770 struct omap_mpu_state_s *s = opaque; 771 772 if (size != 4) { 773 return omap_badwidth_read32(opaque, addr); 774 } 775 776 switch (addr) { 777 case 0x00: /* FUNC_MUX_CTRL_0 */ 778 case 0x04: /* FUNC_MUX_CTRL_1 */ 779 case 0x08: /* FUNC_MUX_CTRL_2 */ 780 return s->func_mux_ctrl[addr >> 2]; 781 782 case 0x0c: /* COMP_MODE_CTRL_0 */ 783 return s->comp_mode_ctrl[0]; 784 785 case 0x10: /* FUNC_MUX_CTRL_3 */ 786 case 0x14: /* FUNC_MUX_CTRL_4 */ 787 case 0x18: /* FUNC_MUX_CTRL_5 */ 788 case 0x1c: /* FUNC_MUX_CTRL_6 */ 789 case 0x20: /* FUNC_MUX_CTRL_7 */ 790 case 0x24: /* FUNC_MUX_CTRL_8 */ 791 case 0x28: /* FUNC_MUX_CTRL_9 */ 792 case 0x2c: /* FUNC_MUX_CTRL_A */ 793 case 0x30: /* FUNC_MUX_CTRL_B */ 794 case 0x34: /* FUNC_MUX_CTRL_C */ 795 case 0x38: /* FUNC_MUX_CTRL_D */ 796 return s->func_mux_ctrl[(addr >> 2) - 1]; 797 798 case 0x40: /* PULL_DWN_CTRL_0 */ 799 case 0x44: /* PULL_DWN_CTRL_1 */ 800 case 0x48: /* PULL_DWN_CTRL_2 */ 801 case 0x4c: /* PULL_DWN_CTRL_3 */ 802 return s->pull_dwn_ctrl[(addr & 0xf) >> 2]; 803 804 case 0x50: /* GATE_INH_CTRL_0 */ 805 return s->gate_inh_ctrl[0]; 806 807 case 0x60: /* VOLTAGE_CTRL_0 */ 808 return s->voltage_ctrl[0]; 809 810 case 0x70: /* TEST_DBG_CTRL_0 */ 811 return s->test_dbg_ctrl[0]; 812 813 case 0x80: /* MOD_CONF_CTRL_0 */ 814 return s->mod_conf_ctrl[0]; 815 } 816 817 OMAP_BAD_REG(addr); 818 return 0; 819 } 820 821 static inline void omap_pin_funcmux0_update(struct omap_mpu_state_s *s, 822 uint32_t diff, uint32_t value) 823 { 824 if (s->compat1509) { 825 if (diff & (1 << 9)) /* BLUETOOTH */ 826 omap_clk_onoff(omap_findclk(s, "bt_mclk_out"), 827 (~value >> 9) & 1); 828 if (diff & (1 << 7)) /* USB.CLKO */ 829 omap_clk_onoff(omap_findclk(s, "usb.clko"), 830 (value >> 7) & 1); 831 } 832 } 833 834 static inline void omap_pin_funcmux1_update(struct omap_mpu_state_s *s, 835 uint32_t diff, uint32_t value) 836 { 837 if (s->compat1509) { 838 if (diff & (1U << 31)) { 839 /* MCBSP3_CLK_HIZ_DI */ 840 omap_clk_onoff(omap_findclk(s, "mcbsp3.clkx"), (value >> 31) & 1); 841 } 842 if (diff & (1 << 1)) { 843 /* CLK32K */ 844 omap_clk_onoff(omap_findclk(s, "clk32k_out"), (~value >> 1) & 1); 845 } 846 } 847 } 848 849 static inline void omap_pin_modconf1_update(struct omap_mpu_state_s *s, 850 uint32_t diff, uint32_t value) 851 { 852 if (diff & (1U << 31)) { 853 /* CONF_MOD_UART3_CLK_MODE_R */ 854 omap_clk_reparent(omap_findclk(s, "uart3_ck"), 855 omap_findclk(s, ((value >> 31) & 1) ? 856 "ck_48m" : "armper_ck")); 857 } 858 if (diff & (1 << 30)) /* CONF_MOD_UART2_CLK_MODE_R */ 859 omap_clk_reparent(omap_findclk(s, "uart2_ck"), 860 omap_findclk(s, ((value >> 30) & 1) ? 861 "ck_48m" : "armper_ck")); 862 if (diff & (1 << 29)) /* CONF_MOD_UART1_CLK_MODE_R */ 863 omap_clk_reparent(omap_findclk(s, "uart1_ck"), 864 omap_findclk(s, ((value >> 29) & 1) ? 865 "ck_48m" : "armper_ck")); 866 if (diff & (1 << 23)) /* CONF_MOD_MMC_SD_CLK_REQ_R */ 867 omap_clk_reparent(omap_findclk(s, "mmc_ck"), 868 omap_findclk(s, ((value >> 23) & 1) ? 869 "ck_48m" : "armper_ck")); 870 if (diff & (1 << 12)) /* CONF_MOD_COM_MCLK_12_48_S */ 871 omap_clk_reparent(omap_findclk(s, "com_mclk_out"), 872 omap_findclk(s, ((value >> 12) & 1) ? 873 "ck_48m" : "armper_ck")); 874 if (diff & (1 << 9)) /* CONF_MOD_USB_HOST_HHC_UHO */ 875 omap_clk_onoff(omap_findclk(s, "usb_hhc_ck"), (value >> 9) & 1); 876 } 877 878 static void omap_pin_cfg_write(void *opaque, hwaddr addr, 879 uint64_t value, unsigned size) 880 { 881 struct omap_mpu_state_s *s = opaque; 882 uint32_t diff; 883 884 if (size != 4) { 885 omap_badwidth_write32(opaque, addr, value); 886 return; 887 } 888 889 switch (addr) { 890 case 0x00: /* FUNC_MUX_CTRL_0 */ 891 diff = s->func_mux_ctrl[addr >> 2] ^ value; 892 s->func_mux_ctrl[addr >> 2] = value; 893 omap_pin_funcmux0_update(s, diff, value); 894 return; 895 896 case 0x04: /* FUNC_MUX_CTRL_1 */ 897 diff = s->func_mux_ctrl[addr >> 2] ^ value; 898 s->func_mux_ctrl[addr >> 2] = value; 899 omap_pin_funcmux1_update(s, diff, value); 900 return; 901 902 case 0x08: /* FUNC_MUX_CTRL_2 */ 903 s->func_mux_ctrl[addr >> 2] = value; 904 return; 905 906 case 0x0c: /* COMP_MODE_CTRL_0 */ 907 s->comp_mode_ctrl[0] = value; 908 s->compat1509 = (value != 0x0000eaef); 909 omap_pin_funcmux0_update(s, ~0, s->func_mux_ctrl[0]); 910 omap_pin_funcmux1_update(s, ~0, s->func_mux_ctrl[1]); 911 return; 912 913 case 0x10: /* FUNC_MUX_CTRL_3 */ 914 case 0x14: /* FUNC_MUX_CTRL_4 */ 915 case 0x18: /* FUNC_MUX_CTRL_5 */ 916 case 0x1c: /* FUNC_MUX_CTRL_6 */ 917 case 0x20: /* FUNC_MUX_CTRL_7 */ 918 case 0x24: /* FUNC_MUX_CTRL_8 */ 919 case 0x28: /* FUNC_MUX_CTRL_9 */ 920 case 0x2c: /* FUNC_MUX_CTRL_A */ 921 case 0x30: /* FUNC_MUX_CTRL_B */ 922 case 0x34: /* FUNC_MUX_CTRL_C */ 923 case 0x38: /* FUNC_MUX_CTRL_D */ 924 s->func_mux_ctrl[(addr >> 2) - 1] = value; 925 return; 926 927 case 0x40: /* PULL_DWN_CTRL_0 */ 928 case 0x44: /* PULL_DWN_CTRL_1 */ 929 case 0x48: /* PULL_DWN_CTRL_2 */ 930 case 0x4c: /* PULL_DWN_CTRL_3 */ 931 s->pull_dwn_ctrl[(addr & 0xf) >> 2] = value; 932 return; 933 934 case 0x50: /* GATE_INH_CTRL_0 */ 935 s->gate_inh_ctrl[0] = value; 936 return; 937 938 case 0x60: /* VOLTAGE_CTRL_0 */ 939 s->voltage_ctrl[0] = value; 940 return; 941 942 case 0x70: /* TEST_DBG_CTRL_0 */ 943 s->test_dbg_ctrl[0] = value; 944 return; 945 946 case 0x80: /* MOD_CONF_CTRL_0 */ 947 diff = s->mod_conf_ctrl[0] ^ value; 948 s->mod_conf_ctrl[0] = value; 949 omap_pin_modconf1_update(s, diff, value); 950 return; 951 952 default: 953 OMAP_BAD_REG(addr); 954 } 955 } 956 957 static const MemoryRegionOps omap_pin_cfg_ops = { 958 .read = omap_pin_cfg_read, 959 .write = omap_pin_cfg_write, 960 .endianness = DEVICE_NATIVE_ENDIAN, 961 }; 962 963 static void omap_pin_cfg_reset(struct omap_mpu_state_s *mpu) 964 { 965 /* Start in Compatibility Mode. */ 966 mpu->compat1509 = 1; 967 omap_pin_funcmux0_update(mpu, mpu->func_mux_ctrl[0], 0); 968 omap_pin_funcmux1_update(mpu, mpu->func_mux_ctrl[1], 0); 969 omap_pin_modconf1_update(mpu, mpu->mod_conf_ctrl[0], 0); 970 memset(mpu->func_mux_ctrl, 0, sizeof(mpu->func_mux_ctrl)); 971 memset(mpu->comp_mode_ctrl, 0, sizeof(mpu->comp_mode_ctrl)); 972 memset(mpu->pull_dwn_ctrl, 0, sizeof(mpu->pull_dwn_ctrl)); 973 memset(mpu->gate_inh_ctrl, 0, sizeof(mpu->gate_inh_ctrl)); 974 memset(mpu->voltage_ctrl, 0, sizeof(mpu->voltage_ctrl)); 975 memset(mpu->test_dbg_ctrl, 0, sizeof(mpu->test_dbg_ctrl)); 976 memset(mpu->mod_conf_ctrl, 0, sizeof(mpu->mod_conf_ctrl)); 977 } 978 979 static void omap_pin_cfg_init(MemoryRegion *system_memory, 980 hwaddr base, 981 struct omap_mpu_state_s *mpu) 982 { 983 memory_region_init_io(&mpu->pin_cfg_iomem, NULL, &omap_pin_cfg_ops, mpu, 984 "omap-pin-cfg", 0x800); 985 memory_region_add_subregion(system_memory, base, &mpu->pin_cfg_iomem); 986 omap_pin_cfg_reset(mpu); 987 } 988 989 /* Device Identification, Die Identification */ 990 static uint64_t omap_id_read(void *opaque, hwaddr addr, 991 unsigned size) 992 { 993 struct omap_mpu_state_s *s = opaque; 994 995 if (size != 4) { 996 return omap_badwidth_read32(opaque, addr); 997 } 998 999 switch (addr) { 1000 case 0xfffe1800: /* DIE_ID_LSB */ 1001 return 0xc9581f0e; 1002 case 0xfffe1804: /* DIE_ID_MSB */ 1003 return 0xa8858bfa; 1004 1005 case 0xfffe2000: /* PRODUCT_ID_LSB */ 1006 return 0x00aaaafc; 1007 case 0xfffe2004: /* PRODUCT_ID_MSB */ 1008 return 0xcafeb574; 1009 1010 case 0xfffed400: /* JTAG_ID_LSB */ 1011 switch (s->mpu_model) { 1012 case omap310: 1013 return 0x03310315; 1014 case omap1510: 1015 return 0x03310115; 1016 default: 1017 hw_error("%s: bad mpu model\n", __func__); 1018 } 1019 break; 1020 1021 case 0xfffed404: /* JTAG_ID_MSB */ 1022 switch (s->mpu_model) { 1023 case omap310: 1024 return 0xfb57402f; 1025 case omap1510: 1026 return 0xfb47002f; 1027 default: 1028 hw_error("%s: bad mpu model\n", __func__); 1029 } 1030 break; 1031 } 1032 1033 OMAP_BAD_REG(addr); 1034 return 0; 1035 } 1036 1037 static void omap_id_write(void *opaque, hwaddr addr, 1038 uint64_t value, unsigned size) 1039 { 1040 if (size != 4) { 1041 omap_badwidth_write32(opaque, addr, value); 1042 return; 1043 } 1044 1045 OMAP_BAD_REG(addr); 1046 } 1047 1048 static const MemoryRegionOps omap_id_ops = { 1049 .read = omap_id_read, 1050 .write = omap_id_write, 1051 .endianness = DEVICE_NATIVE_ENDIAN, 1052 }; 1053 1054 static void omap_id_init(MemoryRegion *memory, struct omap_mpu_state_s *mpu) 1055 { 1056 memory_region_init_io(&mpu->id_iomem, NULL, &omap_id_ops, mpu, 1057 "omap-id", 0x100000000ULL); 1058 memory_region_init_alias(&mpu->id_iomem_e18, NULL, "omap-id-e18", &mpu->id_iomem, 1059 0xfffe1800, 0x800); 1060 memory_region_add_subregion(memory, 0xfffe1800, &mpu->id_iomem_e18); 1061 memory_region_init_alias(&mpu->id_iomem_ed4, NULL, "omap-id-ed4", &mpu->id_iomem, 1062 0xfffed400, 0x100); 1063 memory_region_add_subregion(memory, 0xfffed400, &mpu->id_iomem_ed4); 1064 if (!cpu_is_omap15xx(mpu)) { 1065 memory_region_init_alias(&mpu->id_iomem_ed4, NULL, "omap-id-e20", 1066 &mpu->id_iomem, 0xfffe2000, 0x800); 1067 memory_region_add_subregion(memory, 0xfffe2000, &mpu->id_iomem_e20); 1068 } 1069 } 1070 1071 /* MPUI Control (Dummy) */ 1072 static uint64_t omap_mpui_read(void *opaque, hwaddr addr, 1073 unsigned size) 1074 { 1075 struct omap_mpu_state_s *s = opaque; 1076 1077 if (size != 4) { 1078 return omap_badwidth_read32(opaque, addr); 1079 } 1080 1081 switch (addr) { 1082 case 0x00: /* CTRL */ 1083 return s->mpui_ctrl; 1084 case 0x04: /* DEBUG_ADDR */ 1085 return 0x01ffffff; 1086 case 0x08: /* DEBUG_DATA */ 1087 return 0xffffffff; 1088 case 0x0c: /* DEBUG_FLAG */ 1089 return 0x00000800; 1090 case 0x10: /* STATUS */ 1091 return 0x00000000; 1092 1093 /* Not in OMAP310 */ 1094 case 0x14: /* DSP_STATUS */ 1095 case 0x18: /* DSP_BOOT_CONFIG */ 1096 return 0x00000000; 1097 case 0x1c: /* DSP_MPUI_CONFIG */ 1098 return 0x0000ffff; 1099 } 1100 1101 OMAP_BAD_REG(addr); 1102 return 0; 1103 } 1104 1105 static void omap_mpui_write(void *opaque, hwaddr addr, 1106 uint64_t value, unsigned size) 1107 { 1108 struct omap_mpu_state_s *s = opaque; 1109 1110 if (size != 4) { 1111 omap_badwidth_write32(opaque, addr, value); 1112 return; 1113 } 1114 1115 switch (addr) { 1116 case 0x00: /* CTRL */ 1117 s->mpui_ctrl = value & 0x007fffff; 1118 break; 1119 1120 case 0x04: /* DEBUG_ADDR */ 1121 case 0x08: /* DEBUG_DATA */ 1122 case 0x0c: /* DEBUG_FLAG */ 1123 case 0x10: /* STATUS */ 1124 /* Not in OMAP310 */ 1125 case 0x14: /* DSP_STATUS */ 1126 OMAP_RO_REG(addr); 1127 break; 1128 case 0x18: /* DSP_BOOT_CONFIG */ 1129 case 0x1c: /* DSP_MPUI_CONFIG */ 1130 break; 1131 1132 default: 1133 OMAP_BAD_REG(addr); 1134 } 1135 } 1136 1137 static const MemoryRegionOps omap_mpui_ops = { 1138 .read = omap_mpui_read, 1139 .write = omap_mpui_write, 1140 .endianness = DEVICE_NATIVE_ENDIAN, 1141 }; 1142 1143 static void omap_mpui_reset(struct omap_mpu_state_s *s) 1144 { 1145 s->mpui_ctrl = 0x0003ff1b; 1146 } 1147 1148 static void omap_mpui_init(MemoryRegion *memory, hwaddr base, 1149 struct omap_mpu_state_s *mpu) 1150 { 1151 memory_region_init_io(&mpu->mpui_iomem, NULL, &omap_mpui_ops, mpu, 1152 "omap-mpui", 0x100); 1153 memory_region_add_subregion(memory, base, &mpu->mpui_iomem); 1154 1155 omap_mpui_reset(mpu); 1156 } 1157 1158 /* TIPB Bridges */ 1159 struct omap_tipb_bridge_s { 1160 qemu_irq abort; 1161 MemoryRegion iomem; 1162 1163 int width_intr; 1164 uint16_t control; 1165 uint16_t alloc; 1166 uint16_t buffer; 1167 uint16_t enh_control; 1168 }; 1169 1170 static uint64_t omap_tipb_bridge_read(void *opaque, hwaddr addr, 1171 unsigned size) 1172 { 1173 struct omap_tipb_bridge_s *s = opaque; 1174 1175 if (size < 2) { 1176 return omap_badwidth_read16(opaque, addr); 1177 } 1178 1179 switch (addr) { 1180 case 0x00: /* TIPB_CNTL */ 1181 return s->control; 1182 case 0x04: /* TIPB_BUS_ALLOC */ 1183 return s->alloc; 1184 case 0x08: /* MPU_TIPB_CNTL */ 1185 return s->buffer; 1186 case 0x0c: /* ENHANCED_TIPB_CNTL */ 1187 return s->enh_control; 1188 case 0x10: /* ADDRESS_DBG */ 1189 case 0x14: /* DATA_DEBUG_LOW */ 1190 case 0x18: /* DATA_DEBUG_HIGH */ 1191 return 0xffff; 1192 case 0x1c: /* DEBUG_CNTR_SIG */ 1193 return 0x00f8; 1194 } 1195 1196 OMAP_BAD_REG(addr); 1197 return 0; 1198 } 1199 1200 static void omap_tipb_bridge_write(void *opaque, hwaddr addr, 1201 uint64_t value, unsigned size) 1202 { 1203 struct omap_tipb_bridge_s *s = opaque; 1204 1205 if (size < 2) { 1206 omap_badwidth_write16(opaque, addr, value); 1207 return; 1208 } 1209 1210 switch (addr) { 1211 case 0x00: /* TIPB_CNTL */ 1212 s->control = value & 0xffff; 1213 break; 1214 1215 case 0x04: /* TIPB_BUS_ALLOC */ 1216 s->alloc = value & 0x003f; 1217 break; 1218 1219 case 0x08: /* MPU_TIPB_CNTL */ 1220 s->buffer = value & 0x0003; 1221 break; 1222 1223 case 0x0c: /* ENHANCED_TIPB_CNTL */ 1224 s->width_intr = !(value & 2); 1225 s->enh_control = value & 0x000f; 1226 break; 1227 1228 case 0x10: /* ADDRESS_DBG */ 1229 case 0x14: /* DATA_DEBUG_LOW */ 1230 case 0x18: /* DATA_DEBUG_HIGH */ 1231 case 0x1c: /* DEBUG_CNTR_SIG */ 1232 OMAP_RO_REG(addr); 1233 break; 1234 1235 default: 1236 OMAP_BAD_REG(addr); 1237 } 1238 } 1239 1240 static const MemoryRegionOps omap_tipb_bridge_ops = { 1241 .read = omap_tipb_bridge_read, 1242 .write = omap_tipb_bridge_write, 1243 .endianness = DEVICE_NATIVE_ENDIAN, 1244 }; 1245 1246 static void omap_tipb_bridge_reset(struct omap_tipb_bridge_s *s) 1247 { 1248 s->control = 0xffff; 1249 s->alloc = 0x0009; 1250 s->buffer = 0x0000; 1251 s->enh_control = 0x000f; 1252 } 1253 1254 static struct omap_tipb_bridge_s *omap_tipb_bridge_init( 1255 MemoryRegion *memory, hwaddr base, 1256 qemu_irq abort_irq, omap_clk clk) 1257 { 1258 struct omap_tipb_bridge_s *s = g_new0(struct omap_tipb_bridge_s, 1); 1259 1260 s->abort = abort_irq; 1261 omap_tipb_bridge_reset(s); 1262 1263 memory_region_init_io(&s->iomem, NULL, &omap_tipb_bridge_ops, s, 1264 "omap-tipb-bridge", 0x100); 1265 memory_region_add_subregion(memory, base, &s->iomem); 1266 1267 return s; 1268 } 1269 1270 /* Dummy Traffic Controller's Memory Interface */ 1271 static uint64_t omap_tcmi_read(void *opaque, hwaddr addr, 1272 unsigned size) 1273 { 1274 struct omap_mpu_state_s *s = opaque; 1275 uint32_t ret; 1276 1277 if (size != 4) { 1278 return omap_badwidth_read32(opaque, addr); 1279 } 1280 1281 switch (addr) { 1282 case 0x00: /* IMIF_PRIO */ 1283 case 0x04: /* EMIFS_PRIO */ 1284 case 0x08: /* EMIFF_PRIO */ 1285 case 0x0c: /* EMIFS_CONFIG */ 1286 case 0x10: /* EMIFS_CS0_CONFIG */ 1287 case 0x14: /* EMIFS_CS1_CONFIG */ 1288 case 0x18: /* EMIFS_CS2_CONFIG */ 1289 case 0x1c: /* EMIFS_CS3_CONFIG */ 1290 case 0x24: /* EMIFF_MRS */ 1291 case 0x28: /* TIMEOUT1 */ 1292 case 0x2c: /* TIMEOUT2 */ 1293 case 0x30: /* TIMEOUT3 */ 1294 case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */ 1295 case 0x40: /* EMIFS_CFG_DYN_WAIT */ 1296 return s->tcmi_regs[addr >> 2]; 1297 1298 case 0x20: /* EMIFF_SDRAM_CONFIG */ 1299 ret = s->tcmi_regs[addr >> 2]; 1300 s->tcmi_regs[addr >> 2] &= ~1; /* XXX: Clear SLRF on SDRAM access */ 1301 /* XXX: We can try using the VGA_DIRTY flag for this */ 1302 return ret; 1303 } 1304 1305 OMAP_BAD_REG(addr); 1306 return 0; 1307 } 1308 1309 static void omap_tcmi_write(void *opaque, hwaddr addr, 1310 uint64_t value, unsigned size) 1311 { 1312 struct omap_mpu_state_s *s = opaque; 1313 1314 if (size != 4) { 1315 omap_badwidth_write32(opaque, addr, value); 1316 return; 1317 } 1318 1319 switch (addr) { 1320 case 0x00: /* IMIF_PRIO */ 1321 case 0x04: /* EMIFS_PRIO */ 1322 case 0x08: /* EMIFF_PRIO */ 1323 case 0x10: /* EMIFS_CS0_CONFIG */ 1324 case 0x14: /* EMIFS_CS1_CONFIG */ 1325 case 0x18: /* EMIFS_CS2_CONFIG */ 1326 case 0x1c: /* EMIFS_CS3_CONFIG */ 1327 case 0x20: /* EMIFF_SDRAM_CONFIG */ 1328 case 0x24: /* EMIFF_MRS */ 1329 case 0x28: /* TIMEOUT1 */ 1330 case 0x2c: /* TIMEOUT2 */ 1331 case 0x30: /* TIMEOUT3 */ 1332 case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */ 1333 case 0x40: /* EMIFS_CFG_DYN_WAIT */ 1334 s->tcmi_regs[addr >> 2] = value; 1335 break; 1336 case 0x0c: /* EMIFS_CONFIG */ 1337 s->tcmi_regs[addr >> 2] = (value & 0xf) | (1 << 4); 1338 break; 1339 1340 default: 1341 OMAP_BAD_REG(addr); 1342 } 1343 } 1344 1345 static const MemoryRegionOps omap_tcmi_ops = { 1346 .read = omap_tcmi_read, 1347 .write = omap_tcmi_write, 1348 .endianness = DEVICE_NATIVE_ENDIAN, 1349 }; 1350 1351 static void omap_tcmi_reset(struct omap_mpu_state_s *mpu) 1352 { 1353 mpu->tcmi_regs[0x00 >> 2] = 0x00000000; 1354 mpu->tcmi_regs[0x04 >> 2] = 0x00000000; 1355 mpu->tcmi_regs[0x08 >> 2] = 0x00000000; 1356 mpu->tcmi_regs[0x0c >> 2] = 0x00000010; 1357 mpu->tcmi_regs[0x10 >> 2] = 0x0010fffb; 1358 mpu->tcmi_regs[0x14 >> 2] = 0x0010fffb; 1359 mpu->tcmi_regs[0x18 >> 2] = 0x0010fffb; 1360 mpu->tcmi_regs[0x1c >> 2] = 0x0010fffb; 1361 mpu->tcmi_regs[0x20 >> 2] = 0x00618800; 1362 mpu->tcmi_regs[0x24 >> 2] = 0x00000037; 1363 mpu->tcmi_regs[0x28 >> 2] = 0x00000000; 1364 mpu->tcmi_regs[0x2c >> 2] = 0x00000000; 1365 mpu->tcmi_regs[0x30 >> 2] = 0x00000000; 1366 mpu->tcmi_regs[0x3c >> 2] = 0x00000003; 1367 mpu->tcmi_regs[0x40 >> 2] = 0x00000000; 1368 } 1369 1370 static void omap_tcmi_init(MemoryRegion *memory, hwaddr base, 1371 struct omap_mpu_state_s *mpu) 1372 { 1373 memory_region_init_io(&mpu->tcmi_iomem, NULL, &omap_tcmi_ops, mpu, 1374 "omap-tcmi", 0x100); 1375 memory_region_add_subregion(memory, base, &mpu->tcmi_iomem); 1376 omap_tcmi_reset(mpu); 1377 } 1378 1379 /* Digital phase-locked loops control */ 1380 struct dpll_ctl_s { 1381 MemoryRegion iomem; 1382 uint16_t mode; 1383 omap_clk dpll; 1384 }; 1385 1386 static uint64_t omap_dpll_read(void *opaque, hwaddr addr, 1387 unsigned size) 1388 { 1389 struct dpll_ctl_s *s = opaque; 1390 1391 if (size != 2) { 1392 return omap_badwidth_read16(opaque, addr); 1393 } 1394 1395 if (addr == 0x00) /* CTL_REG */ 1396 return s->mode; 1397 1398 OMAP_BAD_REG(addr); 1399 return 0; 1400 } 1401 1402 static void omap_dpll_write(void *opaque, hwaddr addr, 1403 uint64_t value, unsigned size) 1404 { 1405 struct dpll_ctl_s *s = opaque; 1406 uint16_t diff; 1407 static const int bypass_div[4] = { 1, 2, 4, 4 }; 1408 int div, mult; 1409 1410 if (size != 2) { 1411 omap_badwidth_write16(opaque, addr, value); 1412 return; 1413 } 1414 1415 if (addr == 0x00) { /* CTL_REG */ 1416 /* See omap_ulpd_pm_write() too */ 1417 diff = s->mode & value; 1418 s->mode = value & 0x2fff; 1419 if (diff & (0x3ff << 2)) { 1420 if (value & (1 << 4)) { /* PLL_ENABLE */ 1421 div = ((value >> 5) & 3) + 1; /* PLL_DIV */ 1422 mult = MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */ 1423 } else { 1424 div = bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */ 1425 mult = 1; 1426 } 1427 omap_clk_setrate(s->dpll, div, mult); 1428 } 1429 1430 /* Enter the desired mode. */ 1431 s->mode = (s->mode & 0xfffe) | ((s->mode >> 4) & 1); 1432 1433 /* Act as if the lock is restored. */ 1434 s->mode |= 2; 1435 } else { 1436 OMAP_BAD_REG(addr); 1437 } 1438 } 1439 1440 static const MemoryRegionOps omap_dpll_ops = { 1441 .read = omap_dpll_read, 1442 .write = omap_dpll_write, 1443 .endianness = DEVICE_NATIVE_ENDIAN, 1444 }; 1445 1446 static void omap_dpll_reset(struct dpll_ctl_s *s) 1447 { 1448 s->mode = 0x2002; 1449 omap_clk_setrate(s->dpll, 1, 1); 1450 } 1451 1452 static struct dpll_ctl_s *omap_dpll_init(MemoryRegion *memory, 1453 hwaddr base, omap_clk clk) 1454 { 1455 struct dpll_ctl_s *s = g_malloc0(sizeof(*s)); 1456 memory_region_init_io(&s->iomem, NULL, &omap_dpll_ops, s, "omap-dpll", 0x100); 1457 1458 s->dpll = clk; 1459 omap_dpll_reset(s); 1460 1461 memory_region_add_subregion(memory, base, &s->iomem); 1462 return s; 1463 } 1464 1465 /* MPU Clock/Reset/Power Mode Control */ 1466 static uint64_t omap_clkm_read(void *opaque, hwaddr addr, 1467 unsigned size) 1468 { 1469 struct omap_mpu_state_s *s = opaque; 1470 1471 if (size != 2) { 1472 return omap_badwidth_read16(opaque, addr); 1473 } 1474 1475 switch (addr) { 1476 case 0x00: /* ARM_CKCTL */ 1477 return s->clkm.arm_ckctl; 1478 1479 case 0x04: /* ARM_IDLECT1 */ 1480 return s->clkm.arm_idlect1; 1481 1482 case 0x08: /* ARM_IDLECT2 */ 1483 return s->clkm.arm_idlect2; 1484 1485 case 0x0c: /* ARM_EWUPCT */ 1486 return s->clkm.arm_ewupct; 1487 1488 case 0x10: /* ARM_RSTCT1 */ 1489 return s->clkm.arm_rstct1; 1490 1491 case 0x14: /* ARM_RSTCT2 */ 1492 return s->clkm.arm_rstct2; 1493 1494 case 0x18: /* ARM_SYSST */ 1495 return (s->clkm.clocking_scheme << 11) | s->clkm.cold_start; 1496 1497 case 0x1c: /* ARM_CKOUT1 */ 1498 return s->clkm.arm_ckout1; 1499 1500 case 0x20: /* ARM_CKOUT2 */ 1501 break; 1502 } 1503 1504 OMAP_BAD_REG(addr); 1505 return 0; 1506 } 1507 1508 static inline void omap_clkm_ckctl_update(struct omap_mpu_state_s *s, 1509 uint16_t diff, uint16_t value) 1510 { 1511 omap_clk clk; 1512 1513 if (diff & (1 << 14)) { /* ARM_INTHCK_SEL */ 1514 if (value & (1 << 14)) 1515 /* Reserved */; 1516 else { 1517 clk = omap_findclk(s, "arminth_ck"); 1518 omap_clk_reparent(clk, omap_findclk(s, "tc_ck")); 1519 } 1520 } 1521 if (diff & (1 << 12)) { /* ARM_TIMXO */ 1522 clk = omap_findclk(s, "armtim_ck"); 1523 if (value & (1 << 12)) 1524 omap_clk_reparent(clk, omap_findclk(s, "clkin")); 1525 else 1526 omap_clk_reparent(clk, omap_findclk(s, "ck_gen1")); 1527 } 1528 /* XXX: en_dspck */ 1529 if (diff & (3 << 10)) { /* DSPMMUDIV */ 1530 clk = omap_findclk(s, "dspmmu_ck"); 1531 omap_clk_setrate(clk, 1 << ((value >> 10) & 3), 1); 1532 } 1533 if (diff & (3 << 8)) { /* TCDIV */ 1534 clk = omap_findclk(s, "tc_ck"); 1535 omap_clk_setrate(clk, 1 << ((value >> 8) & 3), 1); 1536 } 1537 if (diff & (3 << 6)) { /* DSPDIV */ 1538 clk = omap_findclk(s, "dsp_ck"); 1539 omap_clk_setrate(clk, 1 << ((value >> 6) & 3), 1); 1540 } 1541 if (diff & (3 << 4)) { /* ARMDIV */ 1542 clk = omap_findclk(s, "arm_ck"); 1543 omap_clk_setrate(clk, 1 << ((value >> 4) & 3), 1); 1544 } 1545 if (diff & (3 << 2)) { /* LCDDIV */ 1546 clk = omap_findclk(s, "lcd_ck"); 1547 omap_clk_setrate(clk, 1 << ((value >> 2) & 3), 1); 1548 } 1549 if (diff & (3 << 0)) { /* PERDIV */ 1550 clk = omap_findclk(s, "armper_ck"); 1551 omap_clk_setrate(clk, 1 << ((value >> 0) & 3), 1); 1552 } 1553 } 1554 1555 static inline void omap_clkm_idlect1_update(struct omap_mpu_state_s *s, 1556 uint16_t diff, uint16_t value) 1557 { 1558 omap_clk clk; 1559 1560 if (value & (1 << 11)) { /* SETARM_IDLE */ 1561 cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT); 1562 } 1563 if (!(value & (1 << 10))) { /* WKUP_MODE */ 1564 /* XXX: disable wakeup from IRQ */ 1565 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); 1566 } 1567 1568 #define SET_CANIDLE(clock, bit) \ 1569 if (diff & (1 << bit)) { \ 1570 clk = omap_findclk(s, clock); \ 1571 omap_clk_canidle(clk, (value >> bit) & 1); \ 1572 } 1573 SET_CANIDLE("mpuwd_ck", 0) /* IDLWDT_ARM */ 1574 SET_CANIDLE("armxor_ck", 1) /* IDLXORP_ARM */ 1575 SET_CANIDLE("mpuper_ck", 2) /* IDLPER_ARM */ 1576 SET_CANIDLE("lcd_ck", 3) /* IDLLCD_ARM */ 1577 SET_CANIDLE("lb_ck", 4) /* IDLLB_ARM */ 1578 SET_CANIDLE("hsab_ck", 5) /* IDLHSAB_ARM */ 1579 SET_CANIDLE("tipb_ck", 6) /* IDLIF_ARM */ 1580 SET_CANIDLE("dma_ck", 6) /* IDLIF_ARM */ 1581 SET_CANIDLE("tc_ck", 6) /* IDLIF_ARM */ 1582 SET_CANIDLE("dpll1", 7) /* IDLDPLL_ARM */ 1583 SET_CANIDLE("dpll2", 7) /* IDLDPLL_ARM */ 1584 SET_CANIDLE("dpll3", 7) /* IDLDPLL_ARM */ 1585 SET_CANIDLE("mpui_ck", 8) /* IDLAPI_ARM */ 1586 SET_CANIDLE("armtim_ck", 9) /* IDLTIM_ARM */ 1587 } 1588 1589 static inline void omap_clkm_idlect2_update(struct omap_mpu_state_s *s, 1590 uint16_t diff, uint16_t value) 1591 { 1592 omap_clk clk; 1593 1594 #define SET_ONOFF(clock, bit) \ 1595 if (diff & (1 << bit)) { \ 1596 clk = omap_findclk(s, clock); \ 1597 omap_clk_onoff(clk, (value >> bit) & 1); \ 1598 } 1599 SET_ONOFF("mpuwd_ck", 0) /* EN_WDTCK */ 1600 SET_ONOFF("armxor_ck", 1) /* EN_XORPCK */ 1601 SET_ONOFF("mpuper_ck", 2) /* EN_PERCK */ 1602 SET_ONOFF("lcd_ck", 3) /* EN_LCDCK */ 1603 SET_ONOFF("lb_ck", 4) /* EN_LBCK */ 1604 SET_ONOFF("hsab_ck", 5) /* EN_HSABCK */ 1605 SET_ONOFF("mpui_ck", 6) /* EN_APICK */ 1606 SET_ONOFF("armtim_ck", 7) /* EN_TIMCK */ 1607 SET_CANIDLE("dma_ck", 8) /* DMACK_REQ */ 1608 SET_ONOFF("arm_gpio_ck", 9) /* EN_GPIOCK */ 1609 SET_ONOFF("lbfree_ck", 10) /* EN_LBFREECK */ 1610 } 1611 1612 static inline void omap_clkm_ckout1_update(struct omap_mpu_state_s *s, 1613 uint16_t diff, uint16_t value) 1614 { 1615 omap_clk clk; 1616 1617 if (diff & (3 << 4)) { /* TCLKOUT */ 1618 clk = omap_findclk(s, "tclk_out"); 1619 switch ((value >> 4) & 3) { 1620 case 1: 1621 omap_clk_reparent(clk, omap_findclk(s, "ck_gen3")); 1622 omap_clk_onoff(clk, 1); 1623 break; 1624 case 2: 1625 omap_clk_reparent(clk, omap_findclk(s, "tc_ck")); 1626 omap_clk_onoff(clk, 1); 1627 break; 1628 default: 1629 omap_clk_onoff(clk, 0); 1630 } 1631 } 1632 if (diff & (3 << 2)) { /* DCLKOUT */ 1633 clk = omap_findclk(s, "dclk_out"); 1634 switch ((value >> 2) & 3) { 1635 case 0: 1636 omap_clk_reparent(clk, omap_findclk(s, "dspmmu_ck")); 1637 break; 1638 case 1: 1639 omap_clk_reparent(clk, omap_findclk(s, "ck_gen2")); 1640 break; 1641 case 2: 1642 omap_clk_reparent(clk, omap_findclk(s, "dsp_ck")); 1643 break; 1644 case 3: 1645 omap_clk_reparent(clk, omap_findclk(s, "ck_ref14")); 1646 break; 1647 } 1648 } 1649 if (diff & (3 << 0)) { /* ACLKOUT */ 1650 clk = omap_findclk(s, "aclk_out"); 1651 switch ((value >> 0) & 3) { 1652 case 1: 1653 omap_clk_reparent(clk, omap_findclk(s, "ck_gen1")); 1654 omap_clk_onoff(clk, 1); 1655 break; 1656 case 2: 1657 omap_clk_reparent(clk, omap_findclk(s, "arm_ck")); 1658 omap_clk_onoff(clk, 1); 1659 break; 1660 case 3: 1661 omap_clk_reparent(clk, omap_findclk(s, "ck_ref14")); 1662 omap_clk_onoff(clk, 1); 1663 break; 1664 default: 1665 omap_clk_onoff(clk, 0); 1666 } 1667 } 1668 } 1669 1670 static void omap_clkm_write(void *opaque, hwaddr addr, 1671 uint64_t value, unsigned size) 1672 { 1673 struct omap_mpu_state_s *s = opaque; 1674 uint16_t diff; 1675 omap_clk clk; 1676 static const char *clkschemename[8] = { 1677 "fully synchronous", "fully asynchronous", "synchronous scalable", 1678 "mix mode 1", "mix mode 2", "bypass mode", "mix mode 3", "mix mode 4", 1679 }; 1680 1681 if (size != 2) { 1682 omap_badwidth_write16(opaque, addr, value); 1683 return; 1684 } 1685 1686 switch (addr) { 1687 case 0x00: /* ARM_CKCTL */ 1688 diff = s->clkm.arm_ckctl ^ value; 1689 s->clkm.arm_ckctl = value & 0x7fff; 1690 omap_clkm_ckctl_update(s, diff, value); 1691 return; 1692 1693 case 0x04: /* ARM_IDLECT1 */ 1694 diff = s->clkm.arm_idlect1 ^ value; 1695 s->clkm.arm_idlect1 = value & 0x0fff; 1696 omap_clkm_idlect1_update(s, diff, value); 1697 return; 1698 1699 case 0x08: /* ARM_IDLECT2 */ 1700 diff = s->clkm.arm_idlect2 ^ value; 1701 s->clkm.arm_idlect2 = value & 0x07ff; 1702 omap_clkm_idlect2_update(s, diff, value); 1703 return; 1704 1705 case 0x0c: /* ARM_EWUPCT */ 1706 s->clkm.arm_ewupct = value & 0x003f; 1707 return; 1708 1709 case 0x10: /* ARM_RSTCT1 */ 1710 diff = s->clkm.arm_rstct1 ^ value; 1711 s->clkm.arm_rstct1 = value & 0x0007; 1712 if (value & 9) { 1713 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 1714 s->clkm.cold_start = 0xa; 1715 } 1716 if (diff & ~value & 4) { /* DSP_RST */ 1717 omap_mpui_reset(s); 1718 omap_tipb_bridge_reset(s->private_tipb); 1719 omap_tipb_bridge_reset(s->public_tipb); 1720 } 1721 if (diff & 2) { /* DSP_EN */ 1722 clk = omap_findclk(s, "dsp_ck"); 1723 omap_clk_canidle(clk, (~value >> 1) & 1); 1724 } 1725 return; 1726 1727 case 0x14: /* ARM_RSTCT2 */ 1728 s->clkm.arm_rstct2 = value & 0x0001; 1729 return; 1730 1731 case 0x18: /* ARM_SYSST */ 1732 if ((s->clkm.clocking_scheme ^ (value >> 11)) & 7) { 1733 s->clkm.clocking_scheme = (value >> 11) & 7; 1734 printf("%s: clocking scheme set to %s\n", __func__, 1735 clkschemename[s->clkm.clocking_scheme]); 1736 } 1737 s->clkm.cold_start &= value & 0x3f; 1738 return; 1739 1740 case 0x1c: /* ARM_CKOUT1 */ 1741 diff = s->clkm.arm_ckout1 ^ value; 1742 s->clkm.arm_ckout1 = value & 0x003f; 1743 omap_clkm_ckout1_update(s, diff, value); 1744 return; 1745 1746 case 0x20: /* ARM_CKOUT2 */ 1747 default: 1748 OMAP_BAD_REG(addr); 1749 } 1750 } 1751 1752 static const MemoryRegionOps omap_clkm_ops = { 1753 .read = omap_clkm_read, 1754 .write = omap_clkm_write, 1755 .endianness = DEVICE_NATIVE_ENDIAN, 1756 }; 1757 1758 static uint64_t omap_clkdsp_read(void *opaque, hwaddr addr, 1759 unsigned size) 1760 { 1761 struct omap_mpu_state_s *s = opaque; 1762 CPUState *cpu = CPU(s->cpu); 1763 1764 if (size != 2) { 1765 return omap_badwidth_read16(opaque, addr); 1766 } 1767 1768 switch (addr) { 1769 case 0x04: /* DSP_IDLECT1 */ 1770 return s->clkm.dsp_idlect1; 1771 1772 case 0x08: /* DSP_IDLECT2 */ 1773 return s->clkm.dsp_idlect2; 1774 1775 case 0x14: /* DSP_RSTCT2 */ 1776 return s->clkm.dsp_rstct2; 1777 1778 case 0x18: /* DSP_SYSST */ 1779 return (s->clkm.clocking_scheme << 11) | s->clkm.cold_start | 1780 (cpu->halted << 6); /* Quite useless... */ 1781 } 1782 1783 OMAP_BAD_REG(addr); 1784 return 0; 1785 } 1786 1787 static inline void omap_clkdsp_idlect1_update(struct omap_mpu_state_s *s, 1788 uint16_t diff, uint16_t value) 1789 { 1790 omap_clk clk; 1791 1792 SET_CANIDLE("dspxor_ck", 1); /* IDLXORP_DSP */ 1793 } 1794 1795 static inline void omap_clkdsp_idlect2_update(struct omap_mpu_state_s *s, 1796 uint16_t diff, uint16_t value) 1797 { 1798 omap_clk clk; 1799 1800 SET_ONOFF("dspxor_ck", 1); /* EN_XORPCK */ 1801 } 1802 1803 static void omap_clkdsp_write(void *opaque, hwaddr addr, 1804 uint64_t value, unsigned size) 1805 { 1806 struct omap_mpu_state_s *s = opaque; 1807 uint16_t diff; 1808 1809 if (size != 2) { 1810 omap_badwidth_write16(opaque, addr, value); 1811 return; 1812 } 1813 1814 switch (addr) { 1815 case 0x04: /* DSP_IDLECT1 */ 1816 diff = s->clkm.dsp_idlect1 ^ value; 1817 s->clkm.dsp_idlect1 = value & 0x01f7; 1818 omap_clkdsp_idlect1_update(s, diff, value); 1819 break; 1820 1821 case 0x08: /* DSP_IDLECT2 */ 1822 s->clkm.dsp_idlect2 = value & 0x0037; 1823 diff = s->clkm.dsp_idlect1 ^ value; 1824 omap_clkdsp_idlect2_update(s, diff, value); 1825 break; 1826 1827 case 0x14: /* DSP_RSTCT2 */ 1828 s->clkm.dsp_rstct2 = value & 0x0001; 1829 break; 1830 1831 case 0x18: /* DSP_SYSST */ 1832 s->clkm.cold_start &= value & 0x3f; 1833 break; 1834 1835 default: 1836 OMAP_BAD_REG(addr); 1837 } 1838 } 1839 1840 static const MemoryRegionOps omap_clkdsp_ops = { 1841 .read = omap_clkdsp_read, 1842 .write = omap_clkdsp_write, 1843 .endianness = DEVICE_NATIVE_ENDIAN, 1844 }; 1845 1846 static void omap_clkm_reset(struct omap_mpu_state_s *s) 1847 { 1848 if (s->wdt && s->wdt->reset) 1849 s->clkm.cold_start = 0x6; 1850 s->clkm.clocking_scheme = 0; 1851 omap_clkm_ckctl_update(s, ~0, 0x3000); 1852 s->clkm.arm_ckctl = 0x3000; 1853 omap_clkm_idlect1_update(s, s->clkm.arm_idlect1 ^ 0x0400, 0x0400); 1854 s->clkm.arm_idlect1 = 0x0400; 1855 omap_clkm_idlect2_update(s, s->clkm.arm_idlect2 ^ 0x0100, 0x0100); 1856 s->clkm.arm_idlect2 = 0x0100; 1857 s->clkm.arm_ewupct = 0x003f; 1858 s->clkm.arm_rstct1 = 0x0000; 1859 s->clkm.arm_rstct2 = 0x0000; 1860 s->clkm.arm_ckout1 = 0x0015; 1861 s->clkm.dpll1_mode = 0x2002; 1862 omap_clkdsp_idlect1_update(s, s->clkm.dsp_idlect1 ^ 0x0040, 0x0040); 1863 s->clkm.dsp_idlect1 = 0x0040; 1864 omap_clkdsp_idlect2_update(s, ~0, 0x0000); 1865 s->clkm.dsp_idlect2 = 0x0000; 1866 s->clkm.dsp_rstct2 = 0x0000; 1867 } 1868 1869 static void omap_clkm_init(MemoryRegion *memory, hwaddr mpu_base, 1870 hwaddr dsp_base, struct omap_mpu_state_s *s) 1871 { 1872 memory_region_init_io(&s->clkm_iomem, NULL, &omap_clkm_ops, s, 1873 "omap-clkm", 0x100); 1874 memory_region_init_io(&s->clkdsp_iomem, NULL, &omap_clkdsp_ops, s, 1875 "omap-clkdsp", 0x1000); 1876 1877 s->clkm.arm_idlect1 = 0x03ff; 1878 s->clkm.arm_idlect2 = 0x0100; 1879 s->clkm.dsp_idlect1 = 0x0002; 1880 omap_clkm_reset(s); 1881 s->clkm.cold_start = 0x3a; 1882 1883 memory_region_add_subregion(memory, mpu_base, &s->clkm_iomem); 1884 memory_region_add_subregion(memory, dsp_base, &s->clkdsp_iomem); 1885 } 1886 1887 /* MPU I/O */ 1888 struct omap_mpuio_s { 1889 qemu_irq irq; 1890 qemu_irq kbd_irq; 1891 qemu_irq *in; 1892 qemu_irq handler[16]; 1893 qemu_irq wakeup; 1894 MemoryRegion iomem; 1895 1896 uint16_t inputs; 1897 uint16_t outputs; 1898 uint16_t dir; 1899 uint16_t edge; 1900 uint16_t mask; 1901 uint16_t ints; 1902 1903 uint16_t debounce; 1904 uint16_t latch; 1905 uint8_t event; 1906 1907 uint8_t buttons[5]; 1908 uint8_t row_latch; 1909 uint8_t cols; 1910 int kbd_mask; 1911 int clk; 1912 }; 1913 1914 static void omap_mpuio_set(void *opaque, int line, int level) 1915 { 1916 struct omap_mpuio_s *s = opaque; 1917 uint16_t prev = s->inputs; 1918 1919 if (level) 1920 s->inputs |= 1 << line; 1921 else 1922 s->inputs &= ~(1 << line); 1923 1924 if (((1 << line) & s->dir & ~s->mask) && s->clk) { 1925 if ((s->edge & s->inputs & ~prev) | (~s->edge & ~s->inputs & prev)) { 1926 s->ints |= 1 << line; 1927 qemu_irq_raise(s->irq); 1928 /* TODO: wakeup */ 1929 } 1930 if ((s->event & (1 << 0)) && /* SET_GPIO_EVENT_MODE */ 1931 (s->event >> 1) == line) /* PIN_SELECT */ 1932 s->latch = s->inputs; 1933 } 1934 } 1935 1936 static void omap_mpuio_kbd_update(struct omap_mpuio_s *s) 1937 { 1938 int i; 1939 uint8_t *row, rows = 0, cols = ~s->cols; 1940 1941 for (row = s->buttons + 4, i = 1 << 4; i; row --, i >>= 1) 1942 if (*row & cols) 1943 rows |= i; 1944 1945 qemu_set_irq(s->kbd_irq, rows && !s->kbd_mask && s->clk); 1946 s->row_latch = ~rows; 1947 } 1948 1949 static uint64_t omap_mpuio_read(void *opaque, hwaddr addr, 1950 unsigned size) 1951 { 1952 struct omap_mpuio_s *s = opaque; 1953 int offset = addr & OMAP_MPUI_REG_MASK; 1954 uint16_t ret; 1955 1956 if (size != 2) { 1957 return omap_badwidth_read16(opaque, addr); 1958 } 1959 1960 switch (offset) { 1961 case 0x00: /* INPUT_LATCH */ 1962 return s->inputs; 1963 1964 case 0x04: /* OUTPUT_REG */ 1965 return s->outputs; 1966 1967 case 0x08: /* IO_CNTL */ 1968 return s->dir; 1969 1970 case 0x10: /* KBR_LATCH */ 1971 return s->row_latch; 1972 1973 case 0x14: /* KBC_REG */ 1974 return s->cols; 1975 1976 case 0x18: /* GPIO_EVENT_MODE_REG */ 1977 return s->event; 1978 1979 case 0x1c: /* GPIO_INT_EDGE_REG */ 1980 return s->edge; 1981 1982 case 0x20: /* KBD_INT */ 1983 return (~s->row_latch & 0x1f) && !s->kbd_mask; 1984 1985 case 0x24: /* GPIO_INT */ 1986 ret = s->ints; 1987 s->ints &= s->mask; 1988 if (ret) 1989 qemu_irq_lower(s->irq); 1990 return ret; 1991 1992 case 0x28: /* KBD_MASKIT */ 1993 return s->kbd_mask; 1994 1995 case 0x2c: /* GPIO_MASKIT */ 1996 return s->mask; 1997 1998 case 0x30: /* GPIO_DEBOUNCING_REG */ 1999 return s->debounce; 2000 2001 case 0x34: /* GPIO_LATCH_REG */ 2002 return s->latch; 2003 } 2004 2005 OMAP_BAD_REG(addr); 2006 return 0; 2007 } 2008 2009 static void omap_mpuio_write(void *opaque, hwaddr addr, 2010 uint64_t value, unsigned size) 2011 { 2012 struct omap_mpuio_s *s = opaque; 2013 int offset = addr & OMAP_MPUI_REG_MASK; 2014 uint16_t diff; 2015 int ln; 2016 2017 if (size != 2) { 2018 omap_badwidth_write16(opaque, addr, value); 2019 return; 2020 } 2021 2022 switch (offset) { 2023 case 0x04: /* OUTPUT_REG */ 2024 diff = (s->outputs ^ value) & ~s->dir; 2025 s->outputs = value; 2026 while ((ln = ctz32(diff)) != 32) { 2027 if (s->handler[ln]) 2028 qemu_set_irq(s->handler[ln], (value >> ln) & 1); 2029 diff &= ~(1 << ln); 2030 } 2031 break; 2032 2033 case 0x08: /* IO_CNTL */ 2034 diff = s->outputs & (s->dir ^ value); 2035 s->dir = value; 2036 2037 value = s->outputs & ~s->dir; 2038 while ((ln = ctz32(diff)) != 32) { 2039 if (s->handler[ln]) 2040 qemu_set_irq(s->handler[ln], (value >> ln) & 1); 2041 diff &= ~(1 << ln); 2042 } 2043 break; 2044 2045 case 0x14: /* KBC_REG */ 2046 s->cols = value; 2047 omap_mpuio_kbd_update(s); 2048 break; 2049 2050 case 0x18: /* GPIO_EVENT_MODE_REG */ 2051 s->event = value & 0x1f; 2052 break; 2053 2054 case 0x1c: /* GPIO_INT_EDGE_REG */ 2055 s->edge = value; 2056 break; 2057 2058 case 0x28: /* KBD_MASKIT */ 2059 s->kbd_mask = value & 1; 2060 omap_mpuio_kbd_update(s); 2061 break; 2062 2063 case 0x2c: /* GPIO_MASKIT */ 2064 s->mask = value; 2065 break; 2066 2067 case 0x30: /* GPIO_DEBOUNCING_REG */ 2068 s->debounce = value & 0x1ff; 2069 break; 2070 2071 case 0x00: /* INPUT_LATCH */ 2072 case 0x10: /* KBR_LATCH */ 2073 case 0x20: /* KBD_INT */ 2074 case 0x24: /* GPIO_INT */ 2075 case 0x34: /* GPIO_LATCH_REG */ 2076 OMAP_RO_REG(addr); 2077 return; 2078 2079 default: 2080 OMAP_BAD_REG(addr); 2081 return; 2082 } 2083 } 2084 2085 static const MemoryRegionOps omap_mpuio_ops = { 2086 .read = omap_mpuio_read, 2087 .write = omap_mpuio_write, 2088 .endianness = DEVICE_NATIVE_ENDIAN, 2089 }; 2090 2091 static void omap_mpuio_reset(struct omap_mpuio_s *s) 2092 { 2093 s->inputs = 0; 2094 s->outputs = 0; 2095 s->dir = ~0; 2096 s->event = 0; 2097 s->edge = 0; 2098 s->kbd_mask = 0; 2099 s->mask = 0; 2100 s->debounce = 0; 2101 s->latch = 0; 2102 s->ints = 0; 2103 s->row_latch = 0x1f; 2104 s->clk = 1; 2105 } 2106 2107 static void omap_mpuio_onoff(void *opaque, int line, int on) 2108 { 2109 struct omap_mpuio_s *s = opaque; 2110 2111 s->clk = on; 2112 if (on) 2113 omap_mpuio_kbd_update(s); 2114 } 2115 2116 static struct omap_mpuio_s *omap_mpuio_init(MemoryRegion *memory, 2117 hwaddr base, 2118 qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup, 2119 omap_clk clk) 2120 { 2121 struct omap_mpuio_s *s = g_new0(struct omap_mpuio_s, 1); 2122 2123 s->irq = gpio_int; 2124 s->kbd_irq = kbd_int; 2125 s->wakeup = wakeup; 2126 s->in = qemu_allocate_irqs(omap_mpuio_set, s, 16); 2127 omap_mpuio_reset(s); 2128 2129 memory_region_init_io(&s->iomem, NULL, &omap_mpuio_ops, s, 2130 "omap-mpuio", 0x800); 2131 memory_region_add_subregion(memory, base, &s->iomem); 2132 2133 omap_clk_adduser(clk, qemu_allocate_irq(omap_mpuio_onoff, s, 0)); 2134 2135 return s; 2136 } 2137 2138 qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s) 2139 { 2140 return s->in; 2141 } 2142 2143 void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler) 2144 { 2145 if (line >= 16 || line < 0) 2146 hw_error("%s: No GPIO line %i\n", __func__, line); 2147 s->handler[line] = handler; 2148 } 2149 2150 void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down) 2151 { 2152 if (row >= 5 || row < 0) 2153 hw_error("%s: No key %i-%i\n", __func__, col, row); 2154 2155 if (down) 2156 s->buttons[row] |= 1 << col; 2157 else 2158 s->buttons[row] &= ~(1 << col); 2159 2160 omap_mpuio_kbd_update(s); 2161 } 2162 2163 /* MicroWire Interface */ 2164 struct omap_uwire_s { 2165 MemoryRegion iomem; 2166 qemu_irq txirq; 2167 qemu_irq rxirq; 2168 qemu_irq txdrq; 2169 2170 uint16_t txbuf; 2171 uint16_t rxbuf; 2172 uint16_t control; 2173 uint16_t setup[5]; 2174 }; 2175 2176 static void omap_uwire_transfer_start(struct omap_uwire_s *s) 2177 { 2178 int chipselect = (s->control >> 10) & 3; /* INDEX */ 2179 2180 if ((s->control >> 5) & 0x1f) { /* NB_BITS_WR */ 2181 if (s->control & (1 << 12)) { /* CS_CMD */ 2182 qemu_log_mask(LOG_UNIMP, "uWireSlave TX CS:%d data:0x%04x\n", 2183 chipselect, 2184 s->txbuf >> (16 - ((s->control >> 5) & 0x1f))); 2185 } 2186 s->control &= ~(1 << 14); /* CSRB */ 2187 /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or 2188 * a DRQ. When is the level IRQ supposed to be reset? */ 2189 } 2190 2191 if ((s->control >> 0) & 0x1f) { /* NB_BITS_RD */ 2192 if (s->control & (1 << 12)) { /* CS_CMD */ 2193 qemu_log_mask(LOG_UNIMP, "uWireSlave RX CS:%d\n", chipselect); 2194 } 2195 s->control |= 1 << 15; /* RDRB */ 2196 /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or 2197 * a DRQ. When is the level IRQ supposed to be reset? */ 2198 } 2199 } 2200 2201 static uint64_t omap_uwire_read(void *opaque, hwaddr addr, unsigned size) 2202 { 2203 struct omap_uwire_s *s = opaque; 2204 int offset = addr & OMAP_MPUI_REG_MASK; 2205 2206 if (size != 2) { 2207 return omap_badwidth_read16(opaque, addr); 2208 } 2209 2210 switch (offset) { 2211 case 0x00: /* RDR */ 2212 s->control &= ~(1 << 15); /* RDRB */ 2213 return s->rxbuf; 2214 2215 case 0x04: /* CSR */ 2216 return s->control; 2217 2218 case 0x08: /* SR1 */ 2219 return s->setup[0]; 2220 case 0x0c: /* SR2 */ 2221 return s->setup[1]; 2222 case 0x10: /* SR3 */ 2223 return s->setup[2]; 2224 case 0x14: /* SR4 */ 2225 return s->setup[3]; 2226 case 0x18: /* SR5 */ 2227 return s->setup[4]; 2228 } 2229 2230 OMAP_BAD_REG(addr); 2231 return 0; 2232 } 2233 2234 static void omap_uwire_write(void *opaque, hwaddr addr, 2235 uint64_t value, unsigned size) 2236 { 2237 struct omap_uwire_s *s = opaque; 2238 int offset = addr & OMAP_MPUI_REG_MASK; 2239 2240 if (size != 2) { 2241 omap_badwidth_write16(opaque, addr, value); 2242 return; 2243 } 2244 2245 switch (offset) { 2246 case 0x00: /* TDR */ 2247 s->txbuf = value; /* TD */ 2248 if ((s->setup[4] & (1 << 2)) && /* AUTO_TX_EN */ 2249 ((s->setup[4] & (1 << 3)) || /* CS_TOGGLE_TX_EN */ 2250 (s->control & (1 << 12)))) { /* CS_CMD */ 2251 s->control |= 1 << 14; /* CSRB */ 2252 omap_uwire_transfer_start(s); 2253 } 2254 break; 2255 2256 case 0x04: /* CSR */ 2257 s->control = value & 0x1fff; 2258 if (value & (1 << 13)) /* START */ 2259 omap_uwire_transfer_start(s); 2260 break; 2261 2262 case 0x08: /* SR1 */ 2263 s->setup[0] = value & 0x003f; 2264 break; 2265 2266 case 0x0c: /* SR2 */ 2267 s->setup[1] = value & 0x0fc0; 2268 break; 2269 2270 case 0x10: /* SR3 */ 2271 s->setup[2] = value & 0x0003; 2272 break; 2273 2274 case 0x14: /* SR4 */ 2275 s->setup[3] = value & 0x0001; 2276 break; 2277 2278 case 0x18: /* SR5 */ 2279 s->setup[4] = value & 0x000f; 2280 break; 2281 2282 default: 2283 OMAP_BAD_REG(addr); 2284 return; 2285 } 2286 } 2287 2288 static const MemoryRegionOps omap_uwire_ops = { 2289 .read = omap_uwire_read, 2290 .write = omap_uwire_write, 2291 .endianness = DEVICE_NATIVE_ENDIAN, 2292 }; 2293 2294 static void omap_uwire_reset(struct omap_uwire_s *s) 2295 { 2296 s->control = 0; 2297 s->setup[0] = 0; 2298 s->setup[1] = 0; 2299 s->setup[2] = 0; 2300 s->setup[3] = 0; 2301 s->setup[4] = 0; 2302 } 2303 2304 static struct omap_uwire_s *omap_uwire_init(MemoryRegion *system_memory, 2305 hwaddr base, 2306 qemu_irq txirq, qemu_irq rxirq, 2307 qemu_irq dma, 2308 omap_clk clk) 2309 { 2310 struct omap_uwire_s *s = g_new0(struct omap_uwire_s, 1); 2311 2312 s->txirq = txirq; 2313 s->rxirq = rxirq; 2314 s->txdrq = dma; 2315 omap_uwire_reset(s); 2316 2317 memory_region_init_io(&s->iomem, NULL, &omap_uwire_ops, s, "omap-uwire", 0x800); 2318 memory_region_add_subregion(system_memory, base, &s->iomem); 2319 2320 return s; 2321 } 2322 2323 /* Pseudonoise Pulse-Width Light Modulator */ 2324 struct omap_pwl_s { 2325 MemoryRegion iomem; 2326 uint8_t output; 2327 uint8_t level; 2328 uint8_t enable; 2329 int clk; 2330 }; 2331 2332 static void omap_pwl_update(struct omap_pwl_s *s) 2333 { 2334 int output = (s->clk && s->enable) ? s->level : 0; 2335 2336 if (output != s->output) { 2337 s->output = output; 2338 printf("%s: Backlight now at %i/256\n", __func__, output); 2339 } 2340 } 2341 2342 static uint64_t omap_pwl_read(void *opaque, hwaddr addr, unsigned size) 2343 { 2344 struct omap_pwl_s *s = opaque; 2345 int offset = addr & OMAP_MPUI_REG_MASK; 2346 2347 if (size != 1) { 2348 return omap_badwidth_read8(opaque, addr); 2349 } 2350 2351 switch (offset) { 2352 case 0x00: /* PWL_LEVEL */ 2353 return s->level; 2354 case 0x04: /* PWL_CTRL */ 2355 return s->enable; 2356 } 2357 OMAP_BAD_REG(addr); 2358 return 0; 2359 } 2360 2361 static void omap_pwl_write(void *opaque, hwaddr addr, 2362 uint64_t value, unsigned size) 2363 { 2364 struct omap_pwl_s *s = opaque; 2365 int offset = addr & OMAP_MPUI_REG_MASK; 2366 2367 if (size != 1) { 2368 omap_badwidth_write8(opaque, addr, value); 2369 return; 2370 } 2371 2372 switch (offset) { 2373 case 0x00: /* PWL_LEVEL */ 2374 s->level = value; 2375 omap_pwl_update(s); 2376 break; 2377 case 0x04: /* PWL_CTRL */ 2378 s->enable = value & 1; 2379 omap_pwl_update(s); 2380 break; 2381 default: 2382 OMAP_BAD_REG(addr); 2383 return; 2384 } 2385 } 2386 2387 static const MemoryRegionOps omap_pwl_ops = { 2388 .read = omap_pwl_read, 2389 .write = omap_pwl_write, 2390 .endianness = DEVICE_NATIVE_ENDIAN, 2391 }; 2392 2393 static void omap_pwl_reset(struct omap_pwl_s *s) 2394 { 2395 s->output = 0; 2396 s->level = 0; 2397 s->enable = 0; 2398 s->clk = 1; 2399 omap_pwl_update(s); 2400 } 2401 2402 static void omap_pwl_clk_update(void *opaque, int line, int on) 2403 { 2404 struct omap_pwl_s *s = opaque; 2405 2406 s->clk = on; 2407 omap_pwl_update(s); 2408 } 2409 2410 static struct omap_pwl_s *omap_pwl_init(MemoryRegion *system_memory, 2411 hwaddr base, 2412 omap_clk clk) 2413 { 2414 struct omap_pwl_s *s = g_malloc0(sizeof(*s)); 2415 2416 omap_pwl_reset(s); 2417 2418 memory_region_init_io(&s->iomem, NULL, &omap_pwl_ops, s, 2419 "omap-pwl", 0x800); 2420 memory_region_add_subregion(system_memory, base, &s->iomem); 2421 2422 omap_clk_adduser(clk, qemu_allocate_irq(omap_pwl_clk_update, s, 0)); 2423 return s; 2424 } 2425 2426 /* Pulse-Width Tone module */ 2427 struct omap_pwt_s { 2428 MemoryRegion iomem; 2429 uint8_t frc; 2430 uint8_t vrc; 2431 uint8_t gcr; 2432 omap_clk clk; 2433 }; 2434 2435 static uint64_t omap_pwt_read(void *opaque, hwaddr addr, unsigned size) 2436 { 2437 struct omap_pwt_s *s = opaque; 2438 int offset = addr & OMAP_MPUI_REG_MASK; 2439 2440 if (size != 1) { 2441 return omap_badwidth_read8(opaque, addr); 2442 } 2443 2444 switch (offset) { 2445 case 0x00: /* FRC */ 2446 return s->frc; 2447 case 0x04: /* VCR */ 2448 return s->vrc; 2449 case 0x08: /* GCR */ 2450 return s->gcr; 2451 } 2452 OMAP_BAD_REG(addr); 2453 return 0; 2454 } 2455 2456 static void omap_pwt_write(void *opaque, hwaddr addr, 2457 uint64_t value, unsigned size) 2458 { 2459 struct omap_pwt_s *s = opaque; 2460 int offset = addr & OMAP_MPUI_REG_MASK; 2461 2462 if (size != 1) { 2463 omap_badwidth_write8(opaque, addr, value); 2464 return; 2465 } 2466 2467 switch (offset) { 2468 case 0x00: /* FRC */ 2469 s->frc = value & 0x3f; 2470 break; 2471 case 0x04: /* VRC */ 2472 if ((value ^ s->vrc) & 1) { 2473 if (value & 1) 2474 printf("%s: %iHz buzz on\n", __func__, (int) 2475 /* 1.5 MHz from a 12-MHz or 13-MHz PWT_CLK */ 2476 ((omap_clk_getrate(s->clk) >> 3) / 2477 /* Pre-multiplexer divider */ 2478 ((s->gcr & 2) ? 1 : 154) / 2479 /* Octave multiplexer */ 2480 (2 << (value & 3)) * 2481 /* 101/107 divider */ 2482 ((value & (1 << 2)) ? 101 : 107) * 2483 /* 49/55 divider */ 2484 ((value & (1 << 3)) ? 49 : 55) * 2485 /* 50/63 divider */ 2486 ((value & (1 << 4)) ? 50 : 63) * 2487 /* 80/127 divider */ 2488 ((value & (1 << 5)) ? 80 : 127) / 2489 (107 * 55 * 63 * 127))); 2490 else 2491 printf("%s: silence!\n", __func__); 2492 } 2493 s->vrc = value & 0x7f; 2494 break; 2495 case 0x08: /* GCR */ 2496 s->gcr = value & 3; 2497 break; 2498 default: 2499 OMAP_BAD_REG(addr); 2500 return; 2501 } 2502 } 2503 2504 static const MemoryRegionOps omap_pwt_ops = { 2505 .read =omap_pwt_read, 2506 .write = omap_pwt_write, 2507 .endianness = DEVICE_NATIVE_ENDIAN, 2508 }; 2509 2510 static void omap_pwt_reset(struct omap_pwt_s *s) 2511 { 2512 s->frc = 0; 2513 s->vrc = 0; 2514 s->gcr = 0; 2515 } 2516 2517 static struct omap_pwt_s *omap_pwt_init(MemoryRegion *system_memory, 2518 hwaddr base, 2519 omap_clk clk) 2520 { 2521 struct omap_pwt_s *s = g_malloc0(sizeof(*s)); 2522 s->clk = clk; 2523 omap_pwt_reset(s); 2524 2525 memory_region_init_io(&s->iomem, NULL, &omap_pwt_ops, s, 2526 "omap-pwt", 0x800); 2527 memory_region_add_subregion(system_memory, base, &s->iomem); 2528 return s; 2529 } 2530 2531 /* Real-time Clock module */ 2532 struct omap_rtc_s { 2533 MemoryRegion iomem; 2534 qemu_irq irq; 2535 qemu_irq alarm; 2536 QEMUTimer *clk; 2537 2538 uint8_t interrupts; 2539 uint8_t status; 2540 int16_t comp_reg; 2541 int running; 2542 int pm_am; 2543 int auto_comp; 2544 int round; 2545 struct tm alarm_tm; 2546 time_t alarm_ti; 2547 2548 struct tm current_tm; 2549 time_t ti; 2550 uint64_t tick; 2551 }; 2552 2553 static void omap_rtc_interrupts_update(struct omap_rtc_s *s) 2554 { 2555 /* s->alarm is level-triggered */ 2556 qemu_set_irq(s->alarm, (s->status >> 6) & 1); 2557 } 2558 2559 static void omap_rtc_alarm_update(struct omap_rtc_s *s) 2560 { 2561 s->alarm_ti = mktimegm(&s->alarm_tm); 2562 if (s->alarm_ti == -1) 2563 printf("%s: conversion failed\n", __func__); 2564 } 2565 2566 static uint64_t omap_rtc_read(void *opaque, hwaddr addr, unsigned size) 2567 { 2568 struct omap_rtc_s *s = opaque; 2569 int offset = addr & OMAP_MPUI_REG_MASK; 2570 uint8_t i; 2571 2572 if (size != 1) { 2573 return omap_badwidth_read8(opaque, addr); 2574 } 2575 2576 switch (offset) { 2577 case 0x00: /* SECONDS_REG */ 2578 return to_bcd(s->current_tm.tm_sec); 2579 2580 case 0x04: /* MINUTES_REG */ 2581 return to_bcd(s->current_tm.tm_min); 2582 2583 case 0x08: /* HOURS_REG */ 2584 if (s->pm_am) 2585 return ((s->current_tm.tm_hour > 11) << 7) | 2586 to_bcd(((s->current_tm.tm_hour - 1) % 12) + 1); 2587 else 2588 return to_bcd(s->current_tm.tm_hour); 2589 2590 case 0x0c: /* DAYS_REG */ 2591 return to_bcd(s->current_tm.tm_mday); 2592 2593 case 0x10: /* MONTHS_REG */ 2594 return to_bcd(s->current_tm.tm_mon + 1); 2595 2596 case 0x14: /* YEARS_REG */ 2597 return to_bcd(s->current_tm.tm_year % 100); 2598 2599 case 0x18: /* WEEK_REG */ 2600 return s->current_tm.tm_wday; 2601 2602 case 0x20: /* ALARM_SECONDS_REG */ 2603 return to_bcd(s->alarm_tm.tm_sec); 2604 2605 case 0x24: /* ALARM_MINUTES_REG */ 2606 return to_bcd(s->alarm_tm.tm_min); 2607 2608 case 0x28: /* ALARM_HOURS_REG */ 2609 if (s->pm_am) 2610 return ((s->alarm_tm.tm_hour > 11) << 7) | 2611 to_bcd(((s->alarm_tm.tm_hour - 1) % 12) + 1); 2612 else 2613 return to_bcd(s->alarm_tm.tm_hour); 2614 2615 case 0x2c: /* ALARM_DAYS_REG */ 2616 return to_bcd(s->alarm_tm.tm_mday); 2617 2618 case 0x30: /* ALARM_MONTHS_REG */ 2619 return to_bcd(s->alarm_tm.tm_mon + 1); 2620 2621 case 0x34: /* ALARM_YEARS_REG */ 2622 return to_bcd(s->alarm_tm.tm_year % 100); 2623 2624 case 0x40: /* RTC_CTRL_REG */ 2625 return (s->pm_am << 3) | (s->auto_comp << 2) | 2626 (s->round << 1) | s->running; 2627 2628 case 0x44: /* RTC_STATUS_REG */ 2629 i = s->status; 2630 s->status &= ~0x3d; 2631 return i; 2632 2633 case 0x48: /* RTC_INTERRUPTS_REG */ 2634 return s->interrupts; 2635 2636 case 0x4c: /* RTC_COMP_LSB_REG */ 2637 return ((uint16_t) s->comp_reg) & 0xff; 2638 2639 case 0x50: /* RTC_COMP_MSB_REG */ 2640 return ((uint16_t) s->comp_reg) >> 8; 2641 } 2642 2643 OMAP_BAD_REG(addr); 2644 return 0; 2645 } 2646 2647 static void omap_rtc_write(void *opaque, hwaddr addr, 2648 uint64_t value, unsigned size) 2649 { 2650 struct omap_rtc_s *s = opaque; 2651 int offset = addr & OMAP_MPUI_REG_MASK; 2652 struct tm new_tm; 2653 time_t ti[2]; 2654 2655 if (size != 1) { 2656 omap_badwidth_write8(opaque, addr, value); 2657 return; 2658 } 2659 2660 switch (offset) { 2661 case 0x00: /* SECONDS_REG */ 2662 #ifdef ALMDEBUG 2663 printf("RTC SEC_REG <-- %02x\n", value); 2664 #endif 2665 s->ti -= s->current_tm.tm_sec; 2666 s->ti += from_bcd(value); 2667 return; 2668 2669 case 0x04: /* MINUTES_REG */ 2670 #ifdef ALMDEBUG 2671 printf("RTC MIN_REG <-- %02x\n", value); 2672 #endif 2673 s->ti -= s->current_tm.tm_min * 60; 2674 s->ti += from_bcd(value) * 60; 2675 return; 2676 2677 case 0x08: /* HOURS_REG */ 2678 #ifdef ALMDEBUG 2679 printf("RTC HRS_REG <-- %02x\n", value); 2680 #endif 2681 s->ti -= s->current_tm.tm_hour * 3600; 2682 if (s->pm_am) { 2683 s->ti += (from_bcd(value & 0x3f) & 12) * 3600; 2684 s->ti += ((value >> 7) & 1) * 43200; 2685 } else 2686 s->ti += from_bcd(value & 0x3f) * 3600; 2687 return; 2688 2689 case 0x0c: /* DAYS_REG */ 2690 #ifdef ALMDEBUG 2691 printf("RTC DAY_REG <-- %02x\n", value); 2692 #endif 2693 s->ti -= s->current_tm.tm_mday * 86400; 2694 s->ti += from_bcd(value) * 86400; 2695 return; 2696 2697 case 0x10: /* MONTHS_REG */ 2698 #ifdef ALMDEBUG 2699 printf("RTC MTH_REG <-- %02x\n", value); 2700 #endif 2701 memcpy(&new_tm, &s->current_tm, sizeof(new_tm)); 2702 new_tm.tm_mon = from_bcd(value); 2703 ti[0] = mktimegm(&s->current_tm); 2704 ti[1] = mktimegm(&new_tm); 2705 2706 if (ti[0] != -1 && ti[1] != -1) { 2707 s->ti -= ti[0]; 2708 s->ti += ti[1]; 2709 } else { 2710 /* A less accurate version */ 2711 s->ti -= s->current_tm.tm_mon * 2592000; 2712 s->ti += from_bcd(value) * 2592000; 2713 } 2714 return; 2715 2716 case 0x14: /* YEARS_REG */ 2717 #ifdef ALMDEBUG 2718 printf("RTC YRS_REG <-- %02x\n", value); 2719 #endif 2720 memcpy(&new_tm, &s->current_tm, sizeof(new_tm)); 2721 new_tm.tm_year += from_bcd(value) - (new_tm.tm_year % 100); 2722 ti[0] = mktimegm(&s->current_tm); 2723 ti[1] = mktimegm(&new_tm); 2724 2725 if (ti[0] != -1 && ti[1] != -1) { 2726 s->ti -= ti[0]; 2727 s->ti += ti[1]; 2728 } else { 2729 /* A less accurate version */ 2730 s->ti -= (time_t)(s->current_tm.tm_year % 100) * 31536000; 2731 s->ti += (time_t)from_bcd(value) * 31536000; 2732 } 2733 return; 2734 2735 case 0x18: /* WEEK_REG */ 2736 return; /* Ignored */ 2737 2738 case 0x20: /* ALARM_SECONDS_REG */ 2739 #ifdef ALMDEBUG 2740 printf("ALM SEC_REG <-- %02x\n", value); 2741 #endif 2742 s->alarm_tm.tm_sec = from_bcd(value); 2743 omap_rtc_alarm_update(s); 2744 return; 2745 2746 case 0x24: /* ALARM_MINUTES_REG */ 2747 #ifdef ALMDEBUG 2748 printf("ALM MIN_REG <-- %02x\n", value); 2749 #endif 2750 s->alarm_tm.tm_min = from_bcd(value); 2751 omap_rtc_alarm_update(s); 2752 return; 2753 2754 case 0x28: /* ALARM_HOURS_REG */ 2755 #ifdef ALMDEBUG 2756 printf("ALM HRS_REG <-- %02x\n", value); 2757 #endif 2758 if (s->pm_am) 2759 s->alarm_tm.tm_hour = 2760 ((from_bcd(value & 0x3f)) % 12) + 2761 ((value >> 7) & 1) * 12; 2762 else 2763 s->alarm_tm.tm_hour = from_bcd(value); 2764 omap_rtc_alarm_update(s); 2765 return; 2766 2767 case 0x2c: /* ALARM_DAYS_REG */ 2768 #ifdef ALMDEBUG 2769 printf("ALM DAY_REG <-- %02x\n", value); 2770 #endif 2771 s->alarm_tm.tm_mday = from_bcd(value); 2772 omap_rtc_alarm_update(s); 2773 return; 2774 2775 case 0x30: /* ALARM_MONTHS_REG */ 2776 #ifdef ALMDEBUG 2777 printf("ALM MON_REG <-- %02x\n", value); 2778 #endif 2779 s->alarm_tm.tm_mon = from_bcd(value); 2780 omap_rtc_alarm_update(s); 2781 return; 2782 2783 case 0x34: /* ALARM_YEARS_REG */ 2784 #ifdef ALMDEBUG 2785 printf("ALM YRS_REG <-- %02x\n", value); 2786 #endif 2787 s->alarm_tm.tm_year = from_bcd(value); 2788 omap_rtc_alarm_update(s); 2789 return; 2790 2791 case 0x40: /* RTC_CTRL_REG */ 2792 #ifdef ALMDEBUG 2793 printf("RTC CONTROL <-- %02x\n", value); 2794 #endif 2795 s->pm_am = (value >> 3) & 1; 2796 s->auto_comp = (value >> 2) & 1; 2797 s->round = (value >> 1) & 1; 2798 s->running = value & 1; 2799 s->status &= 0xfd; 2800 s->status |= s->running << 1; 2801 return; 2802 2803 case 0x44: /* RTC_STATUS_REG */ 2804 #ifdef ALMDEBUG 2805 printf("RTC STATUSL <-- %02x\n", value); 2806 #endif 2807 s->status &= ~((value & 0xc0) ^ 0x80); 2808 omap_rtc_interrupts_update(s); 2809 return; 2810 2811 case 0x48: /* RTC_INTERRUPTS_REG */ 2812 #ifdef ALMDEBUG 2813 printf("RTC INTRS <-- %02x\n", value); 2814 #endif 2815 s->interrupts = value; 2816 return; 2817 2818 case 0x4c: /* RTC_COMP_LSB_REG */ 2819 #ifdef ALMDEBUG 2820 printf("RTC COMPLSB <-- %02x\n", value); 2821 #endif 2822 s->comp_reg &= 0xff00; 2823 s->comp_reg |= 0x00ff & value; 2824 return; 2825 2826 case 0x50: /* RTC_COMP_MSB_REG */ 2827 #ifdef ALMDEBUG 2828 printf("RTC COMPMSB <-- %02x\n", value); 2829 #endif 2830 s->comp_reg &= 0x00ff; 2831 s->comp_reg |= 0xff00 & (value << 8); 2832 return; 2833 2834 default: 2835 OMAP_BAD_REG(addr); 2836 return; 2837 } 2838 } 2839 2840 static const MemoryRegionOps omap_rtc_ops = { 2841 .read = omap_rtc_read, 2842 .write = omap_rtc_write, 2843 .endianness = DEVICE_NATIVE_ENDIAN, 2844 }; 2845 2846 static void omap_rtc_tick(void *opaque) 2847 { 2848 struct omap_rtc_s *s = opaque; 2849 2850 if (s->round) { 2851 /* Round to nearest full minute. */ 2852 if (s->current_tm.tm_sec < 30) 2853 s->ti -= s->current_tm.tm_sec; 2854 else 2855 s->ti += 60 - s->current_tm.tm_sec; 2856 2857 s->round = 0; 2858 } 2859 2860 localtime_r(&s->ti, &s->current_tm); 2861 2862 if ((s->interrupts & 0x08) && s->ti == s->alarm_ti) { 2863 s->status |= 0x40; 2864 omap_rtc_interrupts_update(s); 2865 } 2866 2867 if (s->interrupts & 0x04) 2868 switch (s->interrupts & 3) { 2869 case 0: 2870 s->status |= 0x04; 2871 qemu_irq_pulse(s->irq); 2872 break; 2873 case 1: 2874 if (s->current_tm.tm_sec) 2875 break; 2876 s->status |= 0x08; 2877 qemu_irq_pulse(s->irq); 2878 break; 2879 case 2: 2880 if (s->current_tm.tm_sec || s->current_tm.tm_min) 2881 break; 2882 s->status |= 0x10; 2883 qemu_irq_pulse(s->irq); 2884 break; 2885 case 3: 2886 if (s->current_tm.tm_sec || 2887 s->current_tm.tm_min || s->current_tm.tm_hour) 2888 break; 2889 s->status |= 0x20; 2890 qemu_irq_pulse(s->irq); 2891 break; 2892 } 2893 2894 /* Move on */ 2895 if (s->running) 2896 s->ti ++; 2897 s->tick += 1000; 2898 2899 /* 2900 * Every full hour add a rough approximation of the compensation 2901 * register to the 32kHz Timer (which drives the RTC) value. 2902 */ 2903 if (s->auto_comp && !s->current_tm.tm_sec && !s->current_tm.tm_min) 2904 s->tick += s->comp_reg * 1000 / 32768; 2905 2906 timer_mod(s->clk, s->tick); 2907 } 2908 2909 static void omap_rtc_reset(struct omap_rtc_s *s) 2910 { 2911 struct tm tm; 2912 2913 s->interrupts = 0; 2914 s->comp_reg = 0; 2915 s->running = 0; 2916 s->pm_am = 0; 2917 s->auto_comp = 0; 2918 s->round = 0; 2919 s->tick = qemu_clock_get_ms(rtc_clock); 2920 memset(&s->alarm_tm, 0, sizeof(s->alarm_tm)); 2921 s->alarm_tm.tm_mday = 0x01; 2922 s->status = 1 << 7; 2923 qemu_get_timedate(&tm, 0); 2924 s->ti = mktimegm(&tm); 2925 2926 omap_rtc_alarm_update(s); 2927 omap_rtc_tick(s); 2928 } 2929 2930 static struct omap_rtc_s *omap_rtc_init(MemoryRegion *system_memory, 2931 hwaddr base, 2932 qemu_irq timerirq, qemu_irq alarmirq, 2933 omap_clk clk) 2934 { 2935 struct omap_rtc_s *s = g_new0(struct omap_rtc_s, 1); 2936 2937 s->irq = timerirq; 2938 s->alarm = alarmirq; 2939 s->clk = timer_new_ms(rtc_clock, omap_rtc_tick, s); 2940 2941 omap_rtc_reset(s); 2942 2943 memory_region_init_io(&s->iomem, NULL, &omap_rtc_ops, s, 2944 "omap-rtc", 0x800); 2945 memory_region_add_subregion(system_memory, base, &s->iomem); 2946 2947 return s; 2948 } 2949 2950 /* Multi-channel Buffered Serial Port interfaces */ 2951 struct omap_mcbsp_s { 2952 MemoryRegion iomem; 2953 qemu_irq txirq; 2954 qemu_irq rxirq; 2955 qemu_irq txdrq; 2956 qemu_irq rxdrq; 2957 2958 uint16_t spcr[2]; 2959 uint16_t rcr[2]; 2960 uint16_t xcr[2]; 2961 uint16_t srgr[2]; 2962 uint16_t mcr[2]; 2963 uint16_t pcr; 2964 uint16_t rcer[8]; 2965 uint16_t xcer[8]; 2966 int tx_rate; 2967 int rx_rate; 2968 int tx_req; 2969 int rx_req; 2970 2971 I2SCodec *codec; 2972 QEMUTimer *source_timer; 2973 QEMUTimer *sink_timer; 2974 }; 2975 2976 static void omap_mcbsp_intr_update(struct omap_mcbsp_s *s) 2977 { 2978 int irq; 2979 2980 switch ((s->spcr[0] >> 4) & 3) { /* RINTM */ 2981 case 0: 2982 irq = (s->spcr[0] >> 1) & 1; /* RRDY */ 2983 break; 2984 case 3: 2985 irq = (s->spcr[0] >> 3) & 1; /* RSYNCERR */ 2986 break; 2987 default: 2988 irq = 0; 2989 break; 2990 } 2991 2992 if (irq) 2993 qemu_irq_pulse(s->rxirq); 2994 2995 switch ((s->spcr[1] >> 4) & 3) { /* XINTM */ 2996 case 0: 2997 irq = (s->spcr[1] >> 1) & 1; /* XRDY */ 2998 break; 2999 case 3: 3000 irq = (s->spcr[1] >> 3) & 1; /* XSYNCERR */ 3001 break; 3002 default: 3003 irq = 0; 3004 break; 3005 } 3006 3007 if (irq) 3008 qemu_irq_pulse(s->txirq); 3009 } 3010 3011 static void omap_mcbsp_rx_newdata(struct omap_mcbsp_s *s) 3012 { 3013 if ((s->spcr[0] >> 1) & 1) /* RRDY */ 3014 s->spcr[0] |= 1 << 2; /* RFULL */ 3015 s->spcr[0] |= 1 << 1; /* RRDY */ 3016 qemu_irq_raise(s->rxdrq); 3017 omap_mcbsp_intr_update(s); 3018 } 3019 3020 static void omap_mcbsp_source_tick(void *opaque) 3021 { 3022 struct omap_mcbsp_s *s = opaque; 3023 static const int bps[8] = { 0, 1, 1, 2, 2, 2, -255, -255 }; 3024 3025 if (!s->rx_rate) 3026 return; 3027 if (s->rx_req) 3028 printf("%s: Rx FIFO overrun\n", __func__); 3029 3030 s->rx_req = s->rx_rate << bps[(s->rcr[0] >> 5) & 7]; 3031 3032 omap_mcbsp_rx_newdata(s); 3033 timer_mod(s->source_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 3034 NANOSECONDS_PER_SECOND); 3035 } 3036 3037 static void omap_mcbsp_rx_start(struct omap_mcbsp_s *s) 3038 { 3039 if (!s->codec || !s->codec->rts) 3040 omap_mcbsp_source_tick(s); 3041 else if (s->codec->in.len) { 3042 s->rx_req = s->codec->in.len; 3043 omap_mcbsp_rx_newdata(s); 3044 } 3045 } 3046 3047 static void omap_mcbsp_rx_stop(struct omap_mcbsp_s *s) 3048 { 3049 timer_del(s->source_timer); 3050 } 3051 3052 static void omap_mcbsp_rx_done(struct omap_mcbsp_s *s) 3053 { 3054 s->spcr[0] &= ~(1 << 1); /* RRDY */ 3055 qemu_irq_lower(s->rxdrq); 3056 omap_mcbsp_intr_update(s); 3057 } 3058 3059 static void omap_mcbsp_tx_newdata(struct omap_mcbsp_s *s) 3060 { 3061 s->spcr[1] |= 1 << 1; /* XRDY */ 3062 qemu_irq_raise(s->txdrq); 3063 omap_mcbsp_intr_update(s); 3064 } 3065 3066 static void omap_mcbsp_sink_tick(void *opaque) 3067 { 3068 struct omap_mcbsp_s *s = opaque; 3069 static const int bps[8] = { 0, 1, 1, 2, 2, 2, -255, -255 }; 3070 3071 if (!s->tx_rate) 3072 return; 3073 if (s->tx_req) 3074 printf("%s: Tx FIFO underrun\n", __func__); 3075 3076 s->tx_req = s->tx_rate << bps[(s->xcr[0] >> 5) & 7]; 3077 3078 omap_mcbsp_tx_newdata(s); 3079 timer_mod(s->sink_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 3080 NANOSECONDS_PER_SECOND); 3081 } 3082 3083 static void omap_mcbsp_tx_start(struct omap_mcbsp_s *s) 3084 { 3085 if (!s->codec || !s->codec->cts) 3086 omap_mcbsp_sink_tick(s); 3087 else if (s->codec->out.size) { 3088 s->tx_req = s->codec->out.size; 3089 omap_mcbsp_tx_newdata(s); 3090 } 3091 } 3092 3093 static void omap_mcbsp_tx_done(struct omap_mcbsp_s *s) 3094 { 3095 s->spcr[1] &= ~(1 << 1); /* XRDY */ 3096 qemu_irq_lower(s->txdrq); 3097 omap_mcbsp_intr_update(s); 3098 if (s->codec && s->codec->cts) 3099 s->codec->tx_swallow(s->codec->opaque); 3100 } 3101 3102 static void omap_mcbsp_tx_stop(struct omap_mcbsp_s *s) 3103 { 3104 s->tx_req = 0; 3105 omap_mcbsp_tx_done(s); 3106 timer_del(s->sink_timer); 3107 } 3108 3109 static void omap_mcbsp_req_update(struct omap_mcbsp_s *s) 3110 { 3111 int prev_rx_rate, prev_tx_rate; 3112 int rx_rate = 0, tx_rate = 0; 3113 int cpu_rate = 1500000; /* XXX */ 3114 3115 /* TODO: check CLKSTP bit */ 3116 if (s->spcr[1] & (1 << 6)) { /* GRST */ 3117 if (s->spcr[0] & (1 << 0)) { /* RRST */ 3118 if ((s->srgr[1] & (1 << 13)) && /* CLKSM */ 3119 (s->pcr & (1 << 8))) { /* CLKRM */ 3120 if (~s->pcr & (1 << 7)) /* SCLKME */ 3121 rx_rate = cpu_rate / 3122 ((s->srgr[0] & 0xff) + 1); /* CLKGDV */ 3123 } else 3124 if (s->codec) 3125 rx_rate = s->codec->rx_rate; 3126 } 3127 3128 if (s->spcr[1] & (1 << 0)) { /* XRST */ 3129 if ((s->srgr[1] & (1 << 13)) && /* CLKSM */ 3130 (s->pcr & (1 << 9))) { /* CLKXM */ 3131 if (~s->pcr & (1 << 7)) /* SCLKME */ 3132 tx_rate = cpu_rate / 3133 ((s->srgr[0] & 0xff) + 1); /* CLKGDV */ 3134 } else 3135 if (s->codec) 3136 tx_rate = s->codec->tx_rate; 3137 } 3138 } 3139 prev_tx_rate = s->tx_rate; 3140 prev_rx_rate = s->rx_rate; 3141 s->tx_rate = tx_rate; 3142 s->rx_rate = rx_rate; 3143 3144 if (s->codec) 3145 s->codec->set_rate(s->codec->opaque, rx_rate, tx_rate); 3146 3147 if (!prev_tx_rate && tx_rate) 3148 omap_mcbsp_tx_start(s); 3149 else if (s->tx_rate && !tx_rate) 3150 omap_mcbsp_tx_stop(s); 3151 3152 if (!prev_rx_rate && rx_rate) 3153 omap_mcbsp_rx_start(s); 3154 else if (prev_tx_rate && !tx_rate) 3155 omap_mcbsp_rx_stop(s); 3156 } 3157 3158 static uint64_t omap_mcbsp_read(void *opaque, hwaddr addr, 3159 unsigned size) 3160 { 3161 struct omap_mcbsp_s *s = opaque; 3162 int offset = addr & OMAP_MPUI_REG_MASK; 3163 uint16_t ret; 3164 3165 if (size != 2) { 3166 return omap_badwidth_read16(opaque, addr); 3167 } 3168 3169 switch (offset) { 3170 case 0x00: /* DRR2 */ 3171 if (((s->rcr[0] >> 5) & 7) < 3) /* RWDLEN1 */ 3172 return 0x0000; 3173 /* Fall through. */ 3174 case 0x02: /* DRR1 */ 3175 if (s->rx_req < 2) { 3176 printf("%s: Rx FIFO underrun\n", __func__); 3177 omap_mcbsp_rx_done(s); 3178 } else { 3179 s->tx_req -= 2; 3180 if (s->codec && s->codec->in.len >= 2) { 3181 ret = s->codec->in.fifo[s->codec->in.start ++] << 8; 3182 ret |= s->codec->in.fifo[s->codec->in.start ++]; 3183 s->codec->in.len -= 2; 3184 } else 3185 ret = 0x0000; 3186 if (!s->tx_req) 3187 omap_mcbsp_rx_done(s); 3188 return ret; 3189 } 3190 return 0x0000; 3191 3192 case 0x04: /* DXR2 */ 3193 case 0x06: /* DXR1 */ 3194 return 0x0000; 3195 3196 case 0x08: /* SPCR2 */ 3197 return s->spcr[1]; 3198 case 0x0a: /* SPCR1 */ 3199 return s->spcr[0]; 3200 case 0x0c: /* RCR2 */ 3201 return s->rcr[1]; 3202 case 0x0e: /* RCR1 */ 3203 return s->rcr[0]; 3204 case 0x10: /* XCR2 */ 3205 return s->xcr[1]; 3206 case 0x12: /* XCR1 */ 3207 return s->xcr[0]; 3208 case 0x14: /* SRGR2 */ 3209 return s->srgr[1]; 3210 case 0x16: /* SRGR1 */ 3211 return s->srgr[0]; 3212 case 0x18: /* MCR2 */ 3213 return s->mcr[1]; 3214 case 0x1a: /* MCR1 */ 3215 return s->mcr[0]; 3216 case 0x1c: /* RCERA */ 3217 return s->rcer[0]; 3218 case 0x1e: /* RCERB */ 3219 return s->rcer[1]; 3220 case 0x20: /* XCERA */ 3221 return s->xcer[0]; 3222 case 0x22: /* XCERB */ 3223 return s->xcer[1]; 3224 case 0x24: /* PCR0 */ 3225 return s->pcr; 3226 case 0x26: /* RCERC */ 3227 return s->rcer[2]; 3228 case 0x28: /* RCERD */ 3229 return s->rcer[3]; 3230 case 0x2a: /* XCERC */ 3231 return s->xcer[2]; 3232 case 0x2c: /* XCERD */ 3233 return s->xcer[3]; 3234 case 0x2e: /* RCERE */ 3235 return s->rcer[4]; 3236 case 0x30: /* RCERF */ 3237 return s->rcer[5]; 3238 case 0x32: /* XCERE */ 3239 return s->xcer[4]; 3240 case 0x34: /* XCERF */ 3241 return s->xcer[5]; 3242 case 0x36: /* RCERG */ 3243 return s->rcer[6]; 3244 case 0x38: /* RCERH */ 3245 return s->rcer[7]; 3246 case 0x3a: /* XCERG */ 3247 return s->xcer[6]; 3248 case 0x3c: /* XCERH */ 3249 return s->xcer[7]; 3250 } 3251 3252 OMAP_BAD_REG(addr); 3253 return 0; 3254 } 3255 3256 static void omap_mcbsp_writeh(void *opaque, hwaddr addr, 3257 uint32_t value) 3258 { 3259 struct omap_mcbsp_s *s = opaque; 3260 int offset = addr & OMAP_MPUI_REG_MASK; 3261 3262 switch (offset) { 3263 case 0x00: /* DRR2 */ 3264 case 0x02: /* DRR1 */ 3265 OMAP_RO_REG(addr); 3266 return; 3267 3268 case 0x04: /* DXR2 */ 3269 if (((s->xcr[0] >> 5) & 7) < 3) /* XWDLEN1 */ 3270 return; 3271 /* Fall through. */ 3272 case 0x06: /* DXR1 */ 3273 if (s->tx_req > 1) { 3274 s->tx_req -= 2; 3275 if (s->codec && s->codec->cts) { 3276 s->codec->out.fifo[s->codec->out.len ++] = (value >> 8) & 0xff; 3277 s->codec->out.fifo[s->codec->out.len ++] = (value >> 0) & 0xff; 3278 } 3279 if (s->tx_req < 2) 3280 omap_mcbsp_tx_done(s); 3281 } else 3282 printf("%s: Tx FIFO overrun\n", __func__); 3283 return; 3284 3285 case 0x08: /* SPCR2 */ 3286 s->spcr[1] &= 0x0002; 3287 s->spcr[1] |= 0x03f9 & value; 3288 s->spcr[1] |= 0x0004 & (value << 2); /* XEMPTY := XRST */ 3289 if (~value & 1) /* XRST */ 3290 s->spcr[1] &= ~6; 3291 omap_mcbsp_req_update(s); 3292 return; 3293 case 0x0a: /* SPCR1 */ 3294 s->spcr[0] &= 0x0006; 3295 s->spcr[0] |= 0xf8f9 & value; 3296 if (value & (1 << 15)) /* DLB */ 3297 printf("%s: Digital Loopback mode enable attempt\n", __func__); 3298 if (~value & 1) { /* RRST */ 3299 s->spcr[0] &= ~6; 3300 s->rx_req = 0; 3301 omap_mcbsp_rx_done(s); 3302 } 3303 omap_mcbsp_req_update(s); 3304 return; 3305 3306 case 0x0c: /* RCR2 */ 3307 s->rcr[1] = value & 0xffff; 3308 return; 3309 case 0x0e: /* RCR1 */ 3310 s->rcr[0] = value & 0x7fe0; 3311 return; 3312 case 0x10: /* XCR2 */ 3313 s->xcr[1] = value & 0xffff; 3314 return; 3315 case 0x12: /* XCR1 */ 3316 s->xcr[0] = value & 0x7fe0; 3317 return; 3318 case 0x14: /* SRGR2 */ 3319 s->srgr[1] = value & 0xffff; 3320 omap_mcbsp_req_update(s); 3321 return; 3322 case 0x16: /* SRGR1 */ 3323 s->srgr[0] = value & 0xffff; 3324 omap_mcbsp_req_update(s); 3325 return; 3326 case 0x18: /* MCR2 */ 3327 s->mcr[1] = value & 0x03e3; 3328 if (value & 3) /* XMCM */ 3329 printf("%s: Tx channel selection mode enable attempt\n", __func__); 3330 return; 3331 case 0x1a: /* MCR1 */ 3332 s->mcr[0] = value & 0x03e1; 3333 if (value & 1) /* RMCM */ 3334 printf("%s: Rx channel selection mode enable attempt\n", __func__); 3335 return; 3336 case 0x1c: /* RCERA */ 3337 s->rcer[0] = value & 0xffff; 3338 return; 3339 case 0x1e: /* RCERB */ 3340 s->rcer[1] = value & 0xffff; 3341 return; 3342 case 0x20: /* XCERA */ 3343 s->xcer[0] = value & 0xffff; 3344 return; 3345 case 0x22: /* XCERB */ 3346 s->xcer[1] = value & 0xffff; 3347 return; 3348 case 0x24: /* PCR0 */ 3349 s->pcr = value & 0x7faf; 3350 return; 3351 case 0x26: /* RCERC */ 3352 s->rcer[2] = value & 0xffff; 3353 return; 3354 case 0x28: /* RCERD */ 3355 s->rcer[3] = value & 0xffff; 3356 return; 3357 case 0x2a: /* XCERC */ 3358 s->xcer[2] = value & 0xffff; 3359 return; 3360 case 0x2c: /* XCERD */ 3361 s->xcer[3] = value & 0xffff; 3362 return; 3363 case 0x2e: /* RCERE */ 3364 s->rcer[4] = value & 0xffff; 3365 return; 3366 case 0x30: /* RCERF */ 3367 s->rcer[5] = value & 0xffff; 3368 return; 3369 case 0x32: /* XCERE */ 3370 s->xcer[4] = value & 0xffff; 3371 return; 3372 case 0x34: /* XCERF */ 3373 s->xcer[5] = value & 0xffff; 3374 return; 3375 case 0x36: /* RCERG */ 3376 s->rcer[6] = value & 0xffff; 3377 return; 3378 case 0x38: /* RCERH */ 3379 s->rcer[7] = value & 0xffff; 3380 return; 3381 case 0x3a: /* XCERG */ 3382 s->xcer[6] = value & 0xffff; 3383 return; 3384 case 0x3c: /* XCERH */ 3385 s->xcer[7] = value & 0xffff; 3386 return; 3387 } 3388 3389 OMAP_BAD_REG(addr); 3390 } 3391 3392 static void omap_mcbsp_writew(void *opaque, hwaddr addr, 3393 uint32_t value) 3394 { 3395 struct omap_mcbsp_s *s = opaque; 3396 int offset = addr & OMAP_MPUI_REG_MASK; 3397 3398 if (offset == 0x04) { /* DXR */ 3399 if (((s->xcr[0] >> 5) & 7) < 3) /* XWDLEN1 */ 3400 return; 3401 if (s->tx_req > 3) { 3402 s->tx_req -= 4; 3403 if (s->codec && s->codec->cts) { 3404 s->codec->out.fifo[s->codec->out.len ++] = 3405 (value >> 24) & 0xff; 3406 s->codec->out.fifo[s->codec->out.len ++] = 3407 (value >> 16) & 0xff; 3408 s->codec->out.fifo[s->codec->out.len ++] = 3409 (value >> 8) & 0xff; 3410 s->codec->out.fifo[s->codec->out.len ++] = 3411 (value >> 0) & 0xff; 3412 } 3413 if (s->tx_req < 4) 3414 omap_mcbsp_tx_done(s); 3415 } else 3416 printf("%s: Tx FIFO overrun\n", __func__); 3417 return; 3418 } 3419 3420 omap_badwidth_write16(opaque, addr, value); 3421 } 3422 3423 static void omap_mcbsp_write(void *opaque, hwaddr addr, 3424 uint64_t value, unsigned size) 3425 { 3426 switch (size) { 3427 case 2: 3428 omap_mcbsp_writeh(opaque, addr, value); 3429 break; 3430 case 4: 3431 omap_mcbsp_writew(opaque, addr, value); 3432 break; 3433 default: 3434 omap_badwidth_write16(opaque, addr, value); 3435 } 3436 } 3437 3438 static const MemoryRegionOps omap_mcbsp_ops = { 3439 .read = omap_mcbsp_read, 3440 .write = omap_mcbsp_write, 3441 .endianness = DEVICE_NATIVE_ENDIAN, 3442 }; 3443 3444 static void omap_mcbsp_reset(struct omap_mcbsp_s *s) 3445 { 3446 memset(&s->spcr, 0, sizeof(s->spcr)); 3447 memset(&s->rcr, 0, sizeof(s->rcr)); 3448 memset(&s->xcr, 0, sizeof(s->xcr)); 3449 s->srgr[0] = 0x0001; 3450 s->srgr[1] = 0x2000; 3451 memset(&s->mcr, 0, sizeof(s->mcr)); 3452 memset(&s->pcr, 0, sizeof(s->pcr)); 3453 memset(&s->rcer, 0, sizeof(s->rcer)); 3454 memset(&s->xcer, 0, sizeof(s->xcer)); 3455 s->tx_req = 0; 3456 s->rx_req = 0; 3457 s->tx_rate = 0; 3458 s->rx_rate = 0; 3459 timer_del(s->source_timer); 3460 timer_del(s->sink_timer); 3461 } 3462 3463 static struct omap_mcbsp_s *omap_mcbsp_init(MemoryRegion *system_memory, 3464 hwaddr base, 3465 qemu_irq txirq, qemu_irq rxirq, 3466 qemu_irq *dma, omap_clk clk) 3467 { 3468 struct omap_mcbsp_s *s = g_new0(struct omap_mcbsp_s, 1); 3469 3470 s->txirq = txirq; 3471 s->rxirq = rxirq; 3472 s->txdrq = dma[0]; 3473 s->rxdrq = dma[1]; 3474 s->sink_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_mcbsp_sink_tick, s); 3475 s->source_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_mcbsp_source_tick, s); 3476 omap_mcbsp_reset(s); 3477 3478 memory_region_init_io(&s->iomem, NULL, &omap_mcbsp_ops, s, "omap-mcbsp", 0x800); 3479 memory_region_add_subregion(system_memory, base, &s->iomem); 3480 3481 return s; 3482 } 3483 3484 static void omap_mcbsp_i2s_swallow(void *opaque, int line, int level) 3485 { 3486 struct omap_mcbsp_s *s = opaque; 3487 3488 if (s->rx_rate) { 3489 s->rx_req = s->codec->in.len; 3490 omap_mcbsp_rx_newdata(s); 3491 } 3492 } 3493 3494 static void omap_mcbsp_i2s_start(void *opaque, int line, int level) 3495 { 3496 struct omap_mcbsp_s *s = opaque; 3497 3498 if (s->tx_rate) { 3499 s->tx_req = s->codec->out.size; 3500 omap_mcbsp_tx_newdata(s); 3501 } 3502 } 3503 3504 void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, I2SCodec *slave) 3505 { 3506 s->codec = slave; 3507 slave->rx_swallow = qemu_allocate_irq(omap_mcbsp_i2s_swallow, s, 0); 3508 slave->tx_start = qemu_allocate_irq(omap_mcbsp_i2s_start, s, 0); 3509 } 3510 3511 /* LED Pulse Generators */ 3512 struct omap_lpg_s { 3513 MemoryRegion iomem; 3514 QEMUTimer *tm; 3515 3516 uint8_t control; 3517 uint8_t power; 3518 int64_t on; 3519 int64_t period; 3520 int clk; 3521 int cycle; 3522 }; 3523 3524 static void omap_lpg_tick(void *opaque) 3525 { 3526 struct omap_lpg_s *s = opaque; 3527 3528 if (s->cycle) 3529 timer_mod(s->tm, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + s->period - s->on); 3530 else 3531 timer_mod(s->tm, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + s->on); 3532 3533 s->cycle = !s->cycle; 3534 printf("%s: LED is %s\n", __func__, s->cycle ? "on" : "off"); 3535 } 3536 3537 static void omap_lpg_update(struct omap_lpg_s *s) 3538 { 3539 int64_t on, period = 1, ticks = 1000; 3540 static const int per[8] = { 1, 2, 4, 8, 12, 16, 20, 24 }; 3541 3542 if (~s->control & (1 << 6)) /* LPGRES */ 3543 on = 0; 3544 else if (s->control & (1 << 7)) /* PERM_ON */ 3545 on = period; 3546 else { 3547 period = muldiv64(ticks, per[s->control & 7], /* PERCTRL */ 3548 256 / 32); 3549 on = (s->clk && s->power) ? muldiv64(ticks, 3550 per[(s->control >> 3) & 7], 256) : 0; /* ONCTRL */ 3551 } 3552 3553 timer_del(s->tm); 3554 if (on == period && s->on < s->period) 3555 printf("%s: LED is on\n", __func__); 3556 else if (on == 0 && s->on) 3557 printf("%s: LED is off\n", __func__); 3558 else if (on && (on != s->on || period != s->period)) { 3559 s->cycle = 0; 3560 s->on = on; 3561 s->period = period; 3562 omap_lpg_tick(s); 3563 return; 3564 } 3565 3566 s->on = on; 3567 s->period = period; 3568 } 3569 3570 static void omap_lpg_reset(struct omap_lpg_s *s) 3571 { 3572 s->control = 0x00; 3573 s->power = 0x00; 3574 s->clk = 1; 3575 omap_lpg_update(s); 3576 } 3577 3578 static uint64_t omap_lpg_read(void *opaque, hwaddr addr, unsigned size) 3579 { 3580 struct omap_lpg_s *s = opaque; 3581 int offset = addr & OMAP_MPUI_REG_MASK; 3582 3583 if (size != 1) { 3584 return omap_badwidth_read8(opaque, addr); 3585 } 3586 3587 switch (offset) { 3588 case 0x00: /* LCR */ 3589 return s->control; 3590 3591 case 0x04: /* PMR */ 3592 return s->power; 3593 } 3594 3595 OMAP_BAD_REG(addr); 3596 return 0; 3597 } 3598 3599 static void omap_lpg_write(void *opaque, hwaddr addr, 3600 uint64_t value, unsigned size) 3601 { 3602 struct omap_lpg_s *s = opaque; 3603 int offset = addr & OMAP_MPUI_REG_MASK; 3604 3605 if (size != 1) { 3606 omap_badwidth_write8(opaque, addr, value); 3607 return; 3608 } 3609 3610 switch (offset) { 3611 case 0x00: /* LCR */ 3612 if (~value & (1 << 6)) /* LPGRES */ 3613 omap_lpg_reset(s); 3614 s->control = value & 0xff; 3615 omap_lpg_update(s); 3616 return; 3617 3618 case 0x04: /* PMR */ 3619 s->power = value & 0x01; 3620 omap_lpg_update(s); 3621 return; 3622 3623 default: 3624 OMAP_BAD_REG(addr); 3625 return; 3626 } 3627 } 3628 3629 static const MemoryRegionOps omap_lpg_ops = { 3630 .read = omap_lpg_read, 3631 .write = omap_lpg_write, 3632 .endianness = DEVICE_NATIVE_ENDIAN, 3633 }; 3634 3635 static void omap_lpg_clk_update(void *opaque, int line, int on) 3636 { 3637 struct omap_lpg_s *s = opaque; 3638 3639 s->clk = on; 3640 omap_lpg_update(s); 3641 } 3642 3643 static struct omap_lpg_s *omap_lpg_init(MemoryRegion *system_memory, 3644 hwaddr base, omap_clk clk) 3645 { 3646 struct omap_lpg_s *s = g_new0(struct omap_lpg_s, 1); 3647 3648 s->tm = timer_new_ms(QEMU_CLOCK_VIRTUAL, omap_lpg_tick, s); 3649 3650 omap_lpg_reset(s); 3651 3652 memory_region_init_io(&s->iomem, NULL, &omap_lpg_ops, s, "omap-lpg", 0x800); 3653 memory_region_add_subregion(system_memory, base, &s->iomem); 3654 3655 omap_clk_adduser(clk, qemu_allocate_irq(omap_lpg_clk_update, s, 0)); 3656 3657 return s; 3658 } 3659 3660 /* MPUI Peripheral Bridge configuration */ 3661 static uint64_t omap_mpui_io_read(void *opaque, hwaddr addr, 3662 unsigned size) 3663 { 3664 if (size != 2) { 3665 return omap_badwidth_read16(opaque, addr); 3666 } 3667 3668 if (addr == OMAP_MPUI_BASE) /* CMR */ 3669 return 0xfe4d; 3670 3671 OMAP_BAD_REG(addr); 3672 return 0; 3673 } 3674 3675 static void omap_mpui_io_write(void *opaque, hwaddr addr, 3676 uint64_t value, unsigned size) 3677 { 3678 /* FIXME: infinite loop */ 3679 omap_badwidth_write16(opaque, addr, value); 3680 } 3681 3682 static const MemoryRegionOps omap_mpui_io_ops = { 3683 .read = omap_mpui_io_read, 3684 .write = omap_mpui_io_write, 3685 .endianness = DEVICE_NATIVE_ENDIAN, 3686 }; 3687 3688 static void omap_setup_mpui_io(MemoryRegion *system_memory, 3689 struct omap_mpu_state_s *mpu) 3690 { 3691 memory_region_init_io(&mpu->mpui_io_iomem, NULL, &omap_mpui_io_ops, mpu, 3692 "omap-mpui-io", 0x7fff); 3693 memory_region_add_subregion(system_memory, OMAP_MPUI_BASE, 3694 &mpu->mpui_io_iomem); 3695 } 3696 3697 /* General chip reset */ 3698 static void omap1_mpu_reset(void *opaque) 3699 { 3700 struct omap_mpu_state_s *mpu = opaque; 3701 3702 omap_dma_reset(mpu->dma); 3703 omap_mpu_timer_reset(mpu->timer[0]); 3704 omap_mpu_timer_reset(mpu->timer[1]); 3705 omap_mpu_timer_reset(mpu->timer[2]); 3706 omap_wd_timer_reset(mpu->wdt); 3707 omap_os_timer_reset(mpu->os_timer); 3708 omap_lcdc_reset(mpu->lcd); 3709 omap_ulpd_pm_reset(mpu); 3710 omap_pin_cfg_reset(mpu); 3711 omap_mpui_reset(mpu); 3712 omap_tipb_bridge_reset(mpu->private_tipb); 3713 omap_tipb_bridge_reset(mpu->public_tipb); 3714 omap_dpll_reset(mpu->dpll[0]); 3715 omap_dpll_reset(mpu->dpll[1]); 3716 omap_dpll_reset(mpu->dpll[2]); 3717 omap_uart_reset(mpu->uart[0]); 3718 omap_uart_reset(mpu->uart[1]); 3719 omap_uart_reset(mpu->uart[2]); 3720 omap_mpuio_reset(mpu->mpuio); 3721 omap_uwire_reset(mpu->microwire); 3722 omap_pwl_reset(mpu->pwl); 3723 omap_pwt_reset(mpu->pwt); 3724 omap_rtc_reset(mpu->rtc); 3725 omap_mcbsp_reset(mpu->mcbsp1); 3726 omap_mcbsp_reset(mpu->mcbsp2); 3727 omap_mcbsp_reset(mpu->mcbsp3); 3728 omap_lpg_reset(mpu->led[0]); 3729 omap_lpg_reset(mpu->led[1]); 3730 omap_clkm_reset(mpu); 3731 cpu_reset(CPU(mpu->cpu)); 3732 } 3733 3734 static const struct omap_map_s { 3735 hwaddr phys_dsp; 3736 hwaddr phys_mpu; 3737 uint32_t size; 3738 const char *name; 3739 } omap15xx_dsp_mm[] = { 3740 /* Strobe 0 */ 3741 { 0xe1010000, 0xfffb0000, 0x800, "UART1 BT" }, /* CS0 */ 3742 { 0xe1010800, 0xfffb0800, 0x800, "UART2 COM" }, /* CS1 */ 3743 { 0xe1011800, 0xfffb1800, 0x800, "McBSP1 audio" }, /* CS3 */ 3744 { 0xe1012000, 0xfffb2000, 0x800, "MCSI2 communication" }, /* CS4 */ 3745 { 0xe1012800, 0xfffb2800, 0x800, "MCSI1 BT u-Law" }, /* CS5 */ 3746 { 0xe1013000, 0xfffb3000, 0x800, "uWire" }, /* CS6 */ 3747 { 0xe1013800, 0xfffb3800, 0x800, "I^2C" }, /* CS7 */ 3748 { 0xe1014000, 0xfffb4000, 0x800, "USB W2FC" }, /* CS8 */ 3749 { 0xe1014800, 0xfffb4800, 0x800, "RTC" }, /* CS9 */ 3750 { 0xe1015000, 0xfffb5000, 0x800, "MPUIO" }, /* CS10 */ 3751 { 0xe1015800, 0xfffb5800, 0x800, "PWL" }, /* CS11 */ 3752 { 0xe1016000, 0xfffb6000, 0x800, "PWT" }, /* CS12 */ 3753 { 0xe1017000, 0xfffb7000, 0x800, "McBSP3" }, /* CS14 */ 3754 { 0xe1017800, 0xfffb7800, 0x800, "MMC" }, /* CS15 */ 3755 { 0xe1019000, 0xfffb9000, 0x800, "32-kHz timer" }, /* CS18 */ 3756 { 0xe1019800, 0xfffb9800, 0x800, "UART3" }, /* CS19 */ 3757 { 0xe101c800, 0xfffbc800, 0x800, "TIPB switches" }, /* CS25 */ 3758 /* Strobe 1 */ 3759 { 0xe101e000, 0xfffce000, 0x800, "GPIOs" }, /* CS28 */ 3760 3761 { 0 } 3762 }; 3763 3764 static void omap_setup_dsp_mapping(MemoryRegion *system_memory, 3765 const struct omap_map_s *map) 3766 { 3767 MemoryRegion *io; 3768 3769 for (; map->phys_dsp; map ++) { 3770 io = g_new(MemoryRegion, 1); 3771 memory_region_init_alias(io, NULL, map->name, 3772 system_memory, map->phys_mpu, map->size); 3773 memory_region_add_subregion(system_memory, map->phys_dsp, io); 3774 } 3775 } 3776 3777 void omap_mpu_wakeup(void *opaque, int irq, int req) 3778 { 3779 struct omap_mpu_state_s *mpu = opaque; 3780 CPUState *cpu = CPU(mpu->cpu); 3781 3782 if (cpu->halted) { 3783 cpu_interrupt(cpu, CPU_INTERRUPT_EXITTB); 3784 } 3785 } 3786 3787 static const struct dma_irq_map omap1_dma_irq_map[] = { 3788 { 0, OMAP_INT_DMA_CH0_6 }, 3789 { 0, OMAP_INT_DMA_CH1_7 }, 3790 { 0, OMAP_INT_DMA_CH2_8 }, 3791 { 0, OMAP_INT_DMA_CH3 }, 3792 { 0, OMAP_INT_DMA_CH4 }, 3793 { 0, OMAP_INT_DMA_CH5 }, 3794 { 1, OMAP_INT_1610_DMA_CH6 }, 3795 { 1, OMAP_INT_1610_DMA_CH7 }, 3796 { 1, OMAP_INT_1610_DMA_CH8 }, 3797 { 1, OMAP_INT_1610_DMA_CH9 }, 3798 { 1, OMAP_INT_1610_DMA_CH10 }, 3799 { 1, OMAP_INT_1610_DMA_CH11 }, 3800 { 1, OMAP_INT_1610_DMA_CH12 }, 3801 { 1, OMAP_INT_1610_DMA_CH13 }, 3802 { 1, OMAP_INT_1610_DMA_CH14 }, 3803 { 1, OMAP_INT_1610_DMA_CH15 } 3804 }; 3805 3806 /* DMA ports for OMAP1 */ 3807 static int omap_validate_emiff_addr(struct omap_mpu_state_s *s, 3808 hwaddr addr) 3809 { 3810 return range_covers_byte(OMAP_EMIFF_BASE, s->sdram_size, addr); 3811 } 3812 3813 static int omap_validate_emifs_addr(struct omap_mpu_state_s *s, 3814 hwaddr addr) 3815 { 3816 return range_covers_byte(OMAP_EMIFS_BASE, OMAP_EMIFF_BASE - OMAP_EMIFS_BASE, 3817 addr); 3818 } 3819 3820 static int omap_validate_imif_addr(struct omap_mpu_state_s *s, 3821 hwaddr addr) 3822 { 3823 return range_covers_byte(OMAP_IMIF_BASE, s->sram_size, addr); 3824 } 3825 3826 static int omap_validate_tipb_addr(struct omap_mpu_state_s *s, 3827 hwaddr addr) 3828 { 3829 return range_covers_byte(0xfffb0000, 0xffff0000 - 0xfffb0000, addr); 3830 } 3831 3832 static int omap_validate_local_addr(struct omap_mpu_state_s *s, 3833 hwaddr addr) 3834 { 3835 return range_covers_byte(OMAP_LOCALBUS_BASE, 0x1000000, addr); 3836 } 3837 3838 static int omap_validate_tipb_mpui_addr(struct omap_mpu_state_s *s, 3839 hwaddr addr) 3840 { 3841 return range_covers_byte(0xe1010000, 0xe1020004 - 0xe1010000, addr); 3842 } 3843 3844 struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *dram, 3845 const char *cpu_type) 3846 { 3847 int i; 3848 struct omap_mpu_state_s *s = g_new0(struct omap_mpu_state_s, 1); 3849 qemu_irq dma_irqs[6]; 3850 DriveInfo *dinfo; 3851 SysBusDevice *busdev; 3852 MemoryRegion *system_memory = get_system_memory(); 3853 3854 /* Core */ 3855 s->mpu_model = omap310; 3856 s->cpu = ARM_CPU(cpu_create(cpu_type)); 3857 s->sdram_size = memory_region_size(dram); 3858 s->sram_size = OMAP15XX_SRAM_SIZE; 3859 3860 s->wakeup = qemu_allocate_irq(omap_mpu_wakeup, s, 0); 3861 3862 /* Clocks */ 3863 omap_clk_init(s); 3864 3865 /* Memory-mapped stuff */ 3866 memory_region_init_ram(&s->imif_ram, NULL, "omap1.sram", s->sram_size, 3867 &error_fatal); 3868 memory_region_add_subregion(system_memory, OMAP_IMIF_BASE, &s->imif_ram); 3869 3870 omap_clkm_init(system_memory, 0xfffece00, 0xe1008000, s); 3871 3872 s->ih[0] = qdev_new("omap-intc"); 3873 qdev_prop_set_uint32(s->ih[0], "size", 0x100); 3874 omap_intc_set_iclk(OMAP_INTC(s->ih[0]), omap_findclk(s, "arminth_ck")); 3875 busdev = SYS_BUS_DEVICE(s->ih[0]); 3876 sysbus_realize_and_unref(busdev, &error_fatal); 3877 sysbus_connect_irq(busdev, 0, 3878 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ)); 3879 sysbus_connect_irq(busdev, 1, 3880 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_FIQ)); 3881 sysbus_mmio_map(busdev, 0, 0xfffecb00); 3882 s->ih[1] = qdev_new("omap-intc"); 3883 qdev_prop_set_uint32(s->ih[1], "size", 0x800); 3884 omap_intc_set_iclk(OMAP_INTC(s->ih[1]), omap_findclk(s, "arminth_ck")); 3885 busdev = SYS_BUS_DEVICE(s->ih[1]); 3886 sysbus_realize_and_unref(busdev, &error_fatal); 3887 sysbus_connect_irq(busdev, 0, 3888 qdev_get_gpio_in(s->ih[0], OMAP_INT_15XX_IH2_IRQ)); 3889 /* The second interrupt controller's FIQ output is not wired up */ 3890 sysbus_mmio_map(busdev, 0, 0xfffe0000); 3891 3892 for (i = 0; i < 6; i++) { 3893 dma_irqs[i] = qdev_get_gpio_in(s->ih[omap1_dma_irq_map[i].ih], 3894 omap1_dma_irq_map[i].intr); 3895 } 3896 s->dma = omap_dma_init(0xfffed800, dma_irqs, system_memory, 3897 qdev_get_gpio_in(s->ih[0], OMAP_INT_DMA_LCD), 3898 s, omap_findclk(s, "dma_ck"), omap_dma_3_1); 3899 3900 s->port[emiff ].addr_valid = omap_validate_emiff_addr; 3901 s->port[emifs ].addr_valid = omap_validate_emifs_addr; 3902 s->port[imif ].addr_valid = omap_validate_imif_addr; 3903 s->port[tipb ].addr_valid = omap_validate_tipb_addr; 3904 s->port[local ].addr_valid = omap_validate_local_addr; 3905 s->port[tipb_mpui].addr_valid = omap_validate_tipb_mpui_addr; 3906 3907 /* Register SDRAM and SRAM DMA ports for fast transfers. */ 3908 soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(dram), 3909 OMAP_EMIFF_BASE, s->sdram_size); 3910 soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(&s->imif_ram), 3911 OMAP_IMIF_BASE, s->sram_size); 3912 3913 s->timer[0] = omap_mpu_timer_init(system_memory, 0xfffec500, 3914 qdev_get_gpio_in(s->ih[0], OMAP_INT_TIMER1), 3915 omap_findclk(s, "mputim_ck")); 3916 s->timer[1] = omap_mpu_timer_init(system_memory, 0xfffec600, 3917 qdev_get_gpio_in(s->ih[0], OMAP_INT_TIMER2), 3918 omap_findclk(s, "mputim_ck")); 3919 s->timer[2] = omap_mpu_timer_init(system_memory, 0xfffec700, 3920 qdev_get_gpio_in(s->ih[0], OMAP_INT_TIMER3), 3921 omap_findclk(s, "mputim_ck")); 3922 3923 s->wdt = omap_wd_timer_init(system_memory, 0xfffec800, 3924 qdev_get_gpio_in(s->ih[0], OMAP_INT_WD_TIMER), 3925 omap_findclk(s, "armwdt_ck")); 3926 3927 s->os_timer = omap_os_timer_init(system_memory, 0xfffb9000, 3928 qdev_get_gpio_in(s->ih[1], OMAP_INT_OS_TIMER), 3929 omap_findclk(s, "clk32-kHz")); 3930 3931 s->lcd = omap_lcdc_init(system_memory, 0xfffec000, 3932 qdev_get_gpio_in(s->ih[0], OMAP_INT_LCD_CTRL), 3933 omap_dma_get_lcdch(s->dma), 3934 omap_findclk(s, "lcd_ck")); 3935 3936 omap_ulpd_pm_init(system_memory, 0xfffe0800, s); 3937 omap_pin_cfg_init(system_memory, 0xfffe1000, s); 3938 omap_id_init(system_memory, s); 3939 3940 omap_mpui_init(system_memory, 0xfffec900, s); 3941 3942 s->private_tipb = omap_tipb_bridge_init(system_memory, 0xfffeca00, 3943 qdev_get_gpio_in(s->ih[0], OMAP_INT_BRIDGE_PRIV), 3944 omap_findclk(s, "tipb_ck")); 3945 s->public_tipb = omap_tipb_bridge_init(system_memory, 0xfffed300, 3946 qdev_get_gpio_in(s->ih[0], OMAP_INT_BRIDGE_PUB), 3947 omap_findclk(s, "tipb_ck")); 3948 3949 omap_tcmi_init(system_memory, 0xfffecc00, s); 3950 3951 s->uart[0] = omap_uart_init(0xfffb0000, 3952 qdev_get_gpio_in(s->ih[1], OMAP_INT_UART1), 3953 omap_findclk(s, "uart1_ck"), 3954 omap_findclk(s, "uart1_ck"), 3955 s->drq[OMAP_DMA_UART1_TX], s->drq[OMAP_DMA_UART1_RX], 3956 "uart1", 3957 serial_hd(0)); 3958 s->uart[1] = omap_uart_init(0xfffb0800, 3959 qdev_get_gpio_in(s->ih[1], OMAP_INT_UART2), 3960 omap_findclk(s, "uart2_ck"), 3961 omap_findclk(s, "uart2_ck"), 3962 s->drq[OMAP_DMA_UART2_TX], s->drq[OMAP_DMA_UART2_RX], 3963 "uart2", 3964 serial_hd(0) ? serial_hd(1) : NULL); 3965 s->uart[2] = omap_uart_init(0xfffb9800, 3966 qdev_get_gpio_in(s->ih[0], OMAP_INT_UART3), 3967 omap_findclk(s, "uart3_ck"), 3968 omap_findclk(s, "uart3_ck"), 3969 s->drq[OMAP_DMA_UART3_TX], s->drq[OMAP_DMA_UART3_RX], 3970 "uart3", 3971 serial_hd(0) && serial_hd(1) ? serial_hd(2) : NULL); 3972 3973 s->dpll[0] = omap_dpll_init(system_memory, 0xfffecf00, 3974 omap_findclk(s, "dpll1")); 3975 s->dpll[1] = omap_dpll_init(system_memory, 0xfffed000, 3976 omap_findclk(s, "dpll2")); 3977 s->dpll[2] = omap_dpll_init(system_memory, 0xfffed100, 3978 omap_findclk(s, "dpll3")); 3979 3980 dinfo = drive_get(IF_SD, 0, 0); 3981 if (!dinfo && !qtest_enabled()) { 3982 warn_report("missing SecureDigital device"); 3983 } 3984 3985 s->mmc = qdev_new(TYPE_OMAP_MMC); 3986 sysbus_realize_and_unref(SYS_BUS_DEVICE(s->mmc), &error_fatal); 3987 omap_mmc_set_clk(s->mmc, omap_findclk(s, "mmc_ck")); 3988 3989 memory_region_add_subregion(system_memory, 0xfffb7800, 3990 sysbus_mmio_get_region(SYS_BUS_DEVICE(s->mmc), 0)); 3991 qdev_connect_gpio_out_named(s->mmc, "dma-tx", 0, s->drq[OMAP_DMA_MMC_TX]); 3992 qdev_connect_gpio_out_named(s->mmc, "dma-rx", 0, s->drq[OMAP_DMA_MMC_RX]); 3993 sysbus_connect_irq(SYS_BUS_DEVICE(s->mmc), 0, 3994 qdev_get_gpio_in(s->ih[1], OMAP_INT_OQN)); 3995 3996 if (dinfo) { 3997 DeviceState *card = qdev_new(TYPE_SD_CARD); 3998 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo), 3999 &error_fatal); 4000 qdev_realize_and_unref(card, qdev_get_child_bus(s->mmc, "sd-bus"), 4001 &error_fatal); 4002 } 4003 4004 s->mpuio = omap_mpuio_init(system_memory, 0xfffb5000, 4005 qdev_get_gpio_in(s->ih[1], OMAP_INT_KEYBOARD), 4006 qdev_get_gpio_in(s->ih[1], OMAP_INT_MPUIO), 4007 s->wakeup, omap_findclk(s, "clk32-kHz")); 4008 4009 s->gpio = qdev_new("omap-gpio"); 4010 qdev_prop_set_int32(s->gpio, "mpu_model", s->mpu_model); 4011 omap_gpio_set_clk(OMAP1_GPIO(s->gpio), omap_findclk(s, "arm_gpio_ck")); 4012 sysbus_realize_and_unref(SYS_BUS_DEVICE(s->gpio), &error_fatal); 4013 sysbus_connect_irq(SYS_BUS_DEVICE(s->gpio), 0, 4014 qdev_get_gpio_in(s->ih[0], OMAP_INT_GPIO_BANK1)); 4015 sysbus_mmio_map(SYS_BUS_DEVICE(s->gpio), 0, 0xfffce000); 4016 4017 s->microwire = omap_uwire_init(system_memory, 0xfffb3000, 4018 qdev_get_gpio_in(s->ih[1], OMAP_INT_uWireTX), 4019 qdev_get_gpio_in(s->ih[1], OMAP_INT_uWireRX), 4020 s->drq[OMAP_DMA_UWIRE_TX], omap_findclk(s, "mpuper_ck")); 4021 4022 s->pwl = omap_pwl_init(system_memory, 0xfffb5800, 4023 omap_findclk(s, "armxor_ck")); 4024 s->pwt = omap_pwt_init(system_memory, 0xfffb6000, 4025 omap_findclk(s, "armxor_ck")); 4026 4027 s->i2c[0] = qdev_new("omap_i2c"); 4028 qdev_prop_set_uint8(s->i2c[0], "revision", 0x11); 4029 omap_i2c_set_fclk(OMAP_I2C(s->i2c[0]), omap_findclk(s, "mpuper_ck")); 4030 busdev = SYS_BUS_DEVICE(s->i2c[0]); 4031 sysbus_realize_and_unref(busdev, &error_fatal); 4032 sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(s->ih[1], OMAP_INT_I2C)); 4033 sysbus_connect_irq(busdev, 1, s->drq[OMAP_DMA_I2C_TX]); 4034 sysbus_connect_irq(busdev, 2, s->drq[OMAP_DMA_I2C_RX]); 4035 sysbus_mmio_map(busdev, 0, 0xfffb3800); 4036 4037 s->rtc = omap_rtc_init(system_memory, 0xfffb4800, 4038 qdev_get_gpio_in(s->ih[1], OMAP_INT_RTC_TIMER), 4039 qdev_get_gpio_in(s->ih[1], OMAP_INT_RTC_ALARM), 4040 omap_findclk(s, "clk32-kHz")); 4041 4042 s->mcbsp1 = omap_mcbsp_init(system_memory, 0xfffb1800, 4043 qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP1TX), 4044 qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP1RX), 4045 &s->drq[OMAP_DMA_MCBSP1_TX], omap_findclk(s, "dspxor_ck")); 4046 s->mcbsp2 = omap_mcbsp_init(system_memory, 0xfffb1000, 4047 qdev_get_gpio_in(s->ih[0], 4048 OMAP_INT_310_McBSP2_TX), 4049 qdev_get_gpio_in(s->ih[0], 4050 OMAP_INT_310_McBSP2_RX), 4051 &s->drq[OMAP_DMA_MCBSP2_TX], omap_findclk(s, "mpuper_ck")); 4052 s->mcbsp3 = omap_mcbsp_init(system_memory, 0xfffb7000, 4053 qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP3TX), 4054 qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP3RX), 4055 &s->drq[OMAP_DMA_MCBSP3_TX], omap_findclk(s, "dspxor_ck")); 4056 4057 s->led[0] = omap_lpg_init(system_memory, 4058 0xfffbd000, omap_findclk(s, "clk32-kHz")); 4059 s->led[1] = omap_lpg_init(system_memory, 4060 0xfffbd800, omap_findclk(s, "clk32-kHz")); 4061 4062 /* Register mappings not currently implemented: 4063 * MCSI2 Comm fffb2000 - fffb27ff (not mapped on OMAP310) 4064 * MCSI1 Bluetooth fffb2800 - fffb2fff (not mapped on OMAP310) 4065 * USB W2FC fffb4000 - fffb47ff 4066 * Camera Interface fffb6800 - fffb6fff 4067 * USB Host fffba000 - fffba7ff 4068 * FAC fffba800 - fffbafff 4069 * HDQ/1-Wire fffbc000 - fffbc7ff 4070 * TIPB switches fffbc800 - fffbcfff 4071 * Mailbox fffcf000 - fffcf7ff 4072 * Local bus IF fffec100 - fffec1ff 4073 * Local bus MMU fffec200 - fffec2ff 4074 * DSP MMU fffed200 - fffed2ff 4075 */ 4076 4077 omap_setup_dsp_mapping(system_memory, omap15xx_dsp_mm); 4078 omap_setup_mpui_io(system_memory, s); 4079 4080 qemu_register_reset(omap1_mpu_reset, s); 4081 4082 return s; 4083 } 4084