1 /* 2 * Nordic Semiconductor nRF51 SoC 3 * http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.1.pdf 4 * 5 * Copyright 2018 Joel Stanley <joel@jms.id.au> 6 * 7 * This code is licensed under the GPL version 2 or later. See 8 * the COPYING file in the top-level directory. 9 */ 10 11 #include "qemu/osdep.h" 12 #include "qapi/error.h" 13 #include "hw/arm/boot.h" 14 #include "hw/sysbus.h" 15 #include "hw/misc/unimp.h" 16 #include "exec/address-spaces.h" 17 #include "qemu/log.h" 18 19 #include "hw/arm/nrf51.h" 20 #include "hw/arm/nrf51_soc.h" 21 22 /* 23 * The size and base is for the NRF51822 part. If other parts 24 * are supported in the future, add a sub-class of NRF51SoC for 25 * the specific variants 26 */ 27 #define NRF51822_FLASH_PAGES 256 28 #define NRF51822_SRAM_PAGES 16 29 #define NRF51822_FLASH_SIZE (NRF51822_FLASH_PAGES * NRF51_PAGE_SIZE) 30 #define NRF51822_SRAM_SIZE (NRF51822_SRAM_PAGES * NRF51_PAGE_SIZE) 31 32 #define BASE_TO_IRQ(base) ((base >> 12) & 0x1F) 33 34 /* HCLK (the main CPU clock) on this SoC is always 16MHz */ 35 #define HCLK_FRQ 16000000 36 37 static uint64_t clock_read(void *opaque, hwaddr addr, unsigned int size) 38 { 39 qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " [%u]\n", 40 __func__, addr, size); 41 return 1; 42 } 43 44 static void clock_write(void *opaque, hwaddr addr, uint64_t data, 45 unsigned int size) 46 { 47 qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " <- 0x%" PRIx64 " [%u]\n", 48 __func__, addr, data, size); 49 } 50 51 static const MemoryRegionOps clock_ops = { 52 .read = clock_read, 53 .write = clock_write 54 }; 55 56 57 static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp) 58 { 59 NRF51State *s = NRF51_SOC(dev_soc); 60 MemoryRegion *mr; 61 Error *err = NULL; 62 uint8_t i = 0; 63 hwaddr base_addr = 0; 64 65 if (!s->board_memory) { 66 error_setg(errp, "memory property was not set"); 67 return; 68 } 69 70 system_clock_scale = NANOSECONDS_PER_SECOND / HCLK_FRQ; 71 72 object_property_set_link(OBJECT(&s->cpu), "memory", OBJECT(&s->container), 73 &error_abort); 74 if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpu), errp)) { 75 return; 76 } 77 78 memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -1); 79 80 memory_region_init_ram(&s->sram, OBJECT(s), "nrf51.sram", s->sram_size, 81 &err); 82 if (err) { 83 error_propagate(errp, err); 84 return; 85 } 86 memory_region_add_subregion(&s->container, NRF51_SRAM_BASE, &s->sram); 87 88 /* UART */ 89 if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart), errp)) { 90 return; 91 } 92 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->uart), 0); 93 memory_region_add_subregion_overlap(&s->container, NRF51_UART_BASE, mr, 0); 94 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 0, 95 qdev_get_gpio_in(DEVICE(&s->cpu), 96 BASE_TO_IRQ(NRF51_UART_BASE))); 97 98 /* RNG */ 99 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rng), errp)) { 100 return; 101 } 102 103 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->rng), 0); 104 memory_region_add_subregion_overlap(&s->container, NRF51_RNG_BASE, mr, 0); 105 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rng), 0, 106 qdev_get_gpio_in(DEVICE(&s->cpu), 107 BASE_TO_IRQ(NRF51_RNG_BASE))); 108 109 /* UICR, FICR, NVMC, FLASH */ 110 if (!object_property_set_uint(OBJECT(&s->nvm), "flash-size", 111 s->flash_size, errp)) { 112 return; 113 } 114 115 if (!sysbus_realize(SYS_BUS_DEVICE(&s->nvm), errp)) { 116 return; 117 } 118 119 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 0); 120 memory_region_add_subregion_overlap(&s->container, NRF51_NVMC_BASE, mr, 0); 121 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 1); 122 memory_region_add_subregion_overlap(&s->container, NRF51_FICR_BASE, mr, 0); 123 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 2); 124 memory_region_add_subregion_overlap(&s->container, NRF51_UICR_BASE, mr, 0); 125 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 3); 126 memory_region_add_subregion_overlap(&s->container, NRF51_FLASH_BASE, mr, 0); 127 128 /* GPIO */ 129 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { 130 return; 131 } 132 133 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gpio), 0); 134 memory_region_add_subregion_overlap(&s->container, NRF51_GPIO_BASE, mr, 0); 135 136 /* Pass all GPIOs to the SOC layer so they are available to the board */ 137 qdev_pass_gpios(DEVICE(&s->gpio), dev_soc, NULL); 138 139 /* TIMER */ 140 for (i = 0; i < NRF51_NUM_TIMERS; i++) { 141 if (!object_property_set_uint(OBJECT(&s->timer[i]), "id", i, errp)) { 142 return; 143 } 144 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer[i]), errp)) { 145 return; 146 } 147 148 base_addr = NRF51_TIMER_BASE + i * NRF51_PERIPHERAL_SIZE; 149 150 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer[i]), 0, base_addr); 151 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer[i]), 0, 152 qdev_get_gpio_in(DEVICE(&s->cpu), 153 BASE_TO_IRQ(base_addr))); 154 } 155 156 /* STUB Peripherals */ 157 memory_region_init_io(&s->clock, OBJECT(dev_soc), &clock_ops, NULL, 158 "nrf51_soc.clock", NRF51_PERIPHERAL_SIZE); 159 memory_region_add_subregion_overlap(&s->container, 160 NRF51_IOMEM_BASE, &s->clock, -1); 161 162 create_unimplemented_device("nrf51_soc.io", NRF51_IOMEM_BASE, 163 NRF51_IOMEM_SIZE); 164 create_unimplemented_device("nrf51_soc.private", 165 NRF51_PRIVATE_BASE, NRF51_PRIVATE_SIZE); 166 } 167 168 static void nrf51_soc_init(Object *obj) 169 { 170 uint8_t i = 0; 171 172 NRF51State *s = NRF51_SOC(obj); 173 174 memory_region_init(&s->container, obj, "nrf51-container", UINT64_MAX); 175 176 object_initialize_child(OBJECT(s), "armv6m", &s->cpu, TYPE_ARMV7M); 177 qdev_prop_set_string(DEVICE(&s->cpu), "cpu-type", 178 ARM_CPU_TYPE_NAME("cortex-m0")); 179 qdev_prop_set_uint32(DEVICE(&s->cpu), "num-irq", 32); 180 181 object_initialize_child(obj, "uart", &s->uart, TYPE_NRF51_UART); 182 object_property_add_alias(obj, "serial0", OBJECT(&s->uart), "chardev"); 183 184 object_initialize_child(obj, "rng", &s->rng, TYPE_NRF51_RNG); 185 186 object_initialize_child(obj, "nvm", &s->nvm, TYPE_NRF51_NVM); 187 188 object_initialize_child(obj, "gpio", &s->gpio, TYPE_NRF51_GPIO); 189 190 for (i = 0; i < NRF51_NUM_TIMERS; i++) { 191 object_initialize_child(obj, "timer[*]", &s->timer[i], 192 TYPE_NRF51_TIMER); 193 194 } 195 } 196 197 static Property nrf51_soc_properties[] = { 198 DEFINE_PROP_LINK("memory", NRF51State, board_memory, TYPE_MEMORY_REGION, 199 MemoryRegion *), 200 DEFINE_PROP_UINT32("sram-size", NRF51State, sram_size, NRF51822_SRAM_SIZE), 201 DEFINE_PROP_UINT32("flash-size", NRF51State, flash_size, 202 NRF51822_FLASH_SIZE), 203 DEFINE_PROP_END_OF_LIST(), 204 }; 205 206 static void nrf51_soc_class_init(ObjectClass *klass, void *data) 207 { 208 DeviceClass *dc = DEVICE_CLASS(klass); 209 210 dc->realize = nrf51_soc_realize; 211 device_class_set_props(dc, nrf51_soc_properties); 212 } 213 214 static const TypeInfo nrf51_soc_info = { 215 .name = TYPE_NRF51_SOC, 216 .parent = TYPE_SYS_BUS_DEVICE, 217 .instance_size = sizeof(NRF51State), 218 .instance_init = nrf51_soc_init, 219 .class_init = nrf51_soc_class_init, 220 }; 221 222 static void nrf51_soc_types(void) 223 { 224 type_register_static(&nrf51_soc_info); 225 } 226 type_init(nrf51_soc_types) 227