1 /* 2 * Machine definitions for boards featuring an NPCM8xx SoC. 3 * 4 * Copyright 2021 Google LLC 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14 * for more details. 15 */ 16 17 #include "qemu/osdep.h" 18 19 #include "chardev/char.h" 20 #include "hw/arm/npcm8xx.h" 21 #include "hw/core/cpu.h" 22 #include "hw/loader.h" 23 #include "hw/qdev-core.h" 24 #include "hw/qdev-properties.h" 25 #include "qapi/error.h" 26 #include "qemu/error-report.h" 27 #include "qemu/datadir.h" 28 #include "qemu/units.h" 29 30 #define NPCM845_EVB_POWER_ON_STRAPS 0x000017ff 31 32 static const char npcm8xx_default_bootrom[] = "npcm8xx_bootrom.bin"; 33 34 static void npcm8xx_load_bootrom(MachineState *machine, NPCM8xxState *soc) 35 { 36 const char *bios_name = machine->firmware ?: npcm8xx_default_bootrom; 37 g_autofree char *filename = NULL; 38 int ret; 39 40 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 41 if (!filename) { 42 error_report("Could not find ROM image '%s'", bios_name); 43 if (!machine->kernel_filename) { 44 /* We can't boot without a bootrom or a kernel image. */ 45 exit(1); 46 } 47 return; 48 } 49 ret = load_image_mr(filename, machine->ram); 50 if (ret < 0) { 51 error_report("Failed to load ROM image '%s'", filename); 52 exit(1); 53 } 54 } 55 56 static void npcm8xx_connect_flash(NPCM7xxFIUState *fiu, int cs_no, 57 const char *flash_type, DriveInfo *dinfo) 58 { 59 DeviceState *flash; 60 qemu_irq flash_cs; 61 62 flash = qdev_new(flash_type); 63 if (dinfo) { 64 qdev_prop_set_drive(flash, "drive", blk_by_legacy_dinfo(dinfo)); 65 } 66 qdev_realize_and_unref(flash, BUS(fiu->spi), &error_fatal); 67 68 flash_cs = qdev_get_gpio_in_named(flash, SSI_GPIO_CS, 0); 69 qdev_connect_gpio_out_named(DEVICE(fiu), "cs", cs_no, flash_cs); 70 } 71 72 static void npcm8xx_connect_dram(NPCM8xxState *soc, MemoryRegion *dram) 73 { 74 memory_region_add_subregion(get_system_memory(), NPCM8XX_DRAM_BA, dram); 75 76 object_property_set_link(OBJECT(soc), "dram-mr", OBJECT(dram), 77 &error_abort); 78 } 79 80 static NPCM8xxState *npcm8xx_create_soc(MachineState *machine, 81 uint32_t hw_straps) 82 { 83 NPCM8xxMachineClass *nmc = NPCM8XX_MACHINE_GET_CLASS(machine); 84 Object *obj; 85 86 obj = object_new_with_props(nmc->soc_type, OBJECT(machine), "soc", 87 &error_abort, NULL); 88 object_property_set_uint(obj, "power-on-straps", hw_straps, &error_abort); 89 90 return NPCM8XX(obj); 91 } 92 93 static I2CBus *npcm8xx_i2c_get_bus(NPCM8xxState *soc, uint32_t num) 94 { 95 g_assert(num < ARRAY_SIZE(soc->smbus)); 96 return I2C_BUS(qdev_get_child_bus(DEVICE(&soc->smbus[num]), "i2c-bus")); 97 } 98 99 static void npcm8xx_init_pwm_splitter(NPCM8xxMachine *machine, 100 NPCM8xxState *soc, const int *fan_counts) 101 { 102 SplitIRQ *splitters = machine->fan_splitter; 103 104 /* 105 * PWM 0~3 belong to module 0 output 0~3. 106 * PWM 4~7 belong to module 1 output 0~3. 107 */ 108 for (int i = 0; i < NPCM8XX_NR_PWM_MODULES; ++i) { 109 for (int j = 0; j < NPCM7XX_PWM_PER_MODULE; ++j) { 110 int splitter_no = i * NPCM7XX_PWM_PER_MODULE + j; 111 DeviceState *splitter; 112 113 if (fan_counts[splitter_no] < 1) { 114 continue; 115 } 116 object_initialize_child(OBJECT(machine), "fan-splitter[*]", 117 &splitters[splitter_no], TYPE_SPLIT_IRQ); 118 splitter = DEVICE(&splitters[splitter_no]); 119 qdev_prop_set_uint16(splitter, "num-lines", 120 fan_counts[splitter_no]); 121 qdev_realize(splitter, NULL, &error_abort); 122 qdev_connect_gpio_out_named(DEVICE(&soc->pwm[i]), "duty-gpio-out", 123 j, qdev_get_gpio_in(splitter, 0)); 124 } 125 } 126 } 127 128 static void npcm8xx_connect_pwm_fan(NPCM8xxState *soc, SplitIRQ *splitter, 129 int fan_no, int output_no) 130 { 131 DeviceState *fan; 132 int fan_input; 133 qemu_irq fan_duty_gpio; 134 135 g_assert(fan_no >= 0 && fan_no <= NPCM7XX_MFT_MAX_FAN_INPUT); 136 /* 137 * Fan 0~1 belong to module 0 input 0~1. 138 * Fan 2~3 belong to module 1 input 0~1. 139 * ... 140 * Fan 14~15 belong to module 7 input 0~1. 141 * Fan 16~17 belong to module 0 input 2~3. 142 * Fan 18~19 belong to module 1 input 2~3. 143 */ 144 if (fan_no < 16) { 145 fan = DEVICE(&soc->mft[fan_no / 2]); 146 fan_input = fan_no % 2; 147 } else { 148 fan = DEVICE(&soc->mft[(fan_no - 16) / 2]); 149 fan_input = fan_no % 2 + 2; 150 } 151 152 /* Connect the Fan to PWM module */ 153 fan_duty_gpio = qdev_get_gpio_in_named(fan, "duty", fan_input); 154 qdev_connect_gpio_out(DEVICE(splitter), output_no, fan_duty_gpio); 155 } 156 157 static void npcm845_evb_i2c_init(NPCM8xxState *soc) 158 { 159 /* tmp100 temperature sensor on SVB, tmp105 is compatible */ 160 i2c_slave_create_simple(npcm8xx_i2c_get_bus(soc, 6), "tmp105", 0x48); 161 } 162 163 static void npcm845_evb_fan_init(NPCM8xxMachine *machine, NPCM8xxState *soc) 164 { 165 SplitIRQ *splitter = machine->fan_splitter; 166 static const int fan_counts[] = {2, 2, 2, 2, 2, 2, 2, 2, 0, 0, 0, 0}; 167 168 npcm8xx_init_pwm_splitter(machine, soc, fan_counts); 169 npcm8xx_connect_pwm_fan(soc, &splitter[0], 0x00, 0); 170 npcm8xx_connect_pwm_fan(soc, &splitter[0], 0x01, 1); 171 npcm8xx_connect_pwm_fan(soc, &splitter[1], 0x02, 0); 172 npcm8xx_connect_pwm_fan(soc, &splitter[1], 0x03, 1); 173 npcm8xx_connect_pwm_fan(soc, &splitter[2], 0x04, 0); 174 npcm8xx_connect_pwm_fan(soc, &splitter[2], 0x05, 1); 175 npcm8xx_connect_pwm_fan(soc, &splitter[3], 0x06, 0); 176 npcm8xx_connect_pwm_fan(soc, &splitter[3], 0x07, 1); 177 npcm8xx_connect_pwm_fan(soc, &splitter[4], 0x08, 0); 178 npcm8xx_connect_pwm_fan(soc, &splitter[4], 0x09, 1); 179 npcm8xx_connect_pwm_fan(soc, &splitter[5], 0x0a, 0); 180 npcm8xx_connect_pwm_fan(soc, &splitter[5], 0x0b, 1); 181 npcm8xx_connect_pwm_fan(soc, &splitter[6], 0x0c, 0); 182 npcm8xx_connect_pwm_fan(soc, &splitter[6], 0x0d, 1); 183 npcm8xx_connect_pwm_fan(soc, &splitter[7], 0x0e, 0); 184 npcm8xx_connect_pwm_fan(soc, &splitter[7], 0x0f, 1); 185 } 186 187 static void npcm845_evb_init(MachineState *machine) 188 { 189 NPCM8xxState *soc; 190 191 soc = npcm8xx_create_soc(machine, NPCM845_EVB_POWER_ON_STRAPS); 192 npcm8xx_connect_dram(soc, machine->ram); 193 qdev_realize(DEVICE(soc), NULL, &error_fatal); 194 195 npcm8xx_load_bootrom(machine, soc); 196 npcm8xx_connect_flash(&soc->fiu[0], 0, "w25q256", drive_get(IF_MTD, 0, 0)); 197 npcm845_evb_i2c_init(soc); 198 npcm845_evb_fan_init(NPCM8XX_MACHINE(machine), soc); 199 npcm8xx_load_kernel(machine, soc); 200 } 201 202 static void npcm8xx_set_soc_type(NPCM8xxMachineClass *nmc, const char *type) 203 { 204 NPCM8xxClass *sc = NPCM8XX_CLASS(object_class_by_name(type)); 205 MachineClass *mc = MACHINE_CLASS(nmc); 206 207 nmc->soc_type = type; 208 mc->default_cpus = mc->min_cpus = mc->max_cpus = sc->num_cpus; 209 } 210 211 static void npcm8xx_machine_class_init(ObjectClass *oc, void *data) 212 { 213 MachineClass *mc = MACHINE_CLASS(oc); 214 static const char * const valid_cpu_types[] = { 215 ARM_CPU_TYPE_NAME("cortex-a9"), 216 NULL 217 }; 218 219 mc->no_floppy = 1; 220 mc->no_cdrom = 1; 221 mc->no_parallel = 1; 222 mc->default_ram_id = "ram"; 223 mc->valid_cpu_types = valid_cpu_types; 224 } 225 226 static void npcm845_evb_machine_class_init(ObjectClass *oc, void *data) 227 { 228 NPCM8xxMachineClass *nmc = NPCM8XX_MACHINE_CLASS(oc); 229 MachineClass *mc = MACHINE_CLASS(oc); 230 231 npcm8xx_set_soc_type(nmc, TYPE_NPCM8XX); 232 233 mc->desc = "Nuvoton NPCM845 Evaluation Board (Cortex-A35)"; 234 mc->init = npcm845_evb_init; 235 mc->default_ram_size = 1 * GiB; 236 }; 237 238 static const TypeInfo npcm8xx_machine_types[] = { 239 { 240 .name = TYPE_NPCM8XX_MACHINE, 241 .parent = TYPE_MACHINE, 242 .instance_size = sizeof(NPCM8xxMachine), 243 .class_size = sizeof(NPCM8xxMachineClass), 244 .class_init = npcm8xx_machine_class_init, 245 .abstract = true, 246 }, { 247 .name = MACHINE_TYPE_NAME("npcm845-evb"), 248 .parent = TYPE_NPCM8XX_MACHINE, 249 .class_init = npcm845_evb_machine_class_init, 250 }, 251 }; 252 253 DEFINE_TYPES(npcm8xx_machine_types) 254