1 /* 2 * Nuvoton NPCM8xx SoC family. 3 * 4 * Copyright 2022 Google LLC 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14 * for more details. 15 */ 16 17 #include "qemu/osdep.h" 18 19 #include "hw/boards.h" 20 #include "hw/arm/boot.h" 21 #include "hw/arm/bsa.h" 22 #include "hw/arm/npcm8xx.h" 23 #include "hw/char/serial-mm.h" 24 #include "hw/intc/arm_gic.h" 25 #include "hw/loader.h" 26 #include "hw/misc/unimp.h" 27 #include "hw/qdev-clock.h" 28 #include "hw/qdev-properties.h" 29 #include "qapi/error.h" 30 #include "qemu/units.h" 31 #include "system/system.h" 32 33 /* 34 * This covers the whole MMIO space. We'll use this to catch any MMIO accesses 35 * that aren't handled by a device. 36 */ 37 #define NPCM8XX_MMIO_BA 0x80000000 38 #define NPCM8XX_MMIO_SZ 0x7ffd0000 39 40 /* OTP fuse array */ 41 #define NPCM8XX_OTP_BA 0xf0189000 42 43 /* GIC Distributor */ 44 #define NPCM8XX_GICD_BA 0xdfff9000 45 #define NPCM8XX_GICC_BA 0xdfffa000 46 47 /* Core system modules. */ 48 #define NPCM8XX_CPUP_BA 0xf03fe000 49 #define NPCM8XX_GCR_BA 0xf0800000 50 #define NPCM8XX_CLK_BA 0xf0801000 51 #define NPCM8XX_MC_BA 0xf0824000 52 #define NPCM8XX_RNG_BA 0xf000b000 53 54 /* ADC Module */ 55 #define NPCM8XX_ADC_BA 0xf000c000 56 57 /* Internal AHB SRAM */ 58 #define NPCM8XX_RAM3_BA 0xc0008000 59 #define NPCM8XX_RAM3_SZ (4 * KiB) 60 61 /* Memory blocks at the end of the address space */ 62 #define NPCM8XX_RAM2_BA 0xfffb0000 63 #define NPCM8XX_RAM2_SZ (256 * KiB) 64 #define NPCM8XX_ROM_BA 0xffff0100 65 #define NPCM8XX_ROM_SZ (64 * KiB) 66 67 /* SDHCI Modules */ 68 #define NPCM8XX_MMC_BA 0xf0842000 69 70 /* PSPI Modules */ 71 #define NPCM8XX_PSPI_BA 0xf0201000 72 73 /* Run PLL1 at 1600 MHz */ 74 #define NPCM8XX_PLLCON1_FIXUP_VAL 0x00402101 75 /* Run the CPU from PLL1 and UART from PLL2 */ 76 #define NPCM8XX_CLKSEL_FIXUP_VAL 0x004aaba9 77 78 /* Clock configuration values to be fixed up when bypassing bootloader */ 79 80 /* 81 * Interrupt lines going into the GIC. This does not include internal Cortex-A35 82 * interrupts. 83 */ 84 enum NPCM8xxInterrupt { 85 NPCM8XX_ADC_IRQ = 0, 86 NPCM8XX_PECI_IRQ = 6, 87 NPCM8XX_KCS_HIB_IRQ = 9, 88 NPCM8XX_MMC_IRQ = 26, 89 NPCM8XX_PSPI_IRQ = 28, 90 NPCM8XX_TIMER0_IRQ = 32, /* Timer Module 0 */ 91 NPCM8XX_TIMER1_IRQ, 92 NPCM8XX_TIMER2_IRQ, 93 NPCM8XX_TIMER3_IRQ, 94 NPCM8XX_TIMER4_IRQ, 95 NPCM8XX_TIMER5_IRQ, /* Timer Module 1 */ 96 NPCM8XX_TIMER6_IRQ, 97 NPCM8XX_TIMER7_IRQ, 98 NPCM8XX_TIMER8_IRQ, 99 NPCM8XX_TIMER9_IRQ, 100 NPCM8XX_TIMER10_IRQ, /* Timer Module 2 */ 101 NPCM8XX_TIMER11_IRQ, 102 NPCM8XX_TIMER12_IRQ, 103 NPCM8XX_TIMER13_IRQ, 104 NPCM8XX_TIMER14_IRQ, 105 NPCM8XX_WDG0_IRQ = 47, /* Timer Module 0 Watchdog */ 106 NPCM8XX_WDG1_IRQ, /* Timer Module 1 Watchdog */ 107 NPCM8XX_WDG2_IRQ, /* Timer Module 2 Watchdog */ 108 NPCM8XX_EHCI1_IRQ = 61, 109 NPCM8XX_OHCI1_IRQ, 110 NPCM8XX_EHCI2_IRQ, 111 NPCM8XX_OHCI2_IRQ, 112 NPCM8XX_PWM0_IRQ = 93, /* PWM module 0 */ 113 NPCM8XX_PWM1_IRQ, /* PWM module 1 */ 114 NPCM8XX_MFT0_IRQ = 96, /* MFT module 0 */ 115 NPCM8XX_MFT1_IRQ, /* MFT module 1 */ 116 NPCM8XX_MFT2_IRQ, /* MFT module 2 */ 117 NPCM8XX_MFT3_IRQ, /* MFT module 3 */ 118 NPCM8XX_MFT4_IRQ, /* MFT module 4 */ 119 NPCM8XX_MFT5_IRQ, /* MFT module 5 */ 120 NPCM8XX_MFT6_IRQ, /* MFT module 6 */ 121 NPCM8XX_MFT7_IRQ, /* MFT module 7 */ 122 NPCM8XX_PCI_MBOX1_IRQ = 105, 123 NPCM8XX_PCI_MBOX2_IRQ, 124 NPCM8XX_GPIO0_IRQ = 116, 125 NPCM8XX_GPIO1_IRQ, 126 NPCM8XX_GPIO2_IRQ, 127 NPCM8XX_GPIO3_IRQ, 128 NPCM8XX_GPIO4_IRQ, 129 NPCM8XX_GPIO5_IRQ, 130 NPCM8XX_GPIO6_IRQ, 131 NPCM8XX_GPIO7_IRQ, 132 NPCM8XX_SMBUS0_IRQ = 128, 133 NPCM8XX_SMBUS1_IRQ, 134 NPCM8XX_SMBUS2_IRQ, 135 NPCM8XX_SMBUS3_IRQ, 136 NPCM8XX_SMBUS4_IRQ, 137 NPCM8XX_SMBUS5_IRQ, 138 NPCM8XX_SMBUS6_IRQ, 139 NPCM8XX_SMBUS7_IRQ, 140 NPCM8XX_SMBUS8_IRQ, 141 NPCM8XX_SMBUS9_IRQ, 142 NPCM8XX_SMBUS10_IRQ, 143 NPCM8XX_SMBUS11_IRQ, 144 NPCM8XX_SMBUS12_IRQ, 145 NPCM8XX_SMBUS13_IRQ, 146 NPCM8XX_SMBUS14_IRQ, 147 NPCM8XX_SMBUS15_IRQ, 148 NPCM8XX_SMBUS16_IRQ, 149 NPCM8XX_SMBUS17_IRQ, 150 NPCM8XX_SMBUS18_IRQ, 151 NPCM8XX_SMBUS19_IRQ, 152 NPCM8XX_SMBUS20_IRQ, 153 NPCM8XX_SMBUS21_IRQ, 154 NPCM8XX_SMBUS22_IRQ, 155 NPCM8XX_SMBUS23_IRQ, 156 NPCM8XX_SMBUS24_IRQ, 157 NPCM8XX_SMBUS25_IRQ, 158 NPCM8XX_SMBUS26_IRQ, 159 NPCM8XX_UART0_IRQ = 192, 160 NPCM8XX_UART1_IRQ, 161 NPCM8XX_UART2_IRQ, 162 NPCM8XX_UART3_IRQ, 163 NPCM8XX_UART4_IRQ, 164 NPCM8XX_UART5_IRQ, 165 NPCM8XX_UART6_IRQ, 166 }; 167 168 /* Total number of GIC interrupts, including internal Cortex-A35 interrupts. */ 169 #define NPCM8XX_NUM_IRQ (288) 170 #define NPCM8XX_PPI_BASE(cpu) \ 171 ((NPCM8XX_NUM_IRQ - GIC_INTERNAL) + (cpu) * GIC_INTERNAL) 172 173 /* Register base address for each Timer Module */ 174 static const hwaddr npcm8xx_tim_addr[] = { 175 0xf0008000, 176 0xf0009000, 177 0xf000a000, 178 }; 179 180 /* Register base address for each 16550 UART */ 181 static const hwaddr npcm8xx_uart_addr[] = { 182 0xf0000000, 183 0xf0001000, 184 0xf0002000, 185 0xf0003000, 186 0xf0004000, 187 0xf0005000, 188 0xf0006000, 189 }; 190 191 /* Direct memory-mapped access to SPI0 CS0-1. */ 192 static const hwaddr npcm8xx_fiu0_flash_addr[] = { 193 0x80000000, /* CS0 */ 194 0x88000000, /* CS1 */ 195 }; 196 197 /* Direct memory-mapped access to SPI1 CS0-3. */ 198 static const hwaddr npcm8xx_fiu1_flash_addr[] = { 199 0x90000000, /* CS0 */ 200 0x91000000, /* CS1 */ 201 0x92000000, /* CS2 */ 202 0x93000000, /* CS3 */ 203 }; 204 205 /* Direct memory-mapped access to SPI3 CS0-3. */ 206 static const hwaddr npcm8xx_fiu3_flash_addr[] = { 207 0xa0000000, /* CS0 */ 208 0xa8000000, /* CS1 */ 209 0xb0000000, /* CS2 */ 210 0xb8000000, /* CS3 */ 211 }; 212 213 /* Register base address for each PWM Module */ 214 static const hwaddr npcm8xx_pwm_addr[] = { 215 0xf0103000, 216 0xf0104000, 217 0xf0105000, 218 }; 219 220 /* Register base address for each MFT Module */ 221 static const hwaddr npcm8xx_mft_addr[] = { 222 0xf0180000, 223 0xf0181000, 224 0xf0182000, 225 0xf0183000, 226 0xf0184000, 227 0xf0185000, 228 0xf0186000, 229 0xf0187000, 230 }; 231 232 /* Direct memory-mapped access to each SMBus Module. */ 233 static const hwaddr npcm8xx_smbus_addr[] = { 234 0xf0080000, 235 0xf0081000, 236 0xf0082000, 237 0xf0083000, 238 0xf0084000, 239 0xf0085000, 240 0xf0086000, 241 0xf0087000, 242 0xf0088000, 243 0xf0089000, 244 0xf008a000, 245 0xf008b000, 246 0xf008c000, 247 0xf008d000, 248 0xf008e000, 249 0xf008f000, 250 0xfff00000, 251 0xfff01000, 252 0xfff02000, 253 0xfff03000, 254 0xfff04000, 255 0xfff05000, 256 0xfff06000, 257 0xfff07000, 258 0xfff08000, 259 0xfff09000, 260 0xfff0a000, 261 }; 262 263 /* Register base address for each USB host EHCI registers */ 264 static const hwaddr npcm8xx_ehci_addr[] = { 265 0xf0828100, 266 0xf082a100, 267 }; 268 269 /* Register base address for each USB host OHCI registers */ 270 static const hwaddr npcm8xx_ohci_addr[] = { 271 0xf0829000, 272 0xf082b000, 273 }; 274 275 static const struct { 276 hwaddr regs_addr; 277 uint32_t reset_pu; 278 uint32_t reset_pd; 279 uint32_t reset_osrc; 280 uint32_t reset_odsc; 281 } npcm8xx_gpio[] = { 282 { 283 .regs_addr = 0xf0010000, 284 .reset_pu = 0x00000300, 285 .reset_pd = 0x000f0000, 286 }, { 287 .regs_addr = 0xf0011000, 288 .reset_pu = 0xe0fefe01, 289 .reset_pd = 0x07000000, 290 }, { 291 .regs_addr = 0xf0012000, 292 .reset_pu = 0xc00fffff, 293 .reset_pd = 0x3ff00000, 294 }, { 295 .regs_addr = 0xf0013000, 296 .reset_pd = 0x00003000, 297 }, { 298 .regs_addr = 0xf0014000, 299 .reset_pu = 0xffff0000, 300 }, { 301 .regs_addr = 0xf0015000, 302 .reset_pu = 0xff8387fe, 303 .reset_pd = 0x007c0001, 304 .reset_osrc = 0x08000000, 305 }, { 306 .regs_addr = 0xf0016000, 307 .reset_pu = 0x00000801, 308 .reset_pd = 0x00000302, 309 }, { 310 .regs_addr = 0xf0017000, 311 .reset_pu = 0x000002ff, 312 .reset_pd = 0x00000c00, 313 }, 314 }; 315 316 static const struct { 317 const char *name; 318 hwaddr regs_addr; 319 int cs_count; 320 const hwaddr *flash_addr; 321 size_t flash_size; 322 } npcm8xx_fiu[] = { 323 { 324 .name = "fiu0", 325 .regs_addr = 0xfb000000, 326 .cs_count = ARRAY_SIZE(npcm8xx_fiu0_flash_addr), 327 .flash_addr = npcm8xx_fiu0_flash_addr, 328 .flash_size = 128 * MiB, 329 }, 330 { 331 .name = "fiu1", 332 .regs_addr = 0xfb002000, 333 .cs_count = ARRAY_SIZE(npcm8xx_fiu1_flash_addr), 334 .flash_addr = npcm8xx_fiu1_flash_addr, 335 .flash_size = 16 * MiB, 336 }, { 337 .name = "fiu3", 338 .regs_addr = 0xc0000000, 339 .cs_count = ARRAY_SIZE(npcm8xx_fiu3_flash_addr), 340 .flash_addr = npcm8xx_fiu3_flash_addr, 341 .flash_size = 128 * MiB, 342 }, 343 }; 344 345 static struct arm_boot_info npcm8xx_binfo = { 346 .loader_start = NPCM8XX_LOADER_START, 347 .smp_loader_start = NPCM8XX_SMP_LOADER_START, 348 .smp_bootreg_addr = NPCM8XX_SMP_BOOTREG_ADDR, 349 .gic_cpu_if_addr = NPCM8XX_GICC_BA, 350 .secure_boot = false, 351 .board_id = -1, 352 .board_setup_addr = NPCM8XX_BOARD_SETUP_ADDR, 353 }; 354 355 void npcm8xx_load_kernel(MachineState *machine, NPCM8xxState *soc) 356 { 357 npcm8xx_binfo.ram_size = machine->ram_size; 358 359 arm_load_kernel(&soc->cpu[0], machine, &npcm8xx_binfo); 360 } 361 362 static void npcm8xx_init_fuses(NPCM8xxState *s) 363 { 364 NPCM8xxClass *nc = NPCM8XX_GET_CLASS(s); 365 uint32_t value; 366 367 /* 368 * The initial mask of disabled modules indicates the chip derivative (e.g. 369 * NPCM750 or NPCM730). 370 */ 371 value = cpu_to_le32(nc->disabled_modules); 372 npcm7xx_otp_array_write(&s->fuse_array, &value, NPCM7XX_FUSE_DERIVATIVE, 373 sizeof(value)); 374 } 375 376 static void npcm8xx_write_adc_calibration(NPCM8xxState *s) 377 { 378 /* Both ADC and the fuse array must have realized. */ 379 QEMU_BUILD_BUG_ON(sizeof(s->adc.calibration_r_values) != 4); 380 npcm7xx_otp_array_write(&s->fuse_array, s->adc.calibration_r_values, 381 NPCM7XX_FUSE_ADC_CALIB, sizeof(s->adc.calibration_r_values)); 382 } 383 384 static qemu_irq npcm8xx_irq(NPCM8xxState *s, int n) 385 { 386 return qdev_get_gpio_in(DEVICE(&s->gic), n); 387 } 388 389 static void npcm8xx_init(Object *obj) 390 { 391 NPCM8xxState *s = NPCM8XX(obj); 392 int i; 393 394 object_initialize_child(obj, "cpu-cluster", &s->cpu_cluster, 395 TYPE_CPU_CLUSTER); 396 for (i = 0; i < NPCM8XX_MAX_NUM_CPUS; i++) { 397 object_initialize_child(OBJECT(&s->cpu_cluster), "cpu[*]", &s->cpu[i], 398 ARM_CPU_TYPE_NAME("cortex-a35")); 399 } 400 object_initialize_child(obj, "gic", &s->gic, TYPE_ARM_GIC); 401 object_initialize_child(obj, "gcr", &s->gcr, TYPE_NPCM8XX_GCR); 402 object_property_add_alias(obj, "power-on-straps", OBJECT(&s->gcr), 403 "power-on-straps"); 404 object_initialize_child(obj, "clk", &s->clk, TYPE_NPCM8XX_CLK); 405 object_initialize_child(obj, "otp", &s->fuse_array, 406 TYPE_NPCM7XX_FUSE_ARRAY); 407 object_initialize_child(obj, "mc", &s->mc, TYPE_NPCM7XX_MC); 408 object_initialize_child(obj, "rng", &s->rng, TYPE_NPCM7XX_RNG); 409 object_initialize_child(obj, "adc", &s->adc, TYPE_NPCM7XX_ADC); 410 411 for (i = 0; i < ARRAY_SIZE(s->tim); i++) { 412 object_initialize_child(obj, "tim[*]", &s->tim[i], TYPE_NPCM7XX_TIMER); 413 } 414 415 for (i = 0; i < ARRAY_SIZE(s->gpio); i++) { 416 object_initialize_child(obj, "gpio[*]", &s->gpio[i], TYPE_NPCM7XX_GPIO); 417 } 418 419 420 for (i = 0; i < ARRAY_SIZE(s->smbus); i++) { 421 object_initialize_child(obj, "smbus[*]", &s->smbus[i], 422 TYPE_NPCM7XX_SMBUS); 423 DEVICE(&s->smbus[i])->id = g_strdup_printf("smbus[%d]", i); 424 } 425 426 for (i = 0; i < ARRAY_SIZE(s->ehci); i++) { 427 object_initialize_child(obj, "ehci[*]", &s->ehci[i], TYPE_NPCM7XX_EHCI); 428 } 429 for (i = 0; i < ARRAY_SIZE(s->ohci); i++) { 430 object_initialize_child(obj, "ohci[*]", &s->ohci[i], TYPE_SYSBUS_OHCI); 431 } 432 433 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm8xx_fiu) != ARRAY_SIZE(s->fiu)); 434 for (i = 0; i < ARRAY_SIZE(s->fiu); i++) { 435 object_initialize_child(obj, npcm8xx_fiu[i].name, &s->fiu[i], 436 TYPE_NPCM7XX_FIU); 437 } 438 439 for (i = 0; i < ARRAY_SIZE(s->pwm); i++) { 440 object_initialize_child(obj, "pwm[*]", &s->pwm[i], TYPE_NPCM7XX_PWM); 441 } 442 443 for (i = 0; i < ARRAY_SIZE(s->mft); i++) { 444 object_initialize_child(obj, "mft[*]", &s->mft[i], TYPE_NPCM7XX_MFT); 445 } 446 447 object_initialize_child(obj, "mmc", &s->mmc, TYPE_NPCM7XX_SDHCI); 448 object_initialize_child(obj, "pspi", &s->pspi, TYPE_NPCM_PSPI); 449 } 450 451 static void npcm8xx_realize(DeviceState *dev, Error **errp) 452 { 453 NPCM8xxState *s = NPCM8XX(dev); 454 NPCM8xxClass *nc = NPCM8XX_GET_CLASS(s); 455 int i; 456 457 if (memory_region_size(s->dram) > NPCM8XX_DRAM_SZ) { 458 error_setg(errp, "%s: NPCM8xx cannot address more than %" PRIu64 459 " MiB of DRAM", __func__, NPCM8XX_DRAM_SZ / MiB); 460 return; 461 } 462 463 /* CPUs */ 464 for (i = 0; i < nc->num_cpus; i++) { 465 object_property_set_int(OBJECT(&s->cpu[i]), "mp-affinity", 466 arm_build_mp_affinity(i, NPCM8XX_MAX_NUM_CPUS), 467 &error_abort); 468 object_property_set_bool(OBJECT(&s->cpu[i]), "reset-hivecs", true, 469 &error_abort); 470 object_property_set_int(OBJECT(&s->cpu[i]), "core-count", 471 nc->num_cpus, &error_abort); 472 473 /* Disable security extensions. */ 474 object_property_set_bool(OBJECT(&s->cpu[i]), "has_el3", false, 475 &error_abort); 476 477 if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) { 478 return; 479 } 480 } 481 482 /* ARM GIC for Cortex A35. Can only fail if we pass bad parameters here. */ 483 object_property_set_uint(OBJECT(&s->gic), "num-cpu", nc->num_cpus, errp); 484 object_property_set_uint(OBJECT(&s->gic), "num-irq", NPCM8XX_NUM_IRQ, errp); 485 object_property_set_uint(OBJECT(&s->gic), "revision", 2, errp); 486 object_property_set_bool(OBJECT(&s->gic), "has-security-extensions", true, 487 errp); 488 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic), errp)) { 489 return; 490 } 491 for (i = 0; i < nc->num_cpus; i++) { 492 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i, 493 qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IRQ)); 494 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + nc->num_cpus, 495 qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_FIQ)); 496 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + nc->num_cpus * 2, 497 qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_VIRQ)); 498 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + nc->num_cpus * 3, 499 qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_VFIQ)); 500 501 qdev_connect_gpio_out(DEVICE(&s->cpu[i]), GTIMER_PHYS, 502 qdev_get_gpio_in(DEVICE(&s->gic), 503 NPCM8XX_PPI_BASE(i) + ARCH_TIMER_NS_EL1_IRQ)); 504 qdev_connect_gpio_out(DEVICE(&s->cpu[i]), GTIMER_VIRT, 505 qdev_get_gpio_in(DEVICE(&s->gic), 506 NPCM8XX_PPI_BASE(i) + ARCH_TIMER_VIRT_IRQ)); 507 qdev_connect_gpio_out(DEVICE(&s->cpu[i]), GTIMER_HYP, 508 qdev_get_gpio_in(DEVICE(&s->gic), 509 NPCM8XX_PPI_BASE(i) + ARCH_TIMER_NS_EL2_IRQ)); 510 qdev_connect_gpio_out(DEVICE(&s->cpu[i]), GTIMER_SEC, 511 qdev_get_gpio_in(DEVICE(&s->gic), 512 NPCM8XX_PPI_BASE(i) + ARCH_TIMER_S_EL1_IRQ)); 513 } 514 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 0, NPCM8XX_GICD_BA); 515 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 1, NPCM8XX_GICC_BA); 516 517 /* CPU cluster */ 518 qdev_prop_set_uint32(DEVICE(&s->cpu_cluster), "cluster-id", 0); 519 qdev_realize(DEVICE(&s->cpu_cluster), NULL, &error_fatal); 520 521 /* System Global Control Registers (GCR). Can fail due to user input. */ 522 object_property_set_int(OBJECT(&s->gcr), "disabled-modules", 523 nc->disabled_modules, &error_abort); 524 object_property_add_const_link(OBJECT(&s->gcr), "dram-mr", OBJECT(s->dram)); 525 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gcr), errp)) { 526 return; 527 } 528 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gcr), 0, NPCM8XX_GCR_BA); 529 530 /* Clock Control Registers (CLK). Cannot fail. */ 531 sysbus_realize(SYS_BUS_DEVICE(&s->clk), &error_abort); 532 sysbus_mmio_map(SYS_BUS_DEVICE(&s->clk), 0, NPCM8XX_CLK_BA); 533 534 /* OTP fuse strap array. Cannot fail. */ 535 sysbus_realize(SYS_BUS_DEVICE(&s->fuse_array), &error_abort); 536 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fuse_array), 0, NPCM8XX_OTP_BA); 537 npcm8xx_init_fuses(s); 538 539 /* Fake Memory Controller (MC). Cannot fail. */ 540 sysbus_realize(SYS_BUS_DEVICE(&s->mc), &error_abort); 541 sysbus_mmio_map(SYS_BUS_DEVICE(&s->mc), 0, NPCM8XX_MC_BA); 542 543 /* ADC Modules. Cannot fail. */ 544 qdev_connect_clock_in(DEVICE(&s->adc), "clock", qdev_get_clock_out( 545 DEVICE(&s->clk), "adc-clock")); 546 sysbus_realize(SYS_BUS_DEVICE(&s->adc), &error_abort); 547 sysbus_mmio_map(SYS_BUS_DEVICE(&s->adc), 0, NPCM8XX_ADC_BA); 548 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, 549 npcm8xx_irq(s, NPCM8XX_ADC_IRQ)); 550 npcm8xx_write_adc_calibration(s); 551 552 /* Timer Modules (TIM). Cannot fail. */ 553 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm8xx_tim_addr) != ARRAY_SIZE(s->tim)); 554 for (i = 0; i < ARRAY_SIZE(s->tim); i++) { 555 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->tim[i]); 556 int first_irq; 557 int j; 558 559 /* Connect the timer clock. */ 560 qdev_connect_clock_in(DEVICE(&s->tim[i]), "clock", qdev_get_clock_out( 561 DEVICE(&s->clk), "timer-clock")); 562 563 sysbus_realize(sbd, &error_abort); 564 sysbus_mmio_map(sbd, 0, npcm8xx_tim_addr[i]); 565 566 first_irq = NPCM8XX_TIMER0_IRQ + i * NPCM7XX_TIMERS_PER_CTRL; 567 for (j = 0; j < NPCM7XX_TIMERS_PER_CTRL; j++) { 568 qemu_irq irq = npcm8xx_irq(s, first_irq + j); 569 sysbus_connect_irq(sbd, j, irq); 570 } 571 572 /* IRQ for watchdogs */ 573 sysbus_connect_irq(sbd, NPCM7XX_TIMERS_PER_CTRL, 574 npcm8xx_irq(s, NPCM8XX_WDG0_IRQ + i)); 575 /* GPIO that connects clk module with watchdog */ 576 qdev_connect_gpio_out_named(DEVICE(&s->tim[i]), 577 NPCM7XX_WATCHDOG_RESET_GPIO_OUT, 0, 578 qdev_get_gpio_in_named(DEVICE(&s->clk), 579 NPCM7XX_WATCHDOG_RESET_GPIO_IN, i)); 580 } 581 582 /* UART0..6 (16550 compatible) */ 583 for (i = 0; i < ARRAY_SIZE(npcm8xx_uart_addr); i++) { 584 serial_mm_init(get_system_memory(), npcm8xx_uart_addr[i], 2, 585 npcm8xx_irq(s, NPCM8XX_UART0_IRQ + i), 115200, 586 serial_hd(i), DEVICE_LITTLE_ENDIAN); 587 } 588 589 /* Random Number Generator. Cannot fail. */ 590 sysbus_realize(SYS_BUS_DEVICE(&s->rng), &error_abort); 591 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rng), 0, NPCM8XX_RNG_BA); 592 593 /* GPIO modules. Cannot fail. */ 594 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm8xx_gpio) != ARRAY_SIZE(s->gpio)); 595 for (i = 0; i < ARRAY_SIZE(s->gpio); i++) { 596 Object *obj = OBJECT(&s->gpio[i]); 597 598 object_property_set_uint(obj, "reset-pullup", 599 npcm8xx_gpio[i].reset_pu, &error_abort); 600 object_property_set_uint(obj, "reset-pulldown", 601 npcm8xx_gpio[i].reset_pd, &error_abort); 602 object_property_set_uint(obj, "reset-osrc", 603 npcm8xx_gpio[i].reset_osrc, &error_abort); 604 object_property_set_uint(obj, "reset-odsc", 605 npcm8xx_gpio[i].reset_odsc, &error_abort); 606 sysbus_realize(SYS_BUS_DEVICE(obj), &error_abort); 607 sysbus_mmio_map(SYS_BUS_DEVICE(obj), 0, npcm8xx_gpio[i].regs_addr); 608 sysbus_connect_irq(SYS_BUS_DEVICE(obj), 0, 609 npcm8xx_irq(s, NPCM8XX_GPIO0_IRQ + i)); 610 } 611 612 /* SMBus modules. Cannot fail. */ 613 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm8xx_smbus_addr) != ARRAY_SIZE(s->smbus)); 614 for (i = 0; i < ARRAY_SIZE(s->smbus); i++) { 615 Object *obj = OBJECT(&s->smbus[i]); 616 617 sysbus_realize(SYS_BUS_DEVICE(obj), &error_abort); 618 sysbus_mmio_map(SYS_BUS_DEVICE(obj), 0, npcm8xx_smbus_addr[i]); 619 sysbus_connect_irq(SYS_BUS_DEVICE(obj), 0, 620 npcm8xx_irq(s, NPCM8XX_SMBUS0_IRQ + i)); 621 } 622 623 /* USB Host */ 624 QEMU_BUILD_BUG_ON(ARRAY_SIZE(s->ohci) != ARRAY_SIZE(s->ehci)); 625 for (i = 0; i < ARRAY_SIZE(s->ehci); i++) { 626 object_property_set_bool(OBJECT(&s->ehci[i]), "companion-enable", true, 627 &error_abort); 628 sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), &error_abort); 629 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0, npcm8xx_ehci_addr[i]); 630 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, 631 npcm8xx_irq(s, NPCM8XX_EHCI1_IRQ + 2 * i)); 632 } 633 for (i = 0; i < ARRAY_SIZE(s->ohci); i++) { 634 object_property_set_str(OBJECT(&s->ohci[i]), "masterbus", "usb-bus.0", 635 &error_abort); 636 object_property_set_uint(OBJECT(&s->ohci[i]), "num-ports", 1, 637 &error_abort); 638 object_property_set_uint(OBJECT(&s->ohci[i]), "firstport", i, 639 &error_abort); 640 sysbus_realize(SYS_BUS_DEVICE(&s->ohci[i]), &error_abort); 641 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ohci[i]), 0, npcm8xx_ohci_addr[i]); 642 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ohci[i]), 0, 643 npcm8xx_irq(s, NPCM8XX_OHCI1_IRQ + 2 * i)); 644 } 645 646 /* PWM Modules. Cannot fail. */ 647 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm8xx_pwm_addr) != ARRAY_SIZE(s->pwm)); 648 for (i = 0; i < ARRAY_SIZE(s->pwm); i++) { 649 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->pwm[i]); 650 651 qdev_connect_clock_in(DEVICE(&s->pwm[i]), "clock", qdev_get_clock_out( 652 DEVICE(&s->clk), "apb3-clock")); 653 sysbus_realize(sbd, &error_abort); 654 sysbus_mmio_map(sbd, 0, npcm8xx_pwm_addr[i]); 655 sysbus_connect_irq(sbd, i, npcm8xx_irq(s, NPCM8XX_PWM0_IRQ + i)); 656 } 657 658 /* MFT Modules. Cannot fail. */ 659 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm8xx_mft_addr) != ARRAY_SIZE(s->mft)); 660 for (i = 0; i < ARRAY_SIZE(s->mft); i++) { 661 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->mft[i]); 662 663 qdev_connect_clock_in(DEVICE(&s->mft[i]), "clock-in", 664 qdev_get_clock_out(DEVICE(&s->clk), 665 "apb4-clock")); 666 sysbus_realize(sbd, &error_abort); 667 sysbus_mmio_map(sbd, 0, npcm8xx_mft_addr[i]); 668 sysbus_connect_irq(sbd, 0, npcm8xx_irq(s, NPCM8XX_MFT0_IRQ + i)); 669 } 670 671 /* 672 * Flash Interface Unit (FIU). Can fail if incorrect number of chip selects 673 * specified, but this is a programming error. 674 */ 675 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm8xx_fiu) != ARRAY_SIZE(s->fiu)); 676 for (i = 0; i < ARRAY_SIZE(s->fiu); i++) { 677 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->fiu[i]); 678 int j; 679 680 object_property_set_int(OBJECT(sbd), "cs-count", 681 npcm8xx_fiu[i].cs_count, &error_abort); 682 object_property_set_int(OBJECT(sbd), "flash-size", 683 npcm8xx_fiu[i].flash_size, &error_abort); 684 sysbus_realize(sbd, &error_abort); 685 686 sysbus_mmio_map(sbd, 0, npcm8xx_fiu[i].regs_addr); 687 for (j = 0; j < npcm8xx_fiu[i].cs_count; j++) { 688 sysbus_mmio_map(sbd, j + 1, npcm8xx_fiu[i].flash_addr[j]); 689 } 690 } 691 692 /* RAM2 (SRAM) */ 693 memory_region_init_ram(&s->sram, OBJECT(dev), "ram2", 694 NPCM8XX_RAM2_SZ, &error_abort); 695 memory_region_add_subregion(get_system_memory(), NPCM8XX_RAM2_BA, &s->sram); 696 697 /* RAM3 (SRAM) */ 698 memory_region_init_ram(&s->ram3, OBJECT(dev), "ram3", 699 NPCM8XX_RAM3_SZ, &error_abort); 700 memory_region_add_subregion(get_system_memory(), NPCM8XX_RAM3_BA, &s->ram3); 701 702 /* Internal ROM */ 703 memory_region_init_rom(&s->irom, OBJECT(dev), "irom", NPCM8XX_ROM_SZ, 704 &error_abort); 705 memory_region_add_subregion(get_system_memory(), NPCM8XX_ROM_BA, &s->irom); 706 707 /* SDHCI */ 708 sysbus_realize(SYS_BUS_DEVICE(&s->mmc), &error_abort); 709 sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc), 0, NPCM8XX_MMC_BA); 710 sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc), 0, 711 npcm8xx_irq(s, NPCM8XX_MMC_IRQ)); 712 713 /* PSPI */ 714 sysbus_realize(SYS_BUS_DEVICE(&s->pspi), &error_abort); 715 sysbus_mmio_map(SYS_BUS_DEVICE(&s->pspi), 0, NPCM8XX_PSPI_BA); 716 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pspi), 0, 717 npcm8xx_irq(s, NPCM8XX_PSPI_IRQ)); 718 719 create_unimplemented_device("npcm8xx.shm", 0xc0001000, 4 * KiB); 720 create_unimplemented_device("npcm8xx.gicextra", 0xdfffa000, 24 * KiB); 721 create_unimplemented_device("npcm8xx.vdmx", 0xe0800000, 4 * KiB); 722 create_unimplemented_device("npcm8xx.pcierc", 0xe1000000, 64 * KiB); 723 create_unimplemented_device("npcm8xx.rootc", 0xe8000000, 128 * MiB); 724 create_unimplemented_device("npcm8xx.kcs", 0xf0007000, 4 * KiB); 725 create_unimplemented_device("npcm8xx.gfxi", 0xf000e000, 4 * KiB); 726 create_unimplemented_device("npcm8xx.fsw", 0xf000f000, 4 * KiB); 727 create_unimplemented_device("npcm8xx.bt", 0xf0030000, 4 * KiB); 728 create_unimplemented_device("npcm8xx.espi", 0xf009f000, 4 * KiB); 729 create_unimplemented_device("npcm8xx.peci", 0xf0100000, 4 * KiB); 730 create_unimplemented_device("npcm8xx.siox[1]", 0xf0101000, 4 * KiB); 731 create_unimplemented_device("npcm8xx.siox[2]", 0xf0102000, 4 * KiB); 732 create_unimplemented_device("npcm8xx.tmps", 0xf0188000, 4 * KiB); 733 create_unimplemented_device("npcm8xx.viru1", 0xf0204000, 4 * KiB); 734 create_unimplemented_device("npcm8xx.viru2", 0xf0205000, 4 * KiB); 735 create_unimplemented_device("npcm8xx.jtm1", 0xf0208000, 4 * KiB); 736 create_unimplemented_device("npcm8xx.jtm2", 0xf0209000, 4 * KiB); 737 create_unimplemented_device("npcm8xx.flm0", 0xf0210000, 4 * KiB); 738 create_unimplemented_device("npcm8xx.flm1", 0xf0211000, 4 * KiB); 739 create_unimplemented_device("npcm8xx.flm2", 0xf0212000, 4 * KiB); 740 create_unimplemented_device("npcm8xx.flm3", 0xf0213000, 4 * KiB); 741 create_unimplemented_device("npcm8xx.ahbpci", 0xf0400000, 1 * MiB); 742 create_unimplemented_device("npcm8xx.dap", 0xf0500000, 960 * KiB); 743 create_unimplemented_device("npcm8xx.mcphy", 0xf05f0000, 64 * KiB); 744 create_unimplemented_device("npcm8xx.pcs", 0xf0780000, 256 * KiB); 745 create_unimplemented_device("npcm8xx.tsgen", 0xf07fc000, 8 * KiB); 746 create_unimplemented_device("npcm8xx.gmac1", 0xf0802000, 8 * KiB); 747 create_unimplemented_device("npcm8xx.gmac2", 0xf0804000, 8 * KiB); 748 create_unimplemented_device("npcm8xx.gmac3", 0xf0806000, 8 * KiB); 749 create_unimplemented_device("npcm8xx.gmac4", 0xf0808000, 8 * KiB); 750 create_unimplemented_device("npcm8xx.copctl", 0xf080c000, 4 * KiB); 751 create_unimplemented_device("npcm8xx.tipctl", 0xf080d000, 4 * KiB); 752 create_unimplemented_device("npcm8xx.rst", 0xf080e000, 4 * KiB); 753 create_unimplemented_device("npcm8xx.vcd", 0xf0810000, 64 * KiB); 754 create_unimplemented_device("npcm8xx.ece", 0xf0820000, 8 * KiB); 755 create_unimplemented_device("npcm8xx.vdma", 0xf0822000, 8 * KiB); 756 create_unimplemented_device("npcm8xx.usbd[0]", 0xf0830000, 4 * KiB); 757 create_unimplemented_device("npcm8xx.usbd[1]", 0xf0831000, 4 * KiB); 758 create_unimplemented_device("npcm8xx.usbd[2]", 0xf0832000, 4 * KiB); 759 create_unimplemented_device("npcm8xx.usbd[3]", 0xf0833000, 4 * KiB); 760 create_unimplemented_device("npcm8xx.usbd[4]", 0xf0834000, 4 * KiB); 761 create_unimplemented_device("npcm8xx.usbd[5]", 0xf0835000, 4 * KiB); 762 create_unimplemented_device("npcm8xx.usbd[6]", 0xf0836000, 4 * KiB); 763 create_unimplemented_device("npcm8xx.usbd[7]", 0xf0837000, 4 * KiB); 764 create_unimplemented_device("npcm8xx.usbd[8]", 0xf0838000, 4 * KiB); 765 create_unimplemented_device("npcm8xx.usbd[9]", 0xf0839000, 4 * KiB); 766 create_unimplemented_device("npcm8xx.pci_mbox1", 0xf0848000, 64 * KiB); 767 create_unimplemented_device("npcm8xx.gdma0", 0xf0850000, 4 * KiB); 768 create_unimplemented_device("npcm8xx.gdma1", 0xf0851000, 4 * KiB); 769 create_unimplemented_device("npcm8xx.gdma2", 0xf0852000, 4 * KiB); 770 create_unimplemented_device("npcm8xx.aes", 0xf0858000, 4 * KiB); 771 create_unimplemented_device("npcm8xx.des", 0xf0859000, 4 * KiB); 772 create_unimplemented_device("npcm8xx.sha", 0xf085a000, 4 * KiB); 773 create_unimplemented_device("npcm8xx.pci_mbox2", 0xf0868000, 64 * KiB); 774 create_unimplemented_device("npcm8xx.i3c0", 0xfff10000, 4 * KiB); 775 create_unimplemented_device("npcm8xx.i3c1", 0xfff11000, 4 * KiB); 776 create_unimplemented_device("npcm8xx.i3c2", 0xfff12000, 4 * KiB); 777 create_unimplemented_device("npcm8xx.i3c3", 0xfff13000, 4 * KiB); 778 create_unimplemented_device("npcm8xx.i3c4", 0xfff14000, 4 * KiB); 779 create_unimplemented_device("npcm8xx.i3c5", 0xfff15000, 4 * KiB); 780 create_unimplemented_device("npcm8xx.spixcs0", 0xf8000000, 16 * MiB); 781 create_unimplemented_device("npcm8xx.spixcs1", 0xf9000000, 16 * MiB); 782 create_unimplemented_device("npcm8xx.spix", 0xfb001000, 4 * KiB); 783 create_unimplemented_device("npcm8xx.vect", 0xffff0000, 256); 784 } 785 786 static const Property npcm8xx_properties[] = { 787 DEFINE_PROP_LINK("dram-mr", NPCM8xxState, dram, TYPE_MEMORY_REGION, 788 MemoryRegion *), 789 }; 790 791 static void npcm8xx_class_init(ObjectClass *oc, const void *data) 792 { 793 DeviceClass *dc = DEVICE_CLASS(oc); 794 NPCM8xxClass *nc = NPCM8XX_CLASS(oc); 795 796 dc->realize = npcm8xx_realize; 797 dc->user_creatable = false; 798 nc->disabled_modules = 0x00000000; 799 nc->num_cpus = NPCM8XX_MAX_NUM_CPUS; 800 device_class_set_props(dc, npcm8xx_properties); 801 } 802 803 static const TypeInfo npcm8xx_soc_types[] = { 804 { 805 .name = TYPE_NPCM8XX, 806 .parent = TYPE_DEVICE, 807 .instance_size = sizeof(NPCM8xxState), 808 .instance_init = npcm8xx_init, 809 .class_size = sizeof(NPCM8xxClass), 810 .class_init = npcm8xx_class_init, 811 }, 812 }; 813 814 DEFINE_TYPES(npcm8xx_soc_types); 815