1 /* 2 * Nuvoton NPCM8xx SoC family. 3 * 4 * Copyright 2022 Google LLC 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14 * for more details. 15 */ 16 17 #include "qemu/osdep.h" 18 19 #include "hw/boards.h" 20 #include "hw/arm/boot.h" 21 #include "hw/arm/bsa.h" 22 #include "hw/arm/npcm8xx.h" 23 #include "hw/char/serial-mm.h" 24 #include "hw/intc/arm_gic.h" 25 #include "hw/loader.h" 26 #include "hw/misc/unimp.h" 27 #include "hw/qdev-clock.h" 28 #include "hw/qdev-properties.h" 29 #include "qapi/error.h" 30 #include "qemu/units.h" 31 #include "system/system.h" 32 33 /* 34 * This covers the whole MMIO space. We'll use this to catch any MMIO accesses 35 * that aren't handled by a device. 36 */ 37 #define NPCM8XX_MMIO_BA 0x80000000 38 #define NPCM8XX_MMIO_SZ 0x7ffd0000 39 40 /* OTP fuse array */ 41 #define NPCM8XX_OTP_BA 0xf0189000 42 43 /* GIC Distributor */ 44 #define NPCM8XX_GICD_BA 0xdfff9000 45 #define NPCM8XX_GICC_BA 0xdfffa000 46 47 /* Core system modules. */ 48 #define NPCM8XX_CPUP_BA 0xf03fe000 49 #define NPCM8XX_GCR_BA 0xf0800000 50 #define NPCM8XX_CLK_BA 0xf0801000 51 #define NPCM8XX_MC_BA 0xf0824000 52 #define NPCM8XX_RNG_BA 0xf000b000 53 54 /* ADC Module */ 55 #define NPCM8XX_ADC_BA 0xf000c000 56 57 /* Internal AHB SRAM */ 58 #define NPCM8XX_RAM3_BA 0xc0008000 59 #define NPCM8XX_RAM3_SZ (4 * KiB) 60 61 /* Memory blocks at the end of the address space */ 62 #define NPCM8XX_RAM2_BA 0xfffb0000 63 #define NPCM8XX_RAM2_SZ (256 * KiB) 64 #define NPCM8XX_ROM_BA 0xffff0100 65 #define NPCM8XX_ROM_SZ (64 * KiB) 66 67 /* SDHCI Modules */ 68 #define NPCM8XX_MMC_BA 0xf0842000 69 70 /* Run PLL1 at 1600 MHz */ 71 #define NPCM8XX_PLLCON1_FIXUP_VAL 0x00402101 72 /* Run the CPU from PLL1 and UART from PLL2 */ 73 #define NPCM8XX_CLKSEL_FIXUP_VAL 0x004aaba9 74 75 /* Clock configuration values to be fixed up when bypassing bootloader */ 76 77 /* 78 * Interrupt lines going into the GIC. This does not include internal Cortex-A35 79 * interrupts. 80 */ 81 enum NPCM8xxInterrupt { 82 NPCM8XX_ADC_IRQ = 0, 83 NPCM8XX_PECI_IRQ = 6, 84 NPCM8XX_KCS_HIB_IRQ = 9, 85 NPCM8XX_MMC_IRQ = 26, 86 NPCM8XX_TIMER0_IRQ = 32, /* Timer Module 0 */ 87 NPCM8XX_TIMER1_IRQ, 88 NPCM8XX_TIMER2_IRQ, 89 NPCM8XX_TIMER3_IRQ, 90 NPCM8XX_TIMER4_IRQ, 91 NPCM8XX_TIMER5_IRQ, /* Timer Module 1 */ 92 NPCM8XX_TIMER6_IRQ, 93 NPCM8XX_TIMER7_IRQ, 94 NPCM8XX_TIMER8_IRQ, 95 NPCM8XX_TIMER9_IRQ, 96 NPCM8XX_TIMER10_IRQ, /* Timer Module 2 */ 97 NPCM8XX_TIMER11_IRQ, 98 NPCM8XX_TIMER12_IRQ, 99 NPCM8XX_TIMER13_IRQ, 100 NPCM8XX_TIMER14_IRQ, 101 NPCM8XX_WDG0_IRQ = 47, /* Timer Module 0 Watchdog */ 102 NPCM8XX_WDG1_IRQ, /* Timer Module 1 Watchdog */ 103 NPCM8XX_WDG2_IRQ, /* Timer Module 2 Watchdog */ 104 NPCM8XX_EHCI1_IRQ = 61, 105 NPCM8XX_OHCI1_IRQ, 106 NPCM8XX_EHCI2_IRQ, 107 NPCM8XX_OHCI2_IRQ, 108 NPCM8XX_PWM0_IRQ = 93, /* PWM module 0 */ 109 NPCM8XX_PWM1_IRQ, /* PWM module 1 */ 110 NPCM8XX_MFT0_IRQ = 96, /* MFT module 0 */ 111 NPCM8XX_MFT1_IRQ, /* MFT module 1 */ 112 NPCM8XX_MFT2_IRQ, /* MFT module 2 */ 113 NPCM8XX_MFT3_IRQ, /* MFT module 3 */ 114 NPCM8XX_MFT4_IRQ, /* MFT module 4 */ 115 NPCM8XX_MFT5_IRQ, /* MFT module 5 */ 116 NPCM8XX_MFT6_IRQ, /* MFT module 6 */ 117 NPCM8XX_MFT7_IRQ, /* MFT module 7 */ 118 NPCM8XX_PCI_MBOX1_IRQ = 105, 119 NPCM8XX_PCI_MBOX2_IRQ, 120 NPCM8XX_GPIO0_IRQ = 116, 121 NPCM8XX_GPIO1_IRQ, 122 NPCM8XX_GPIO2_IRQ, 123 NPCM8XX_GPIO3_IRQ, 124 NPCM8XX_GPIO4_IRQ, 125 NPCM8XX_GPIO5_IRQ, 126 NPCM8XX_GPIO6_IRQ, 127 NPCM8XX_GPIO7_IRQ, 128 NPCM8XX_SMBUS0_IRQ = 128, 129 NPCM8XX_SMBUS1_IRQ, 130 NPCM8XX_SMBUS2_IRQ, 131 NPCM8XX_SMBUS3_IRQ, 132 NPCM8XX_SMBUS4_IRQ, 133 NPCM8XX_SMBUS5_IRQ, 134 NPCM8XX_SMBUS6_IRQ, 135 NPCM8XX_SMBUS7_IRQ, 136 NPCM8XX_SMBUS8_IRQ, 137 NPCM8XX_SMBUS9_IRQ, 138 NPCM8XX_SMBUS10_IRQ, 139 NPCM8XX_SMBUS11_IRQ, 140 NPCM8XX_SMBUS12_IRQ, 141 NPCM8XX_SMBUS13_IRQ, 142 NPCM8XX_SMBUS14_IRQ, 143 NPCM8XX_SMBUS15_IRQ, 144 NPCM8XX_SMBUS16_IRQ, 145 NPCM8XX_SMBUS17_IRQ, 146 NPCM8XX_SMBUS18_IRQ, 147 NPCM8XX_SMBUS19_IRQ, 148 NPCM8XX_SMBUS20_IRQ, 149 NPCM8XX_SMBUS21_IRQ, 150 NPCM8XX_SMBUS22_IRQ, 151 NPCM8XX_SMBUS23_IRQ, 152 NPCM8XX_SMBUS24_IRQ, 153 NPCM8XX_SMBUS25_IRQ, 154 NPCM8XX_SMBUS26_IRQ, 155 NPCM8XX_UART0_IRQ = 192, 156 NPCM8XX_UART1_IRQ, 157 NPCM8XX_UART2_IRQ, 158 NPCM8XX_UART3_IRQ, 159 NPCM8XX_UART4_IRQ, 160 NPCM8XX_UART5_IRQ, 161 NPCM8XX_UART6_IRQ, 162 }; 163 164 /* Total number of GIC interrupts, including internal Cortex-A35 interrupts. */ 165 #define NPCM8XX_NUM_IRQ (288) 166 #define NPCM8XX_PPI_BASE(cpu) \ 167 ((NPCM8XX_NUM_IRQ - GIC_INTERNAL) + (cpu) * GIC_INTERNAL) 168 169 /* Register base address for each Timer Module */ 170 static const hwaddr npcm8xx_tim_addr[] = { 171 0xf0008000, 172 0xf0009000, 173 0xf000a000, 174 }; 175 176 /* Register base address for each 16550 UART */ 177 static const hwaddr npcm8xx_uart_addr[] = { 178 0xf0000000, 179 0xf0001000, 180 0xf0002000, 181 0xf0003000, 182 0xf0004000, 183 0xf0005000, 184 0xf0006000, 185 }; 186 187 /* Direct memory-mapped access to SPI0 CS0-1. */ 188 static const hwaddr npcm8xx_fiu0_flash_addr[] = { 189 0x80000000, /* CS0 */ 190 0x88000000, /* CS1 */ 191 }; 192 193 /* Direct memory-mapped access to SPI1 CS0-3. */ 194 static const hwaddr npcm8xx_fiu1_flash_addr[] = { 195 0x90000000, /* CS0 */ 196 0x91000000, /* CS1 */ 197 0x92000000, /* CS2 */ 198 0x93000000, /* CS3 */ 199 }; 200 201 /* Direct memory-mapped access to SPI3 CS0-3. */ 202 static const hwaddr npcm8xx_fiu3_flash_addr[] = { 203 0xa0000000, /* CS0 */ 204 0xa8000000, /* CS1 */ 205 0xb0000000, /* CS2 */ 206 0xb8000000, /* CS3 */ 207 }; 208 209 /* Register base address for each PWM Module */ 210 static const hwaddr npcm8xx_pwm_addr[] = { 211 0xf0103000, 212 0xf0104000, 213 0xf0105000, 214 }; 215 216 /* Register base address for each MFT Module */ 217 static const hwaddr npcm8xx_mft_addr[] = { 218 0xf0180000, 219 0xf0181000, 220 0xf0182000, 221 0xf0183000, 222 0xf0184000, 223 0xf0185000, 224 0xf0186000, 225 0xf0187000, 226 }; 227 228 /* Direct memory-mapped access to each SMBus Module. */ 229 static const hwaddr npcm8xx_smbus_addr[] = { 230 0xf0080000, 231 0xf0081000, 232 0xf0082000, 233 0xf0083000, 234 0xf0084000, 235 0xf0085000, 236 0xf0086000, 237 0xf0087000, 238 0xf0088000, 239 0xf0089000, 240 0xf008a000, 241 0xf008b000, 242 0xf008c000, 243 0xf008d000, 244 0xf008e000, 245 0xf008f000, 246 0xfff00000, 247 0xfff01000, 248 0xfff02000, 249 0xfff03000, 250 0xfff04000, 251 0xfff05000, 252 0xfff06000, 253 0xfff07000, 254 0xfff08000, 255 0xfff09000, 256 0xfff0a000, 257 }; 258 259 /* Register base address for each USB host EHCI registers */ 260 static const hwaddr npcm8xx_ehci_addr[] = { 261 0xf0828100, 262 0xf082a100, 263 }; 264 265 /* Register base address for each USB host OHCI registers */ 266 static const hwaddr npcm8xx_ohci_addr[] = { 267 0xf0829000, 268 0xf082b000, 269 }; 270 271 static const struct { 272 hwaddr regs_addr; 273 uint32_t reset_pu; 274 uint32_t reset_pd; 275 uint32_t reset_osrc; 276 uint32_t reset_odsc; 277 } npcm8xx_gpio[] = { 278 { 279 .regs_addr = 0xf0010000, 280 .reset_pu = 0x00000300, 281 .reset_pd = 0x000f0000, 282 }, { 283 .regs_addr = 0xf0011000, 284 .reset_pu = 0xe0fefe01, 285 .reset_pd = 0x07000000, 286 }, { 287 .regs_addr = 0xf0012000, 288 .reset_pu = 0xc00fffff, 289 .reset_pd = 0x3ff00000, 290 }, { 291 .regs_addr = 0xf0013000, 292 .reset_pd = 0x00003000, 293 }, { 294 .regs_addr = 0xf0014000, 295 .reset_pu = 0xffff0000, 296 }, { 297 .regs_addr = 0xf0015000, 298 .reset_pu = 0xff8387fe, 299 .reset_pd = 0x007c0001, 300 .reset_osrc = 0x08000000, 301 }, { 302 .regs_addr = 0xf0016000, 303 .reset_pu = 0x00000801, 304 .reset_pd = 0x00000302, 305 }, { 306 .regs_addr = 0xf0017000, 307 .reset_pu = 0x000002ff, 308 .reset_pd = 0x00000c00, 309 }, 310 }; 311 312 static const struct { 313 const char *name; 314 hwaddr regs_addr; 315 int cs_count; 316 const hwaddr *flash_addr; 317 size_t flash_size; 318 } npcm8xx_fiu[] = { 319 { 320 .name = "fiu0", 321 .regs_addr = 0xfb000000, 322 .cs_count = ARRAY_SIZE(npcm8xx_fiu0_flash_addr), 323 .flash_addr = npcm8xx_fiu0_flash_addr, 324 .flash_size = 128 * MiB, 325 }, 326 { 327 .name = "fiu1", 328 .regs_addr = 0xfb002000, 329 .cs_count = ARRAY_SIZE(npcm8xx_fiu1_flash_addr), 330 .flash_addr = npcm8xx_fiu1_flash_addr, 331 .flash_size = 16 * MiB, 332 }, { 333 .name = "fiu3", 334 .regs_addr = 0xc0000000, 335 .cs_count = ARRAY_SIZE(npcm8xx_fiu3_flash_addr), 336 .flash_addr = npcm8xx_fiu3_flash_addr, 337 .flash_size = 128 * MiB, 338 }, 339 }; 340 341 static struct arm_boot_info npcm8xx_binfo = { 342 .loader_start = NPCM8XX_LOADER_START, 343 .smp_loader_start = NPCM8XX_SMP_LOADER_START, 344 .smp_bootreg_addr = NPCM8XX_SMP_BOOTREG_ADDR, 345 .gic_cpu_if_addr = NPCM8XX_GICC_BA, 346 .secure_boot = false, 347 .board_id = -1, 348 .board_setup_addr = NPCM8XX_BOARD_SETUP_ADDR, 349 }; 350 351 void npcm8xx_load_kernel(MachineState *machine, NPCM8xxState *soc) 352 { 353 npcm8xx_binfo.ram_size = machine->ram_size; 354 355 arm_load_kernel(&soc->cpu[0], machine, &npcm8xx_binfo); 356 } 357 358 static void npcm8xx_init_fuses(NPCM8xxState *s) 359 { 360 NPCM8xxClass *nc = NPCM8XX_GET_CLASS(s); 361 uint32_t value; 362 363 /* 364 * The initial mask of disabled modules indicates the chip derivative (e.g. 365 * NPCM750 or NPCM730). 366 */ 367 value = cpu_to_le32(nc->disabled_modules); 368 npcm7xx_otp_array_write(&s->fuse_array, &value, NPCM7XX_FUSE_DERIVATIVE, 369 sizeof(value)); 370 } 371 372 static void npcm8xx_write_adc_calibration(NPCM8xxState *s) 373 { 374 /* Both ADC and the fuse array must have realized. */ 375 QEMU_BUILD_BUG_ON(sizeof(s->adc.calibration_r_values) != 4); 376 npcm7xx_otp_array_write(&s->fuse_array, s->adc.calibration_r_values, 377 NPCM7XX_FUSE_ADC_CALIB, sizeof(s->adc.calibration_r_values)); 378 } 379 380 static qemu_irq npcm8xx_irq(NPCM8xxState *s, int n) 381 { 382 return qdev_get_gpio_in(DEVICE(&s->gic), n); 383 } 384 385 static void npcm8xx_init(Object *obj) 386 { 387 NPCM8xxState *s = NPCM8XX(obj); 388 int i; 389 390 object_initialize_child(obj, "cpu-cluster", &s->cpu_cluster, 391 TYPE_CPU_CLUSTER); 392 for (i = 0; i < NPCM8XX_MAX_NUM_CPUS; i++) { 393 object_initialize_child(OBJECT(&s->cpu_cluster), "cpu[*]", &s->cpu[i], 394 ARM_CPU_TYPE_NAME("cortex-a35")); 395 } 396 object_initialize_child(obj, "gic", &s->gic, TYPE_ARM_GIC); 397 object_initialize_child(obj, "gcr", &s->gcr, TYPE_NPCM8XX_GCR); 398 object_property_add_alias(obj, "power-on-straps", OBJECT(&s->gcr), 399 "power-on-straps"); 400 object_initialize_child(obj, "clk", &s->clk, TYPE_NPCM8XX_CLK); 401 object_initialize_child(obj, "otp", &s->fuse_array, 402 TYPE_NPCM7XX_FUSE_ARRAY); 403 object_initialize_child(obj, "mc", &s->mc, TYPE_NPCM7XX_MC); 404 object_initialize_child(obj, "rng", &s->rng, TYPE_NPCM7XX_RNG); 405 object_initialize_child(obj, "adc", &s->adc, TYPE_NPCM7XX_ADC); 406 407 for (i = 0; i < ARRAY_SIZE(s->tim); i++) { 408 object_initialize_child(obj, "tim[*]", &s->tim[i], TYPE_NPCM7XX_TIMER); 409 } 410 411 for (i = 0; i < ARRAY_SIZE(s->gpio); i++) { 412 object_initialize_child(obj, "gpio[*]", &s->gpio[i], TYPE_NPCM7XX_GPIO); 413 } 414 415 416 for (i = 0; i < ARRAY_SIZE(s->smbus); i++) { 417 object_initialize_child(obj, "smbus[*]", &s->smbus[i], 418 TYPE_NPCM7XX_SMBUS); 419 DEVICE(&s->smbus[i])->id = g_strdup_printf("smbus[%d]", i); 420 } 421 422 for (i = 0; i < ARRAY_SIZE(s->ehci); i++) { 423 object_initialize_child(obj, "ehci[*]", &s->ehci[i], TYPE_NPCM7XX_EHCI); 424 } 425 for (i = 0; i < ARRAY_SIZE(s->ohci); i++) { 426 object_initialize_child(obj, "ohci[*]", &s->ohci[i], TYPE_SYSBUS_OHCI); 427 } 428 429 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm8xx_fiu) != ARRAY_SIZE(s->fiu)); 430 for (i = 0; i < ARRAY_SIZE(s->fiu); i++) { 431 object_initialize_child(obj, npcm8xx_fiu[i].name, &s->fiu[i], 432 TYPE_NPCM7XX_FIU); 433 } 434 435 for (i = 0; i < ARRAY_SIZE(s->pwm); i++) { 436 object_initialize_child(obj, "pwm[*]", &s->pwm[i], TYPE_NPCM7XX_PWM); 437 } 438 439 for (i = 0; i < ARRAY_SIZE(s->mft); i++) { 440 object_initialize_child(obj, "mft[*]", &s->mft[i], TYPE_NPCM7XX_MFT); 441 } 442 443 object_initialize_child(obj, "mmc", &s->mmc, TYPE_NPCM7XX_SDHCI); 444 } 445 446 static void npcm8xx_realize(DeviceState *dev, Error **errp) 447 { 448 NPCM8xxState *s = NPCM8XX(dev); 449 NPCM8xxClass *nc = NPCM8XX_GET_CLASS(s); 450 int i; 451 452 if (memory_region_size(s->dram) > NPCM8XX_DRAM_SZ) { 453 error_setg(errp, "%s: NPCM8xx cannot address more than %" PRIu64 454 " MiB of DRAM", __func__, NPCM8XX_DRAM_SZ / MiB); 455 return; 456 } 457 458 /* CPUs */ 459 for (i = 0; i < nc->num_cpus; i++) { 460 object_property_set_int(OBJECT(&s->cpu[i]), "mp-affinity", 461 arm_build_mp_affinity(i, NPCM8XX_MAX_NUM_CPUS), 462 &error_abort); 463 object_property_set_bool(OBJECT(&s->cpu[i]), "reset-hivecs", true, 464 &error_abort); 465 object_property_set_int(OBJECT(&s->cpu[i]), "core-count", 466 nc->num_cpus, &error_abort); 467 468 /* Disable security extensions. */ 469 object_property_set_bool(OBJECT(&s->cpu[i]), "has_el3", false, 470 &error_abort); 471 472 if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) { 473 return; 474 } 475 } 476 477 /* ARM GIC for Cortex A35. Can only fail if we pass bad parameters here. */ 478 object_property_set_uint(OBJECT(&s->gic), "num-cpu", nc->num_cpus, errp); 479 object_property_set_uint(OBJECT(&s->gic), "num-irq", NPCM8XX_NUM_IRQ, errp); 480 object_property_set_uint(OBJECT(&s->gic), "revision", 2, errp); 481 object_property_set_bool(OBJECT(&s->gic), "has-security-extensions", true, 482 errp); 483 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic), errp)) { 484 return; 485 } 486 for (i = 0; i < nc->num_cpus; i++) { 487 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i, 488 qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IRQ)); 489 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + nc->num_cpus, 490 qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_FIQ)); 491 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + nc->num_cpus * 2, 492 qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_VIRQ)); 493 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + nc->num_cpus * 3, 494 qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_VFIQ)); 495 496 qdev_connect_gpio_out(DEVICE(&s->cpu[i]), GTIMER_PHYS, 497 qdev_get_gpio_in(DEVICE(&s->gic), 498 NPCM8XX_PPI_BASE(i) + ARCH_TIMER_NS_EL1_IRQ)); 499 qdev_connect_gpio_out(DEVICE(&s->cpu[i]), GTIMER_VIRT, 500 qdev_get_gpio_in(DEVICE(&s->gic), 501 NPCM8XX_PPI_BASE(i) + ARCH_TIMER_VIRT_IRQ)); 502 qdev_connect_gpio_out(DEVICE(&s->cpu[i]), GTIMER_HYP, 503 qdev_get_gpio_in(DEVICE(&s->gic), 504 NPCM8XX_PPI_BASE(i) + ARCH_TIMER_NS_EL2_IRQ)); 505 qdev_connect_gpio_out(DEVICE(&s->cpu[i]), GTIMER_SEC, 506 qdev_get_gpio_in(DEVICE(&s->gic), 507 NPCM8XX_PPI_BASE(i) + ARCH_TIMER_S_EL1_IRQ)); 508 } 509 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 0, NPCM8XX_GICD_BA); 510 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 1, NPCM8XX_GICC_BA); 511 512 /* CPU cluster */ 513 qdev_prop_set_uint32(DEVICE(&s->cpu_cluster), "cluster-id", 0); 514 qdev_realize(DEVICE(&s->cpu_cluster), NULL, &error_fatal); 515 516 /* System Global Control Registers (GCR). Can fail due to user input. */ 517 object_property_set_int(OBJECT(&s->gcr), "disabled-modules", 518 nc->disabled_modules, &error_abort); 519 object_property_add_const_link(OBJECT(&s->gcr), "dram-mr", OBJECT(s->dram)); 520 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gcr), errp)) { 521 return; 522 } 523 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gcr), 0, NPCM8XX_GCR_BA); 524 525 /* Clock Control Registers (CLK). Cannot fail. */ 526 sysbus_realize(SYS_BUS_DEVICE(&s->clk), &error_abort); 527 sysbus_mmio_map(SYS_BUS_DEVICE(&s->clk), 0, NPCM8XX_CLK_BA); 528 529 /* OTP fuse strap array. Cannot fail. */ 530 sysbus_realize(SYS_BUS_DEVICE(&s->fuse_array), &error_abort); 531 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fuse_array), 0, NPCM8XX_OTP_BA); 532 npcm8xx_init_fuses(s); 533 534 /* Fake Memory Controller (MC). Cannot fail. */ 535 sysbus_realize(SYS_BUS_DEVICE(&s->mc), &error_abort); 536 sysbus_mmio_map(SYS_BUS_DEVICE(&s->mc), 0, NPCM8XX_MC_BA); 537 538 /* ADC Modules. Cannot fail. */ 539 qdev_connect_clock_in(DEVICE(&s->adc), "clock", qdev_get_clock_out( 540 DEVICE(&s->clk), "adc-clock")); 541 sysbus_realize(SYS_BUS_DEVICE(&s->adc), &error_abort); 542 sysbus_mmio_map(SYS_BUS_DEVICE(&s->adc), 0, NPCM8XX_ADC_BA); 543 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, 544 npcm8xx_irq(s, NPCM8XX_ADC_IRQ)); 545 npcm8xx_write_adc_calibration(s); 546 547 /* Timer Modules (TIM). Cannot fail. */ 548 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm8xx_tim_addr) != ARRAY_SIZE(s->tim)); 549 for (i = 0; i < ARRAY_SIZE(s->tim); i++) { 550 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->tim[i]); 551 int first_irq; 552 int j; 553 554 /* Connect the timer clock. */ 555 qdev_connect_clock_in(DEVICE(&s->tim[i]), "clock", qdev_get_clock_out( 556 DEVICE(&s->clk), "timer-clock")); 557 558 sysbus_realize(sbd, &error_abort); 559 sysbus_mmio_map(sbd, 0, npcm8xx_tim_addr[i]); 560 561 first_irq = NPCM8XX_TIMER0_IRQ + i * NPCM7XX_TIMERS_PER_CTRL; 562 for (j = 0; j < NPCM7XX_TIMERS_PER_CTRL; j++) { 563 qemu_irq irq = npcm8xx_irq(s, first_irq + j); 564 sysbus_connect_irq(sbd, j, irq); 565 } 566 567 /* IRQ for watchdogs */ 568 sysbus_connect_irq(sbd, NPCM7XX_TIMERS_PER_CTRL, 569 npcm8xx_irq(s, NPCM8XX_WDG0_IRQ + i)); 570 /* GPIO that connects clk module with watchdog */ 571 qdev_connect_gpio_out_named(DEVICE(&s->tim[i]), 572 NPCM7XX_WATCHDOG_RESET_GPIO_OUT, 0, 573 qdev_get_gpio_in_named(DEVICE(&s->clk), 574 NPCM7XX_WATCHDOG_RESET_GPIO_IN, i)); 575 } 576 577 /* UART0..6 (16550 compatible) */ 578 for (i = 0; i < ARRAY_SIZE(npcm8xx_uart_addr); i++) { 579 serial_mm_init(get_system_memory(), npcm8xx_uart_addr[i], 2, 580 npcm8xx_irq(s, NPCM8XX_UART0_IRQ + i), 115200, 581 serial_hd(i), DEVICE_LITTLE_ENDIAN); 582 } 583 584 /* Random Number Generator. Cannot fail. */ 585 sysbus_realize(SYS_BUS_DEVICE(&s->rng), &error_abort); 586 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rng), 0, NPCM8XX_RNG_BA); 587 588 /* GPIO modules. Cannot fail. */ 589 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm8xx_gpio) != ARRAY_SIZE(s->gpio)); 590 for (i = 0; i < ARRAY_SIZE(s->gpio); i++) { 591 Object *obj = OBJECT(&s->gpio[i]); 592 593 object_property_set_uint(obj, "reset-pullup", 594 npcm8xx_gpio[i].reset_pu, &error_abort); 595 object_property_set_uint(obj, "reset-pulldown", 596 npcm8xx_gpio[i].reset_pd, &error_abort); 597 object_property_set_uint(obj, "reset-osrc", 598 npcm8xx_gpio[i].reset_osrc, &error_abort); 599 object_property_set_uint(obj, "reset-odsc", 600 npcm8xx_gpio[i].reset_odsc, &error_abort); 601 sysbus_realize(SYS_BUS_DEVICE(obj), &error_abort); 602 sysbus_mmio_map(SYS_BUS_DEVICE(obj), 0, npcm8xx_gpio[i].regs_addr); 603 sysbus_connect_irq(SYS_BUS_DEVICE(obj), 0, 604 npcm8xx_irq(s, NPCM8XX_GPIO0_IRQ + i)); 605 } 606 607 /* SMBus modules. Cannot fail. */ 608 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm8xx_smbus_addr) != ARRAY_SIZE(s->smbus)); 609 for (i = 0; i < ARRAY_SIZE(s->smbus); i++) { 610 Object *obj = OBJECT(&s->smbus[i]); 611 612 sysbus_realize(SYS_BUS_DEVICE(obj), &error_abort); 613 sysbus_mmio_map(SYS_BUS_DEVICE(obj), 0, npcm8xx_smbus_addr[i]); 614 sysbus_connect_irq(SYS_BUS_DEVICE(obj), 0, 615 npcm8xx_irq(s, NPCM8XX_SMBUS0_IRQ + i)); 616 } 617 618 /* USB Host */ 619 QEMU_BUILD_BUG_ON(ARRAY_SIZE(s->ohci) != ARRAY_SIZE(s->ehci)); 620 for (i = 0; i < ARRAY_SIZE(s->ehci); i++) { 621 object_property_set_bool(OBJECT(&s->ehci[i]), "companion-enable", true, 622 &error_abort); 623 sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), &error_abort); 624 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0, npcm8xx_ehci_addr[i]); 625 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, 626 npcm8xx_irq(s, NPCM8XX_EHCI1_IRQ + 2 * i)); 627 } 628 for (i = 0; i < ARRAY_SIZE(s->ohci); i++) { 629 object_property_set_str(OBJECT(&s->ohci[i]), "masterbus", "usb-bus.0", 630 &error_abort); 631 object_property_set_uint(OBJECT(&s->ohci[i]), "num-ports", 1, 632 &error_abort); 633 object_property_set_uint(OBJECT(&s->ohci[i]), "firstport", i, 634 &error_abort); 635 sysbus_realize(SYS_BUS_DEVICE(&s->ohci[i]), &error_abort); 636 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ohci[i]), 0, npcm8xx_ohci_addr[i]); 637 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ohci[i]), 0, 638 npcm8xx_irq(s, NPCM8XX_OHCI1_IRQ + 2 * i)); 639 } 640 641 /* PWM Modules. Cannot fail. */ 642 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm8xx_pwm_addr) != ARRAY_SIZE(s->pwm)); 643 for (i = 0; i < ARRAY_SIZE(s->pwm); i++) { 644 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->pwm[i]); 645 646 qdev_connect_clock_in(DEVICE(&s->pwm[i]), "clock", qdev_get_clock_out( 647 DEVICE(&s->clk), "apb3-clock")); 648 sysbus_realize(sbd, &error_abort); 649 sysbus_mmio_map(sbd, 0, npcm8xx_pwm_addr[i]); 650 sysbus_connect_irq(sbd, i, npcm8xx_irq(s, NPCM8XX_PWM0_IRQ + i)); 651 } 652 653 /* MFT Modules. Cannot fail. */ 654 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm8xx_mft_addr) != ARRAY_SIZE(s->mft)); 655 for (i = 0; i < ARRAY_SIZE(s->mft); i++) { 656 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->mft[i]); 657 658 qdev_connect_clock_in(DEVICE(&s->mft[i]), "clock-in", 659 qdev_get_clock_out(DEVICE(&s->clk), 660 "apb4-clock")); 661 sysbus_realize(sbd, &error_abort); 662 sysbus_mmio_map(sbd, 0, npcm8xx_mft_addr[i]); 663 sysbus_connect_irq(sbd, 0, npcm8xx_irq(s, NPCM8XX_MFT0_IRQ + i)); 664 } 665 666 /* 667 * Flash Interface Unit (FIU). Can fail if incorrect number of chip selects 668 * specified, but this is a programming error. 669 */ 670 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm8xx_fiu) != ARRAY_SIZE(s->fiu)); 671 for (i = 0; i < ARRAY_SIZE(s->fiu); i++) { 672 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->fiu[i]); 673 int j; 674 675 object_property_set_int(OBJECT(sbd), "cs-count", 676 npcm8xx_fiu[i].cs_count, &error_abort); 677 object_property_set_int(OBJECT(sbd), "flash-size", 678 npcm8xx_fiu[i].flash_size, &error_abort); 679 sysbus_realize(sbd, &error_abort); 680 681 sysbus_mmio_map(sbd, 0, npcm8xx_fiu[i].regs_addr); 682 for (j = 0; j < npcm8xx_fiu[i].cs_count; j++) { 683 sysbus_mmio_map(sbd, j + 1, npcm8xx_fiu[i].flash_addr[j]); 684 } 685 } 686 687 /* RAM2 (SRAM) */ 688 memory_region_init_ram(&s->sram, OBJECT(dev), "ram2", 689 NPCM8XX_RAM2_SZ, &error_abort); 690 memory_region_add_subregion(get_system_memory(), NPCM8XX_RAM2_BA, &s->sram); 691 692 /* RAM3 (SRAM) */ 693 memory_region_init_ram(&s->ram3, OBJECT(dev), "ram3", 694 NPCM8XX_RAM3_SZ, &error_abort); 695 memory_region_add_subregion(get_system_memory(), NPCM8XX_RAM3_BA, &s->ram3); 696 697 /* Internal ROM */ 698 memory_region_init_rom(&s->irom, OBJECT(dev), "irom", NPCM8XX_ROM_SZ, 699 &error_abort); 700 memory_region_add_subregion(get_system_memory(), NPCM8XX_ROM_BA, &s->irom); 701 702 /* SDHCI */ 703 sysbus_realize(SYS_BUS_DEVICE(&s->mmc), &error_abort); 704 sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc), 0, NPCM8XX_MMC_BA); 705 sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc), 0, 706 npcm8xx_irq(s, NPCM8XX_MMC_IRQ)); 707 708 709 create_unimplemented_device("npcm8xx.shm", 0xc0001000, 4 * KiB); 710 create_unimplemented_device("npcm8xx.gicextra", 0xdfffa000, 24 * KiB); 711 create_unimplemented_device("npcm8xx.vdmx", 0xe0800000, 4 * KiB); 712 create_unimplemented_device("npcm8xx.pcierc", 0xe1000000, 64 * KiB); 713 create_unimplemented_device("npcm8xx.rootc", 0xe8000000, 128 * MiB); 714 create_unimplemented_device("npcm8xx.kcs", 0xf0007000, 4 * KiB); 715 create_unimplemented_device("npcm8xx.gfxi", 0xf000e000, 4 * KiB); 716 create_unimplemented_device("npcm8xx.fsw", 0xf000f000, 4 * KiB); 717 create_unimplemented_device("npcm8xx.bt", 0xf0030000, 4 * KiB); 718 create_unimplemented_device("npcm8xx.espi", 0xf009f000, 4 * KiB); 719 create_unimplemented_device("npcm8xx.peci", 0xf0100000, 4 * KiB); 720 create_unimplemented_device("npcm8xx.siox[1]", 0xf0101000, 4 * KiB); 721 create_unimplemented_device("npcm8xx.siox[2]", 0xf0102000, 4 * KiB); 722 create_unimplemented_device("npcm8xx.tmps", 0xf0188000, 4 * KiB); 723 create_unimplemented_device("npcm8xx.pspi", 0xf0201000, 4 * KiB); 724 create_unimplemented_device("npcm8xx.viru1", 0xf0204000, 4 * KiB); 725 create_unimplemented_device("npcm8xx.viru2", 0xf0205000, 4 * KiB); 726 create_unimplemented_device("npcm8xx.jtm1", 0xf0208000, 4 * KiB); 727 create_unimplemented_device("npcm8xx.jtm2", 0xf0209000, 4 * KiB); 728 create_unimplemented_device("npcm8xx.flm0", 0xf0210000, 4 * KiB); 729 create_unimplemented_device("npcm8xx.flm1", 0xf0211000, 4 * KiB); 730 create_unimplemented_device("npcm8xx.flm2", 0xf0212000, 4 * KiB); 731 create_unimplemented_device("npcm8xx.flm3", 0xf0213000, 4 * KiB); 732 create_unimplemented_device("npcm8xx.ahbpci", 0xf0400000, 1 * MiB); 733 create_unimplemented_device("npcm8xx.dap", 0xf0500000, 960 * KiB); 734 create_unimplemented_device("npcm8xx.mcphy", 0xf05f0000, 64 * KiB); 735 create_unimplemented_device("npcm8xx.pcs", 0xf0780000, 256 * KiB); 736 create_unimplemented_device("npcm8xx.tsgen", 0xf07fc000, 8 * KiB); 737 create_unimplemented_device("npcm8xx.gmac1", 0xf0802000, 8 * KiB); 738 create_unimplemented_device("npcm8xx.gmac2", 0xf0804000, 8 * KiB); 739 create_unimplemented_device("npcm8xx.gmac3", 0xf0806000, 8 * KiB); 740 create_unimplemented_device("npcm8xx.gmac4", 0xf0808000, 8 * KiB); 741 create_unimplemented_device("npcm8xx.copctl", 0xf080c000, 4 * KiB); 742 create_unimplemented_device("npcm8xx.tipctl", 0xf080d000, 4 * KiB); 743 create_unimplemented_device("npcm8xx.rst", 0xf080e000, 4 * KiB); 744 create_unimplemented_device("npcm8xx.vcd", 0xf0810000, 64 * KiB); 745 create_unimplemented_device("npcm8xx.ece", 0xf0820000, 8 * KiB); 746 create_unimplemented_device("npcm8xx.vdma", 0xf0822000, 8 * KiB); 747 create_unimplemented_device("npcm8xx.usbd[0]", 0xf0830000, 4 * KiB); 748 create_unimplemented_device("npcm8xx.usbd[1]", 0xf0831000, 4 * KiB); 749 create_unimplemented_device("npcm8xx.usbd[2]", 0xf0832000, 4 * KiB); 750 create_unimplemented_device("npcm8xx.usbd[3]", 0xf0833000, 4 * KiB); 751 create_unimplemented_device("npcm8xx.usbd[4]", 0xf0834000, 4 * KiB); 752 create_unimplemented_device("npcm8xx.usbd[5]", 0xf0835000, 4 * KiB); 753 create_unimplemented_device("npcm8xx.usbd[6]", 0xf0836000, 4 * KiB); 754 create_unimplemented_device("npcm8xx.usbd[7]", 0xf0837000, 4 * KiB); 755 create_unimplemented_device("npcm8xx.usbd[8]", 0xf0838000, 4 * KiB); 756 create_unimplemented_device("npcm8xx.usbd[9]", 0xf0839000, 4 * KiB); 757 create_unimplemented_device("npcm8xx.pci_mbox1", 0xf0848000, 64 * KiB); 758 create_unimplemented_device("npcm8xx.gdma0", 0xf0850000, 4 * KiB); 759 create_unimplemented_device("npcm8xx.gdma1", 0xf0851000, 4 * KiB); 760 create_unimplemented_device("npcm8xx.gdma2", 0xf0852000, 4 * KiB); 761 create_unimplemented_device("npcm8xx.aes", 0xf0858000, 4 * KiB); 762 create_unimplemented_device("npcm8xx.des", 0xf0859000, 4 * KiB); 763 create_unimplemented_device("npcm8xx.sha", 0xf085a000, 4 * KiB); 764 create_unimplemented_device("npcm8xx.pci_mbox2", 0xf0868000, 64 * KiB); 765 create_unimplemented_device("npcm8xx.i3c0", 0xfff10000, 4 * KiB); 766 create_unimplemented_device("npcm8xx.i3c1", 0xfff11000, 4 * KiB); 767 create_unimplemented_device("npcm8xx.i3c2", 0xfff12000, 4 * KiB); 768 create_unimplemented_device("npcm8xx.i3c3", 0xfff13000, 4 * KiB); 769 create_unimplemented_device("npcm8xx.i3c4", 0xfff14000, 4 * KiB); 770 create_unimplemented_device("npcm8xx.i3c5", 0xfff15000, 4 * KiB); 771 create_unimplemented_device("npcm8xx.spixcs0", 0xf8000000, 16 * MiB); 772 create_unimplemented_device("npcm8xx.spixcs1", 0xf9000000, 16 * MiB); 773 create_unimplemented_device("npcm8xx.spix", 0xfb001000, 4 * KiB); 774 create_unimplemented_device("npcm8xx.vect", 0xffff0000, 256); 775 } 776 777 static const Property npcm8xx_properties[] = { 778 DEFINE_PROP_LINK("dram-mr", NPCM8xxState, dram, TYPE_MEMORY_REGION, 779 MemoryRegion *), 780 }; 781 782 static void npcm8xx_class_init(ObjectClass *oc, void *data) 783 { 784 DeviceClass *dc = DEVICE_CLASS(oc); 785 NPCM8xxClass *nc = NPCM8XX_CLASS(oc); 786 787 dc->realize = npcm8xx_realize; 788 dc->user_creatable = false; 789 nc->disabled_modules = 0x00000000; 790 nc->num_cpus = NPCM8XX_MAX_NUM_CPUS; 791 device_class_set_props(dc, npcm8xx_properties); 792 } 793 794 static const TypeInfo npcm8xx_soc_types[] = { 795 { 796 .name = TYPE_NPCM8XX, 797 .parent = TYPE_DEVICE, 798 .instance_size = sizeof(NPCM8xxState), 799 .instance_init = npcm8xx_init, 800 .class_size = sizeof(NPCM8xxClass), 801 .class_init = npcm8xx_class_init, 802 }, 803 }; 804 805 DEFINE_TYPES(npcm8xx_soc_types); 806