1 /* 2 * Nuvoton NPCM7xx SoC family. 3 * 4 * Copyright 2020 Google LLC 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14 * for more details. 15 */ 16 17 #include "qemu/osdep.h" 18 19 #include "hw/arm/boot.h" 20 #include "hw/arm/npcm7xx.h" 21 #include "hw/char/serial-mm.h" 22 #include "hw/loader.h" 23 #include "hw/misc/unimp.h" 24 #include "hw/qdev-clock.h" 25 #include "hw/qdev-properties.h" 26 #include "qapi/error.h" 27 #include "qemu/bswap.h" 28 #include "qemu/units.h" 29 #include "system/system.h" 30 #include "target/arm/cpu-qom.h" 31 32 /* 33 * This covers the whole MMIO space. We'll use this to catch any MMIO accesses 34 * that aren't handled by any device. 35 */ 36 #define NPCM7XX_MMIO_BA (0x80000000) 37 #define NPCM7XX_MMIO_SZ (0x7ffd0000) 38 39 /* OTP key storage and fuse strap array */ 40 #define NPCM7XX_OTP1_BA (0xf0189000) 41 #define NPCM7XX_OTP2_BA (0xf018a000) 42 43 /* Core system modules. */ 44 #define NPCM7XX_L2C_BA (0xf03fc000) 45 #define NPCM7XX_CPUP_BA (0xf03fe000) 46 #define NPCM7XX_GCR_BA (0xf0800000) 47 #define NPCM7XX_CLK_BA (0xf0801000) 48 #define NPCM7XX_MC_BA (0xf0824000) 49 #define NPCM7XX_RNG_BA (0xf000b000) 50 51 /* USB Host modules */ 52 #define NPCM7XX_EHCI_BA (0xf0806000) 53 #define NPCM7XX_OHCI_BA (0xf0807000) 54 55 /* ADC Module */ 56 #define NPCM7XX_ADC_BA (0xf000c000) 57 58 /* Internal AHB SRAM */ 59 #define NPCM7XX_RAM3_BA (0xc0008000) 60 #define NPCM7XX_RAM3_SZ (4 * KiB) 61 62 /* Memory blocks at the end of the address space */ 63 #define NPCM7XX_RAM2_BA (0xfffd0000) 64 #define NPCM7XX_RAM2_SZ (128 * KiB) 65 #define NPCM7XX_ROM_BA (0xffff0000) 66 #define NPCM7XX_ROM_SZ (64 * KiB) 67 68 /* SDHCI Modules */ 69 #define NPCM7XX_MMC_BA (0xf0842000) 70 71 /* Clock configuration values to be fixed up when bypassing bootloader */ 72 73 /* Run PLL1 at 1600 MHz */ 74 #define NPCM7XX_PLLCON1_FIXUP_VAL (0x00402101) 75 /* Run the CPU from PLL1 and UART from PLL2 */ 76 #define NPCM7XX_CLKSEL_FIXUP_VAL (0x004aaba9) 77 78 /* 79 * Interrupt lines going into the GIC. This does not include internal Cortex-A9 80 * interrupts. 81 */ 82 enum NPCM7xxInterrupt { 83 NPCM7XX_ADC_IRQ = 0, 84 NPCM7XX_UART0_IRQ = 2, 85 NPCM7XX_UART1_IRQ, 86 NPCM7XX_UART2_IRQ, 87 NPCM7XX_UART3_IRQ, 88 NPCM7XX_GMAC1_IRQ = 14, 89 NPCM7XX_EMC1RX_IRQ = 15, 90 NPCM7XX_EMC1TX_IRQ, 91 NPCM7XX_GMAC2_IRQ, 92 NPCM7XX_MMC_IRQ = 26, 93 NPCM7XX_PSPI2_IRQ = 28, 94 NPCM7XX_PSPI1_IRQ = 31, 95 NPCM7XX_TIMER0_IRQ = 32, /* Timer Module 0 */ 96 NPCM7XX_TIMER1_IRQ, 97 NPCM7XX_TIMER2_IRQ, 98 NPCM7XX_TIMER3_IRQ, 99 NPCM7XX_TIMER4_IRQ, 100 NPCM7XX_TIMER5_IRQ, /* Timer Module 1 */ 101 NPCM7XX_TIMER6_IRQ, 102 NPCM7XX_TIMER7_IRQ, 103 NPCM7XX_TIMER8_IRQ, 104 NPCM7XX_TIMER9_IRQ, 105 NPCM7XX_TIMER10_IRQ, /* Timer Module 2 */ 106 NPCM7XX_TIMER11_IRQ, 107 NPCM7XX_TIMER12_IRQ, 108 NPCM7XX_TIMER13_IRQ, 109 NPCM7XX_TIMER14_IRQ, 110 NPCM7XX_WDG0_IRQ = 47, /* Timer Module 0 Watchdog */ 111 NPCM7XX_WDG1_IRQ, /* Timer Module 1 Watchdog */ 112 NPCM7XX_WDG2_IRQ, /* Timer Module 2 Watchdog */ 113 NPCM7XX_EHCI_IRQ = 61, 114 NPCM7XX_OHCI_IRQ = 62, 115 NPCM7XX_SMBUS0_IRQ = 64, 116 NPCM7XX_SMBUS1_IRQ, 117 NPCM7XX_SMBUS2_IRQ, 118 NPCM7XX_SMBUS3_IRQ, 119 NPCM7XX_SMBUS4_IRQ, 120 NPCM7XX_SMBUS5_IRQ, 121 NPCM7XX_SMBUS6_IRQ, 122 NPCM7XX_SMBUS7_IRQ, 123 NPCM7XX_SMBUS8_IRQ, 124 NPCM7XX_SMBUS9_IRQ, 125 NPCM7XX_SMBUS10_IRQ, 126 NPCM7XX_SMBUS11_IRQ, 127 NPCM7XX_SMBUS12_IRQ, 128 NPCM7XX_SMBUS13_IRQ, 129 NPCM7XX_SMBUS14_IRQ, 130 NPCM7XX_SMBUS15_IRQ, 131 NPCM7XX_PWM0_IRQ = 93, /* PWM module 0 */ 132 NPCM7XX_PWM1_IRQ, /* PWM module 1 */ 133 NPCM7XX_MFT0_IRQ = 96, /* MFT module 0 */ 134 NPCM7XX_MFT1_IRQ, /* MFT module 1 */ 135 NPCM7XX_MFT2_IRQ, /* MFT module 2 */ 136 NPCM7XX_MFT3_IRQ, /* MFT module 3 */ 137 NPCM7XX_MFT4_IRQ, /* MFT module 4 */ 138 NPCM7XX_MFT5_IRQ, /* MFT module 5 */ 139 NPCM7XX_MFT6_IRQ, /* MFT module 6 */ 140 NPCM7XX_MFT7_IRQ, /* MFT module 7 */ 141 NPCM7XX_EMC2RX_IRQ = 114, 142 NPCM7XX_EMC2TX_IRQ, 143 NPCM7XX_GPIO0_IRQ = 116, 144 NPCM7XX_GPIO1_IRQ, 145 NPCM7XX_GPIO2_IRQ, 146 NPCM7XX_GPIO3_IRQ, 147 NPCM7XX_GPIO4_IRQ, 148 NPCM7XX_GPIO5_IRQ, 149 NPCM7XX_GPIO6_IRQ, 150 NPCM7XX_GPIO7_IRQ, 151 }; 152 153 /* Total number of GIC interrupts, including internal Cortex-A9 interrupts. */ 154 #define NPCM7XX_NUM_IRQ (160) 155 156 /* Register base address for each Timer Module */ 157 static const hwaddr npcm7xx_tim_addr[] = { 158 0xf0008000, 159 0xf0009000, 160 0xf000a000, 161 }; 162 163 /* Register base address for each 16550 UART */ 164 static const hwaddr npcm7xx_uart_addr[] = { 165 0xf0001000, 166 0xf0002000, 167 0xf0003000, 168 0xf0004000, 169 }; 170 171 /* Direct memory-mapped access to SPI0 CS0-1. */ 172 static const hwaddr npcm7xx_fiu0_flash_addr[] = { 173 0x80000000, /* CS0 */ 174 0x88000000, /* CS1 */ 175 }; 176 177 /* Direct memory-mapped access to SPI3 CS0-3. */ 178 static const hwaddr npcm7xx_fiu3_flash_addr[] = { 179 0xa0000000, /* CS0 */ 180 0xa8000000, /* CS1 */ 181 0xb0000000, /* CS2 */ 182 0xb8000000, /* CS3 */ 183 }; 184 185 /* Register base address for each PWM Module */ 186 static const hwaddr npcm7xx_pwm_addr[] = { 187 0xf0103000, 188 0xf0104000, 189 }; 190 191 /* Register base address for each MFT Module */ 192 static const hwaddr npcm7xx_mft_addr[] = { 193 0xf0180000, 194 0xf0181000, 195 0xf0182000, 196 0xf0183000, 197 0xf0184000, 198 0xf0185000, 199 0xf0186000, 200 0xf0187000, 201 }; 202 203 /* Direct memory-mapped access to each SMBus Module. */ 204 static const hwaddr npcm7xx_smbus_addr[] = { 205 0xf0080000, 206 0xf0081000, 207 0xf0082000, 208 0xf0083000, 209 0xf0084000, 210 0xf0085000, 211 0xf0086000, 212 0xf0087000, 213 0xf0088000, 214 0xf0089000, 215 0xf008a000, 216 0xf008b000, 217 0xf008c000, 218 0xf008d000, 219 0xf008e000, 220 0xf008f000, 221 }; 222 223 /* Register base address for each EMC Module */ 224 static const hwaddr npcm7xx_emc_addr[] = { 225 0xf0825000, 226 0xf0826000, 227 }; 228 229 /* Register base address for each PSPI Module */ 230 static const hwaddr npcm7xx_pspi_addr[] = { 231 0xf0200000, 232 0xf0201000, 233 }; 234 235 /* Register base address for each GMAC Module */ 236 static const hwaddr npcm7xx_gmac_addr[] = { 237 0xf0802000, 238 0xf0804000, 239 }; 240 241 static const struct { 242 hwaddr regs_addr; 243 uint32_t unconnected_pins; 244 uint32_t reset_pu; 245 uint32_t reset_pd; 246 uint32_t reset_osrc; 247 uint32_t reset_odsc; 248 } npcm7xx_gpio[] = { 249 { 250 .regs_addr = 0xf0010000, 251 .reset_pu = 0xff03ffff, 252 .reset_pd = 0x00fc0000, 253 }, { 254 .regs_addr = 0xf0011000, 255 .unconnected_pins = 0x0000001e, 256 .reset_pu = 0xfefffe07, 257 .reset_pd = 0x010001e0, 258 }, { 259 .regs_addr = 0xf0012000, 260 .reset_pu = 0x780fffff, 261 .reset_pd = 0x07f00000, 262 .reset_odsc = 0x00700000, 263 }, { 264 .regs_addr = 0xf0013000, 265 .reset_pu = 0x00fc0000, 266 .reset_pd = 0xff000000, 267 }, { 268 .regs_addr = 0xf0014000, 269 .reset_pu = 0xffffffff, 270 }, { 271 .regs_addr = 0xf0015000, 272 .reset_pu = 0xbf83f801, 273 .reset_pd = 0x007c0000, 274 .reset_osrc = 0x000000f1, 275 .reset_odsc = 0x3f9f80f1, 276 }, { 277 .regs_addr = 0xf0016000, 278 .reset_pu = 0xfc00f801, 279 .reset_pd = 0x000007fe, 280 .reset_odsc = 0x00000800, 281 }, { 282 .regs_addr = 0xf0017000, 283 .unconnected_pins = 0xffffff00, 284 .reset_pu = 0x0000007f, 285 .reset_osrc = 0x0000007f, 286 .reset_odsc = 0x0000007f, 287 }, 288 }; 289 290 static const struct { 291 const char *name; 292 hwaddr regs_addr; 293 int cs_count; 294 const hwaddr *flash_addr; 295 size_t flash_size; 296 } npcm7xx_fiu[] = { 297 { 298 .name = "fiu0", 299 .regs_addr = 0xfb000000, 300 .cs_count = ARRAY_SIZE(npcm7xx_fiu0_flash_addr), 301 .flash_addr = npcm7xx_fiu0_flash_addr, 302 .flash_size = 128 * MiB, 303 304 }, { 305 .name = "fiu3", 306 .regs_addr = 0xc0000000, 307 .cs_count = ARRAY_SIZE(npcm7xx_fiu3_flash_addr), 308 .flash_addr = npcm7xx_fiu3_flash_addr, 309 .flash_size = 128 * MiB, 310 }, 311 }; 312 313 static void npcm7xx_write_board_setup(ARMCPU *cpu, 314 const struct arm_boot_info *info) 315 { 316 uint32_t board_setup[] = { 317 0xe59f0010, /* ldr r0, clk_base_addr */ 318 0xe59f1010, /* ldr r1, pllcon1_value */ 319 0xe5801010, /* str r1, [r0, #16] */ 320 0xe59f100c, /* ldr r1, clksel_value */ 321 0xe5801004, /* str r1, [r0, #4] */ 322 0xe12fff1e, /* bx lr */ 323 NPCM7XX_CLK_BA, 324 NPCM7XX_PLLCON1_FIXUP_VAL, 325 NPCM7XX_CLKSEL_FIXUP_VAL, 326 }; 327 int i; 328 329 for (i = 0; i < ARRAY_SIZE(board_setup); i++) { 330 board_setup[i] = tswap32(board_setup[i]); 331 } 332 rom_add_blob_fixed("board-setup", board_setup, sizeof(board_setup), 333 info->board_setup_addr); 334 } 335 336 static void npcm7xx_write_secondary_boot(ARMCPU *cpu, 337 const struct arm_boot_info *info) 338 { 339 /* 340 * The default smpboot stub halts the secondary CPU with a 'wfi' 341 * instruction, but the arch/arm/mach-npcm/platsmp.c in the Linux kernel 342 * does not send an IPI to wake it up, so the second CPU fails to boot. So 343 * we need to provide our own smpboot stub that can not use 'wfi', it has 344 * to spin the secondary CPU until the first CPU writes to the SCRPAD reg. 345 */ 346 uint32_t smpboot[] = { 347 0xe59f2018, /* ldr r2, bootreg_addr */ 348 0xe3a00000, /* mov r0, #0 */ 349 0xe5820000, /* str r0, [r2] */ 350 0xe320f002, /* wfe */ 351 0xe5921000, /* ldr r1, [r2] */ 352 0xe1110001, /* tst r1, r1 */ 353 0x0afffffb, /* beq <wfe> */ 354 0xe12fff11, /* bx r1 */ 355 NPCM7XX_SMP_BOOTREG_ADDR, 356 }; 357 int i; 358 359 for (i = 0; i < ARRAY_SIZE(smpboot); i++) { 360 smpboot[i] = tswap32(smpboot[i]); 361 } 362 363 rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot), 364 NPCM7XX_SMP_LOADER_START); 365 } 366 367 static struct arm_boot_info npcm7xx_binfo = { 368 .loader_start = NPCM7XX_LOADER_START, 369 .smp_loader_start = NPCM7XX_SMP_LOADER_START, 370 .smp_bootreg_addr = NPCM7XX_SMP_BOOTREG_ADDR, 371 .gic_cpu_if_addr = NPCM7XX_GIC_CPU_IF_ADDR, 372 .write_secondary_boot = npcm7xx_write_secondary_boot, 373 .board_id = -1, 374 .board_setup_addr = NPCM7XX_BOARD_SETUP_ADDR, 375 .write_board_setup = npcm7xx_write_board_setup, 376 }; 377 378 void npcm7xx_load_kernel(MachineState *machine, NPCM7xxState *soc) 379 { 380 npcm7xx_binfo.ram_size = machine->ram_size; 381 382 arm_load_kernel(&soc->cpu[0], machine, &npcm7xx_binfo); 383 } 384 385 static void npcm7xx_init_fuses(NPCM7xxState *s) 386 { 387 NPCM7xxClass *nc = NPCM7XX_GET_CLASS(s); 388 uint32_t value; 389 390 /* 391 * The initial mask of disabled modules indicates the chip derivative (e.g. 392 * NPCM750 or NPCM730). 393 */ 394 value = cpu_to_le32(nc->disabled_modules); 395 npcm7xx_otp_array_write(&s->fuse_array, &value, NPCM7XX_FUSE_DERIVATIVE, 396 sizeof(value)); 397 } 398 399 static void npcm7xx_write_adc_calibration(NPCM7xxState *s) 400 { 401 /* Both ADC and the fuse array must have realized. */ 402 QEMU_BUILD_BUG_ON(sizeof(s->adc.calibration_r_values) != 4); 403 npcm7xx_otp_array_write(&s->fuse_array, s->adc.calibration_r_values, 404 NPCM7XX_FUSE_ADC_CALIB, sizeof(s->adc.calibration_r_values)); 405 } 406 407 static qemu_irq npcm7xx_irq(NPCM7xxState *s, int n) 408 { 409 return qdev_get_gpio_in(DEVICE(&s->a9mpcore), n); 410 } 411 412 static void npcm7xx_init(Object *obj) 413 { 414 NPCM7xxState *s = NPCM7XX(obj); 415 int i; 416 417 for (i = 0; i < NPCM7XX_MAX_NUM_CPUS; i++) { 418 object_initialize_child(obj, "cpu[*]", &s->cpu[i], 419 ARM_CPU_TYPE_NAME("cortex-a9")); 420 } 421 422 object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV); 423 object_initialize_child(obj, "gcr", &s->gcr, TYPE_NPCM7XX_GCR); 424 object_property_add_alias(obj, "power-on-straps", OBJECT(&s->gcr), 425 "power-on-straps"); 426 object_initialize_child(obj, "clk", &s->clk, TYPE_NPCM7XX_CLK); 427 object_initialize_child(obj, "otp1", &s->key_storage, 428 TYPE_NPCM7XX_KEY_STORAGE); 429 object_initialize_child(obj, "otp2", &s->fuse_array, 430 TYPE_NPCM7XX_FUSE_ARRAY); 431 object_initialize_child(obj, "mc", &s->mc, TYPE_NPCM7XX_MC); 432 object_initialize_child(obj, "rng", &s->rng, TYPE_NPCM7XX_RNG); 433 object_initialize_child(obj, "adc", &s->adc, TYPE_NPCM7XX_ADC); 434 435 for (i = 0; i < ARRAY_SIZE(s->tim); i++) { 436 object_initialize_child(obj, "tim[*]", &s->tim[i], TYPE_NPCM7XX_TIMER); 437 } 438 439 for (i = 0; i < ARRAY_SIZE(s->gpio); i++) { 440 object_initialize_child(obj, "gpio[*]", &s->gpio[i], TYPE_NPCM7XX_GPIO); 441 } 442 443 for (i = 0; i < ARRAY_SIZE(s->smbus); i++) { 444 object_initialize_child(obj, "smbus[*]", &s->smbus[i], 445 TYPE_NPCM7XX_SMBUS); 446 } 447 448 object_initialize_child(obj, "ehci", &s->ehci, TYPE_NPCM7XX_EHCI); 449 object_initialize_child(obj, "ohci", &s->ohci, TYPE_SYSBUS_OHCI); 450 451 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_fiu) != ARRAY_SIZE(s->fiu)); 452 for (i = 0; i < ARRAY_SIZE(s->fiu); i++) { 453 object_initialize_child(obj, npcm7xx_fiu[i].name, &s->fiu[i], 454 TYPE_NPCM7XX_FIU); 455 } 456 457 for (i = 0; i < ARRAY_SIZE(s->pwm); i++) { 458 object_initialize_child(obj, "pwm[*]", &s->pwm[i], TYPE_NPCM7XX_PWM); 459 } 460 461 for (i = 0; i < ARRAY_SIZE(s->mft); i++) { 462 object_initialize_child(obj, "mft[*]", &s->mft[i], TYPE_NPCM7XX_MFT); 463 } 464 465 for (i = 0; i < ARRAY_SIZE(s->emc); i++) { 466 object_initialize_child(obj, "emc[*]", &s->emc[i], TYPE_NPCM7XX_EMC); 467 } 468 469 for (i = 0; i < ARRAY_SIZE(s->pspi); i++) { 470 object_initialize_child(obj, "pspi[*]", &s->pspi[i], TYPE_NPCM_PSPI); 471 } 472 473 for (i = 0; i < ARRAY_SIZE(s->gmac); i++) { 474 object_initialize_child(obj, "gmac[*]", &s->gmac[i], TYPE_NPCM_GMAC); 475 } 476 477 object_initialize_child(obj, "mmc", &s->mmc, TYPE_NPCM7XX_SDHCI); 478 } 479 480 static void npcm7xx_realize(DeviceState *dev, Error **errp) 481 { 482 NPCM7xxState *s = NPCM7XX(dev); 483 NPCM7xxClass *nc = NPCM7XX_GET_CLASS(s); 484 int i; 485 486 if (memory_region_size(s->dram) > NPCM7XX_DRAM_SZ) { 487 error_setg(errp, "%s: NPCM7xx cannot address more than %" PRIu64 488 " MiB of DRAM", __func__, NPCM7XX_DRAM_SZ / MiB); 489 return; 490 } 491 492 /* CPUs */ 493 for (i = 0; i < nc->num_cpus; i++) { 494 object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar", 495 NPCM7XX_GIC_CPU_IF_ADDR, &error_abort); 496 object_property_set_bool(OBJECT(&s->cpu[i]), "reset-hivecs", true, 497 &error_abort); 498 499 /* Disable security extensions. */ 500 object_property_set_bool(OBJECT(&s->cpu[i]), "has_el3", false, 501 &error_abort); 502 503 if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) { 504 return; 505 } 506 } 507 508 /* A9MPCORE peripherals. Can only fail if we pass bad parameters here. */ 509 object_property_set_int(OBJECT(&s->a9mpcore), "num-cpu", nc->num_cpus, 510 &error_abort); 511 object_property_set_int(OBJECT(&s->a9mpcore), "num-irq", NPCM7XX_NUM_IRQ, 512 &error_abort); 513 sysbus_realize(SYS_BUS_DEVICE(&s->a9mpcore), &error_abort); 514 sysbus_mmio_map(SYS_BUS_DEVICE(&s->a9mpcore), 0, NPCM7XX_CPUP_BA); 515 516 for (i = 0; i < nc->num_cpus; i++) { 517 sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i, 518 qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IRQ)); 519 sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i + nc->num_cpus, 520 qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_FIQ)); 521 } 522 523 /* L2 cache controller */ 524 sysbus_create_simple("l2x0", NPCM7XX_L2C_BA, NULL); 525 526 /* System Global Control Registers (GCR). Can fail due to user input. */ 527 object_property_set_int(OBJECT(&s->gcr), "disabled-modules", 528 nc->disabled_modules, &error_abort); 529 object_property_add_const_link(OBJECT(&s->gcr), "dram-mr", OBJECT(s->dram)); 530 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gcr), errp)) { 531 return; 532 } 533 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gcr), 0, NPCM7XX_GCR_BA); 534 535 /* Clock Control Registers (CLK). Cannot fail. */ 536 sysbus_realize(SYS_BUS_DEVICE(&s->clk), &error_abort); 537 sysbus_mmio_map(SYS_BUS_DEVICE(&s->clk), 0, NPCM7XX_CLK_BA); 538 539 /* OTP key storage and fuse strap array. Cannot fail. */ 540 sysbus_realize(SYS_BUS_DEVICE(&s->key_storage), &error_abort); 541 sysbus_mmio_map(SYS_BUS_DEVICE(&s->key_storage), 0, NPCM7XX_OTP1_BA); 542 sysbus_realize(SYS_BUS_DEVICE(&s->fuse_array), &error_abort); 543 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fuse_array), 0, NPCM7XX_OTP2_BA); 544 npcm7xx_init_fuses(s); 545 546 /* Fake Memory Controller (MC). Cannot fail. */ 547 sysbus_realize(SYS_BUS_DEVICE(&s->mc), &error_abort); 548 sysbus_mmio_map(SYS_BUS_DEVICE(&s->mc), 0, NPCM7XX_MC_BA); 549 550 /* ADC Modules. Cannot fail. */ 551 qdev_connect_clock_in(DEVICE(&s->adc), "clock", qdev_get_clock_out( 552 DEVICE(&s->clk), "adc-clock")); 553 sysbus_realize(SYS_BUS_DEVICE(&s->adc), &error_abort); 554 sysbus_mmio_map(SYS_BUS_DEVICE(&s->adc), 0, NPCM7XX_ADC_BA); 555 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, 556 npcm7xx_irq(s, NPCM7XX_ADC_IRQ)); 557 npcm7xx_write_adc_calibration(s); 558 559 /* Timer Modules (TIM). Cannot fail. */ 560 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_tim_addr) != ARRAY_SIZE(s->tim)); 561 for (i = 0; i < ARRAY_SIZE(s->tim); i++) { 562 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->tim[i]); 563 int first_irq; 564 int j; 565 566 /* Connect the timer clock. */ 567 qdev_connect_clock_in(DEVICE(&s->tim[i]), "clock", qdev_get_clock_out( 568 DEVICE(&s->clk), "timer-clock")); 569 570 sysbus_realize(sbd, &error_abort); 571 sysbus_mmio_map(sbd, 0, npcm7xx_tim_addr[i]); 572 573 first_irq = NPCM7XX_TIMER0_IRQ + i * NPCM7XX_TIMERS_PER_CTRL; 574 for (j = 0; j < NPCM7XX_TIMERS_PER_CTRL; j++) { 575 qemu_irq irq = npcm7xx_irq(s, first_irq + j); 576 sysbus_connect_irq(sbd, j, irq); 577 } 578 579 /* IRQ for watchdogs */ 580 sysbus_connect_irq(sbd, NPCM7XX_TIMERS_PER_CTRL, 581 npcm7xx_irq(s, NPCM7XX_WDG0_IRQ + i)); 582 /* GPIO that connects clk module with watchdog */ 583 qdev_connect_gpio_out_named(DEVICE(&s->tim[i]), 584 NPCM7XX_WATCHDOG_RESET_GPIO_OUT, 0, 585 qdev_get_gpio_in_named(DEVICE(&s->clk), 586 NPCM7XX_WATCHDOG_RESET_GPIO_IN, i)); 587 } 588 589 /* UART0..3 (16550 compatible) */ 590 for (i = 0; i < ARRAY_SIZE(npcm7xx_uart_addr); i++) { 591 serial_mm_init(get_system_memory(), npcm7xx_uart_addr[i], 2, 592 npcm7xx_irq(s, NPCM7XX_UART0_IRQ + i), 115200, 593 serial_hd(i), DEVICE_LITTLE_ENDIAN); 594 } 595 596 /* Random Number Generator. Cannot fail. */ 597 sysbus_realize(SYS_BUS_DEVICE(&s->rng), &error_abort); 598 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rng), 0, NPCM7XX_RNG_BA); 599 600 /* GPIO modules. Cannot fail. */ 601 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_gpio) != ARRAY_SIZE(s->gpio)); 602 for (i = 0; i < ARRAY_SIZE(s->gpio); i++) { 603 Object *obj = OBJECT(&s->gpio[i]); 604 605 object_property_set_uint(obj, "reset-pullup", 606 npcm7xx_gpio[i].reset_pu, &error_abort); 607 object_property_set_uint(obj, "reset-pulldown", 608 npcm7xx_gpio[i].reset_pd, &error_abort); 609 object_property_set_uint(obj, "reset-osrc", 610 npcm7xx_gpio[i].reset_osrc, &error_abort); 611 object_property_set_uint(obj, "reset-odsc", 612 npcm7xx_gpio[i].reset_odsc, &error_abort); 613 sysbus_realize(SYS_BUS_DEVICE(obj), &error_abort); 614 sysbus_mmio_map(SYS_BUS_DEVICE(obj), 0, npcm7xx_gpio[i].regs_addr); 615 sysbus_connect_irq(SYS_BUS_DEVICE(obj), 0, 616 npcm7xx_irq(s, NPCM7XX_GPIO0_IRQ + i)); 617 } 618 619 /* SMBus modules. Cannot fail. */ 620 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_smbus_addr) != ARRAY_SIZE(s->smbus)); 621 for (i = 0; i < ARRAY_SIZE(s->smbus); i++) { 622 Object *obj = OBJECT(&s->smbus[i]); 623 624 sysbus_realize(SYS_BUS_DEVICE(obj), &error_abort); 625 sysbus_mmio_map(SYS_BUS_DEVICE(obj), 0, npcm7xx_smbus_addr[i]); 626 sysbus_connect_irq(SYS_BUS_DEVICE(obj), 0, 627 npcm7xx_irq(s, NPCM7XX_SMBUS0_IRQ + i)); 628 } 629 630 /* USB Host */ 631 object_property_set_bool(OBJECT(&s->ehci), "companion-enable", true, 632 &error_abort); 633 sysbus_realize(SYS_BUS_DEVICE(&s->ehci), &error_abort); 634 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci), 0, NPCM7XX_EHCI_BA); 635 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci), 0, 636 npcm7xx_irq(s, NPCM7XX_EHCI_IRQ)); 637 638 object_property_set_str(OBJECT(&s->ohci), "masterbus", "usb-bus.0", 639 &error_abort); 640 object_property_set_uint(OBJECT(&s->ohci), "num-ports", 1, &error_abort); 641 sysbus_realize(SYS_BUS_DEVICE(&s->ohci), &error_abort); 642 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ohci), 0, NPCM7XX_OHCI_BA); 643 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ohci), 0, 644 npcm7xx_irq(s, NPCM7XX_OHCI_IRQ)); 645 646 /* PWM Modules. Cannot fail. */ 647 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_pwm_addr) != ARRAY_SIZE(s->pwm)); 648 for (i = 0; i < ARRAY_SIZE(s->pwm); i++) { 649 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->pwm[i]); 650 651 qdev_connect_clock_in(DEVICE(&s->pwm[i]), "clock", qdev_get_clock_out( 652 DEVICE(&s->clk), "apb3-clock")); 653 sysbus_realize(sbd, &error_abort); 654 sysbus_mmio_map(sbd, 0, npcm7xx_pwm_addr[i]); 655 sysbus_connect_irq(sbd, i, npcm7xx_irq(s, NPCM7XX_PWM0_IRQ + i)); 656 } 657 658 /* MFT Modules. Cannot fail. */ 659 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_mft_addr) != ARRAY_SIZE(s->mft)); 660 for (i = 0; i < ARRAY_SIZE(s->mft); i++) { 661 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->mft[i]); 662 663 qdev_connect_clock_in(DEVICE(&s->mft[i]), "clock-in", 664 qdev_get_clock_out(DEVICE(&s->clk), 665 "apb4-clock")); 666 sysbus_realize(sbd, &error_abort); 667 sysbus_mmio_map(sbd, 0, npcm7xx_mft_addr[i]); 668 sysbus_connect_irq(sbd, 0, npcm7xx_irq(s, NPCM7XX_MFT0_IRQ + i)); 669 } 670 671 /* 672 * EMC Modules. Cannot fail. 673 * Use the available NIC configurations in order, allowing 'emc0' and 674 * 'emc1' to by used as aliases for the model= parameter to override. 675 * 676 * This works around the inability to specify the netdev property for the 677 * emc device: it's not pluggable and thus the -device option can't be 678 * used. 679 */ 680 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_emc_addr) != ARRAY_SIZE(s->emc)); 681 QEMU_BUILD_BUG_ON(ARRAY_SIZE(s->emc) != 2); 682 for (i = 0; i < ARRAY_SIZE(s->emc); i++) { 683 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->emc[i]); 684 char alias[6]; 685 686 s->emc[i].emc_num = i; 687 snprintf(alias, sizeof(alias), "emc%u", i); 688 qemu_configure_nic_device(DEVICE(sbd), true, alias); 689 690 /* 691 * The device exists regardless of whether it's connected to a QEMU 692 * netdev backend. So always instantiate it even if there is no 693 * backend. 694 */ 695 sysbus_realize(sbd, &error_abort); 696 sysbus_mmio_map(sbd, 0, npcm7xx_emc_addr[i]); 697 int tx_irq = i == 0 ? NPCM7XX_EMC1TX_IRQ : NPCM7XX_EMC2TX_IRQ; 698 int rx_irq = i == 0 ? NPCM7XX_EMC1RX_IRQ : NPCM7XX_EMC2RX_IRQ; 699 /* 700 * N.B. The values for the second argument sysbus_connect_irq are 701 * chosen to match the registration order in npcm7xx_emc_realize. 702 */ 703 sysbus_connect_irq(sbd, 0, npcm7xx_irq(s, tx_irq)); 704 sysbus_connect_irq(sbd, 1, npcm7xx_irq(s, rx_irq)); 705 } 706 707 /* 708 * GMAC Modules. Cannot fail. 709 */ 710 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_gmac_addr) != ARRAY_SIZE(s->gmac)); 711 QEMU_BUILD_BUG_ON(ARRAY_SIZE(s->gmac) != 2); 712 for (i = 0; i < ARRAY_SIZE(s->gmac); i++) { 713 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->gmac[i]); 714 715 qemu_configure_nic_device(DEVICE(sbd), false, NULL); 716 /* 717 * The device exists regardless of whether it's connected to a QEMU 718 * netdev backend. So always instantiate it even if there is no 719 * backend. 720 */ 721 sysbus_realize(sbd, &error_abort); 722 sysbus_mmio_map(sbd, 0, npcm7xx_gmac_addr[i]); 723 int irq = i == 0 ? NPCM7XX_GMAC1_IRQ : NPCM7XX_GMAC2_IRQ; 724 /* 725 * N.B. The values for the second argument sysbus_connect_irq are 726 * chosen to match the registration order in npcm7xx_emc_realize. 727 */ 728 sysbus_connect_irq(sbd, 0, npcm7xx_irq(s, irq)); 729 } 730 731 /* 732 * Flash Interface Unit (FIU). Can fail if incorrect number of chip selects 733 * specified, but this is a programming error. 734 */ 735 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_fiu) != ARRAY_SIZE(s->fiu)); 736 for (i = 0; i < ARRAY_SIZE(s->fiu); i++) { 737 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->fiu[i]); 738 int j; 739 740 object_property_set_int(OBJECT(sbd), "cs-count", 741 npcm7xx_fiu[i].cs_count, &error_abort); 742 object_property_set_int(OBJECT(sbd), "flash-size", 743 npcm7xx_fiu[i].flash_size, &error_abort); 744 sysbus_realize(sbd, &error_abort); 745 746 sysbus_mmio_map(sbd, 0, npcm7xx_fiu[i].regs_addr); 747 for (j = 0; j < npcm7xx_fiu[i].cs_count; j++) { 748 sysbus_mmio_map(sbd, j + 1, npcm7xx_fiu[i].flash_addr[j]); 749 } 750 } 751 752 /* RAM2 (SRAM) */ 753 memory_region_init_ram(&s->sram, OBJECT(dev), "ram2", 754 NPCM7XX_RAM2_SZ, &error_abort); 755 memory_region_add_subregion(get_system_memory(), NPCM7XX_RAM2_BA, &s->sram); 756 757 /* RAM3 (SRAM) */ 758 memory_region_init_ram(&s->ram3, OBJECT(dev), "ram3", 759 NPCM7XX_RAM3_SZ, &error_abort); 760 memory_region_add_subregion(get_system_memory(), NPCM7XX_RAM3_BA, &s->ram3); 761 762 /* Internal ROM */ 763 memory_region_init_rom(&s->irom, OBJECT(dev), "irom", NPCM7XX_ROM_SZ, 764 &error_abort); 765 memory_region_add_subregion(get_system_memory(), NPCM7XX_ROM_BA, &s->irom); 766 767 /* SDHCI */ 768 sysbus_realize(SYS_BUS_DEVICE(&s->mmc), &error_abort); 769 sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc), 0, NPCM7XX_MMC_BA); 770 sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc), 0, 771 npcm7xx_irq(s, NPCM7XX_MMC_IRQ)); 772 773 /* PSPI */ 774 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_pspi_addr) != ARRAY_SIZE(s->pspi)); 775 for (i = 0; i < ARRAY_SIZE(s->pspi); i++) { 776 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->pspi[i]); 777 int irq = (i == 0) ? NPCM7XX_PSPI1_IRQ : NPCM7XX_PSPI2_IRQ; 778 779 sysbus_realize(sbd, &error_abort); 780 sysbus_mmio_map(sbd, 0, npcm7xx_pspi_addr[i]); 781 sysbus_connect_irq(sbd, 0, npcm7xx_irq(s, irq)); 782 } 783 784 create_unimplemented_device("npcm7xx.shm", 0xc0001000, 4 * KiB); 785 create_unimplemented_device("npcm7xx.vdmx", 0xe0800000, 4 * KiB); 786 create_unimplemented_device("npcm7xx.pcierc", 0xe1000000, 64 * KiB); 787 create_unimplemented_device("npcm7xx.kcs", 0xf0007000, 4 * KiB); 788 create_unimplemented_device("npcm7xx.gfxi", 0xf000e000, 4 * KiB); 789 create_unimplemented_device("npcm7xx.espi", 0xf009f000, 4 * KiB); 790 create_unimplemented_device("npcm7xx.peci", 0xf0100000, 4 * KiB); 791 create_unimplemented_device("npcm7xx.siox[1]", 0xf0101000, 4 * KiB); 792 create_unimplemented_device("npcm7xx.siox[2]", 0xf0102000, 4 * KiB); 793 create_unimplemented_device("npcm7xx.ahbpci", 0xf0400000, 1 * MiB); 794 create_unimplemented_device("npcm7xx.mcphy", 0xf05f0000, 64 * KiB); 795 create_unimplemented_device("npcm7xx.vcd", 0xf0810000, 64 * KiB); 796 create_unimplemented_device("npcm7xx.ece", 0xf0820000, 8 * KiB); 797 create_unimplemented_device("npcm7xx.vdma", 0xf0822000, 8 * KiB); 798 create_unimplemented_device("npcm7xx.usbd[0]", 0xf0830000, 4 * KiB); 799 create_unimplemented_device("npcm7xx.usbd[1]", 0xf0831000, 4 * KiB); 800 create_unimplemented_device("npcm7xx.usbd[2]", 0xf0832000, 4 * KiB); 801 create_unimplemented_device("npcm7xx.usbd[3]", 0xf0833000, 4 * KiB); 802 create_unimplemented_device("npcm7xx.usbd[4]", 0xf0834000, 4 * KiB); 803 create_unimplemented_device("npcm7xx.usbd[5]", 0xf0835000, 4 * KiB); 804 create_unimplemented_device("npcm7xx.usbd[6]", 0xf0836000, 4 * KiB); 805 create_unimplemented_device("npcm7xx.usbd[7]", 0xf0837000, 4 * KiB); 806 create_unimplemented_device("npcm7xx.usbd[8]", 0xf0838000, 4 * KiB); 807 create_unimplemented_device("npcm7xx.usbd[9]", 0xf0839000, 4 * KiB); 808 create_unimplemented_device("npcm7xx.sd", 0xf0840000, 8 * KiB); 809 create_unimplemented_device("npcm7xx.pcimbx", 0xf0848000, 512 * KiB); 810 create_unimplemented_device("npcm7xx.aes", 0xf0858000, 4 * KiB); 811 create_unimplemented_device("npcm7xx.des", 0xf0859000, 4 * KiB); 812 create_unimplemented_device("npcm7xx.sha", 0xf085a000, 4 * KiB); 813 create_unimplemented_device("npcm7xx.secacc", 0xf085b000, 4 * KiB); 814 create_unimplemented_device("npcm7xx.spixcs0", 0xf8000000, 16 * MiB); 815 create_unimplemented_device("npcm7xx.spixcs1", 0xf9000000, 16 * MiB); 816 create_unimplemented_device("npcm7xx.spix", 0xfb001000, 4 * KiB); 817 } 818 819 static const Property npcm7xx_properties[] = { 820 DEFINE_PROP_LINK("dram-mr", NPCM7xxState, dram, TYPE_MEMORY_REGION, 821 MemoryRegion *), 822 }; 823 824 static void npcm7xx_class_init(ObjectClass *oc, void *data) 825 { 826 DeviceClass *dc = DEVICE_CLASS(oc); 827 828 dc->realize = npcm7xx_realize; 829 dc->user_creatable = false; 830 device_class_set_props(dc, npcm7xx_properties); 831 } 832 833 static void npcm730_class_init(ObjectClass *oc, void *data) 834 { 835 NPCM7xxClass *nc = NPCM7XX_CLASS(oc); 836 837 /* NPCM730 is optimized for data center use, so no graphics, etc. */ 838 nc->disabled_modules = 0x00300395; 839 nc->num_cpus = 2; 840 } 841 842 static void npcm750_class_init(ObjectClass *oc, void *data) 843 { 844 NPCM7xxClass *nc = NPCM7XX_CLASS(oc); 845 846 /* NPCM750 has 2 cores and a full set of peripherals */ 847 nc->disabled_modules = 0x00000000; 848 nc->num_cpus = 2; 849 } 850 851 static const TypeInfo npcm7xx_soc_types[] = { 852 { 853 .name = TYPE_NPCM7XX, 854 .parent = TYPE_DEVICE, 855 .instance_size = sizeof(NPCM7xxState), 856 .instance_init = npcm7xx_init, 857 .class_size = sizeof(NPCM7xxClass), 858 .class_init = npcm7xx_class_init, 859 .abstract = true, 860 }, { 861 .name = TYPE_NPCM730, 862 .parent = TYPE_NPCM7XX, 863 .class_init = npcm730_class_init, 864 }, { 865 .name = TYPE_NPCM750, 866 .parent = TYPE_NPCM7XX, 867 .class_init = npcm750_class_init, 868 }, 869 }; 870 871 DEFINE_TYPES(npcm7xx_soc_types); 872