1 /* 2 * Arm MPS3 board emulation for Cortex-R-based FPGA images. 3 * (For M-profile images see mps2.c and mps2tz.c.) 4 * 5 * Copyright (c) 2017 Linaro Limited 6 * Written by Peter Maydell 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 or 10 * (at your option) any later version. 11 */ 12 13 /* 14 * The MPS3 is an FPGA based dev board. This file handles FPGA images 15 * which use the Cortex-R CPUs. We model these separately from the 16 * M-profile images, because on M-profile the FPGA image is based on 17 * a "Subsystem for Embedded" which is similar to an SoC, whereas 18 * the R-profile FPGA images don't have that abstraction layer. 19 * 20 * We model the following FPGA images here: 21 * "mps3-an536" -- dual Cortex-R52 as documented in Arm Application Note AN536 22 * 23 * Application Note AN536: 24 * https://developer.arm.com/documentation/dai0536/latest/ 25 */ 26 27 #include "qemu/osdep.h" 28 #include "qemu/units.h" 29 #include "qapi/error.h" 30 #include "qapi/qmp/qlist.h" 31 #include "exec/address-spaces.h" 32 #include "cpu.h" 33 #include "sysemu/sysemu.h" 34 #include "hw/boards.h" 35 #include "hw/or-irq.h" 36 #include "hw/qdev-clock.h" 37 #include "hw/qdev-properties.h" 38 #include "hw/arm/boot.h" 39 #include "hw/arm/bsa.h" 40 #include "hw/char/cmsdk-apb-uart.h" 41 #include "hw/i2c/arm_sbcon_i2c.h" 42 #include "hw/intc/arm_gicv3.h" 43 #include "hw/misc/unimp.h" 44 #include "hw/timer/cmsdk-apb-dualtimer.h" 45 #include "hw/watchdog/cmsdk-apb-watchdog.h" 46 47 /* Define the layout of RAM and ROM in a board */ 48 typedef struct RAMInfo { 49 const char *name; 50 hwaddr base; 51 hwaddr size; 52 int mrindex; /* index into rams[]; -1 for the system RAM block */ 53 int flags; 54 } RAMInfo; 55 56 /* 57 * The MPS3 DDR is 3GiB, but on a 32-bit host QEMU doesn't permit 58 * emulation of that much guest RAM, so artificially make it smaller. 59 */ 60 #if HOST_LONG_BITS == 32 61 #define MPS3_DDR_SIZE (1 * GiB) 62 #else 63 #define MPS3_DDR_SIZE (3 * GiB) 64 #endif 65 66 /* 67 * Flag values: 68 * IS_MAIN: this is the main machine RAM 69 * IS_ROM: this area is read-only 70 */ 71 #define IS_MAIN 1 72 #define IS_ROM 2 73 74 #define MPS3R_RAM_MAX 9 75 #define MPS3R_CPU_MAX 2 76 #define MPS3R_UART_MAX 4 /* shared UART count */ 77 78 #define PERIPHBASE 0xf0000000 79 #define NUM_SPIS 96 80 81 typedef enum MPS3RFPGAType { 82 FPGA_AN536, 83 } MPS3RFPGAType; 84 85 struct MPS3RMachineClass { 86 MachineClass parent; 87 MPS3RFPGAType fpga_type; 88 const RAMInfo *raminfo; 89 hwaddr loader_start; 90 }; 91 92 struct MPS3RMachineState { 93 MachineState parent; 94 struct arm_boot_info bootinfo; 95 MemoryRegion ram[MPS3R_RAM_MAX]; 96 Object *cpu[MPS3R_CPU_MAX]; 97 MemoryRegion cpu_sysmem[MPS3R_CPU_MAX]; 98 MemoryRegion sysmem_alias[MPS3R_CPU_MAX]; 99 MemoryRegion cpu_ram[MPS3R_CPU_MAX]; 100 GICv3State gic; 101 /* per-CPU UARTs followed by the shared UARTs */ 102 CMSDKAPBUART uart[MPS3R_CPU_MAX + MPS3R_UART_MAX]; 103 OrIRQState cpu_uart_oflow[MPS3R_CPU_MAX]; 104 OrIRQState uart_oflow; 105 CMSDKAPBWatchdog watchdog; 106 CMSDKAPBDualTimer dualtimer; 107 ArmSbconI2CState i2c[5]; 108 Clock *clk; 109 }; 110 111 #define TYPE_MPS3R_MACHINE "mps3r" 112 #define TYPE_MPS3R_AN536_MACHINE MACHINE_TYPE_NAME("mps3-an536") 113 114 OBJECT_DECLARE_TYPE(MPS3RMachineState, MPS3RMachineClass, MPS3R_MACHINE) 115 116 /* 117 * Main clock frequency CLK in Hz (50MHz). In the image there are also 118 * ACLK, MCLK, GPUCLK and PERIPHCLK at the same frequency; for our 119 * model we just roll them all into one. 120 */ 121 #define CLK_FRQ 50000000 122 123 static const RAMInfo an536_raminfo[] = { 124 { 125 .name = "ATCM", 126 .base = 0x00000000, 127 .size = 0x00008000, 128 .mrindex = 0, 129 }, { 130 /* We model the QSPI flash as simple ROM for now */ 131 .name = "QSPI", 132 .base = 0x08000000, 133 .size = 0x00800000, 134 .flags = IS_ROM, 135 .mrindex = 1, 136 }, { 137 .name = "BRAM", 138 .base = 0x10000000, 139 .size = 0x00080000, 140 .mrindex = 2, 141 }, { 142 .name = "DDR", 143 .base = 0x20000000, 144 .size = MPS3_DDR_SIZE, 145 .mrindex = -1, 146 }, { 147 .name = "ATCM0", 148 .base = 0xee000000, 149 .size = 0x00008000, 150 .mrindex = 3, 151 }, { 152 .name = "BTCM0", 153 .base = 0xee100000, 154 .size = 0x00008000, 155 .mrindex = 4, 156 }, { 157 .name = "CTCM0", 158 .base = 0xee200000, 159 .size = 0x00008000, 160 .mrindex = 5, 161 }, { 162 .name = "ATCM1", 163 .base = 0xee400000, 164 .size = 0x00008000, 165 .mrindex = 6, 166 }, { 167 .name = "BTCM1", 168 .base = 0xee500000, 169 .size = 0x00008000, 170 .mrindex = 7, 171 }, { 172 .name = "CTCM1", 173 .base = 0xee600000, 174 .size = 0x00008000, 175 .mrindex = 8, 176 }, { 177 .name = NULL, 178 } 179 }; 180 181 static MemoryRegion *mr_for_raminfo(MPS3RMachineState *mms, 182 const RAMInfo *raminfo) 183 { 184 /* Return an initialized MemoryRegion for the RAMInfo. */ 185 MemoryRegion *ram; 186 187 if (raminfo->mrindex < 0) { 188 /* Means this RAMInfo is for QEMU's "system memory" */ 189 MachineState *machine = MACHINE(mms); 190 assert(!(raminfo->flags & IS_ROM)); 191 return machine->ram; 192 } 193 194 assert(raminfo->mrindex < MPS3R_RAM_MAX); 195 ram = &mms->ram[raminfo->mrindex]; 196 197 memory_region_init_ram(ram, NULL, raminfo->name, 198 raminfo->size, &error_fatal); 199 if (raminfo->flags & IS_ROM) { 200 memory_region_set_readonly(ram, true); 201 } 202 return ram; 203 } 204 205 /* 206 * There is no defined secondary boot protocol for Linux for the AN536, 207 * because real hardware has a restriction that atomic operations between 208 * the two CPUs do not function correctly, and so true SMP is not 209 * possible. Therefore for cases where the user is directly booting 210 * a kernel, we treat the system as essentially uniprocessor, and 211 * put the secondary CPU into power-off state (as if the user on the 212 * real hardware had configured the secondary to be halted via the 213 * SCC config registers). 214 * 215 * Note that the default secondary boot code would not work here anyway 216 * as it assumes a GICv2, and we have a GICv3. 217 */ 218 static void mps3r_write_secondary_boot(ARMCPU *cpu, 219 const struct arm_boot_info *info) 220 { 221 /* 222 * Power the secondary CPU off. This means we don't need to write any 223 * boot code into guest memory. Note that the 'cpu' argument to this 224 * function is the primary CPU we passed to arm_load_kernel(), not 225 * the secondary. Loop around all the other CPUs, as the boot.c 226 * code does for the "disable secondaries if PSCI is enabled" case. 227 */ 228 for (CPUState *cs = first_cpu; cs; cs = CPU_NEXT(cs)) { 229 if (cs != first_cpu) { 230 object_property_set_bool(OBJECT(cs), "start-powered-off", true, 231 &error_abort); 232 } 233 } 234 } 235 236 static void mps3r_secondary_cpu_reset(ARMCPU *cpu, 237 const struct arm_boot_info *info) 238 { 239 /* We don't need to do anything here because the CPU will be off */ 240 } 241 242 static void create_gic(MPS3RMachineState *mms, MemoryRegion *sysmem) 243 { 244 MachineState *machine = MACHINE(mms); 245 DeviceState *gicdev; 246 QList *redist_region_count; 247 248 object_initialize_child(OBJECT(mms), "gic", &mms->gic, TYPE_ARM_GICV3); 249 gicdev = DEVICE(&mms->gic); 250 qdev_prop_set_uint32(gicdev, "num-cpu", machine->smp.cpus); 251 qdev_prop_set_uint32(gicdev, "num-irq", NUM_SPIS + GIC_INTERNAL); 252 redist_region_count = qlist_new(); 253 qlist_append_int(redist_region_count, machine->smp.cpus); 254 qdev_prop_set_array(gicdev, "redist-region-count", redist_region_count); 255 object_property_set_link(OBJECT(&mms->gic), "sysmem", 256 OBJECT(sysmem), &error_fatal); 257 sysbus_realize(SYS_BUS_DEVICE(&mms->gic), &error_fatal); 258 sysbus_mmio_map(SYS_BUS_DEVICE(&mms->gic), 0, PERIPHBASE); 259 sysbus_mmio_map(SYS_BUS_DEVICE(&mms->gic), 1, PERIPHBASE + 0x100000); 260 /* 261 * Wire the outputs from each CPU's generic timer and the GICv3 262 * maintenance interrupt signal to the appropriate GIC PPI inputs, 263 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. 264 */ 265 for (int i = 0; i < machine->smp.cpus; i++) { 266 DeviceState *cpudev = DEVICE(mms->cpu[i]); 267 SysBusDevice *gicsbd = SYS_BUS_DEVICE(&mms->gic); 268 int intidbase = NUM_SPIS + i * GIC_INTERNAL; 269 int irq; 270 /* 271 * Mapping from the output timer irq lines from the CPU to the 272 * GIC PPI inputs used for this board. This isn't a BSA board, 273 * but it uses the standard convention for the PPI numbers. 274 */ 275 const int timer_irq[] = { 276 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 277 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 278 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 279 }; 280 281 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { 282 qdev_connect_gpio_out(cpudev, irq, 283 qdev_get_gpio_in(gicdev, 284 intidbase + timer_irq[irq])); 285 } 286 287 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0, 288 qdev_get_gpio_in(gicdev, 289 intidbase + ARCH_GIC_MAINT_IRQ)); 290 291 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, 292 qdev_get_gpio_in(gicdev, 293 intidbase + VIRTUAL_PMU_IRQ)); 294 295 sysbus_connect_irq(gicsbd, i, 296 qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 297 sysbus_connect_irq(gicsbd, i + machine->smp.cpus, 298 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 299 sysbus_connect_irq(gicsbd, i + 2 * machine->smp.cpus, 300 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 301 sysbus_connect_irq(gicsbd, i + 3 * machine->smp.cpus, 302 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 303 } 304 } 305 306 /* 307 * Create UART uartno, and map it into the MemoryRegion mem at address baseaddr. 308 * The qemu_irq arguments are where we connect the various IRQs from the UART. 309 */ 310 static void create_uart(MPS3RMachineState *mms, int uartno, MemoryRegion *mem, 311 hwaddr baseaddr, qemu_irq txirq, qemu_irq rxirq, 312 qemu_irq txoverirq, qemu_irq rxoverirq, 313 qemu_irq combirq) 314 { 315 g_autofree char *s = g_strdup_printf("uart%d", uartno); 316 SysBusDevice *sbd; 317 318 assert(uartno < ARRAY_SIZE(mms->uart)); 319 object_initialize_child(OBJECT(mms), s, &mms->uart[uartno], 320 TYPE_CMSDK_APB_UART); 321 qdev_prop_set_uint32(DEVICE(&mms->uart[uartno]), "pclk-frq", CLK_FRQ); 322 qdev_prop_set_chr(DEVICE(&mms->uart[uartno]), "chardev", serial_hd(uartno)); 323 sbd = SYS_BUS_DEVICE(&mms->uart[uartno]); 324 sysbus_realize(sbd, &error_fatal); 325 memory_region_add_subregion(mem, baseaddr, 326 sysbus_mmio_get_region(sbd, 0)); 327 sysbus_connect_irq(sbd, 0, txirq); 328 sysbus_connect_irq(sbd, 1, rxirq); 329 sysbus_connect_irq(sbd, 2, txoverirq); 330 sysbus_connect_irq(sbd, 3, rxoverirq); 331 sysbus_connect_irq(sbd, 4, combirq); 332 } 333 334 static void mps3r_common_init(MachineState *machine) 335 { 336 MPS3RMachineState *mms = MPS3R_MACHINE(machine); 337 MPS3RMachineClass *mmc = MPS3R_MACHINE_GET_CLASS(mms); 338 MemoryRegion *sysmem = get_system_memory(); 339 DeviceState *gicdev; 340 341 mms->clk = clock_new(OBJECT(machine), "CLK"); 342 clock_set_hz(mms->clk, CLK_FRQ); 343 344 for (const RAMInfo *ri = mmc->raminfo; ri->name; ri++) { 345 MemoryRegion *mr = mr_for_raminfo(mms, ri); 346 memory_region_add_subregion(sysmem, ri->base, mr); 347 } 348 349 assert(machine->smp.cpus <= MPS3R_CPU_MAX); 350 for (int i = 0; i < machine->smp.cpus; i++) { 351 g_autofree char *sysmem_name = g_strdup_printf("cpu-%d-memory", i); 352 g_autofree char *ramname = g_strdup_printf("cpu-%d-memory", i); 353 g_autofree char *alias_name = g_strdup_printf("sysmem-alias-%d", i); 354 355 /* 356 * Each CPU has some private RAM/peripherals, so create the container 357 * which will house those, with the whole-machine system memory being 358 * used where there's no CPU-specific device. Note that we need the 359 * sysmem_alias aliases because we can't put one MR (the original 360 * 'sysmem') into more than one other MR. 361 */ 362 memory_region_init(&mms->cpu_sysmem[i], OBJECT(machine), 363 sysmem_name, UINT64_MAX); 364 memory_region_init_alias(&mms->sysmem_alias[i], OBJECT(machine), 365 alias_name, sysmem, 0, UINT64_MAX); 366 memory_region_add_subregion_overlap(&mms->cpu_sysmem[i], 0, 367 &mms->sysmem_alias[i], -1); 368 369 mms->cpu[i] = object_new(machine->cpu_type); 370 object_property_set_link(mms->cpu[i], "memory", 371 OBJECT(&mms->cpu_sysmem[i]), &error_abort); 372 object_property_set_int(mms->cpu[i], "reset-cbar", 373 PERIPHBASE, &error_abort); 374 qdev_realize(DEVICE(mms->cpu[i]), NULL, &error_fatal); 375 object_unref(mms->cpu[i]); 376 377 /* Per-CPU RAM */ 378 memory_region_init_ram(&mms->cpu_ram[i], NULL, ramname, 379 0x1000, &error_fatal); 380 memory_region_add_subregion(&mms->cpu_sysmem[i], 0xe7c01000, 381 &mms->cpu_ram[i]); 382 } 383 384 create_gic(mms, sysmem); 385 gicdev = DEVICE(&mms->gic); 386 387 /* 388 * UARTs 0 and 1 are per-CPU; their interrupts are wired to 389 * the relevant CPU's PPI 0..3, aka INTID 16..19 390 */ 391 for (int i = 0; i < machine->smp.cpus; i++) { 392 int intidbase = NUM_SPIS + i * GIC_INTERNAL; 393 g_autofree char *s = g_strdup_printf("cpu-uart-oflow-orgate%d", i); 394 DeviceState *orgate; 395 396 /* The two overflow IRQs from the UART are ORed together into PPI 3 */ 397 object_initialize_child(OBJECT(mms), s, &mms->cpu_uart_oflow[i], 398 TYPE_OR_IRQ); 399 orgate = DEVICE(&mms->cpu_uart_oflow[i]); 400 qdev_prop_set_uint32(orgate, "num-lines", 2); 401 qdev_realize(orgate, NULL, &error_fatal); 402 qdev_connect_gpio_out(orgate, 0, 403 qdev_get_gpio_in(gicdev, intidbase + 19)); 404 405 create_uart(mms, i, &mms->cpu_sysmem[i], 0xe7c00000, 406 qdev_get_gpio_in(gicdev, intidbase + 17), /* tx */ 407 qdev_get_gpio_in(gicdev, intidbase + 16), /* rx */ 408 qdev_get_gpio_in(orgate, 0), /* txover */ 409 qdev_get_gpio_in(orgate, 1), /* rxover */ 410 qdev_get_gpio_in(gicdev, intidbase + 18) /* combined */); 411 } 412 /* 413 * UARTs 2 to 5 are whole-system; all overflow IRQs are ORed 414 * together into IRQ 17 415 */ 416 object_initialize_child(OBJECT(mms), "uart-oflow-orgate", 417 &mms->uart_oflow, TYPE_OR_IRQ); 418 qdev_prop_set_uint32(DEVICE(&mms->uart_oflow), "num-lines", 419 MPS3R_UART_MAX * 2); 420 qdev_realize(DEVICE(&mms->uart_oflow), NULL, &error_fatal); 421 qdev_connect_gpio_out(DEVICE(&mms->uart_oflow), 0, 422 qdev_get_gpio_in(gicdev, 17)); 423 424 for (int i = 0; i < MPS3R_UART_MAX; i++) { 425 hwaddr baseaddr = 0xe0205000 + i * 0x1000; 426 int rxirq = 5 + i * 2, txirq = 6 + i * 2, combirq = 13 + i; 427 428 create_uart(mms, i + MPS3R_CPU_MAX, sysmem, baseaddr, 429 qdev_get_gpio_in(gicdev, txirq), 430 qdev_get_gpio_in(gicdev, rxirq), 431 qdev_get_gpio_in(DEVICE(&mms->uart_oflow), i * 2), 432 qdev_get_gpio_in(DEVICE(&mms->uart_oflow), i * 2 + 1), 433 qdev_get_gpio_in(gicdev, combirq)); 434 } 435 436 for (int i = 0; i < 4; i++) { 437 /* CMSDK GPIO controllers */ 438 g_autofree char *s = g_strdup_printf("gpio%d", i); 439 create_unimplemented_device(s, 0xe0000000 + i * 0x1000, 0x1000); 440 } 441 442 object_initialize_child(OBJECT(mms), "watchdog", &mms->watchdog, 443 TYPE_CMSDK_APB_WATCHDOG); 444 qdev_connect_clock_in(DEVICE(&mms->watchdog), "WDOGCLK", mms->clk); 445 sysbus_realize(SYS_BUS_DEVICE(&mms->watchdog), &error_fatal); 446 sysbus_connect_irq(SYS_BUS_DEVICE(&mms->watchdog), 0, 447 qdev_get_gpio_in(gicdev, 0)); 448 sysbus_mmio_map(SYS_BUS_DEVICE(&mms->watchdog), 0, 0xe0100000); 449 450 object_initialize_child(OBJECT(mms), "dualtimer", &mms->dualtimer, 451 TYPE_CMSDK_APB_DUALTIMER); 452 qdev_connect_clock_in(DEVICE(&mms->dualtimer), "TIMCLK", mms->clk); 453 sysbus_realize(SYS_BUS_DEVICE(&mms->dualtimer), &error_fatal); 454 sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 0, 455 qdev_get_gpio_in(gicdev, 3)); 456 sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 1, 457 qdev_get_gpio_in(gicdev, 1)); 458 sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 2, 459 qdev_get_gpio_in(gicdev, 2)); 460 sysbus_mmio_map(SYS_BUS_DEVICE(&mms->dualtimer), 0, 0xe0101000); 461 462 for (int i = 0; i < ARRAY_SIZE(mms->i2c); i++) { 463 static const hwaddr i2cbase[] = {0xe0102000, /* Touch */ 464 0xe0103000, /* Audio */ 465 0xe0107000, /* Shield0 */ 466 0xe0108000, /* Shield1 */ 467 0xe0109000}; /* DDR4 EEPROM */ 468 g_autofree char *s = g_strdup_printf("i2c%d", i); 469 470 object_initialize_child(OBJECT(mms), s, &mms->i2c[i], 471 TYPE_ARM_SBCON_I2C); 472 sysbus_realize(SYS_BUS_DEVICE(&mms->i2c[i]), &error_fatal); 473 sysbus_mmio_map(SYS_BUS_DEVICE(&mms->i2c[i]), 0, i2cbase[i]); 474 if (i != 2 && i != 3) { 475 /* 476 * internal-only bus: mark it full to avoid user-created 477 * i2c devices being plugged into it. 478 */ 479 qbus_mark_full(qdev_get_child_bus(DEVICE(&mms->i2c[i]), "i2c")); 480 } 481 } 482 483 mms->bootinfo.ram_size = machine->ram_size; 484 mms->bootinfo.board_id = -1; 485 mms->bootinfo.loader_start = mmc->loader_start; 486 mms->bootinfo.write_secondary_boot = mps3r_write_secondary_boot; 487 mms->bootinfo.secondary_cpu_reset_hook = mps3r_secondary_cpu_reset; 488 arm_load_kernel(ARM_CPU(mms->cpu[0]), machine, &mms->bootinfo); 489 } 490 491 static void mps3r_set_default_ram_info(MPS3RMachineClass *mmc) 492 { 493 /* 494 * Set mc->default_ram_size and default_ram_id from the 495 * information in mmc->raminfo. 496 */ 497 MachineClass *mc = MACHINE_CLASS(mmc); 498 const RAMInfo *p; 499 500 for (p = mmc->raminfo; p->name; p++) { 501 if (p->mrindex < 0) { 502 /* Found the entry for "system memory" */ 503 mc->default_ram_size = p->size; 504 mc->default_ram_id = p->name; 505 mmc->loader_start = p->base; 506 return; 507 } 508 } 509 g_assert_not_reached(); 510 } 511 512 static void mps3r_class_init(ObjectClass *oc, void *data) 513 { 514 MachineClass *mc = MACHINE_CLASS(oc); 515 516 mc->init = mps3r_common_init; 517 } 518 519 static void mps3r_an536_class_init(ObjectClass *oc, void *data) 520 { 521 MachineClass *mc = MACHINE_CLASS(oc); 522 MPS3RMachineClass *mmc = MPS3R_MACHINE_CLASS(oc); 523 static const char * const valid_cpu_types[] = { 524 ARM_CPU_TYPE_NAME("cortex-r52"), 525 NULL 526 }; 527 528 mc->desc = "ARM MPS3 with AN536 FPGA image for Cortex-R52"; 529 /* 530 * In the real FPGA image there are always two cores, but the standard 531 * initial setting for the SCC SYSCON 0x000 register is 0x21, meaning 532 * that the second core is held in reset and halted. Many images built for 533 * the board do not expect the second core to run at startup (especially 534 * since on the real FPGA image it is not possible to use LDREX/STREX 535 * in RAM between the two cores, so a true SMP setup isn't supported). 536 * 537 * As QEMU's equivalent of this, we support both -smp 1 and -smp 2, 538 * with the default being -smp 1. This seems a more intuitive UI for 539 * QEMU users than, for instance, having a machine property to allow 540 * the user to set the initial value of the SYSCON 0x000 register. 541 */ 542 mc->default_cpus = 1; 543 mc->min_cpus = 1; 544 mc->max_cpus = 2; 545 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-r52"); 546 mc->valid_cpu_types = valid_cpu_types; 547 mmc->raminfo = an536_raminfo; 548 mps3r_set_default_ram_info(mmc); 549 } 550 551 static const TypeInfo mps3r_machine_types[] = { 552 { 553 .name = TYPE_MPS3R_MACHINE, 554 .parent = TYPE_MACHINE, 555 .abstract = true, 556 .instance_size = sizeof(MPS3RMachineState), 557 .class_size = sizeof(MPS3RMachineClass), 558 .class_init = mps3r_class_init, 559 }, { 560 .name = TYPE_MPS3R_AN536_MACHINE, 561 .parent = TYPE_MPS3R_MACHINE, 562 .class_init = mps3r_an536_class_init, 563 }, 564 }; 565 566 DEFINE_TYPES(mps3r_machine_types); 567