1 /* 2 * ARM V2M MPS2 board emulation, trustzone aware FPGA images 3 * 4 * Copyright (c) 2017 Linaro Limited 5 * Written by Peter Maydell 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 or 9 * (at your option) any later version. 10 */ 11 12 /* The MPS2 and MPS2+ dev boards are FPGA based (the 2+ has a bigger 13 * FPGA but is otherwise the same as the 2). Since the CPU itself 14 * and most of the devices are in the FPGA, the details of the board 15 * as seen by the guest depend significantly on the FPGA image. 16 * This source file covers the following FPGA images, for TrustZone cores: 17 * "mps2-an505" -- Cortex-M33 as documented in ARM Application Note AN505 18 * "mps2-an521" -- Dual Cortex-M33 as documented in Application Note AN521 19 * "mps2-an524" -- Dual Cortex-M33 as documented in Application Note AN524 20 * "mps2-an547" -- Single Cortex-M55 as documented in Application Note AN547 21 * 22 * Links to the TRM for the board itself and to the various Application 23 * Notes which document the FPGA images can be found here: 24 * https://developer.arm.com/products/system-design/development-boards/fpga-prototyping-boards/mps2 25 * 26 * Board TRM: 27 * https://developer.arm.com/documentation/100112/latest/ 28 * Application Note AN505: 29 * https://developer.arm.com/documentation/dai0505/latest/ 30 * Application Note AN521: 31 * https://developer.arm.com/documentation/dai0521/latest/ 32 * Application Note AN524: 33 * https://developer.arm.com/documentation/dai0524/latest/ 34 * Application Note AN547: 35 * https://developer.arm.com/-/media/Arm%20Developer%20Community/PDF/DAI0547B_SSE300_PLUS_U55_FPGA_for_mps3.pdf 36 * 37 * The AN505 defers to the Cortex-M33 processor ARMv8M IoT Kit FVP User Guide 38 * (ARM ECM0601256) for the details of some of the device layout: 39 * https://developer.arm.com/documentation/ecm0601256/latest 40 * Similarly, the AN521 and AN524 use the SSE-200, and the SSE-200 TRM defines 41 * most of the device layout: 42 * https://developer.arm.com/documentation/101104/latest/ 43 * and the AN547 uses the SSE-300, whose layout is in the SSE-300 TRM: 44 * https://developer.arm.com/documentation/101773/latest/ 45 */ 46 47 #include "qemu/osdep.h" 48 #include "qemu/units.h" 49 #include "qemu/cutils.h" 50 #include "qapi/error.h" 51 #include "qemu/error-report.h" 52 #include "hw/arm/boot.h" 53 #include "hw/arm/armv7m.h" 54 #include "hw/or-irq.h" 55 #include "hw/boards.h" 56 #include "exec/address-spaces.h" 57 #include "sysemu/sysemu.h" 58 #include "sysemu/reset.h" 59 #include "hw/misc/unimp.h" 60 #include "hw/char/cmsdk-apb-uart.h" 61 #include "hw/timer/cmsdk-apb-timer.h" 62 #include "hw/misc/mps2-scc.h" 63 #include "hw/misc/mps2-fpgaio.h" 64 #include "hw/misc/tz-mpc.h" 65 #include "hw/misc/tz-msc.h" 66 #include "hw/arm/armsse.h" 67 #include "hw/dma/pl080.h" 68 #include "hw/rtc/pl031.h" 69 #include "hw/ssi/pl022.h" 70 #include "hw/i2c/arm_sbcon_i2c.h" 71 #include "hw/net/lan9118.h" 72 #include "net/net.h" 73 #include "hw/core/split-irq.h" 74 #include "hw/qdev-clock.h" 75 #include "qom/object.h" 76 #include "hw/irq.h" 77 78 #define MPS2TZ_NUMIRQ_MAX 96 79 #define MPS2TZ_RAM_MAX 5 80 81 typedef enum MPS2TZFPGAType { 82 FPGA_AN505, 83 FPGA_AN521, 84 FPGA_AN524, 85 FPGA_AN547, 86 } MPS2TZFPGAType; 87 88 /* 89 * Define the layout of RAM in a board, including which parts are 90 * behind which MPCs. 91 * mrindex specifies the index into mms->ram[] to use for the backing RAM; 92 * -1 means "use the system RAM". 93 */ 94 typedef struct RAMInfo { 95 const char *name; 96 uint32_t base; 97 uint32_t size; 98 int mpc; /* MPC number, -1 for "not behind an MPC" */ 99 int mrindex; 100 int flags; 101 } RAMInfo; 102 103 /* 104 * Flag values: 105 * IS_ALIAS: this RAM area is an alias to the upstream end of the 106 * MPC specified by its .mpc value 107 * IS_ROM: this RAM area is read-only 108 */ 109 #define IS_ALIAS 1 110 #define IS_ROM 2 111 112 struct MPS2TZMachineClass { 113 MachineClass parent; 114 MPS2TZFPGAType fpga_type; 115 uint32_t scc_id; 116 uint32_t sysclk_frq; /* Main SYSCLK frequency in Hz */ 117 uint32_t apb_periph_frq; /* APB peripheral frequency in Hz */ 118 uint32_t len_oscclk; 119 const uint32_t *oscclk; 120 uint32_t fpgaio_num_leds; /* Number of LEDs in FPGAIO LED0 register */ 121 bool fpgaio_has_switches; /* Does FPGAIO have SWITCH register? */ 122 bool fpgaio_has_dbgctrl; /* Does FPGAIO have DBGCTRL register? */ 123 int numirq; /* Number of external interrupts */ 124 int uart_overflow_irq; /* number of the combined UART overflow IRQ */ 125 uint32_t init_svtor; /* init-svtor setting for SSE */ 126 const RAMInfo *raminfo; 127 const char *armsse_type; 128 }; 129 130 struct MPS2TZMachineState { 131 MachineState parent; 132 133 ARMSSE iotkit; 134 MemoryRegion ram[MPS2TZ_RAM_MAX]; 135 MemoryRegion eth_usb_container; 136 137 MPS2SCC scc; 138 MPS2FPGAIO fpgaio; 139 TZPPC ppc[5]; 140 TZMPC mpc[3]; 141 PL022State spi[5]; 142 ArmSbconI2CState i2c[5]; 143 UnimplementedDeviceState i2s_audio; 144 UnimplementedDeviceState gpio[4]; 145 UnimplementedDeviceState gfx; 146 UnimplementedDeviceState cldc; 147 UnimplementedDeviceState usb; 148 PL031State rtc; 149 PL080State dma[4]; 150 TZMSC msc[4]; 151 CMSDKAPBUART uart[6]; 152 SplitIRQ sec_resp_splitter; 153 qemu_or_irq uart_irq_orgate; 154 DeviceState *lan9118; 155 SplitIRQ cpu_irq_splitter[MPS2TZ_NUMIRQ_MAX]; 156 Clock *sysclk; 157 Clock *s32kclk; 158 159 bool remap; 160 qemu_irq remap_irq; 161 }; 162 163 #define TYPE_MPS2TZ_MACHINE "mps2tz" 164 #define TYPE_MPS2TZ_AN505_MACHINE MACHINE_TYPE_NAME("mps2-an505") 165 #define TYPE_MPS2TZ_AN521_MACHINE MACHINE_TYPE_NAME("mps2-an521") 166 #define TYPE_MPS3TZ_AN524_MACHINE MACHINE_TYPE_NAME("mps3-an524") 167 #define TYPE_MPS3TZ_AN547_MACHINE MACHINE_TYPE_NAME("mps3-an547") 168 169 OBJECT_DECLARE_TYPE(MPS2TZMachineState, MPS2TZMachineClass, MPS2TZ_MACHINE) 170 171 /* Slow 32Khz S32KCLK frequency in Hz */ 172 #define S32KCLK_FRQ (32 * 1000) 173 174 /* 175 * The MPS3 DDR is 2GiB, but on a 32-bit host QEMU doesn't permit 176 * emulation of that much guest RAM, so artificially make it smaller. 177 */ 178 #if HOST_LONG_BITS == 32 179 #define MPS3_DDR_SIZE (1 * GiB) 180 #else 181 #define MPS3_DDR_SIZE (2 * GiB) 182 #endif 183 184 static const uint32_t an505_oscclk[] = { 185 40000000, 186 24580000, 187 25000000, 188 }; 189 190 static const uint32_t an524_oscclk[] = { 191 24000000, 192 32000000, 193 50000000, 194 50000000, 195 24576000, 196 23750000, 197 }; 198 199 static const RAMInfo an505_raminfo[] = { { 200 .name = "ssram-0", 201 .base = 0x00000000, 202 .size = 0x00400000, 203 .mpc = 0, 204 .mrindex = 0, 205 }, { 206 .name = "ssram-1", 207 .base = 0x28000000, 208 .size = 0x00200000, 209 .mpc = 1, 210 .mrindex = 1, 211 }, { 212 .name = "ssram-2", 213 .base = 0x28200000, 214 .size = 0x00200000, 215 .mpc = 2, 216 .mrindex = 2, 217 }, { 218 .name = "ssram-0-alias", 219 .base = 0x00400000, 220 .size = 0x00400000, 221 .mpc = 0, 222 .mrindex = 3, 223 .flags = IS_ALIAS, 224 }, { 225 /* Use the largest bit of contiguous RAM as our "system memory" */ 226 .name = "mps.ram", 227 .base = 0x80000000, 228 .size = 16 * MiB, 229 .mpc = -1, 230 .mrindex = -1, 231 }, { 232 .name = NULL, 233 }, 234 }; 235 236 /* 237 * Note that the addresses and MPC numbering here should match up 238 * with those used in remap_memory(), which can swap the BRAM and QSPI. 239 */ 240 static const RAMInfo an524_raminfo[] = { { 241 .name = "bram", 242 .base = 0x00000000, 243 .size = 512 * KiB, 244 .mpc = 0, 245 .mrindex = 0, 246 }, { 247 /* We don't model QSPI flash yet; for now expose it as simple ROM */ 248 .name = "QSPI", 249 .base = 0x28000000, 250 .size = 8 * MiB, 251 .mpc = 1, 252 .mrindex = 1, 253 .flags = IS_ROM, 254 }, { 255 .name = "DDR", 256 .base = 0x60000000, 257 .size = MPS3_DDR_SIZE, 258 .mpc = 2, 259 .mrindex = -1, 260 }, { 261 .name = NULL, 262 }, 263 }; 264 265 static const RAMInfo an547_raminfo[] = { { 266 .name = "itcm", 267 .base = 0x00000000, 268 .size = 512 * KiB, 269 .mpc = -1, 270 .mrindex = 0, 271 }, { 272 .name = "sram", 273 .base = 0x01000000, 274 .size = 2 * MiB, 275 .mpc = 0, 276 .mrindex = 1, 277 }, { 278 .name = "dtcm", 279 .base = 0x20000000, 280 .size = 4 * 128 * KiB, 281 .mpc = -1, 282 .mrindex = 2, 283 }, { 284 .name = "sram 2", 285 .base = 0x21000000, 286 .size = 4 * MiB, 287 .mpc = -1, 288 .mrindex = 3, 289 }, { 290 /* We don't model QSPI flash yet; for now expose it as simple ROM */ 291 .name = "QSPI", 292 .base = 0x28000000, 293 .size = 8 * MiB, 294 .mpc = 1, 295 .mrindex = 4, 296 .flags = IS_ROM, 297 }, { 298 .name = "DDR", 299 .base = 0x60000000, 300 .size = MPS3_DDR_SIZE, 301 .mpc = 2, 302 .mrindex = -1, 303 }, { 304 .name = NULL, 305 }, 306 }; 307 308 static const RAMInfo *find_raminfo_for_mpc(MPS2TZMachineState *mms, int mpc) 309 { 310 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); 311 const RAMInfo *p; 312 const RAMInfo *found = NULL; 313 314 for (p = mmc->raminfo; p->name; p++) { 315 if (p->mpc == mpc && !(p->flags & IS_ALIAS)) { 316 /* There should only be one entry in the array for this MPC */ 317 g_assert(!found); 318 found = p; 319 } 320 } 321 /* if raminfo array doesn't have an entry for each MPC this is a bug */ 322 assert(found); 323 return found; 324 } 325 326 static MemoryRegion *mr_for_raminfo(MPS2TZMachineState *mms, 327 const RAMInfo *raminfo) 328 { 329 /* Return an initialized MemoryRegion for the RAMInfo. */ 330 MemoryRegion *ram; 331 332 if (raminfo->mrindex < 0) { 333 /* Means this RAMInfo is for QEMU's "system memory" */ 334 MachineState *machine = MACHINE(mms); 335 assert(!(raminfo->flags & IS_ROM)); 336 return machine->ram; 337 } 338 339 assert(raminfo->mrindex < MPS2TZ_RAM_MAX); 340 ram = &mms->ram[raminfo->mrindex]; 341 342 memory_region_init_ram(ram, NULL, raminfo->name, 343 raminfo->size, &error_fatal); 344 if (raminfo->flags & IS_ROM) { 345 memory_region_set_readonly(ram, true); 346 } 347 return ram; 348 } 349 350 /* Create an alias of an entire original MemoryRegion @orig 351 * located at @base in the memory map. 352 */ 353 static void make_ram_alias(MemoryRegion *mr, const char *name, 354 MemoryRegion *orig, hwaddr base) 355 { 356 memory_region_init_alias(mr, NULL, name, orig, 0, 357 memory_region_size(orig)); 358 memory_region_add_subregion(get_system_memory(), base, mr); 359 } 360 361 static qemu_irq get_sse_irq_in(MPS2TZMachineState *mms, int irqno) 362 { 363 /* 364 * Return a qemu_irq which will signal IRQ n to all CPUs in the 365 * SSE. The irqno should be as the CPU sees it, so the first 366 * external-to-the-SSE interrupt is 32. 367 */ 368 MachineClass *mc = MACHINE_GET_CLASS(mms); 369 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); 370 371 assert(irqno >= 32 && irqno < (mmc->numirq + 32)); 372 373 /* 374 * Convert from "CPU irq number" (as listed in the FPGA image 375 * documentation) to the SSE external-interrupt number. 376 */ 377 irqno -= 32; 378 379 if (mc->max_cpus > 1) { 380 return qdev_get_gpio_in(DEVICE(&mms->cpu_irq_splitter[irqno]), 0); 381 } else { 382 return qdev_get_gpio_in_named(DEVICE(&mms->iotkit), "EXP_IRQ", irqno); 383 } 384 } 385 386 /* Most of the devices in the AN505 FPGA image sit behind 387 * Peripheral Protection Controllers. These data structures 388 * define the layout of which devices sit behind which PPCs. 389 * The devfn for each port is a function which creates, configures 390 * and initializes the device, returning the MemoryRegion which 391 * needs to be plugged into the downstream end of the PPC port. 392 */ 393 typedef MemoryRegion *MakeDevFn(MPS2TZMachineState *mms, void *opaque, 394 const char *name, hwaddr size, 395 const int *irqs); 396 397 typedef struct PPCPortInfo { 398 const char *name; 399 MakeDevFn *devfn; 400 void *opaque; 401 hwaddr addr; 402 hwaddr size; 403 int irqs[3]; /* currently no device needs more IRQ lines than this */ 404 } PPCPortInfo; 405 406 typedef struct PPCInfo { 407 const char *name; 408 PPCPortInfo ports[TZ_NUM_PORTS]; 409 } PPCInfo; 410 411 static MemoryRegion *make_unimp_dev(MPS2TZMachineState *mms, 412 void *opaque, 413 const char *name, hwaddr size, 414 const int *irqs) 415 { 416 /* Initialize, configure and realize a TYPE_UNIMPLEMENTED_DEVICE, 417 * and return a pointer to its MemoryRegion. 418 */ 419 UnimplementedDeviceState *uds = opaque; 420 421 object_initialize_child(OBJECT(mms), name, uds, TYPE_UNIMPLEMENTED_DEVICE); 422 qdev_prop_set_string(DEVICE(uds), "name", name); 423 qdev_prop_set_uint64(DEVICE(uds), "size", size); 424 sysbus_realize(SYS_BUS_DEVICE(uds), &error_fatal); 425 return sysbus_mmio_get_region(SYS_BUS_DEVICE(uds), 0); 426 } 427 428 static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque, 429 const char *name, hwaddr size, 430 const int *irqs) 431 { 432 /* The irq[] array is tx, rx, combined, in that order */ 433 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); 434 CMSDKAPBUART *uart = opaque; 435 int i = uart - &mms->uart[0]; 436 SysBusDevice *s; 437 DeviceState *orgate_dev = DEVICE(&mms->uart_irq_orgate); 438 439 object_initialize_child(OBJECT(mms), name, uart, TYPE_CMSDK_APB_UART); 440 qdev_prop_set_chr(DEVICE(uart), "chardev", serial_hd(i)); 441 qdev_prop_set_uint32(DEVICE(uart), "pclk-frq", mmc->apb_periph_frq); 442 sysbus_realize(SYS_BUS_DEVICE(uart), &error_fatal); 443 s = SYS_BUS_DEVICE(uart); 444 sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0])); 445 sysbus_connect_irq(s, 1, get_sse_irq_in(mms, irqs[1])); 446 sysbus_connect_irq(s, 2, qdev_get_gpio_in(orgate_dev, i * 2)); 447 sysbus_connect_irq(s, 3, qdev_get_gpio_in(orgate_dev, i * 2 + 1)); 448 sysbus_connect_irq(s, 4, get_sse_irq_in(mms, irqs[2])); 449 return sysbus_mmio_get_region(SYS_BUS_DEVICE(uart), 0); 450 } 451 452 static MemoryRegion *make_scc(MPS2TZMachineState *mms, void *opaque, 453 const char *name, hwaddr size, 454 const int *irqs) 455 { 456 MPS2SCC *scc = opaque; 457 DeviceState *sccdev; 458 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); 459 uint32_t i; 460 461 object_initialize_child(OBJECT(mms), "scc", scc, TYPE_MPS2_SCC); 462 sccdev = DEVICE(scc); 463 qdev_prop_set_uint32(sccdev, "scc-cfg0", mms->remap ? 1 : 0); 464 qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2); 465 qdev_prop_set_uint32(sccdev, "scc-aid", 0x00200008); 466 qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id); 467 qdev_prop_set_uint32(sccdev, "len-oscclk", mmc->len_oscclk); 468 for (i = 0; i < mmc->len_oscclk; i++) { 469 g_autofree char *propname = g_strdup_printf("oscclk[%u]", i); 470 qdev_prop_set_uint32(sccdev, propname, mmc->oscclk[i]); 471 } 472 sysbus_realize(SYS_BUS_DEVICE(scc), &error_fatal); 473 return sysbus_mmio_get_region(SYS_BUS_DEVICE(sccdev), 0); 474 } 475 476 static MemoryRegion *make_fpgaio(MPS2TZMachineState *mms, void *opaque, 477 const char *name, hwaddr size, 478 const int *irqs) 479 { 480 MPS2FPGAIO *fpgaio = opaque; 481 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); 482 483 object_initialize_child(OBJECT(mms), "fpgaio", fpgaio, TYPE_MPS2_FPGAIO); 484 qdev_prop_set_uint32(DEVICE(fpgaio), "num-leds", mmc->fpgaio_num_leds); 485 qdev_prop_set_bit(DEVICE(fpgaio), "has-switches", mmc->fpgaio_has_switches); 486 qdev_prop_set_bit(DEVICE(fpgaio), "has-dbgctrl", mmc->fpgaio_has_dbgctrl); 487 sysbus_realize(SYS_BUS_DEVICE(fpgaio), &error_fatal); 488 return sysbus_mmio_get_region(SYS_BUS_DEVICE(fpgaio), 0); 489 } 490 491 static MemoryRegion *make_eth_dev(MPS2TZMachineState *mms, void *opaque, 492 const char *name, hwaddr size, 493 const int *irqs) 494 { 495 SysBusDevice *s; 496 NICInfo *nd = &nd_table[0]; 497 498 /* In hardware this is a LAN9220; the LAN9118 is software compatible 499 * except that it doesn't support the checksum-offload feature. 500 */ 501 qemu_check_nic_model(nd, "lan9118"); 502 mms->lan9118 = qdev_new(TYPE_LAN9118); 503 qdev_set_nic_properties(mms->lan9118, nd); 504 505 s = SYS_BUS_DEVICE(mms->lan9118); 506 sysbus_realize_and_unref(s, &error_fatal); 507 sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0])); 508 return sysbus_mmio_get_region(s, 0); 509 } 510 511 static MemoryRegion *make_eth_usb(MPS2TZMachineState *mms, void *opaque, 512 const char *name, hwaddr size, 513 const int *irqs) 514 { 515 /* 516 * The AN524 makes the ethernet and USB share a PPC port. 517 * irqs[] is the ethernet IRQ. 518 */ 519 SysBusDevice *s; 520 NICInfo *nd = &nd_table[0]; 521 522 memory_region_init(&mms->eth_usb_container, OBJECT(mms), 523 "mps2-tz-eth-usb-container", 0x200000); 524 525 /* 526 * In hardware this is a LAN9220; the LAN9118 is software compatible 527 * except that it doesn't support the checksum-offload feature. 528 */ 529 qemu_check_nic_model(nd, "lan9118"); 530 mms->lan9118 = qdev_new(TYPE_LAN9118); 531 qdev_set_nic_properties(mms->lan9118, nd); 532 533 s = SYS_BUS_DEVICE(mms->lan9118); 534 sysbus_realize_and_unref(s, &error_fatal); 535 sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0])); 536 537 memory_region_add_subregion(&mms->eth_usb_container, 538 0, sysbus_mmio_get_region(s, 0)); 539 540 /* The USB OTG controller is an ISP1763; we don't have a model of it. */ 541 object_initialize_child(OBJECT(mms), "usb-otg", 542 &mms->usb, TYPE_UNIMPLEMENTED_DEVICE); 543 qdev_prop_set_string(DEVICE(&mms->usb), "name", "usb-otg"); 544 qdev_prop_set_uint64(DEVICE(&mms->usb), "size", 0x100000); 545 s = SYS_BUS_DEVICE(&mms->usb); 546 sysbus_realize(s, &error_fatal); 547 548 memory_region_add_subregion(&mms->eth_usb_container, 549 0x100000, sysbus_mmio_get_region(s, 0)); 550 551 return &mms->eth_usb_container; 552 } 553 554 static MemoryRegion *make_mpc(MPS2TZMachineState *mms, void *opaque, 555 const char *name, hwaddr size, 556 const int *irqs) 557 { 558 TZMPC *mpc = opaque; 559 int i = mpc - &mms->mpc[0]; 560 MemoryRegion *upstream; 561 const RAMInfo *raminfo = find_raminfo_for_mpc(mms, i); 562 MemoryRegion *ram = mr_for_raminfo(mms, raminfo); 563 564 object_initialize_child(OBJECT(mms), name, mpc, TYPE_TZ_MPC); 565 object_property_set_link(OBJECT(mpc), "downstream", OBJECT(ram), 566 &error_fatal); 567 sysbus_realize(SYS_BUS_DEVICE(mpc), &error_fatal); 568 /* Map the upstream end of the MPC into system memory */ 569 upstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 1); 570 memory_region_add_subregion(get_system_memory(), raminfo->base, upstream); 571 /* and connect its interrupt to the IoTKit */ 572 qdev_connect_gpio_out_named(DEVICE(mpc), "irq", 0, 573 qdev_get_gpio_in_named(DEVICE(&mms->iotkit), 574 "mpcexp_status", i)); 575 576 /* Return the register interface MR for our caller to map behind the PPC */ 577 return sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 0); 578 } 579 580 static hwaddr boot_mem_base(MPS2TZMachineState *mms) 581 { 582 /* 583 * Return the canonical address of the block which will be mapped 584 * at address 0x0 (i.e. where the vector table is). 585 * This is usually 0, but if the AN524 alternate memory map is 586 * enabled it will be the base address of the QSPI block. 587 */ 588 return mms->remap ? 0x28000000 : 0; 589 } 590 591 static void remap_memory(MPS2TZMachineState *mms, int map) 592 { 593 /* 594 * Remap the memory for the AN524. 'map' is the value of 595 * SCC CFG_REG0 bit 0, i.e. 0 for the default map and 1 596 * for the "option 1" mapping where QSPI is at address 0. 597 * 598 * Effectively we need to swap around the "upstream" ends of 599 * MPC 0 and MPC 1. 600 */ 601 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); 602 int i; 603 604 if (mmc->fpga_type != FPGA_AN524) { 605 return; 606 } 607 608 memory_region_transaction_begin(); 609 for (i = 0; i < 2; i++) { 610 TZMPC *mpc = &mms->mpc[i]; 611 MemoryRegion *upstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 1); 612 hwaddr addr = (i ^ map) ? 0x28000000 : 0; 613 614 memory_region_set_address(upstream, addr); 615 } 616 memory_region_transaction_commit(); 617 } 618 619 static void remap_irq_fn(void *opaque, int n, int level) 620 { 621 MPS2TZMachineState *mms = opaque; 622 623 remap_memory(mms, level); 624 } 625 626 static MemoryRegion *make_dma(MPS2TZMachineState *mms, void *opaque, 627 const char *name, hwaddr size, 628 const int *irqs) 629 { 630 /* The irq[] array is DMACINTR, DMACINTERR, DMACINTTC, in that order */ 631 PL080State *dma = opaque; 632 int i = dma - &mms->dma[0]; 633 SysBusDevice *s; 634 char *mscname = g_strdup_printf("%s-msc", name); 635 TZMSC *msc = &mms->msc[i]; 636 DeviceState *iotkitdev = DEVICE(&mms->iotkit); 637 MemoryRegion *msc_upstream; 638 MemoryRegion *msc_downstream; 639 640 /* 641 * Each DMA device is a PL081 whose transaction master interface 642 * is guarded by a Master Security Controller. The downstream end of 643 * the MSC connects to the IoTKit AHB Slave Expansion port, so the 644 * DMA devices can see all devices and memory that the CPU does. 645 */ 646 object_initialize_child(OBJECT(mms), mscname, msc, TYPE_TZ_MSC); 647 msc_downstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(&mms->iotkit), 0); 648 object_property_set_link(OBJECT(msc), "downstream", 649 OBJECT(msc_downstream), &error_fatal); 650 object_property_set_link(OBJECT(msc), "idau", OBJECT(mms), &error_fatal); 651 sysbus_realize(SYS_BUS_DEVICE(msc), &error_fatal); 652 653 qdev_connect_gpio_out_named(DEVICE(msc), "irq", 0, 654 qdev_get_gpio_in_named(iotkitdev, 655 "mscexp_status", i)); 656 qdev_connect_gpio_out_named(iotkitdev, "mscexp_clear", i, 657 qdev_get_gpio_in_named(DEVICE(msc), 658 "irq_clear", 0)); 659 qdev_connect_gpio_out_named(iotkitdev, "mscexp_ns", i, 660 qdev_get_gpio_in_named(DEVICE(msc), 661 "cfg_nonsec", 0)); 662 qdev_connect_gpio_out(DEVICE(&mms->sec_resp_splitter), 663 ARRAY_SIZE(mms->ppc) + i, 664 qdev_get_gpio_in_named(DEVICE(msc), 665 "cfg_sec_resp", 0)); 666 msc_upstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(msc), 0); 667 668 object_initialize_child(OBJECT(mms), name, dma, TYPE_PL081); 669 object_property_set_link(OBJECT(dma), "downstream", OBJECT(msc_upstream), 670 &error_fatal); 671 sysbus_realize(SYS_BUS_DEVICE(dma), &error_fatal); 672 673 s = SYS_BUS_DEVICE(dma); 674 /* Wire up DMACINTR, DMACINTERR, DMACINTTC */ 675 sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0])); 676 sysbus_connect_irq(s, 1, get_sse_irq_in(mms, irqs[1])); 677 sysbus_connect_irq(s, 2, get_sse_irq_in(mms, irqs[2])); 678 679 g_free(mscname); 680 return sysbus_mmio_get_region(s, 0); 681 } 682 683 static MemoryRegion *make_spi(MPS2TZMachineState *mms, void *opaque, 684 const char *name, hwaddr size, 685 const int *irqs) 686 { 687 /* 688 * The AN505 has five PL022 SPI controllers. 689 * One of these should have the LCD controller behind it; the others 690 * are connected only to the FPGA's "general purpose SPI connector" 691 * or "shield" expansion connectors. 692 * Note that if we do implement devices behind SPI, the chip select 693 * lines are set via the "MISC" register in the MPS2 FPGAIO device. 694 */ 695 PL022State *spi = opaque; 696 SysBusDevice *s; 697 698 object_initialize_child(OBJECT(mms), name, spi, TYPE_PL022); 699 sysbus_realize(SYS_BUS_DEVICE(spi), &error_fatal); 700 s = SYS_BUS_DEVICE(spi); 701 sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0])); 702 return sysbus_mmio_get_region(s, 0); 703 } 704 705 static MemoryRegion *make_i2c(MPS2TZMachineState *mms, void *opaque, 706 const char *name, hwaddr size, 707 const int *irqs) 708 { 709 ArmSbconI2CState *i2c = opaque; 710 SysBusDevice *s; 711 712 object_initialize_child(OBJECT(mms), name, i2c, TYPE_ARM_SBCON_I2C); 713 s = SYS_BUS_DEVICE(i2c); 714 sysbus_realize(s, &error_fatal); 715 return sysbus_mmio_get_region(s, 0); 716 } 717 718 static MemoryRegion *make_rtc(MPS2TZMachineState *mms, void *opaque, 719 const char *name, hwaddr size, 720 const int *irqs) 721 { 722 PL031State *pl031 = opaque; 723 SysBusDevice *s; 724 725 object_initialize_child(OBJECT(mms), name, pl031, TYPE_PL031); 726 s = SYS_BUS_DEVICE(pl031); 727 sysbus_realize(s, &error_fatal); 728 /* 729 * The board docs don't give an IRQ number for the PL031, so 730 * presumably it is not connected. 731 */ 732 return sysbus_mmio_get_region(s, 0); 733 } 734 735 static void create_non_mpc_ram(MPS2TZMachineState *mms) 736 { 737 /* 738 * Handle the RAMs which are either not behind MPCs or which are 739 * aliases to another MPC. 740 */ 741 const RAMInfo *p; 742 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); 743 744 for (p = mmc->raminfo; p->name; p++) { 745 if (p->flags & IS_ALIAS) { 746 SysBusDevice *mpc_sbd = SYS_BUS_DEVICE(&mms->mpc[p->mpc]); 747 MemoryRegion *upstream = sysbus_mmio_get_region(mpc_sbd, 1); 748 make_ram_alias(&mms->ram[p->mrindex], p->name, upstream, p->base); 749 } else if (p->mpc == -1) { 750 /* RAM not behind an MPC */ 751 MemoryRegion *mr = mr_for_raminfo(mms, p); 752 memory_region_add_subregion(get_system_memory(), p->base, mr); 753 } 754 } 755 } 756 757 static uint32_t boot_ram_size(MPS2TZMachineState *mms) 758 { 759 /* Return the size of the RAM block at guest address zero */ 760 const RAMInfo *p; 761 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); 762 763 for (p = mmc->raminfo; p->name; p++) { 764 if (p->base == boot_mem_base(mms)) { 765 return p->size; 766 } 767 } 768 g_assert_not_reached(); 769 } 770 771 static void mps2tz_common_init(MachineState *machine) 772 { 773 MPS2TZMachineState *mms = MPS2TZ_MACHINE(machine); 774 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); 775 MachineClass *mc = MACHINE_GET_CLASS(machine); 776 MemoryRegion *system_memory = get_system_memory(); 777 DeviceState *iotkitdev; 778 DeviceState *dev_splitter; 779 const PPCInfo *ppcs; 780 int num_ppcs; 781 int i; 782 783 if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) { 784 error_report("This board can only be used with CPU %s", 785 mc->default_cpu_type); 786 exit(1); 787 } 788 789 if (machine->ram_size != mc->default_ram_size) { 790 char *sz = size_to_str(mc->default_ram_size); 791 error_report("Invalid RAM size, should be %s", sz); 792 g_free(sz); 793 exit(EXIT_FAILURE); 794 } 795 796 /* These clocks don't need migration because they are fixed-frequency */ 797 mms->sysclk = clock_new(OBJECT(machine), "SYSCLK"); 798 clock_set_hz(mms->sysclk, mmc->sysclk_frq); 799 mms->s32kclk = clock_new(OBJECT(machine), "S32KCLK"); 800 clock_set_hz(mms->s32kclk, S32KCLK_FRQ); 801 802 object_initialize_child(OBJECT(machine), TYPE_IOTKIT, &mms->iotkit, 803 mmc->armsse_type); 804 iotkitdev = DEVICE(&mms->iotkit); 805 object_property_set_link(OBJECT(&mms->iotkit), "memory", 806 OBJECT(system_memory), &error_abort); 807 qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", mmc->numirq); 808 qdev_prop_set_uint32(iotkitdev, "init-svtor", mmc->init_svtor); 809 qdev_connect_clock_in(iotkitdev, "MAINCLK", mms->sysclk); 810 qdev_connect_clock_in(iotkitdev, "S32KCLK", mms->s32kclk); 811 sysbus_realize(SYS_BUS_DEVICE(&mms->iotkit), &error_fatal); 812 813 /* 814 * If this board has more than one CPU, then we need to create splitters 815 * to feed the IRQ inputs for each CPU in the SSE from each device in the 816 * board. If there is only one CPU, we can just wire the device IRQ 817 * directly to the SSE's IRQ input. 818 */ 819 assert(mmc->numirq <= MPS2TZ_NUMIRQ_MAX); 820 if (mc->max_cpus > 1) { 821 for (i = 0; i < mmc->numirq; i++) { 822 char *name = g_strdup_printf("mps2-irq-splitter%d", i); 823 SplitIRQ *splitter = &mms->cpu_irq_splitter[i]; 824 825 object_initialize_child_with_props(OBJECT(machine), name, 826 splitter, sizeof(*splitter), 827 TYPE_SPLIT_IRQ, &error_fatal, 828 NULL); 829 g_free(name); 830 831 object_property_set_int(OBJECT(splitter), "num-lines", 2, 832 &error_fatal); 833 qdev_realize(DEVICE(splitter), NULL, &error_fatal); 834 qdev_connect_gpio_out(DEVICE(splitter), 0, 835 qdev_get_gpio_in_named(DEVICE(&mms->iotkit), 836 "EXP_IRQ", i)); 837 qdev_connect_gpio_out(DEVICE(splitter), 1, 838 qdev_get_gpio_in_named(DEVICE(&mms->iotkit), 839 "EXP_CPU1_IRQ", i)); 840 } 841 } 842 843 /* The sec_resp_cfg output from the IoTKit must be split into multiple 844 * lines, one for each of the PPCs we create here, plus one per MSC. 845 */ 846 object_initialize_child(OBJECT(machine), "sec-resp-splitter", 847 &mms->sec_resp_splitter, TYPE_SPLIT_IRQ); 848 object_property_set_int(OBJECT(&mms->sec_resp_splitter), "num-lines", 849 ARRAY_SIZE(mms->ppc) + ARRAY_SIZE(mms->msc), 850 &error_fatal); 851 qdev_realize(DEVICE(&mms->sec_resp_splitter), NULL, &error_fatal); 852 dev_splitter = DEVICE(&mms->sec_resp_splitter); 853 qdev_connect_gpio_out_named(iotkitdev, "sec_resp_cfg", 0, 854 qdev_get_gpio_in(dev_splitter, 0)); 855 856 /* 857 * The IoTKit sets up much of the memory layout, including 858 * the aliases between secure and non-secure regions in the 859 * address space, and also most of the devices in the system. 860 * The FPGA itself contains various RAMs and some additional devices. 861 * The FPGA images have an odd combination of different RAMs, 862 * because in hardware they are different implementations and 863 * connected to different buses, giving varying performance/size 864 * tradeoffs. For QEMU they're all just RAM, though. We arbitrarily 865 * call the largest lump our "system memory". 866 */ 867 868 /* 869 * The overflow IRQs for all UARTs are ORed together. 870 * Tx, Rx and "combined" IRQs are sent to the NVIC separately. 871 * Create the OR gate for this: it has one input for the TX overflow 872 * and one for the RX overflow for each UART we might have. 873 * (If the board has fewer than the maximum possible number of UARTs 874 * those inputs are never wired up and are treated as always-zero.) 875 */ 876 object_initialize_child(OBJECT(mms), "uart-irq-orgate", 877 &mms->uart_irq_orgate, TYPE_OR_IRQ); 878 object_property_set_int(OBJECT(&mms->uart_irq_orgate), "num-lines", 879 2 * ARRAY_SIZE(mms->uart), 880 &error_fatal); 881 qdev_realize(DEVICE(&mms->uart_irq_orgate), NULL, &error_fatal); 882 qdev_connect_gpio_out(DEVICE(&mms->uart_irq_orgate), 0, 883 get_sse_irq_in(mms, mmc->uart_overflow_irq)); 884 885 /* Most of the devices in the FPGA are behind Peripheral Protection 886 * Controllers. The required order for initializing things is: 887 * + initialize the PPC 888 * + initialize, configure and realize downstream devices 889 * + connect downstream device MemoryRegions to the PPC 890 * + realize the PPC 891 * + map the PPC's MemoryRegions to the places in the address map 892 * where the downstream devices should appear 893 * + wire up the PPC's control lines to the IoTKit object 894 */ 895 896 const PPCInfo an505_ppcs[] = { { 897 .name = "apb_ppcexp0", 898 .ports = { 899 { "ssram-0-mpc", make_mpc, &mms->mpc[0], 0x58007000, 0x1000 }, 900 { "ssram-1-mpc", make_mpc, &mms->mpc[1], 0x58008000, 0x1000 }, 901 { "ssram-2-mpc", make_mpc, &mms->mpc[2], 0x58009000, 0x1000 }, 902 }, 903 }, { 904 .name = "apb_ppcexp1", 905 .ports = { 906 { "spi0", make_spi, &mms->spi[0], 0x40205000, 0x1000, { 51 } }, 907 { "spi1", make_spi, &mms->spi[1], 0x40206000, 0x1000, { 52 } }, 908 { "spi2", make_spi, &mms->spi[2], 0x40209000, 0x1000, { 53 } }, 909 { "spi3", make_spi, &mms->spi[3], 0x4020a000, 0x1000, { 54 } }, 910 { "spi4", make_spi, &mms->spi[4], 0x4020b000, 0x1000, { 55 } }, 911 { "uart0", make_uart, &mms->uart[0], 0x40200000, 0x1000, { 32, 33, 42 } }, 912 { "uart1", make_uart, &mms->uart[1], 0x40201000, 0x1000, { 34, 35, 43 } }, 913 { "uart2", make_uart, &mms->uart[2], 0x40202000, 0x1000, { 36, 37, 44 } }, 914 { "uart3", make_uart, &mms->uart[3], 0x40203000, 0x1000, { 38, 39, 45 } }, 915 { "uart4", make_uart, &mms->uart[4], 0x40204000, 0x1000, { 40, 41, 46 } }, 916 { "i2c0", make_i2c, &mms->i2c[0], 0x40207000, 0x1000 }, 917 { "i2c1", make_i2c, &mms->i2c[1], 0x40208000, 0x1000 }, 918 { "i2c2", make_i2c, &mms->i2c[2], 0x4020c000, 0x1000 }, 919 { "i2c3", make_i2c, &mms->i2c[3], 0x4020d000, 0x1000 }, 920 }, 921 }, { 922 .name = "apb_ppcexp2", 923 .ports = { 924 { "scc", make_scc, &mms->scc, 0x40300000, 0x1000 }, 925 { "i2s-audio", make_unimp_dev, &mms->i2s_audio, 926 0x40301000, 0x1000 }, 927 { "fpgaio", make_fpgaio, &mms->fpgaio, 0x40302000, 0x1000 }, 928 }, 929 }, { 930 .name = "ahb_ppcexp0", 931 .ports = { 932 { "gfx", make_unimp_dev, &mms->gfx, 0x41000000, 0x140000 }, 933 { "gpio0", make_unimp_dev, &mms->gpio[0], 0x40100000, 0x1000 }, 934 { "gpio1", make_unimp_dev, &mms->gpio[1], 0x40101000, 0x1000 }, 935 { "gpio2", make_unimp_dev, &mms->gpio[2], 0x40102000, 0x1000 }, 936 { "gpio3", make_unimp_dev, &mms->gpio[3], 0x40103000, 0x1000 }, 937 { "eth", make_eth_dev, NULL, 0x42000000, 0x100000, { 48 } }, 938 }, 939 }, { 940 .name = "ahb_ppcexp1", 941 .ports = { 942 { "dma0", make_dma, &mms->dma[0], 0x40110000, 0x1000, { 58, 56, 57 } }, 943 { "dma1", make_dma, &mms->dma[1], 0x40111000, 0x1000, { 61, 59, 60 } }, 944 { "dma2", make_dma, &mms->dma[2], 0x40112000, 0x1000, { 64, 62, 63 } }, 945 { "dma3", make_dma, &mms->dma[3], 0x40113000, 0x1000, { 67, 65, 66 } }, 946 }, 947 }, 948 }; 949 950 const PPCInfo an524_ppcs[] = { { 951 .name = "apb_ppcexp0", 952 .ports = { 953 { "bram-mpc", make_mpc, &mms->mpc[0], 0x58007000, 0x1000 }, 954 { "qspi-mpc", make_mpc, &mms->mpc[1], 0x58008000, 0x1000 }, 955 { "ddr-mpc", make_mpc, &mms->mpc[2], 0x58009000, 0x1000 }, 956 }, 957 }, { 958 .name = "apb_ppcexp1", 959 .ports = { 960 { "i2c0", make_i2c, &mms->i2c[0], 0x41200000, 0x1000 }, 961 { "i2c1", make_i2c, &mms->i2c[1], 0x41201000, 0x1000 }, 962 { "spi0", make_spi, &mms->spi[0], 0x41202000, 0x1000, { 52 } }, 963 { "spi1", make_spi, &mms->spi[1], 0x41203000, 0x1000, { 53 } }, 964 { "spi2", make_spi, &mms->spi[2], 0x41204000, 0x1000, { 54 } }, 965 { "i2c2", make_i2c, &mms->i2c[2], 0x41205000, 0x1000 }, 966 { "i2c3", make_i2c, &mms->i2c[3], 0x41206000, 0x1000 }, 967 { /* port 7 reserved */ }, 968 { "i2c4", make_i2c, &mms->i2c[4], 0x41208000, 0x1000 }, 969 }, 970 }, { 971 .name = "apb_ppcexp2", 972 .ports = { 973 { "scc", make_scc, &mms->scc, 0x41300000, 0x1000 }, 974 { "i2s-audio", make_unimp_dev, &mms->i2s_audio, 975 0x41301000, 0x1000 }, 976 { "fpgaio", make_fpgaio, &mms->fpgaio, 0x41302000, 0x1000 }, 977 { "uart0", make_uart, &mms->uart[0], 0x41303000, 0x1000, { 32, 33, 42 } }, 978 { "uart1", make_uart, &mms->uart[1], 0x41304000, 0x1000, { 34, 35, 43 } }, 979 { "uart2", make_uart, &mms->uart[2], 0x41305000, 0x1000, { 36, 37, 44 } }, 980 { "uart3", make_uart, &mms->uart[3], 0x41306000, 0x1000, { 38, 39, 45 } }, 981 { "uart4", make_uart, &mms->uart[4], 0x41307000, 0x1000, { 40, 41, 46 } }, 982 { "uart5", make_uart, &mms->uart[5], 0x41308000, 0x1000, { 124, 125, 126 } }, 983 984 { /* port 9 reserved */ }, 985 { "clcd", make_unimp_dev, &mms->cldc, 0x4130a000, 0x1000 }, 986 { "rtc", make_rtc, &mms->rtc, 0x4130b000, 0x1000 }, 987 }, 988 }, { 989 .name = "ahb_ppcexp0", 990 .ports = { 991 { "gpio0", make_unimp_dev, &mms->gpio[0], 0x41100000, 0x1000 }, 992 { "gpio1", make_unimp_dev, &mms->gpio[1], 0x41101000, 0x1000 }, 993 { "gpio2", make_unimp_dev, &mms->gpio[2], 0x41102000, 0x1000 }, 994 { "gpio3", make_unimp_dev, &mms->gpio[3], 0x41103000, 0x1000 }, 995 { "eth-usb", make_eth_usb, NULL, 0x41400000, 0x200000, { 48 } }, 996 }, 997 }, 998 }; 999 1000 const PPCInfo an547_ppcs[] = { { 1001 .name = "apb_ppcexp0", 1002 .ports = { 1003 { "ssram-mpc", make_mpc, &mms->mpc[0], 0x57000000, 0x1000 }, 1004 { "qspi-mpc", make_mpc, &mms->mpc[1], 0x57001000, 0x1000 }, 1005 { "ddr-mpc", make_mpc, &mms->mpc[2], 0x57002000, 0x1000 }, 1006 }, 1007 }, { 1008 .name = "apb_ppcexp1", 1009 .ports = { 1010 { "i2c0", make_i2c, &mms->i2c[0], 0x49200000, 0x1000 }, 1011 { "i2c1", make_i2c, &mms->i2c[1], 0x49201000, 0x1000 }, 1012 { "spi0", make_spi, &mms->spi[0], 0x49202000, 0x1000, { 53 } }, 1013 { "spi1", make_spi, &mms->spi[1], 0x49203000, 0x1000, { 54 } }, 1014 { "spi2", make_spi, &mms->spi[2], 0x49204000, 0x1000, { 55 } }, 1015 { "i2c2", make_i2c, &mms->i2c[2], 0x49205000, 0x1000 }, 1016 { "i2c3", make_i2c, &mms->i2c[3], 0x49206000, 0x1000 }, 1017 { /* port 7 reserved */ }, 1018 { "i2c4", make_i2c, &mms->i2c[4], 0x49208000, 0x1000 }, 1019 }, 1020 }, { 1021 .name = "apb_ppcexp2", 1022 .ports = { 1023 { "scc", make_scc, &mms->scc, 0x49300000, 0x1000 }, 1024 { "i2s-audio", make_unimp_dev, &mms->i2s_audio, 0x49301000, 0x1000 }, 1025 { "fpgaio", make_fpgaio, &mms->fpgaio, 0x49302000, 0x1000 }, 1026 { "uart0", make_uart, &mms->uart[0], 0x49303000, 0x1000, { 33, 34, 43 } }, 1027 { "uart1", make_uart, &mms->uart[1], 0x49304000, 0x1000, { 35, 36, 44 } }, 1028 { "uart2", make_uart, &mms->uart[2], 0x49305000, 0x1000, { 37, 38, 45 } }, 1029 { "uart3", make_uart, &mms->uart[3], 0x49306000, 0x1000, { 39, 40, 46 } }, 1030 { "uart4", make_uart, &mms->uart[4], 0x49307000, 0x1000, { 41, 42, 47 } }, 1031 { "uart5", make_uart, &mms->uart[5], 0x49308000, 0x1000, { 125, 126, 127 } }, 1032 1033 { /* port 9 reserved */ }, 1034 { "clcd", make_unimp_dev, &mms->cldc, 0x4930a000, 0x1000 }, 1035 { "rtc", make_rtc, &mms->rtc, 0x4930b000, 0x1000 }, 1036 }, 1037 }, { 1038 .name = "ahb_ppcexp0", 1039 .ports = { 1040 { "gpio0", make_unimp_dev, &mms->gpio[0], 0x41100000, 0x1000 }, 1041 { "gpio1", make_unimp_dev, &mms->gpio[1], 0x41101000, 0x1000 }, 1042 { "gpio2", make_unimp_dev, &mms->gpio[2], 0x41102000, 0x1000 }, 1043 { "gpio3", make_unimp_dev, &mms->gpio[3], 0x41103000, 0x1000 }, 1044 { "eth-usb", make_eth_usb, NULL, 0x41400000, 0x200000, { 49 } }, 1045 }, 1046 }, 1047 }; 1048 1049 switch (mmc->fpga_type) { 1050 case FPGA_AN505: 1051 case FPGA_AN521: 1052 ppcs = an505_ppcs; 1053 num_ppcs = ARRAY_SIZE(an505_ppcs); 1054 break; 1055 case FPGA_AN524: 1056 ppcs = an524_ppcs; 1057 num_ppcs = ARRAY_SIZE(an524_ppcs); 1058 break; 1059 case FPGA_AN547: 1060 ppcs = an547_ppcs; 1061 num_ppcs = ARRAY_SIZE(an547_ppcs); 1062 break; 1063 default: 1064 g_assert_not_reached(); 1065 } 1066 1067 for (i = 0; i < num_ppcs; i++) { 1068 const PPCInfo *ppcinfo = &ppcs[i]; 1069 TZPPC *ppc = &mms->ppc[i]; 1070 DeviceState *ppcdev; 1071 int port; 1072 char *gpioname; 1073 1074 object_initialize_child(OBJECT(machine), ppcinfo->name, ppc, 1075 TYPE_TZ_PPC); 1076 ppcdev = DEVICE(ppc); 1077 1078 for (port = 0; port < TZ_NUM_PORTS; port++) { 1079 const PPCPortInfo *pinfo = &ppcinfo->ports[port]; 1080 MemoryRegion *mr; 1081 char *portname; 1082 1083 if (!pinfo->devfn) { 1084 continue; 1085 } 1086 1087 mr = pinfo->devfn(mms, pinfo->opaque, pinfo->name, pinfo->size, 1088 pinfo->irqs); 1089 portname = g_strdup_printf("port[%d]", port); 1090 object_property_set_link(OBJECT(ppc), portname, OBJECT(mr), 1091 &error_fatal); 1092 g_free(portname); 1093 } 1094 1095 sysbus_realize(SYS_BUS_DEVICE(ppc), &error_fatal); 1096 1097 for (port = 0; port < TZ_NUM_PORTS; port++) { 1098 const PPCPortInfo *pinfo = &ppcinfo->ports[port]; 1099 1100 if (!pinfo->devfn) { 1101 continue; 1102 } 1103 sysbus_mmio_map(SYS_BUS_DEVICE(ppc), port, pinfo->addr); 1104 1105 gpioname = g_strdup_printf("%s_nonsec", ppcinfo->name); 1106 qdev_connect_gpio_out_named(iotkitdev, gpioname, port, 1107 qdev_get_gpio_in_named(ppcdev, 1108 "cfg_nonsec", 1109 port)); 1110 g_free(gpioname); 1111 gpioname = g_strdup_printf("%s_ap", ppcinfo->name); 1112 qdev_connect_gpio_out_named(iotkitdev, gpioname, port, 1113 qdev_get_gpio_in_named(ppcdev, 1114 "cfg_ap", port)); 1115 g_free(gpioname); 1116 } 1117 1118 gpioname = g_strdup_printf("%s_irq_enable", ppcinfo->name); 1119 qdev_connect_gpio_out_named(iotkitdev, gpioname, 0, 1120 qdev_get_gpio_in_named(ppcdev, 1121 "irq_enable", 0)); 1122 g_free(gpioname); 1123 gpioname = g_strdup_printf("%s_irq_clear", ppcinfo->name); 1124 qdev_connect_gpio_out_named(iotkitdev, gpioname, 0, 1125 qdev_get_gpio_in_named(ppcdev, 1126 "irq_clear", 0)); 1127 g_free(gpioname); 1128 gpioname = g_strdup_printf("%s_irq_status", ppcinfo->name); 1129 qdev_connect_gpio_out_named(ppcdev, "irq", 0, 1130 qdev_get_gpio_in_named(iotkitdev, 1131 gpioname, 0)); 1132 g_free(gpioname); 1133 1134 qdev_connect_gpio_out(dev_splitter, i, 1135 qdev_get_gpio_in_named(ppcdev, 1136 "cfg_sec_resp", 0)); 1137 } 1138 1139 create_unimplemented_device("FPGA NS PC", 0x48007000, 0x1000); 1140 1141 if (mmc->fpga_type == FPGA_AN547) { 1142 create_unimplemented_device("U55 timing adapter 0", 0x48102000, 0x1000); 1143 create_unimplemented_device("U55 timing adapter 1", 0x48103000, 0x1000); 1144 } 1145 1146 create_non_mpc_ram(mms); 1147 1148 if (mmc->fpga_type == FPGA_AN524) { 1149 /* 1150 * Connect the line from the SCC so that we can remap when the 1151 * guest updates that register. 1152 */ 1153 mms->remap_irq = qemu_allocate_irq(remap_irq_fn, mms, 0); 1154 qdev_connect_gpio_out_named(DEVICE(&mms->scc), "remap", 0, 1155 mms->remap_irq); 1156 } 1157 1158 armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 1159 boot_ram_size(mms)); 1160 } 1161 1162 static void mps2_tz_idau_check(IDAUInterface *ii, uint32_t address, 1163 int *iregion, bool *exempt, bool *ns, bool *nsc) 1164 { 1165 /* 1166 * The MPS2 TZ FPGA images have IDAUs in them which are connected to 1167 * the Master Security Controllers. Thes have the same logic as 1168 * is used by the IoTKit for the IDAU connected to the CPU, except 1169 * that MSCs don't care about the NSC attribute. 1170 */ 1171 int region = extract32(address, 28, 4); 1172 1173 *ns = !(region & 1); 1174 *nsc = false; 1175 /* 0xe0000000..0xe00fffff and 0xf0000000..0xf00fffff are exempt */ 1176 *exempt = (address & 0xeff00000) == 0xe0000000; 1177 *iregion = region; 1178 } 1179 1180 static char *mps2_get_remap(Object *obj, Error **errp) 1181 { 1182 MPS2TZMachineState *mms = MPS2TZ_MACHINE(obj); 1183 const char *val = mms->remap ? "QSPI" : "BRAM"; 1184 return g_strdup(val); 1185 } 1186 1187 static void mps2_set_remap(Object *obj, const char *value, Error **errp) 1188 { 1189 MPS2TZMachineState *mms = MPS2TZ_MACHINE(obj); 1190 1191 if (!strcmp(value, "BRAM")) { 1192 mms->remap = false; 1193 } else if (!strcmp(value, "QSPI")) { 1194 mms->remap = true; 1195 } else { 1196 error_setg(errp, "Invalid remap value"); 1197 error_append_hint(errp, "Valid values are BRAM and QSPI.\n"); 1198 } 1199 } 1200 1201 static void mps2_machine_reset(MachineState *machine) 1202 { 1203 MPS2TZMachineState *mms = MPS2TZ_MACHINE(machine); 1204 1205 /* 1206 * Set the initial memory mapping before triggering the reset of 1207 * the rest of the system, so that the guest image loader and CPU 1208 * reset see the correct mapping. 1209 */ 1210 remap_memory(mms, mms->remap); 1211 qemu_devices_reset(); 1212 } 1213 1214 static void mps2tz_class_init(ObjectClass *oc, void *data) 1215 { 1216 MachineClass *mc = MACHINE_CLASS(oc); 1217 IDAUInterfaceClass *iic = IDAU_INTERFACE_CLASS(oc); 1218 1219 mc->init = mps2tz_common_init; 1220 mc->reset = mps2_machine_reset; 1221 iic->check = mps2_tz_idau_check; 1222 } 1223 1224 static void mps2tz_set_default_ram_info(MPS2TZMachineClass *mmc) 1225 { 1226 /* 1227 * Set mc->default_ram_size and default_ram_id from the 1228 * information in mmc->raminfo. 1229 */ 1230 MachineClass *mc = MACHINE_CLASS(mmc); 1231 const RAMInfo *p; 1232 1233 for (p = mmc->raminfo; p->name; p++) { 1234 if (p->mrindex < 0) { 1235 /* Found the entry for "system memory" */ 1236 mc->default_ram_size = p->size; 1237 mc->default_ram_id = p->name; 1238 return; 1239 } 1240 } 1241 g_assert_not_reached(); 1242 } 1243 1244 static void mps2tz_an505_class_init(ObjectClass *oc, void *data) 1245 { 1246 MachineClass *mc = MACHINE_CLASS(oc); 1247 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc); 1248 1249 mc->desc = "ARM MPS2 with AN505 FPGA image for Cortex-M33"; 1250 mc->default_cpus = 1; 1251 mc->min_cpus = mc->default_cpus; 1252 mc->max_cpus = mc->default_cpus; 1253 mmc->fpga_type = FPGA_AN505; 1254 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"); 1255 mmc->scc_id = 0x41045050; 1256 mmc->sysclk_frq = 20 * 1000 * 1000; /* 20MHz */ 1257 mmc->apb_periph_frq = mmc->sysclk_frq; 1258 mmc->oscclk = an505_oscclk; 1259 mmc->len_oscclk = ARRAY_SIZE(an505_oscclk); 1260 mmc->fpgaio_num_leds = 2; 1261 mmc->fpgaio_has_switches = false; 1262 mmc->fpgaio_has_dbgctrl = false; 1263 mmc->numirq = 92; 1264 mmc->uart_overflow_irq = 47; 1265 mmc->init_svtor = 0x10000000; 1266 mmc->raminfo = an505_raminfo; 1267 mmc->armsse_type = TYPE_IOTKIT; 1268 mps2tz_set_default_ram_info(mmc); 1269 } 1270 1271 static void mps2tz_an521_class_init(ObjectClass *oc, void *data) 1272 { 1273 MachineClass *mc = MACHINE_CLASS(oc); 1274 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc); 1275 1276 mc->desc = "ARM MPS2 with AN521 FPGA image for dual Cortex-M33"; 1277 mc->default_cpus = 2; 1278 mc->min_cpus = mc->default_cpus; 1279 mc->max_cpus = mc->default_cpus; 1280 mmc->fpga_type = FPGA_AN521; 1281 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"); 1282 mmc->scc_id = 0x41045210; 1283 mmc->sysclk_frq = 20 * 1000 * 1000; /* 20MHz */ 1284 mmc->apb_periph_frq = mmc->sysclk_frq; 1285 mmc->oscclk = an505_oscclk; /* AN521 is the same as AN505 here */ 1286 mmc->len_oscclk = ARRAY_SIZE(an505_oscclk); 1287 mmc->fpgaio_num_leds = 2; 1288 mmc->fpgaio_has_switches = false; 1289 mmc->fpgaio_has_dbgctrl = false; 1290 mmc->numirq = 92; 1291 mmc->uart_overflow_irq = 47; 1292 mmc->init_svtor = 0x10000000; 1293 mmc->raminfo = an505_raminfo; /* AN521 is the same as AN505 here */ 1294 mmc->armsse_type = TYPE_SSE200; 1295 mps2tz_set_default_ram_info(mmc); 1296 } 1297 1298 static void mps3tz_an524_class_init(ObjectClass *oc, void *data) 1299 { 1300 MachineClass *mc = MACHINE_CLASS(oc); 1301 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc); 1302 1303 mc->desc = "ARM MPS3 with AN524 FPGA image for dual Cortex-M33"; 1304 mc->default_cpus = 2; 1305 mc->min_cpus = mc->default_cpus; 1306 mc->max_cpus = mc->default_cpus; 1307 mmc->fpga_type = FPGA_AN524; 1308 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"); 1309 mmc->scc_id = 0x41045240; 1310 mmc->sysclk_frq = 32 * 1000 * 1000; /* 32MHz */ 1311 mmc->apb_periph_frq = mmc->sysclk_frq; 1312 mmc->oscclk = an524_oscclk; 1313 mmc->len_oscclk = ARRAY_SIZE(an524_oscclk); 1314 mmc->fpgaio_num_leds = 10; 1315 mmc->fpgaio_has_switches = true; 1316 mmc->fpgaio_has_dbgctrl = false; 1317 mmc->numirq = 95; 1318 mmc->uart_overflow_irq = 47; 1319 mmc->init_svtor = 0x10000000; 1320 mmc->raminfo = an524_raminfo; 1321 mmc->armsse_type = TYPE_SSE200; 1322 mps2tz_set_default_ram_info(mmc); 1323 1324 object_class_property_add_str(oc, "remap", mps2_get_remap, mps2_set_remap); 1325 object_class_property_set_description(oc, "remap", 1326 "Set memory mapping. Valid values " 1327 "are BRAM (default) and QSPI."); 1328 } 1329 1330 static void mps3tz_an547_class_init(ObjectClass *oc, void *data) 1331 { 1332 MachineClass *mc = MACHINE_CLASS(oc); 1333 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc); 1334 1335 mc->desc = "ARM MPS3 with AN547 FPGA image for Cortex-M55"; 1336 mc->default_cpus = 1; 1337 mc->min_cpus = mc->default_cpus; 1338 mc->max_cpus = mc->default_cpus; 1339 mmc->fpga_type = FPGA_AN547; 1340 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m55"); 1341 mmc->scc_id = 0x41055470; 1342 mmc->sysclk_frq = 32 * 1000 * 1000; /* 32MHz */ 1343 mmc->apb_periph_frq = 25 * 1000 * 1000; /* 25MHz */ 1344 mmc->oscclk = an524_oscclk; /* same as AN524 */ 1345 mmc->len_oscclk = ARRAY_SIZE(an524_oscclk); 1346 mmc->fpgaio_num_leds = 10; 1347 mmc->fpgaio_has_switches = true; 1348 mmc->fpgaio_has_dbgctrl = true; 1349 mmc->numirq = 96; 1350 mmc->uart_overflow_irq = 48; 1351 mmc->init_svtor = 0x00000000; 1352 mmc->raminfo = an547_raminfo; 1353 mmc->armsse_type = TYPE_SSE300; 1354 mps2tz_set_default_ram_info(mmc); 1355 } 1356 1357 static const TypeInfo mps2tz_info = { 1358 .name = TYPE_MPS2TZ_MACHINE, 1359 .parent = TYPE_MACHINE, 1360 .abstract = true, 1361 .instance_size = sizeof(MPS2TZMachineState), 1362 .class_size = sizeof(MPS2TZMachineClass), 1363 .class_init = mps2tz_class_init, 1364 .interfaces = (InterfaceInfo[]) { 1365 { TYPE_IDAU_INTERFACE }, 1366 { } 1367 }, 1368 }; 1369 1370 static const TypeInfo mps2tz_an505_info = { 1371 .name = TYPE_MPS2TZ_AN505_MACHINE, 1372 .parent = TYPE_MPS2TZ_MACHINE, 1373 .class_init = mps2tz_an505_class_init, 1374 }; 1375 1376 static const TypeInfo mps2tz_an521_info = { 1377 .name = TYPE_MPS2TZ_AN521_MACHINE, 1378 .parent = TYPE_MPS2TZ_MACHINE, 1379 .class_init = mps2tz_an521_class_init, 1380 }; 1381 1382 static const TypeInfo mps3tz_an524_info = { 1383 .name = TYPE_MPS3TZ_AN524_MACHINE, 1384 .parent = TYPE_MPS2TZ_MACHINE, 1385 .class_init = mps3tz_an524_class_init, 1386 }; 1387 1388 static const TypeInfo mps3tz_an547_info = { 1389 .name = TYPE_MPS3TZ_AN547_MACHINE, 1390 .parent = TYPE_MPS2TZ_MACHINE, 1391 .class_init = mps3tz_an547_class_init, 1392 }; 1393 1394 static void mps2tz_machine_init(void) 1395 { 1396 type_register_static(&mps2tz_info); 1397 type_register_static(&mps2tz_an505_info); 1398 type_register_static(&mps2tz_an521_info); 1399 type_register_static(&mps3tz_an524_info); 1400 type_register_static(&mps3tz_an547_info); 1401 } 1402 1403 type_init(mps2tz_machine_init); 1404