1 /* 2 * ARM V2M MPS2 board emulation, trustzone aware FPGA images 3 * 4 * Copyright (c) 2017 Linaro Limited 5 * Written by Peter Maydell 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 or 9 * (at your option) any later version. 10 */ 11 12 /* The MPS2 and MPS2+ dev boards are FPGA based (the 2+ has a bigger 13 * FPGA but is otherwise the same as the 2). Since the CPU itself 14 * and most of the devices are in the FPGA, the details of the board 15 * as seen by the guest depend significantly on the FPGA image. 16 * This source file covers the following FPGA images, for TrustZone cores: 17 * "mps2-an505" -- Cortex-M33 as documented in ARM Application Note AN505 18 * "mps2-an521" -- Dual Cortex-M33 as documented in Application Note AN521 19 * "mps2-an524" -- Dual Cortex-M33 as documented in Application Note AN524 20 * "mps2-an547" -- Single Cortex-M55 as documented in Application Note AN547 21 * 22 * Links to the TRM for the board itself and to the various Application 23 * Notes which document the FPGA images can be found here: 24 * https://developer.arm.com/products/system-design/development-boards/fpga-prototyping-boards/mps2 25 * 26 * Board TRM: 27 * https://developer.arm.com/documentation/100112/latest/ 28 * Application Note AN505: 29 * https://developer.arm.com/documentation/dai0505/latest/ 30 * Application Note AN521: 31 * https://developer.arm.com/documentation/dai0521/latest/ 32 * Application Note AN524: 33 * https://developer.arm.com/documentation/dai0524/latest/ 34 * Application Note AN547: 35 * https://developer.arm.com/-/media/Arm%20Developer%20Community/PDF/DAI0547B_SSE300_PLUS_U55_FPGA_for_mps3.pdf 36 * 37 * The AN505 defers to the Cortex-M33 processor ARMv8M IoT Kit FVP User Guide 38 * (ARM ECM0601256) for the details of some of the device layout: 39 * https://developer.arm.com/documentation/ecm0601256/latest 40 * Similarly, the AN521 and AN524 use the SSE-200, and the SSE-200 TRM defines 41 * most of the device layout: 42 * https://developer.arm.com/documentation/101104/latest/ 43 * and the AN547 uses the SSE-300, whose layout is in the SSE-300 TRM: 44 * https://developer.arm.com/documentation/101773/latest/ 45 */ 46 47 #include "qemu/osdep.h" 48 #include "qemu/units.h" 49 #include "qemu/cutils.h" 50 #include "qapi/error.h" 51 #include "qemu/error-report.h" 52 #include "hw/arm/boot.h" 53 #include "hw/arm/armv7m.h" 54 #include "hw/or-irq.h" 55 #include "hw/boards.h" 56 #include "exec/address-spaces.h" 57 #include "sysemu/sysemu.h" 58 #include "sysemu/reset.h" 59 #include "hw/misc/unimp.h" 60 #include "hw/char/cmsdk-apb-uart.h" 61 #include "hw/timer/cmsdk-apb-timer.h" 62 #include "hw/misc/mps2-scc.h" 63 #include "hw/misc/mps2-fpgaio.h" 64 #include "hw/misc/tz-mpc.h" 65 #include "hw/misc/tz-msc.h" 66 #include "hw/arm/armsse.h" 67 #include "hw/dma/pl080.h" 68 #include "hw/rtc/pl031.h" 69 #include "hw/ssi/pl022.h" 70 #include "hw/i2c/arm_sbcon_i2c.h" 71 #include "hw/net/lan9118.h" 72 #include "net/net.h" 73 #include "hw/core/split-irq.h" 74 #include "hw/qdev-clock.h" 75 #include "qom/object.h" 76 #include "hw/irq.h" 77 78 #define MPS2TZ_NUMIRQ_MAX 96 79 #define MPS2TZ_RAM_MAX 5 80 81 typedef enum MPS2TZFPGAType { 82 FPGA_AN505, 83 FPGA_AN521, 84 FPGA_AN524, 85 FPGA_AN547, 86 } MPS2TZFPGAType; 87 88 /* 89 * Define the layout of RAM in a board, including which parts are 90 * behind which MPCs. 91 * mrindex specifies the index into mms->ram[] to use for the backing RAM; 92 * -1 means "use the system RAM". 93 */ 94 typedef struct RAMInfo { 95 const char *name; 96 uint32_t base; 97 uint32_t size; 98 int mpc; /* MPC number, -1 for "not behind an MPC" */ 99 int mrindex; 100 int flags; 101 } RAMInfo; 102 103 /* 104 * Flag values: 105 * IS_ALIAS: this RAM area is an alias to the upstream end of the 106 * MPC specified by its .mpc value 107 * IS_ROM: this RAM area is read-only 108 */ 109 #define IS_ALIAS 1 110 #define IS_ROM 2 111 112 struct MPS2TZMachineClass { 113 MachineClass parent; 114 MPS2TZFPGAType fpga_type; 115 uint32_t scc_id; 116 uint32_t sysclk_frq; /* Main SYSCLK frequency in Hz */ 117 uint32_t apb_periph_frq; /* APB peripheral frequency in Hz */ 118 uint32_t len_oscclk; 119 const uint32_t *oscclk; 120 uint32_t fpgaio_num_leds; /* Number of LEDs in FPGAIO LED0 register */ 121 bool fpgaio_has_switches; /* Does FPGAIO have SWITCH register? */ 122 bool fpgaio_has_dbgctrl; /* Does FPGAIO have DBGCTRL register? */ 123 int numirq; /* Number of external interrupts */ 124 int uart_overflow_irq; /* number of the combined UART overflow IRQ */ 125 uint32_t init_svtor; /* init-svtor setting for SSE */ 126 uint32_t sram_addr_width; /* SRAM_ADDR_WIDTH setting for SSE */ 127 const RAMInfo *raminfo; 128 const char *armsse_type; 129 }; 130 131 struct MPS2TZMachineState { 132 MachineState parent; 133 134 ARMSSE iotkit; 135 MemoryRegion ram[MPS2TZ_RAM_MAX]; 136 MemoryRegion eth_usb_container; 137 138 MPS2SCC scc; 139 MPS2FPGAIO fpgaio; 140 TZPPC ppc[5]; 141 TZMPC mpc[3]; 142 PL022State spi[5]; 143 ArmSbconI2CState i2c[5]; 144 UnimplementedDeviceState i2s_audio; 145 UnimplementedDeviceState gpio[4]; 146 UnimplementedDeviceState gfx; 147 UnimplementedDeviceState cldc; 148 UnimplementedDeviceState usb; 149 PL031State rtc; 150 PL080State dma[4]; 151 TZMSC msc[4]; 152 CMSDKAPBUART uart[6]; 153 SplitIRQ sec_resp_splitter; 154 qemu_or_irq uart_irq_orgate; 155 DeviceState *lan9118; 156 SplitIRQ cpu_irq_splitter[MPS2TZ_NUMIRQ_MAX]; 157 Clock *sysclk; 158 Clock *s32kclk; 159 160 bool remap; 161 qemu_irq remap_irq; 162 }; 163 164 #define TYPE_MPS2TZ_MACHINE "mps2tz" 165 #define TYPE_MPS2TZ_AN505_MACHINE MACHINE_TYPE_NAME("mps2-an505") 166 #define TYPE_MPS2TZ_AN521_MACHINE MACHINE_TYPE_NAME("mps2-an521") 167 #define TYPE_MPS3TZ_AN524_MACHINE MACHINE_TYPE_NAME("mps3-an524") 168 #define TYPE_MPS3TZ_AN547_MACHINE MACHINE_TYPE_NAME("mps3-an547") 169 170 OBJECT_DECLARE_TYPE(MPS2TZMachineState, MPS2TZMachineClass, MPS2TZ_MACHINE) 171 172 /* Slow 32Khz S32KCLK frequency in Hz */ 173 #define S32KCLK_FRQ (32 * 1000) 174 175 /* 176 * The MPS3 DDR is 2GiB, but on a 32-bit host QEMU doesn't permit 177 * emulation of that much guest RAM, so artificially make it smaller. 178 */ 179 #if HOST_LONG_BITS == 32 180 #define MPS3_DDR_SIZE (1 * GiB) 181 #else 182 #define MPS3_DDR_SIZE (2 * GiB) 183 #endif 184 185 static const uint32_t an505_oscclk[] = { 186 40000000, 187 24580000, 188 25000000, 189 }; 190 191 static const uint32_t an524_oscclk[] = { 192 24000000, 193 32000000, 194 50000000, 195 50000000, 196 24576000, 197 23750000, 198 }; 199 200 static const RAMInfo an505_raminfo[] = { { 201 .name = "ssram-0", 202 .base = 0x00000000, 203 .size = 0x00400000, 204 .mpc = 0, 205 .mrindex = 0, 206 }, { 207 .name = "ssram-1", 208 .base = 0x28000000, 209 .size = 0x00200000, 210 .mpc = 1, 211 .mrindex = 1, 212 }, { 213 .name = "ssram-2", 214 .base = 0x28200000, 215 .size = 0x00200000, 216 .mpc = 2, 217 .mrindex = 2, 218 }, { 219 .name = "ssram-0-alias", 220 .base = 0x00400000, 221 .size = 0x00400000, 222 .mpc = 0, 223 .mrindex = 3, 224 .flags = IS_ALIAS, 225 }, { 226 /* Use the largest bit of contiguous RAM as our "system memory" */ 227 .name = "mps.ram", 228 .base = 0x80000000, 229 .size = 16 * MiB, 230 .mpc = -1, 231 .mrindex = -1, 232 }, { 233 .name = NULL, 234 }, 235 }; 236 237 /* 238 * Note that the addresses and MPC numbering here should match up 239 * with those used in remap_memory(), which can swap the BRAM and QSPI. 240 */ 241 static const RAMInfo an524_raminfo[] = { { 242 .name = "bram", 243 .base = 0x00000000, 244 .size = 512 * KiB, 245 .mpc = 0, 246 .mrindex = 0, 247 }, { 248 /* We don't model QSPI flash yet; for now expose it as simple ROM */ 249 .name = "QSPI", 250 .base = 0x28000000, 251 .size = 8 * MiB, 252 .mpc = 1, 253 .mrindex = 1, 254 .flags = IS_ROM, 255 }, { 256 .name = "DDR", 257 .base = 0x60000000, 258 .size = MPS3_DDR_SIZE, 259 .mpc = 2, 260 .mrindex = -1, 261 }, { 262 .name = NULL, 263 }, 264 }; 265 266 static const RAMInfo an547_raminfo[] = { { 267 .name = "itcm", 268 .base = 0x00000000, 269 .size = 512 * KiB, 270 .mpc = -1, 271 .mrindex = 0, 272 }, { 273 .name = "sram", 274 .base = 0x01000000, 275 .size = 2 * MiB, 276 .mpc = 0, 277 .mrindex = 1, 278 }, { 279 .name = "dtcm", 280 .base = 0x20000000, 281 .size = 4 * 128 * KiB, 282 .mpc = -1, 283 .mrindex = 2, 284 }, { 285 .name = "sram 2", 286 .base = 0x21000000, 287 .size = 4 * MiB, 288 .mpc = -1, 289 .mrindex = 3, 290 }, { 291 /* We don't model QSPI flash yet; for now expose it as simple ROM */ 292 .name = "QSPI", 293 .base = 0x28000000, 294 .size = 8 * MiB, 295 .mpc = 1, 296 .mrindex = 4, 297 .flags = IS_ROM, 298 }, { 299 .name = "DDR", 300 .base = 0x60000000, 301 .size = MPS3_DDR_SIZE, 302 .mpc = 2, 303 .mrindex = -1, 304 }, { 305 .name = NULL, 306 }, 307 }; 308 309 static const RAMInfo *find_raminfo_for_mpc(MPS2TZMachineState *mms, int mpc) 310 { 311 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); 312 const RAMInfo *p; 313 const RAMInfo *found = NULL; 314 315 for (p = mmc->raminfo; p->name; p++) { 316 if (p->mpc == mpc && !(p->flags & IS_ALIAS)) { 317 /* There should only be one entry in the array for this MPC */ 318 g_assert(!found); 319 found = p; 320 } 321 } 322 /* if raminfo array doesn't have an entry for each MPC this is a bug */ 323 assert(found); 324 return found; 325 } 326 327 static MemoryRegion *mr_for_raminfo(MPS2TZMachineState *mms, 328 const RAMInfo *raminfo) 329 { 330 /* Return an initialized MemoryRegion for the RAMInfo. */ 331 MemoryRegion *ram; 332 333 if (raminfo->mrindex < 0) { 334 /* Means this RAMInfo is for QEMU's "system memory" */ 335 MachineState *machine = MACHINE(mms); 336 assert(!(raminfo->flags & IS_ROM)); 337 return machine->ram; 338 } 339 340 assert(raminfo->mrindex < MPS2TZ_RAM_MAX); 341 ram = &mms->ram[raminfo->mrindex]; 342 343 memory_region_init_ram(ram, NULL, raminfo->name, 344 raminfo->size, &error_fatal); 345 if (raminfo->flags & IS_ROM) { 346 memory_region_set_readonly(ram, true); 347 } 348 return ram; 349 } 350 351 /* Create an alias of an entire original MemoryRegion @orig 352 * located at @base in the memory map. 353 */ 354 static void make_ram_alias(MemoryRegion *mr, const char *name, 355 MemoryRegion *orig, hwaddr base) 356 { 357 memory_region_init_alias(mr, NULL, name, orig, 0, 358 memory_region_size(orig)); 359 memory_region_add_subregion(get_system_memory(), base, mr); 360 } 361 362 static qemu_irq get_sse_irq_in(MPS2TZMachineState *mms, int irqno) 363 { 364 /* 365 * Return a qemu_irq which will signal IRQ n to all CPUs in the 366 * SSE. The irqno should be as the CPU sees it, so the first 367 * external-to-the-SSE interrupt is 32. 368 */ 369 MachineClass *mc = MACHINE_GET_CLASS(mms); 370 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); 371 372 assert(irqno >= 32 && irqno < (mmc->numirq + 32)); 373 374 /* 375 * Convert from "CPU irq number" (as listed in the FPGA image 376 * documentation) to the SSE external-interrupt number. 377 */ 378 irqno -= 32; 379 380 if (mc->max_cpus > 1) { 381 return qdev_get_gpio_in(DEVICE(&mms->cpu_irq_splitter[irqno]), 0); 382 } else { 383 return qdev_get_gpio_in_named(DEVICE(&mms->iotkit), "EXP_IRQ", irqno); 384 } 385 } 386 387 /* Most of the devices in the AN505 FPGA image sit behind 388 * Peripheral Protection Controllers. These data structures 389 * define the layout of which devices sit behind which PPCs. 390 * The devfn for each port is a function which creates, configures 391 * and initializes the device, returning the MemoryRegion which 392 * needs to be plugged into the downstream end of the PPC port. 393 */ 394 typedef MemoryRegion *MakeDevFn(MPS2TZMachineState *mms, void *opaque, 395 const char *name, hwaddr size, 396 const int *irqs); 397 398 typedef struct PPCPortInfo { 399 const char *name; 400 MakeDevFn *devfn; 401 void *opaque; 402 hwaddr addr; 403 hwaddr size; 404 int irqs[3]; /* currently no device needs more IRQ lines than this */ 405 } PPCPortInfo; 406 407 typedef struct PPCInfo { 408 const char *name; 409 PPCPortInfo ports[TZ_NUM_PORTS]; 410 } PPCInfo; 411 412 static MemoryRegion *make_unimp_dev(MPS2TZMachineState *mms, 413 void *opaque, 414 const char *name, hwaddr size, 415 const int *irqs) 416 { 417 /* Initialize, configure and realize a TYPE_UNIMPLEMENTED_DEVICE, 418 * and return a pointer to its MemoryRegion. 419 */ 420 UnimplementedDeviceState *uds = opaque; 421 422 object_initialize_child(OBJECT(mms), name, uds, TYPE_UNIMPLEMENTED_DEVICE); 423 qdev_prop_set_string(DEVICE(uds), "name", name); 424 qdev_prop_set_uint64(DEVICE(uds), "size", size); 425 sysbus_realize(SYS_BUS_DEVICE(uds), &error_fatal); 426 return sysbus_mmio_get_region(SYS_BUS_DEVICE(uds), 0); 427 } 428 429 static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque, 430 const char *name, hwaddr size, 431 const int *irqs) 432 { 433 /* The irq[] array is tx, rx, combined, in that order */ 434 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); 435 CMSDKAPBUART *uart = opaque; 436 int i = uart - &mms->uart[0]; 437 SysBusDevice *s; 438 DeviceState *orgate_dev = DEVICE(&mms->uart_irq_orgate); 439 440 object_initialize_child(OBJECT(mms), name, uart, TYPE_CMSDK_APB_UART); 441 qdev_prop_set_chr(DEVICE(uart), "chardev", serial_hd(i)); 442 qdev_prop_set_uint32(DEVICE(uart), "pclk-frq", mmc->apb_periph_frq); 443 sysbus_realize(SYS_BUS_DEVICE(uart), &error_fatal); 444 s = SYS_BUS_DEVICE(uart); 445 sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0])); 446 sysbus_connect_irq(s, 1, get_sse_irq_in(mms, irqs[1])); 447 sysbus_connect_irq(s, 2, qdev_get_gpio_in(orgate_dev, i * 2)); 448 sysbus_connect_irq(s, 3, qdev_get_gpio_in(orgate_dev, i * 2 + 1)); 449 sysbus_connect_irq(s, 4, get_sse_irq_in(mms, irqs[2])); 450 return sysbus_mmio_get_region(SYS_BUS_DEVICE(uart), 0); 451 } 452 453 static MemoryRegion *make_scc(MPS2TZMachineState *mms, void *opaque, 454 const char *name, hwaddr size, 455 const int *irqs) 456 { 457 MPS2SCC *scc = opaque; 458 DeviceState *sccdev; 459 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); 460 uint32_t i; 461 462 object_initialize_child(OBJECT(mms), "scc", scc, TYPE_MPS2_SCC); 463 sccdev = DEVICE(scc); 464 qdev_prop_set_uint32(sccdev, "scc-cfg0", mms->remap ? 1 : 0); 465 qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2); 466 qdev_prop_set_uint32(sccdev, "scc-aid", 0x00200008); 467 qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id); 468 qdev_prop_set_uint32(sccdev, "len-oscclk", mmc->len_oscclk); 469 for (i = 0; i < mmc->len_oscclk; i++) { 470 g_autofree char *propname = g_strdup_printf("oscclk[%u]", i); 471 qdev_prop_set_uint32(sccdev, propname, mmc->oscclk[i]); 472 } 473 sysbus_realize(SYS_BUS_DEVICE(scc), &error_fatal); 474 return sysbus_mmio_get_region(SYS_BUS_DEVICE(sccdev), 0); 475 } 476 477 static MemoryRegion *make_fpgaio(MPS2TZMachineState *mms, void *opaque, 478 const char *name, hwaddr size, 479 const int *irqs) 480 { 481 MPS2FPGAIO *fpgaio = opaque; 482 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); 483 484 object_initialize_child(OBJECT(mms), "fpgaio", fpgaio, TYPE_MPS2_FPGAIO); 485 qdev_prop_set_uint32(DEVICE(fpgaio), "num-leds", mmc->fpgaio_num_leds); 486 qdev_prop_set_bit(DEVICE(fpgaio), "has-switches", mmc->fpgaio_has_switches); 487 qdev_prop_set_bit(DEVICE(fpgaio), "has-dbgctrl", mmc->fpgaio_has_dbgctrl); 488 sysbus_realize(SYS_BUS_DEVICE(fpgaio), &error_fatal); 489 return sysbus_mmio_get_region(SYS_BUS_DEVICE(fpgaio), 0); 490 } 491 492 static MemoryRegion *make_eth_dev(MPS2TZMachineState *mms, void *opaque, 493 const char *name, hwaddr size, 494 const int *irqs) 495 { 496 SysBusDevice *s; 497 NICInfo *nd = &nd_table[0]; 498 499 /* In hardware this is a LAN9220; the LAN9118 is software compatible 500 * except that it doesn't support the checksum-offload feature. 501 */ 502 qemu_check_nic_model(nd, "lan9118"); 503 mms->lan9118 = qdev_new(TYPE_LAN9118); 504 qdev_set_nic_properties(mms->lan9118, nd); 505 506 s = SYS_BUS_DEVICE(mms->lan9118); 507 sysbus_realize_and_unref(s, &error_fatal); 508 sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0])); 509 return sysbus_mmio_get_region(s, 0); 510 } 511 512 static MemoryRegion *make_eth_usb(MPS2TZMachineState *mms, void *opaque, 513 const char *name, hwaddr size, 514 const int *irqs) 515 { 516 /* 517 * The AN524 makes the ethernet and USB share a PPC port. 518 * irqs[] is the ethernet IRQ. 519 */ 520 SysBusDevice *s; 521 NICInfo *nd = &nd_table[0]; 522 523 memory_region_init(&mms->eth_usb_container, OBJECT(mms), 524 "mps2-tz-eth-usb-container", 0x200000); 525 526 /* 527 * In hardware this is a LAN9220; the LAN9118 is software compatible 528 * except that it doesn't support the checksum-offload feature. 529 */ 530 qemu_check_nic_model(nd, "lan9118"); 531 mms->lan9118 = qdev_new(TYPE_LAN9118); 532 qdev_set_nic_properties(mms->lan9118, nd); 533 534 s = SYS_BUS_DEVICE(mms->lan9118); 535 sysbus_realize_and_unref(s, &error_fatal); 536 sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0])); 537 538 memory_region_add_subregion(&mms->eth_usb_container, 539 0, sysbus_mmio_get_region(s, 0)); 540 541 /* The USB OTG controller is an ISP1763; we don't have a model of it. */ 542 object_initialize_child(OBJECT(mms), "usb-otg", 543 &mms->usb, TYPE_UNIMPLEMENTED_DEVICE); 544 qdev_prop_set_string(DEVICE(&mms->usb), "name", "usb-otg"); 545 qdev_prop_set_uint64(DEVICE(&mms->usb), "size", 0x100000); 546 s = SYS_BUS_DEVICE(&mms->usb); 547 sysbus_realize(s, &error_fatal); 548 549 memory_region_add_subregion(&mms->eth_usb_container, 550 0x100000, sysbus_mmio_get_region(s, 0)); 551 552 return &mms->eth_usb_container; 553 } 554 555 static MemoryRegion *make_mpc(MPS2TZMachineState *mms, void *opaque, 556 const char *name, hwaddr size, 557 const int *irqs) 558 { 559 TZMPC *mpc = opaque; 560 int i = mpc - &mms->mpc[0]; 561 MemoryRegion *upstream; 562 const RAMInfo *raminfo = find_raminfo_for_mpc(mms, i); 563 MemoryRegion *ram = mr_for_raminfo(mms, raminfo); 564 565 object_initialize_child(OBJECT(mms), name, mpc, TYPE_TZ_MPC); 566 object_property_set_link(OBJECT(mpc), "downstream", OBJECT(ram), 567 &error_fatal); 568 sysbus_realize(SYS_BUS_DEVICE(mpc), &error_fatal); 569 /* Map the upstream end of the MPC into system memory */ 570 upstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 1); 571 memory_region_add_subregion(get_system_memory(), raminfo->base, upstream); 572 /* and connect its interrupt to the IoTKit */ 573 qdev_connect_gpio_out_named(DEVICE(mpc), "irq", 0, 574 qdev_get_gpio_in_named(DEVICE(&mms->iotkit), 575 "mpcexp_status", i)); 576 577 /* Return the register interface MR for our caller to map behind the PPC */ 578 return sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 0); 579 } 580 581 static hwaddr boot_mem_base(MPS2TZMachineState *mms) 582 { 583 /* 584 * Return the canonical address of the block which will be mapped 585 * at address 0x0 (i.e. where the vector table is). 586 * This is usually 0, but if the AN524 alternate memory map is 587 * enabled it will be the base address of the QSPI block. 588 */ 589 return mms->remap ? 0x28000000 : 0; 590 } 591 592 static void remap_memory(MPS2TZMachineState *mms, int map) 593 { 594 /* 595 * Remap the memory for the AN524. 'map' is the value of 596 * SCC CFG_REG0 bit 0, i.e. 0 for the default map and 1 597 * for the "option 1" mapping where QSPI is at address 0. 598 * 599 * Effectively we need to swap around the "upstream" ends of 600 * MPC 0 and MPC 1. 601 */ 602 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); 603 int i; 604 605 if (mmc->fpga_type != FPGA_AN524) { 606 return; 607 } 608 609 memory_region_transaction_begin(); 610 for (i = 0; i < 2; i++) { 611 TZMPC *mpc = &mms->mpc[i]; 612 MemoryRegion *upstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 1); 613 hwaddr addr = (i ^ map) ? 0x28000000 : 0; 614 615 memory_region_set_address(upstream, addr); 616 } 617 memory_region_transaction_commit(); 618 } 619 620 static void remap_irq_fn(void *opaque, int n, int level) 621 { 622 MPS2TZMachineState *mms = opaque; 623 624 remap_memory(mms, level); 625 } 626 627 static MemoryRegion *make_dma(MPS2TZMachineState *mms, void *opaque, 628 const char *name, hwaddr size, 629 const int *irqs) 630 { 631 /* The irq[] array is DMACINTR, DMACINTERR, DMACINTTC, in that order */ 632 PL080State *dma = opaque; 633 int i = dma - &mms->dma[0]; 634 SysBusDevice *s; 635 char *mscname = g_strdup_printf("%s-msc", name); 636 TZMSC *msc = &mms->msc[i]; 637 DeviceState *iotkitdev = DEVICE(&mms->iotkit); 638 MemoryRegion *msc_upstream; 639 MemoryRegion *msc_downstream; 640 641 /* 642 * Each DMA device is a PL081 whose transaction master interface 643 * is guarded by a Master Security Controller. The downstream end of 644 * the MSC connects to the IoTKit AHB Slave Expansion port, so the 645 * DMA devices can see all devices and memory that the CPU does. 646 */ 647 object_initialize_child(OBJECT(mms), mscname, msc, TYPE_TZ_MSC); 648 msc_downstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(&mms->iotkit), 0); 649 object_property_set_link(OBJECT(msc), "downstream", 650 OBJECT(msc_downstream), &error_fatal); 651 object_property_set_link(OBJECT(msc), "idau", OBJECT(mms), &error_fatal); 652 sysbus_realize(SYS_BUS_DEVICE(msc), &error_fatal); 653 654 qdev_connect_gpio_out_named(DEVICE(msc), "irq", 0, 655 qdev_get_gpio_in_named(iotkitdev, 656 "mscexp_status", i)); 657 qdev_connect_gpio_out_named(iotkitdev, "mscexp_clear", i, 658 qdev_get_gpio_in_named(DEVICE(msc), 659 "irq_clear", 0)); 660 qdev_connect_gpio_out_named(iotkitdev, "mscexp_ns", i, 661 qdev_get_gpio_in_named(DEVICE(msc), 662 "cfg_nonsec", 0)); 663 qdev_connect_gpio_out(DEVICE(&mms->sec_resp_splitter), 664 ARRAY_SIZE(mms->ppc) + i, 665 qdev_get_gpio_in_named(DEVICE(msc), 666 "cfg_sec_resp", 0)); 667 msc_upstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(msc), 0); 668 669 object_initialize_child(OBJECT(mms), name, dma, TYPE_PL081); 670 object_property_set_link(OBJECT(dma), "downstream", OBJECT(msc_upstream), 671 &error_fatal); 672 sysbus_realize(SYS_BUS_DEVICE(dma), &error_fatal); 673 674 s = SYS_BUS_DEVICE(dma); 675 /* Wire up DMACINTR, DMACINTERR, DMACINTTC */ 676 sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0])); 677 sysbus_connect_irq(s, 1, get_sse_irq_in(mms, irqs[1])); 678 sysbus_connect_irq(s, 2, get_sse_irq_in(mms, irqs[2])); 679 680 g_free(mscname); 681 return sysbus_mmio_get_region(s, 0); 682 } 683 684 static MemoryRegion *make_spi(MPS2TZMachineState *mms, void *opaque, 685 const char *name, hwaddr size, 686 const int *irqs) 687 { 688 /* 689 * The AN505 has five PL022 SPI controllers. 690 * One of these should have the LCD controller behind it; the others 691 * are connected only to the FPGA's "general purpose SPI connector" 692 * or "shield" expansion connectors. 693 * Note that if we do implement devices behind SPI, the chip select 694 * lines are set via the "MISC" register in the MPS2 FPGAIO device. 695 */ 696 PL022State *spi = opaque; 697 SysBusDevice *s; 698 699 object_initialize_child(OBJECT(mms), name, spi, TYPE_PL022); 700 sysbus_realize(SYS_BUS_DEVICE(spi), &error_fatal); 701 s = SYS_BUS_DEVICE(spi); 702 sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0])); 703 return sysbus_mmio_get_region(s, 0); 704 } 705 706 static MemoryRegion *make_i2c(MPS2TZMachineState *mms, void *opaque, 707 const char *name, hwaddr size, 708 const int *irqs) 709 { 710 ArmSbconI2CState *i2c = opaque; 711 SysBusDevice *s; 712 713 object_initialize_child(OBJECT(mms), name, i2c, TYPE_ARM_SBCON_I2C); 714 s = SYS_BUS_DEVICE(i2c); 715 sysbus_realize(s, &error_fatal); 716 return sysbus_mmio_get_region(s, 0); 717 } 718 719 static MemoryRegion *make_rtc(MPS2TZMachineState *mms, void *opaque, 720 const char *name, hwaddr size, 721 const int *irqs) 722 { 723 PL031State *pl031 = opaque; 724 SysBusDevice *s; 725 726 object_initialize_child(OBJECT(mms), name, pl031, TYPE_PL031); 727 s = SYS_BUS_DEVICE(pl031); 728 sysbus_realize(s, &error_fatal); 729 /* 730 * The board docs don't give an IRQ number for the PL031, so 731 * presumably it is not connected. 732 */ 733 return sysbus_mmio_get_region(s, 0); 734 } 735 736 static void create_non_mpc_ram(MPS2TZMachineState *mms) 737 { 738 /* 739 * Handle the RAMs which are either not behind MPCs or which are 740 * aliases to another MPC. 741 */ 742 const RAMInfo *p; 743 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); 744 745 for (p = mmc->raminfo; p->name; p++) { 746 if (p->flags & IS_ALIAS) { 747 SysBusDevice *mpc_sbd = SYS_BUS_DEVICE(&mms->mpc[p->mpc]); 748 MemoryRegion *upstream = sysbus_mmio_get_region(mpc_sbd, 1); 749 make_ram_alias(&mms->ram[p->mrindex], p->name, upstream, p->base); 750 } else if (p->mpc == -1) { 751 /* RAM not behind an MPC */ 752 MemoryRegion *mr = mr_for_raminfo(mms, p); 753 memory_region_add_subregion(get_system_memory(), p->base, mr); 754 } 755 } 756 } 757 758 static uint32_t boot_ram_size(MPS2TZMachineState *mms) 759 { 760 /* Return the size of the RAM block at guest address zero */ 761 const RAMInfo *p; 762 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); 763 764 for (p = mmc->raminfo; p->name; p++) { 765 if (p->base == boot_mem_base(mms)) { 766 return p->size; 767 } 768 } 769 g_assert_not_reached(); 770 } 771 772 static void mps2tz_common_init(MachineState *machine) 773 { 774 MPS2TZMachineState *mms = MPS2TZ_MACHINE(machine); 775 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); 776 MachineClass *mc = MACHINE_GET_CLASS(machine); 777 MemoryRegion *system_memory = get_system_memory(); 778 DeviceState *iotkitdev; 779 DeviceState *dev_splitter; 780 const PPCInfo *ppcs; 781 int num_ppcs; 782 int i; 783 784 if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) { 785 error_report("This board can only be used with CPU %s", 786 mc->default_cpu_type); 787 exit(1); 788 } 789 790 if (machine->ram_size != mc->default_ram_size) { 791 char *sz = size_to_str(mc->default_ram_size); 792 error_report("Invalid RAM size, should be %s", sz); 793 g_free(sz); 794 exit(EXIT_FAILURE); 795 } 796 797 /* These clocks don't need migration because they are fixed-frequency */ 798 mms->sysclk = clock_new(OBJECT(machine), "SYSCLK"); 799 clock_set_hz(mms->sysclk, mmc->sysclk_frq); 800 mms->s32kclk = clock_new(OBJECT(machine), "S32KCLK"); 801 clock_set_hz(mms->s32kclk, S32KCLK_FRQ); 802 803 object_initialize_child(OBJECT(machine), TYPE_IOTKIT, &mms->iotkit, 804 mmc->armsse_type); 805 iotkitdev = DEVICE(&mms->iotkit); 806 object_property_set_link(OBJECT(&mms->iotkit), "memory", 807 OBJECT(system_memory), &error_abort); 808 qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", mmc->numirq); 809 qdev_prop_set_uint32(iotkitdev, "init-svtor", mmc->init_svtor); 810 qdev_prop_set_uint32(iotkitdev, "SRAM_ADDR_WIDTH", mmc->sram_addr_width); 811 qdev_connect_clock_in(iotkitdev, "MAINCLK", mms->sysclk); 812 qdev_connect_clock_in(iotkitdev, "S32KCLK", mms->s32kclk); 813 sysbus_realize(SYS_BUS_DEVICE(&mms->iotkit), &error_fatal); 814 815 /* 816 * If this board has more than one CPU, then we need to create splitters 817 * to feed the IRQ inputs for each CPU in the SSE from each device in the 818 * board. If there is only one CPU, we can just wire the device IRQ 819 * directly to the SSE's IRQ input. 820 */ 821 assert(mmc->numirq <= MPS2TZ_NUMIRQ_MAX); 822 if (mc->max_cpus > 1) { 823 for (i = 0; i < mmc->numirq; i++) { 824 char *name = g_strdup_printf("mps2-irq-splitter%d", i); 825 SplitIRQ *splitter = &mms->cpu_irq_splitter[i]; 826 827 object_initialize_child_with_props(OBJECT(machine), name, 828 splitter, sizeof(*splitter), 829 TYPE_SPLIT_IRQ, &error_fatal, 830 NULL); 831 g_free(name); 832 833 object_property_set_int(OBJECT(splitter), "num-lines", 2, 834 &error_fatal); 835 qdev_realize(DEVICE(splitter), NULL, &error_fatal); 836 qdev_connect_gpio_out(DEVICE(splitter), 0, 837 qdev_get_gpio_in_named(DEVICE(&mms->iotkit), 838 "EXP_IRQ", i)); 839 qdev_connect_gpio_out(DEVICE(splitter), 1, 840 qdev_get_gpio_in_named(DEVICE(&mms->iotkit), 841 "EXP_CPU1_IRQ", i)); 842 } 843 } 844 845 /* The sec_resp_cfg output from the IoTKit must be split into multiple 846 * lines, one for each of the PPCs we create here, plus one per MSC. 847 */ 848 object_initialize_child(OBJECT(machine), "sec-resp-splitter", 849 &mms->sec_resp_splitter, TYPE_SPLIT_IRQ); 850 object_property_set_int(OBJECT(&mms->sec_resp_splitter), "num-lines", 851 ARRAY_SIZE(mms->ppc) + ARRAY_SIZE(mms->msc), 852 &error_fatal); 853 qdev_realize(DEVICE(&mms->sec_resp_splitter), NULL, &error_fatal); 854 dev_splitter = DEVICE(&mms->sec_resp_splitter); 855 qdev_connect_gpio_out_named(iotkitdev, "sec_resp_cfg", 0, 856 qdev_get_gpio_in(dev_splitter, 0)); 857 858 /* 859 * The IoTKit sets up much of the memory layout, including 860 * the aliases between secure and non-secure regions in the 861 * address space, and also most of the devices in the system. 862 * The FPGA itself contains various RAMs and some additional devices. 863 * The FPGA images have an odd combination of different RAMs, 864 * because in hardware they are different implementations and 865 * connected to different buses, giving varying performance/size 866 * tradeoffs. For QEMU they're all just RAM, though. We arbitrarily 867 * call the largest lump our "system memory". 868 */ 869 870 /* 871 * The overflow IRQs for all UARTs are ORed together. 872 * Tx, Rx and "combined" IRQs are sent to the NVIC separately. 873 * Create the OR gate for this: it has one input for the TX overflow 874 * and one for the RX overflow for each UART we might have. 875 * (If the board has fewer than the maximum possible number of UARTs 876 * those inputs are never wired up and are treated as always-zero.) 877 */ 878 object_initialize_child(OBJECT(mms), "uart-irq-orgate", 879 &mms->uart_irq_orgate, TYPE_OR_IRQ); 880 object_property_set_int(OBJECT(&mms->uart_irq_orgate), "num-lines", 881 2 * ARRAY_SIZE(mms->uart), 882 &error_fatal); 883 qdev_realize(DEVICE(&mms->uart_irq_orgate), NULL, &error_fatal); 884 qdev_connect_gpio_out(DEVICE(&mms->uart_irq_orgate), 0, 885 get_sse_irq_in(mms, mmc->uart_overflow_irq)); 886 887 /* Most of the devices in the FPGA are behind Peripheral Protection 888 * Controllers. The required order for initializing things is: 889 * + initialize the PPC 890 * + initialize, configure and realize downstream devices 891 * + connect downstream device MemoryRegions to the PPC 892 * + realize the PPC 893 * + map the PPC's MemoryRegions to the places in the address map 894 * where the downstream devices should appear 895 * + wire up the PPC's control lines to the IoTKit object 896 */ 897 898 const PPCInfo an505_ppcs[] = { { 899 .name = "apb_ppcexp0", 900 .ports = { 901 { "ssram-0-mpc", make_mpc, &mms->mpc[0], 0x58007000, 0x1000 }, 902 { "ssram-1-mpc", make_mpc, &mms->mpc[1], 0x58008000, 0x1000 }, 903 { "ssram-2-mpc", make_mpc, &mms->mpc[2], 0x58009000, 0x1000 }, 904 }, 905 }, { 906 .name = "apb_ppcexp1", 907 .ports = { 908 { "spi0", make_spi, &mms->spi[0], 0x40205000, 0x1000, { 51 } }, 909 { "spi1", make_spi, &mms->spi[1], 0x40206000, 0x1000, { 52 } }, 910 { "spi2", make_spi, &mms->spi[2], 0x40209000, 0x1000, { 53 } }, 911 { "spi3", make_spi, &mms->spi[3], 0x4020a000, 0x1000, { 54 } }, 912 { "spi4", make_spi, &mms->spi[4], 0x4020b000, 0x1000, { 55 } }, 913 { "uart0", make_uart, &mms->uart[0], 0x40200000, 0x1000, { 32, 33, 42 } }, 914 { "uart1", make_uart, &mms->uart[1], 0x40201000, 0x1000, { 34, 35, 43 } }, 915 { "uart2", make_uart, &mms->uart[2], 0x40202000, 0x1000, { 36, 37, 44 } }, 916 { "uart3", make_uart, &mms->uart[3], 0x40203000, 0x1000, { 38, 39, 45 } }, 917 { "uart4", make_uart, &mms->uart[4], 0x40204000, 0x1000, { 40, 41, 46 } }, 918 { "i2c0", make_i2c, &mms->i2c[0], 0x40207000, 0x1000 }, 919 { "i2c1", make_i2c, &mms->i2c[1], 0x40208000, 0x1000 }, 920 { "i2c2", make_i2c, &mms->i2c[2], 0x4020c000, 0x1000 }, 921 { "i2c3", make_i2c, &mms->i2c[3], 0x4020d000, 0x1000 }, 922 }, 923 }, { 924 .name = "apb_ppcexp2", 925 .ports = { 926 { "scc", make_scc, &mms->scc, 0x40300000, 0x1000 }, 927 { "i2s-audio", make_unimp_dev, &mms->i2s_audio, 928 0x40301000, 0x1000 }, 929 { "fpgaio", make_fpgaio, &mms->fpgaio, 0x40302000, 0x1000 }, 930 }, 931 }, { 932 .name = "ahb_ppcexp0", 933 .ports = { 934 { "gfx", make_unimp_dev, &mms->gfx, 0x41000000, 0x140000 }, 935 { "gpio0", make_unimp_dev, &mms->gpio[0], 0x40100000, 0x1000 }, 936 { "gpio1", make_unimp_dev, &mms->gpio[1], 0x40101000, 0x1000 }, 937 { "gpio2", make_unimp_dev, &mms->gpio[2], 0x40102000, 0x1000 }, 938 { "gpio3", make_unimp_dev, &mms->gpio[3], 0x40103000, 0x1000 }, 939 { "eth", make_eth_dev, NULL, 0x42000000, 0x100000, { 48 } }, 940 }, 941 }, { 942 .name = "ahb_ppcexp1", 943 .ports = { 944 { "dma0", make_dma, &mms->dma[0], 0x40110000, 0x1000, { 58, 56, 57 } }, 945 { "dma1", make_dma, &mms->dma[1], 0x40111000, 0x1000, { 61, 59, 60 } }, 946 { "dma2", make_dma, &mms->dma[2], 0x40112000, 0x1000, { 64, 62, 63 } }, 947 { "dma3", make_dma, &mms->dma[3], 0x40113000, 0x1000, { 67, 65, 66 } }, 948 }, 949 }, 950 }; 951 952 const PPCInfo an524_ppcs[] = { { 953 .name = "apb_ppcexp0", 954 .ports = { 955 { "bram-mpc", make_mpc, &mms->mpc[0], 0x58007000, 0x1000 }, 956 { "qspi-mpc", make_mpc, &mms->mpc[1], 0x58008000, 0x1000 }, 957 { "ddr-mpc", make_mpc, &mms->mpc[2], 0x58009000, 0x1000 }, 958 }, 959 }, { 960 .name = "apb_ppcexp1", 961 .ports = { 962 { "i2c0", make_i2c, &mms->i2c[0], 0x41200000, 0x1000 }, 963 { "i2c1", make_i2c, &mms->i2c[1], 0x41201000, 0x1000 }, 964 { "spi0", make_spi, &mms->spi[0], 0x41202000, 0x1000, { 52 } }, 965 { "spi1", make_spi, &mms->spi[1], 0x41203000, 0x1000, { 53 } }, 966 { "spi2", make_spi, &mms->spi[2], 0x41204000, 0x1000, { 54 } }, 967 { "i2c2", make_i2c, &mms->i2c[2], 0x41205000, 0x1000 }, 968 { "i2c3", make_i2c, &mms->i2c[3], 0x41206000, 0x1000 }, 969 { /* port 7 reserved */ }, 970 { "i2c4", make_i2c, &mms->i2c[4], 0x41208000, 0x1000 }, 971 }, 972 }, { 973 .name = "apb_ppcexp2", 974 .ports = { 975 { "scc", make_scc, &mms->scc, 0x41300000, 0x1000 }, 976 { "i2s-audio", make_unimp_dev, &mms->i2s_audio, 977 0x41301000, 0x1000 }, 978 { "fpgaio", make_fpgaio, &mms->fpgaio, 0x41302000, 0x1000 }, 979 { "uart0", make_uart, &mms->uart[0], 0x41303000, 0x1000, { 32, 33, 42 } }, 980 { "uart1", make_uart, &mms->uart[1], 0x41304000, 0x1000, { 34, 35, 43 } }, 981 { "uart2", make_uart, &mms->uart[2], 0x41305000, 0x1000, { 36, 37, 44 } }, 982 { "uart3", make_uart, &mms->uart[3], 0x41306000, 0x1000, { 38, 39, 45 } }, 983 { "uart4", make_uart, &mms->uart[4], 0x41307000, 0x1000, { 40, 41, 46 } }, 984 { "uart5", make_uart, &mms->uart[5], 0x41308000, 0x1000, { 124, 125, 126 } }, 985 986 { /* port 9 reserved */ }, 987 { "clcd", make_unimp_dev, &mms->cldc, 0x4130a000, 0x1000 }, 988 { "rtc", make_rtc, &mms->rtc, 0x4130b000, 0x1000 }, 989 }, 990 }, { 991 .name = "ahb_ppcexp0", 992 .ports = { 993 { "gpio0", make_unimp_dev, &mms->gpio[0], 0x41100000, 0x1000 }, 994 { "gpio1", make_unimp_dev, &mms->gpio[1], 0x41101000, 0x1000 }, 995 { "gpio2", make_unimp_dev, &mms->gpio[2], 0x41102000, 0x1000 }, 996 { "gpio3", make_unimp_dev, &mms->gpio[3], 0x41103000, 0x1000 }, 997 { "eth-usb", make_eth_usb, NULL, 0x41400000, 0x200000, { 48 } }, 998 }, 999 }, 1000 }; 1001 1002 const PPCInfo an547_ppcs[] = { { 1003 .name = "apb_ppcexp0", 1004 .ports = { 1005 { "ssram-mpc", make_mpc, &mms->mpc[0], 0x57000000, 0x1000 }, 1006 { "qspi-mpc", make_mpc, &mms->mpc[1], 0x57001000, 0x1000 }, 1007 { "ddr-mpc", make_mpc, &mms->mpc[2], 0x57002000, 0x1000 }, 1008 }, 1009 }, { 1010 .name = "apb_ppcexp1", 1011 .ports = { 1012 { "i2c0", make_i2c, &mms->i2c[0], 0x49200000, 0x1000 }, 1013 { "i2c1", make_i2c, &mms->i2c[1], 0x49201000, 0x1000 }, 1014 { "spi0", make_spi, &mms->spi[0], 0x49202000, 0x1000, { 53 } }, 1015 { "spi1", make_spi, &mms->spi[1], 0x49203000, 0x1000, { 54 } }, 1016 { "spi2", make_spi, &mms->spi[2], 0x49204000, 0x1000, { 55 } }, 1017 { "i2c2", make_i2c, &mms->i2c[2], 0x49205000, 0x1000 }, 1018 { "i2c3", make_i2c, &mms->i2c[3], 0x49206000, 0x1000 }, 1019 { /* port 7 reserved */ }, 1020 { "i2c4", make_i2c, &mms->i2c[4], 0x49208000, 0x1000 }, 1021 }, 1022 }, { 1023 .name = "apb_ppcexp2", 1024 .ports = { 1025 { "scc", make_scc, &mms->scc, 0x49300000, 0x1000 }, 1026 { "i2s-audio", make_unimp_dev, &mms->i2s_audio, 0x49301000, 0x1000 }, 1027 { "fpgaio", make_fpgaio, &mms->fpgaio, 0x49302000, 0x1000 }, 1028 { "uart0", make_uart, &mms->uart[0], 0x49303000, 0x1000, { 33, 34, 43 } }, 1029 { "uart1", make_uart, &mms->uart[1], 0x49304000, 0x1000, { 35, 36, 44 } }, 1030 { "uart2", make_uart, &mms->uart[2], 0x49305000, 0x1000, { 37, 38, 45 } }, 1031 { "uart3", make_uart, &mms->uart[3], 0x49306000, 0x1000, { 39, 40, 46 } }, 1032 { "uart4", make_uart, &mms->uart[4], 0x49307000, 0x1000, { 41, 42, 47 } }, 1033 { "uart5", make_uart, &mms->uart[5], 0x49308000, 0x1000, { 125, 126, 127 } }, 1034 1035 { /* port 9 reserved */ }, 1036 { "clcd", make_unimp_dev, &mms->cldc, 0x4930a000, 0x1000 }, 1037 { "rtc", make_rtc, &mms->rtc, 0x4930b000, 0x1000 }, 1038 }, 1039 }, { 1040 .name = "ahb_ppcexp0", 1041 .ports = { 1042 { "gpio0", make_unimp_dev, &mms->gpio[0], 0x41100000, 0x1000 }, 1043 { "gpio1", make_unimp_dev, &mms->gpio[1], 0x41101000, 0x1000 }, 1044 { "gpio2", make_unimp_dev, &mms->gpio[2], 0x41102000, 0x1000 }, 1045 { "gpio3", make_unimp_dev, &mms->gpio[3], 0x41103000, 0x1000 }, 1046 { "eth-usb", make_eth_usb, NULL, 0x41400000, 0x200000, { 49 } }, 1047 }, 1048 }, 1049 }; 1050 1051 switch (mmc->fpga_type) { 1052 case FPGA_AN505: 1053 case FPGA_AN521: 1054 ppcs = an505_ppcs; 1055 num_ppcs = ARRAY_SIZE(an505_ppcs); 1056 break; 1057 case FPGA_AN524: 1058 ppcs = an524_ppcs; 1059 num_ppcs = ARRAY_SIZE(an524_ppcs); 1060 break; 1061 case FPGA_AN547: 1062 ppcs = an547_ppcs; 1063 num_ppcs = ARRAY_SIZE(an547_ppcs); 1064 break; 1065 default: 1066 g_assert_not_reached(); 1067 } 1068 1069 for (i = 0; i < num_ppcs; i++) { 1070 const PPCInfo *ppcinfo = &ppcs[i]; 1071 TZPPC *ppc = &mms->ppc[i]; 1072 DeviceState *ppcdev; 1073 int port; 1074 char *gpioname; 1075 1076 object_initialize_child(OBJECT(machine), ppcinfo->name, ppc, 1077 TYPE_TZ_PPC); 1078 ppcdev = DEVICE(ppc); 1079 1080 for (port = 0; port < TZ_NUM_PORTS; port++) { 1081 const PPCPortInfo *pinfo = &ppcinfo->ports[port]; 1082 MemoryRegion *mr; 1083 char *portname; 1084 1085 if (!pinfo->devfn) { 1086 continue; 1087 } 1088 1089 mr = pinfo->devfn(mms, pinfo->opaque, pinfo->name, pinfo->size, 1090 pinfo->irqs); 1091 portname = g_strdup_printf("port[%d]", port); 1092 object_property_set_link(OBJECT(ppc), portname, OBJECT(mr), 1093 &error_fatal); 1094 g_free(portname); 1095 } 1096 1097 sysbus_realize(SYS_BUS_DEVICE(ppc), &error_fatal); 1098 1099 for (port = 0; port < TZ_NUM_PORTS; port++) { 1100 const PPCPortInfo *pinfo = &ppcinfo->ports[port]; 1101 1102 if (!pinfo->devfn) { 1103 continue; 1104 } 1105 sysbus_mmio_map(SYS_BUS_DEVICE(ppc), port, pinfo->addr); 1106 1107 gpioname = g_strdup_printf("%s_nonsec", ppcinfo->name); 1108 qdev_connect_gpio_out_named(iotkitdev, gpioname, port, 1109 qdev_get_gpio_in_named(ppcdev, 1110 "cfg_nonsec", 1111 port)); 1112 g_free(gpioname); 1113 gpioname = g_strdup_printf("%s_ap", ppcinfo->name); 1114 qdev_connect_gpio_out_named(iotkitdev, gpioname, port, 1115 qdev_get_gpio_in_named(ppcdev, 1116 "cfg_ap", port)); 1117 g_free(gpioname); 1118 } 1119 1120 gpioname = g_strdup_printf("%s_irq_enable", ppcinfo->name); 1121 qdev_connect_gpio_out_named(iotkitdev, gpioname, 0, 1122 qdev_get_gpio_in_named(ppcdev, 1123 "irq_enable", 0)); 1124 g_free(gpioname); 1125 gpioname = g_strdup_printf("%s_irq_clear", ppcinfo->name); 1126 qdev_connect_gpio_out_named(iotkitdev, gpioname, 0, 1127 qdev_get_gpio_in_named(ppcdev, 1128 "irq_clear", 0)); 1129 g_free(gpioname); 1130 gpioname = g_strdup_printf("%s_irq_status", ppcinfo->name); 1131 qdev_connect_gpio_out_named(ppcdev, "irq", 0, 1132 qdev_get_gpio_in_named(iotkitdev, 1133 gpioname, 0)); 1134 g_free(gpioname); 1135 1136 qdev_connect_gpio_out(dev_splitter, i, 1137 qdev_get_gpio_in_named(ppcdev, 1138 "cfg_sec_resp", 0)); 1139 } 1140 1141 create_unimplemented_device("FPGA NS PC", 0x48007000, 0x1000); 1142 1143 if (mmc->fpga_type == FPGA_AN547) { 1144 create_unimplemented_device("U55 timing adapter 0", 0x48102000, 0x1000); 1145 create_unimplemented_device("U55 timing adapter 1", 0x48103000, 0x1000); 1146 } 1147 1148 create_non_mpc_ram(mms); 1149 1150 if (mmc->fpga_type == FPGA_AN524) { 1151 /* 1152 * Connect the line from the SCC so that we can remap when the 1153 * guest updates that register. 1154 */ 1155 mms->remap_irq = qemu_allocate_irq(remap_irq_fn, mms, 0); 1156 qdev_connect_gpio_out_named(DEVICE(&mms->scc), "remap", 0, 1157 mms->remap_irq); 1158 } 1159 1160 armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 1161 boot_ram_size(mms)); 1162 } 1163 1164 static void mps2_tz_idau_check(IDAUInterface *ii, uint32_t address, 1165 int *iregion, bool *exempt, bool *ns, bool *nsc) 1166 { 1167 /* 1168 * The MPS2 TZ FPGA images have IDAUs in them which are connected to 1169 * the Master Security Controllers. Thes have the same logic as 1170 * is used by the IoTKit for the IDAU connected to the CPU, except 1171 * that MSCs don't care about the NSC attribute. 1172 */ 1173 int region = extract32(address, 28, 4); 1174 1175 *ns = !(region & 1); 1176 *nsc = false; 1177 /* 0xe0000000..0xe00fffff and 0xf0000000..0xf00fffff are exempt */ 1178 *exempt = (address & 0xeff00000) == 0xe0000000; 1179 *iregion = region; 1180 } 1181 1182 static char *mps2_get_remap(Object *obj, Error **errp) 1183 { 1184 MPS2TZMachineState *mms = MPS2TZ_MACHINE(obj); 1185 const char *val = mms->remap ? "QSPI" : "BRAM"; 1186 return g_strdup(val); 1187 } 1188 1189 static void mps2_set_remap(Object *obj, const char *value, Error **errp) 1190 { 1191 MPS2TZMachineState *mms = MPS2TZ_MACHINE(obj); 1192 1193 if (!strcmp(value, "BRAM")) { 1194 mms->remap = false; 1195 } else if (!strcmp(value, "QSPI")) { 1196 mms->remap = true; 1197 } else { 1198 error_setg(errp, "Invalid remap value"); 1199 error_append_hint(errp, "Valid values are BRAM and QSPI.\n"); 1200 } 1201 } 1202 1203 static void mps2_machine_reset(MachineState *machine) 1204 { 1205 MPS2TZMachineState *mms = MPS2TZ_MACHINE(machine); 1206 1207 /* 1208 * Set the initial memory mapping before triggering the reset of 1209 * the rest of the system, so that the guest image loader and CPU 1210 * reset see the correct mapping. 1211 */ 1212 remap_memory(mms, mms->remap); 1213 qemu_devices_reset(); 1214 } 1215 1216 static void mps2tz_class_init(ObjectClass *oc, void *data) 1217 { 1218 MachineClass *mc = MACHINE_CLASS(oc); 1219 IDAUInterfaceClass *iic = IDAU_INTERFACE_CLASS(oc); 1220 1221 mc->init = mps2tz_common_init; 1222 mc->reset = mps2_machine_reset; 1223 iic->check = mps2_tz_idau_check; 1224 } 1225 1226 static void mps2tz_set_default_ram_info(MPS2TZMachineClass *mmc) 1227 { 1228 /* 1229 * Set mc->default_ram_size and default_ram_id from the 1230 * information in mmc->raminfo. 1231 */ 1232 MachineClass *mc = MACHINE_CLASS(mmc); 1233 const RAMInfo *p; 1234 1235 for (p = mmc->raminfo; p->name; p++) { 1236 if (p->mrindex < 0) { 1237 /* Found the entry for "system memory" */ 1238 mc->default_ram_size = p->size; 1239 mc->default_ram_id = p->name; 1240 return; 1241 } 1242 } 1243 g_assert_not_reached(); 1244 } 1245 1246 static void mps2tz_an505_class_init(ObjectClass *oc, void *data) 1247 { 1248 MachineClass *mc = MACHINE_CLASS(oc); 1249 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc); 1250 1251 mc->desc = "ARM MPS2 with AN505 FPGA image for Cortex-M33"; 1252 mc->default_cpus = 1; 1253 mc->min_cpus = mc->default_cpus; 1254 mc->max_cpus = mc->default_cpus; 1255 mmc->fpga_type = FPGA_AN505; 1256 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"); 1257 mmc->scc_id = 0x41045050; 1258 mmc->sysclk_frq = 20 * 1000 * 1000; /* 20MHz */ 1259 mmc->apb_periph_frq = mmc->sysclk_frq; 1260 mmc->oscclk = an505_oscclk; 1261 mmc->len_oscclk = ARRAY_SIZE(an505_oscclk); 1262 mmc->fpgaio_num_leds = 2; 1263 mmc->fpgaio_has_switches = false; 1264 mmc->fpgaio_has_dbgctrl = false; 1265 mmc->numirq = 92; 1266 mmc->uart_overflow_irq = 47; 1267 mmc->init_svtor = 0x10000000; 1268 mmc->sram_addr_width = 15; 1269 mmc->raminfo = an505_raminfo; 1270 mmc->armsse_type = TYPE_IOTKIT; 1271 mps2tz_set_default_ram_info(mmc); 1272 } 1273 1274 static void mps2tz_an521_class_init(ObjectClass *oc, void *data) 1275 { 1276 MachineClass *mc = MACHINE_CLASS(oc); 1277 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc); 1278 1279 mc->desc = "ARM MPS2 with AN521 FPGA image for dual Cortex-M33"; 1280 mc->default_cpus = 2; 1281 mc->min_cpus = mc->default_cpus; 1282 mc->max_cpus = mc->default_cpus; 1283 mmc->fpga_type = FPGA_AN521; 1284 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"); 1285 mmc->scc_id = 0x41045210; 1286 mmc->sysclk_frq = 20 * 1000 * 1000; /* 20MHz */ 1287 mmc->apb_periph_frq = mmc->sysclk_frq; 1288 mmc->oscclk = an505_oscclk; /* AN521 is the same as AN505 here */ 1289 mmc->len_oscclk = ARRAY_SIZE(an505_oscclk); 1290 mmc->fpgaio_num_leds = 2; 1291 mmc->fpgaio_has_switches = false; 1292 mmc->fpgaio_has_dbgctrl = false; 1293 mmc->numirq = 92; 1294 mmc->uart_overflow_irq = 47; 1295 mmc->init_svtor = 0x10000000; 1296 mmc->sram_addr_width = 15; 1297 mmc->raminfo = an505_raminfo; /* AN521 is the same as AN505 here */ 1298 mmc->armsse_type = TYPE_SSE200; 1299 mps2tz_set_default_ram_info(mmc); 1300 } 1301 1302 static void mps3tz_an524_class_init(ObjectClass *oc, void *data) 1303 { 1304 MachineClass *mc = MACHINE_CLASS(oc); 1305 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc); 1306 1307 mc->desc = "ARM MPS3 with AN524 FPGA image for dual Cortex-M33"; 1308 mc->default_cpus = 2; 1309 mc->min_cpus = mc->default_cpus; 1310 mc->max_cpus = mc->default_cpus; 1311 mmc->fpga_type = FPGA_AN524; 1312 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"); 1313 mmc->scc_id = 0x41045240; 1314 mmc->sysclk_frq = 32 * 1000 * 1000; /* 32MHz */ 1315 mmc->apb_periph_frq = mmc->sysclk_frq; 1316 mmc->oscclk = an524_oscclk; 1317 mmc->len_oscclk = ARRAY_SIZE(an524_oscclk); 1318 mmc->fpgaio_num_leds = 10; 1319 mmc->fpgaio_has_switches = true; 1320 mmc->fpgaio_has_dbgctrl = false; 1321 mmc->numirq = 95; 1322 mmc->uart_overflow_irq = 47; 1323 mmc->init_svtor = 0x10000000; 1324 mmc->sram_addr_width = 15; 1325 mmc->raminfo = an524_raminfo; 1326 mmc->armsse_type = TYPE_SSE200; 1327 mps2tz_set_default_ram_info(mmc); 1328 1329 object_class_property_add_str(oc, "remap", mps2_get_remap, mps2_set_remap); 1330 object_class_property_set_description(oc, "remap", 1331 "Set memory mapping. Valid values " 1332 "are BRAM (default) and QSPI."); 1333 } 1334 1335 static void mps3tz_an547_class_init(ObjectClass *oc, void *data) 1336 { 1337 MachineClass *mc = MACHINE_CLASS(oc); 1338 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc); 1339 1340 mc->desc = "ARM MPS3 with AN547 FPGA image for Cortex-M55"; 1341 mc->default_cpus = 1; 1342 mc->min_cpus = mc->default_cpus; 1343 mc->max_cpus = mc->default_cpus; 1344 mmc->fpga_type = FPGA_AN547; 1345 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m55"); 1346 mmc->scc_id = 0x41055470; 1347 mmc->sysclk_frq = 32 * 1000 * 1000; /* 32MHz */ 1348 mmc->apb_periph_frq = 25 * 1000 * 1000; /* 25MHz */ 1349 mmc->oscclk = an524_oscclk; /* same as AN524 */ 1350 mmc->len_oscclk = ARRAY_SIZE(an524_oscclk); 1351 mmc->fpgaio_num_leds = 10; 1352 mmc->fpgaio_has_switches = true; 1353 mmc->fpgaio_has_dbgctrl = true; 1354 mmc->numirq = 96; 1355 mmc->uart_overflow_irq = 48; 1356 mmc->init_svtor = 0x00000000; 1357 mmc->sram_addr_width = 21; 1358 mmc->raminfo = an547_raminfo; 1359 mmc->armsse_type = TYPE_SSE300; 1360 mps2tz_set_default_ram_info(mmc); 1361 } 1362 1363 static const TypeInfo mps2tz_info = { 1364 .name = TYPE_MPS2TZ_MACHINE, 1365 .parent = TYPE_MACHINE, 1366 .abstract = true, 1367 .instance_size = sizeof(MPS2TZMachineState), 1368 .class_size = sizeof(MPS2TZMachineClass), 1369 .class_init = mps2tz_class_init, 1370 .interfaces = (InterfaceInfo[]) { 1371 { TYPE_IDAU_INTERFACE }, 1372 { } 1373 }, 1374 }; 1375 1376 static const TypeInfo mps2tz_an505_info = { 1377 .name = TYPE_MPS2TZ_AN505_MACHINE, 1378 .parent = TYPE_MPS2TZ_MACHINE, 1379 .class_init = mps2tz_an505_class_init, 1380 }; 1381 1382 static const TypeInfo mps2tz_an521_info = { 1383 .name = TYPE_MPS2TZ_AN521_MACHINE, 1384 .parent = TYPE_MPS2TZ_MACHINE, 1385 .class_init = mps2tz_an521_class_init, 1386 }; 1387 1388 static const TypeInfo mps3tz_an524_info = { 1389 .name = TYPE_MPS3TZ_AN524_MACHINE, 1390 .parent = TYPE_MPS2TZ_MACHINE, 1391 .class_init = mps3tz_an524_class_init, 1392 }; 1393 1394 static const TypeInfo mps3tz_an547_info = { 1395 .name = TYPE_MPS3TZ_AN547_MACHINE, 1396 .parent = TYPE_MPS2TZ_MACHINE, 1397 .class_init = mps3tz_an547_class_init, 1398 }; 1399 1400 static void mps2tz_machine_init(void) 1401 { 1402 type_register_static(&mps2tz_info); 1403 type_register_static(&mps2tz_an505_info); 1404 type_register_static(&mps2tz_an521_info); 1405 type_register_static(&mps3tz_an524_info); 1406 type_register_static(&mps3tz_an547_info); 1407 } 1408 1409 type_init(mps2tz_machine_init); 1410