1 /* 2 * ARM V2M MPS2 board emulation, trustzone aware FPGA images 3 * 4 * Copyright (c) 2017 Linaro Limited 5 * Written by Peter Maydell 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 or 9 * (at your option) any later version. 10 */ 11 12 /* The MPS2 and MPS2+ dev boards are FPGA based (the 2+ has a bigger 13 * FPGA but is otherwise the same as the 2). Since the CPU itself 14 * and most of the devices are in the FPGA, the details of the board 15 * as seen by the guest depend significantly on the FPGA image. 16 * This source file covers the following FPGA images, for TrustZone cores: 17 * "mps2-an505" -- Cortex-M33 as documented in ARM Application Note AN505 18 * 19 * Links to the TRM for the board itself and to the various Application 20 * Notes which document the FPGA images can be found here: 21 * https://developer.arm.com/products/system-design/development-boards/fpga-prototyping-boards/mps2 22 * 23 * Board TRM: 24 * http://infocenter.arm.com/help/topic/com.arm.doc.100112_0200_06_en/versatile_express_cortex_m_prototyping_systems_v2m_mps2_and_v2m_mps2plus_technical_reference_100112_0200_06_en.pdf 25 * Application Note AN505: 26 * http://infocenter.arm.com/help/topic/com.arm.doc.dai0505b/index.html 27 * 28 * The AN505 defers to the Cortex-M33 processor ARMv8M IoT Kit FVP User Guide 29 * (ARM ECM0601256) for the details of some of the device layout: 30 * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html 31 */ 32 33 #include "qemu/osdep.h" 34 #include "qapi/error.h" 35 #include "qemu/error-report.h" 36 #include "hw/arm/arm.h" 37 #include "hw/arm/armv7m.h" 38 #include "hw/or-irq.h" 39 #include "hw/boards.h" 40 #include "exec/address-spaces.h" 41 #include "sysemu/sysemu.h" 42 #include "hw/misc/unimp.h" 43 #include "hw/char/cmsdk-apb-uart.h" 44 #include "hw/timer/cmsdk-apb-timer.h" 45 #include "hw/misc/mps2-scc.h" 46 #include "hw/misc/mps2-fpgaio.h" 47 #include "hw/misc/tz-mpc.h" 48 #include "hw/misc/tz-msc.h" 49 #include "hw/arm/armsse.h" 50 #include "hw/dma/pl080.h" 51 #include "hw/ssi/pl022.h" 52 #include "hw/devices.h" 53 #include "net/net.h" 54 #include "hw/core/split-irq.h" 55 56 #define MPS2TZ_NUMIRQ 92 57 58 typedef enum MPS2TZFPGAType { 59 FPGA_AN505, 60 FPGA_AN521, 61 } MPS2TZFPGAType; 62 63 typedef struct { 64 MachineClass parent; 65 MPS2TZFPGAType fpga_type; 66 uint32_t scc_id; 67 } MPS2TZMachineClass; 68 69 typedef struct { 70 MachineState parent; 71 72 ARMSSE iotkit; 73 MemoryRegion psram; 74 MemoryRegion ssram[3]; 75 MemoryRegion ssram1_m; 76 MPS2SCC scc; 77 MPS2FPGAIO fpgaio; 78 TZPPC ppc[5]; 79 TZMPC ssram_mpc[3]; 80 PL022State spi[5]; 81 UnimplementedDeviceState i2c[4]; 82 UnimplementedDeviceState i2s_audio; 83 UnimplementedDeviceState gpio[4]; 84 UnimplementedDeviceState gfx; 85 PL080State dma[4]; 86 TZMSC msc[4]; 87 CMSDKAPBUART uart[5]; 88 SplitIRQ sec_resp_splitter; 89 qemu_or_irq uart_irq_orgate; 90 DeviceState *lan9118; 91 SplitIRQ cpu_irq_splitter[MPS2TZ_NUMIRQ]; 92 } MPS2TZMachineState; 93 94 #define TYPE_MPS2TZ_MACHINE "mps2tz" 95 #define TYPE_MPS2TZ_AN505_MACHINE MACHINE_TYPE_NAME("mps2-an505") 96 97 #define MPS2TZ_MACHINE(obj) \ 98 OBJECT_CHECK(MPS2TZMachineState, obj, TYPE_MPS2TZ_MACHINE) 99 #define MPS2TZ_MACHINE_GET_CLASS(obj) \ 100 OBJECT_GET_CLASS(MPS2TZMachineClass, obj, TYPE_MPS2TZ_MACHINE) 101 #define MPS2TZ_MACHINE_CLASS(klass) \ 102 OBJECT_CLASS_CHECK(MPS2TZMachineClass, klass, TYPE_MPS2TZ_MACHINE) 103 104 /* Main SYSCLK frequency in Hz */ 105 #define SYSCLK_FRQ 20000000 106 107 /* Create an alias of an entire original MemoryRegion @orig 108 * located at @base in the memory map. 109 */ 110 static void make_ram_alias(MemoryRegion *mr, const char *name, 111 MemoryRegion *orig, hwaddr base) 112 { 113 memory_region_init_alias(mr, NULL, name, orig, 0, 114 memory_region_size(orig)); 115 memory_region_add_subregion(get_system_memory(), base, mr); 116 } 117 118 static qemu_irq get_sse_irq_in(MPS2TZMachineState *mms, int irqno) 119 { 120 /* Return a qemu_irq which will signal IRQ n to all CPUs in the SSE. */ 121 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); 122 123 assert(irqno < MPS2TZ_NUMIRQ); 124 125 switch (mmc->fpga_type) { 126 case FPGA_AN505: 127 return qdev_get_gpio_in_named(DEVICE(&mms->iotkit), "EXP_IRQ", irqno); 128 case FPGA_AN521: 129 return qdev_get_gpio_in(DEVICE(&mms->cpu_irq_splitter[irqno]), 0); 130 default: 131 g_assert_not_reached(); 132 } 133 } 134 135 /* Most of the devices in the AN505 FPGA image sit behind 136 * Peripheral Protection Controllers. These data structures 137 * define the layout of which devices sit behind which PPCs. 138 * The devfn for each port is a function which creates, configures 139 * and initializes the device, returning the MemoryRegion which 140 * needs to be plugged into the downstream end of the PPC port. 141 */ 142 typedef MemoryRegion *MakeDevFn(MPS2TZMachineState *mms, void *opaque, 143 const char *name, hwaddr size); 144 145 typedef struct PPCPortInfo { 146 const char *name; 147 MakeDevFn *devfn; 148 void *opaque; 149 hwaddr addr; 150 hwaddr size; 151 } PPCPortInfo; 152 153 typedef struct PPCInfo { 154 const char *name; 155 PPCPortInfo ports[TZ_NUM_PORTS]; 156 } PPCInfo; 157 158 static MemoryRegion *make_unimp_dev(MPS2TZMachineState *mms, 159 void *opaque, 160 const char *name, hwaddr size) 161 { 162 /* Initialize, configure and realize a TYPE_UNIMPLEMENTED_DEVICE, 163 * and return a pointer to its MemoryRegion. 164 */ 165 UnimplementedDeviceState *uds = opaque; 166 167 sysbus_init_child_obj(OBJECT(mms), name, uds, 168 sizeof(UnimplementedDeviceState), 169 TYPE_UNIMPLEMENTED_DEVICE); 170 qdev_prop_set_string(DEVICE(uds), "name", name); 171 qdev_prop_set_uint64(DEVICE(uds), "size", size); 172 object_property_set_bool(OBJECT(uds), true, "realized", &error_fatal); 173 return sysbus_mmio_get_region(SYS_BUS_DEVICE(uds), 0); 174 } 175 176 static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque, 177 const char *name, hwaddr size) 178 { 179 CMSDKAPBUART *uart = opaque; 180 int i = uart - &mms->uart[0]; 181 int rxirqno = i * 2; 182 int txirqno = i * 2 + 1; 183 int combirqno = i + 10; 184 SysBusDevice *s; 185 DeviceState *orgate_dev = DEVICE(&mms->uart_irq_orgate); 186 187 sysbus_init_child_obj(OBJECT(mms), name, uart, sizeof(mms->uart[0]), 188 TYPE_CMSDK_APB_UART); 189 qdev_prop_set_chr(DEVICE(uart), "chardev", serial_hd(i)); 190 qdev_prop_set_uint32(DEVICE(uart), "pclk-frq", SYSCLK_FRQ); 191 object_property_set_bool(OBJECT(uart), true, "realized", &error_fatal); 192 s = SYS_BUS_DEVICE(uart); 193 sysbus_connect_irq(s, 0, get_sse_irq_in(mms, txirqno)); 194 sysbus_connect_irq(s, 1, get_sse_irq_in(mms, rxirqno)); 195 sysbus_connect_irq(s, 2, qdev_get_gpio_in(orgate_dev, i * 2)); 196 sysbus_connect_irq(s, 3, qdev_get_gpio_in(orgate_dev, i * 2 + 1)); 197 sysbus_connect_irq(s, 4, get_sse_irq_in(mms, combirqno)); 198 return sysbus_mmio_get_region(SYS_BUS_DEVICE(uart), 0); 199 } 200 201 static MemoryRegion *make_scc(MPS2TZMachineState *mms, void *opaque, 202 const char *name, hwaddr size) 203 { 204 MPS2SCC *scc = opaque; 205 DeviceState *sccdev; 206 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); 207 208 object_initialize(scc, sizeof(mms->scc), TYPE_MPS2_SCC); 209 sccdev = DEVICE(scc); 210 qdev_set_parent_bus(sccdev, sysbus_get_default()); 211 qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2); 212 qdev_prop_set_uint32(sccdev, "scc-aid", 0x00200008); 213 qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id); 214 object_property_set_bool(OBJECT(scc), true, "realized", &error_fatal); 215 return sysbus_mmio_get_region(SYS_BUS_DEVICE(sccdev), 0); 216 } 217 218 static MemoryRegion *make_fpgaio(MPS2TZMachineState *mms, void *opaque, 219 const char *name, hwaddr size) 220 { 221 MPS2FPGAIO *fpgaio = opaque; 222 223 object_initialize(fpgaio, sizeof(mms->fpgaio), TYPE_MPS2_FPGAIO); 224 qdev_set_parent_bus(DEVICE(fpgaio), sysbus_get_default()); 225 object_property_set_bool(OBJECT(fpgaio), true, "realized", &error_fatal); 226 return sysbus_mmio_get_region(SYS_BUS_DEVICE(fpgaio), 0); 227 } 228 229 static MemoryRegion *make_eth_dev(MPS2TZMachineState *mms, void *opaque, 230 const char *name, hwaddr size) 231 { 232 SysBusDevice *s; 233 NICInfo *nd = &nd_table[0]; 234 235 /* In hardware this is a LAN9220; the LAN9118 is software compatible 236 * except that it doesn't support the checksum-offload feature. 237 */ 238 qemu_check_nic_model(nd, "lan9118"); 239 mms->lan9118 = qdev_create(NULL, "lan9118"); 240 qdev_set_nic_properties(mms->lan9118, nd); 241 qdev_init_nofail(mms->lan9118); 242 243 s = SYS_BUS_DEVICE(mms->lan9118); 244 sysbus_connect_irq(s, 0, get_sse_irq_in(mms, 16)); 245 return sysbus_mmio_get_region(s, 0); 246 } 247 248 static MemoryRegion *make_mpc(MPS2TZMachineState *mms, void *opaque, 249 const char *name, hwaddr size) 250 { 251 TZMPC *mpc = opaque; 252 int i = mpc - &mms->ssram_mpc[0]; 253 MemoryRegion *ssram = &mms->ssram[i]; 254 MemoryRegion *upstream; 255 char *mpcname = g_strdup_printf("%s-mpc", name); 256 static uint32_t ramsize[] = { 0x00400000, 0x00200000, 0x00200000 }; 257 static uint32_t rambase[] = { 0x00000000, 0x28000000, 0x28200000 }; 258 259 memory_region_init_ram(ssram, NULL, name, ramsize[i], &error_fatal); 260 261 sysbus_init_child_obj(OBJECT(mms), mpcname, mpc, sizeof(mms->ssram_mpc[0]), 262 TYPE_TZ_MPC); 263 object_property_set_link(OBJECT(mpc), OBJECT(ssram), 264 "downstream", &error_fatal); 265 object_property_set_bool(OBJECT(mpc), true, "realized", &error_fatal); 266 /* Map the upstream end of the MPC into system memory */ 267 upstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 1); 268 memory_region_add_subregion(get_system_memory(), rambase[i], upstream); 269 /* and connect its interrupt to the IoTKit */ 270 qdev_connect_gpio_out_named(DEVICE(mpc), "irq", 0, 271 qdev_get_gpio_in_named(DEVICE(&mms->iotkit), 272 "mpcexp_status", i)); 273 274 /* The first SSRAM is a special case as it has an alias; accesses to 275 * the alias region at 0x00400000 must also go to the MPC upstream. 276 */ 277 if (i == 0) { 278 make_ram_alias(&mms->ssram1_m, "mps.ssram1_m", upstream, 0x00400000); 279 } 280 281 g_free(mpcname); 282 /* Return the register interface MR for our caller to map behind the PPC */ 283 return sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 0); 284 } 285 286 static MemoryRegion *make_dma(MPS2TZMachineState *mms, void *opaque, 287 const char *name, hwaddr size) 288 { 289 PL080State *dma = opaque; 290 int i = dma - &mms->dma[0]; 291 SysBusDevice *s; 292 char *mscname = g_strdup_printf("%s-msc", name); 293 TZMSC *msc = &mms->msc[i]; 294 DeviceState *iotkitdev = DEVICE(&mms->iotkit); 295 MemoryRegion *msc_upstream; 296 MemoryRegion *msc_downstream; 297 298 /* 299 * Each DMA device is a PL081 whose transaction master interface 300 * is guarded by a Master Security Controller. The downstream end of 301 * the MSC connects to the IoTKit AHB Slave Expansion port, so the 302 * DMA devices can see all devices and memory that the CPU does. 303 */ 304 sysbus_init_child_obj(OBJECT(mms), mscname, msc, sizeof(*msc), TYPE_TZ_MSC); 305 msc_downstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(&mms->iotkit), 0); 306 object_property_set_link(OBJECT(msc), OBJECT(msc_downstream), 307 "downstream", &error_fatal); 308 object_property_set_link(OBJECT(msc), OBJECT(mms), 309 "idau", &error_fatal); 310 object_property_set_bool(OBJECT(msc), true, "realized", &error_fatal); 311 312 qdev_connect_gpio_out_named(DEVICE(msc), "irq", 0, 313 qdev_get_gpio_in_named(iotkitdev, 314 "mscexp_status", i)); 315 qdev_connect_gpio_out_named(iotkitdev, "mscexp_clear", i, 316 qdev_get_gpio_in_named(DEVICE(msc), 317 "irq_clear", 0)); 318 qdev_connect_gpio_out_named(iotkitdev, "mscexp_ns", i, 319 qdev_get_gpio_in_named(DEVICE(msc), 320 "cfg_nonsec", 0)); 321 qdev_connect_gpio_out(DEVICE(&mms->sec_resp_splitter), 322 ARRAY_SIZE(mms->ppc) + i, 323 qdev_get_gpio_in_named(DEVICE(msc), 324 "cfg_sec_resp", 0)); 325 msc_upstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(msc), 0); 326 327 sysbus_init_child_obj(OBJECT(mms), name, dma, sizeof(*dma), TYPE_PL081); 328 object_property_set_link(OBJECT(dma), OBJECT(msc_upstream), 329 "downstream", &error_fatal); 330 object_property_set_bool(OBJECT(dma), true, "realized", &error_fatal); 331 332 s = SYS_BUS_DEVICE(dma); 333 /* Wire up DMACINTR, DMACINTERR, DMACINTTC */ 334 sysbus_connect_irq(s, 0, get_sse_irq_in(mms, 58 + i * 3)); 335 sysbus_connect_irq(s, 1, get_sse_irq_in(mms, 56 + i * 3)); 336 sysbus_connect_irq(s, 2, get_sse_irq_in(mms, 57 + i * 3)); 337 338 g_free(mscname); 339 return sysbus_mmio_get_region(s, 0); 340 } 341 342 static MemoryRegion *make_spi(MPS2TZMachineState *mms, void *opaque, 343 const char *name, hwaddr size) 344 { 345 /* 346 * The AN505 has five PL022 SPI controllers. 347 * One of these should have the LCD controller behind it; the others 348 * are connected only to the FPGA's "general purpose SPI connector" 349 * or "shield" expansion connectors. 350 * Note that if we do implement devices behind SPI, the chip select 351 * lines are set via the "MISC" register in the MPS2 FPGAIO device. 352 */ 353 PL022State *spi = opaque; 354 int i = spi - &mms->spi[0]; 355 SysBusDevice *s; 356 357 sysbus_init_child_obj(OBJECT(mms), name, spi, sizeof(mms->spi[0]), 358 TYPE_PL022); 359 object_property_set_bool(OBJECT(spi), true, "realized", &error_fatal); 360 s = SYS_BUS_DEVICE(spi); 361 sysbus_connect_irq(s, 0, get_sse_irq_in(mms, 51 + i)); 362 return sysbus_mmio_get_region(s, 0); 363 } 364 365 static void mps2tz_common_init(MachineState *machine) 366 { 367 MPS2TZMachineState *mms = MPS2TZ_MACHINE(machine); 368 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); 369 MachineClass *mc = MACHINE_GET_CLASS(machine); 370 MemoryRegion *system_memory = get_system_memory(); 371 DeviceState *iotkitdev; 372 DeviceState *dev_splitter; 373 int i; 374 375 if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) { 376 error_report("This board can only be used with CPU %s", 377 mc->default_cpu_type); 378 exit(1); 379 } 380 381 sysbus_init_child_obj(OBJECT(machine), "iotkit", &mms->iotkit, 382 sizeof(mms->iotkit), TYPE_IOTKIT); 383 iotkitdev = DEVICE(&mms->iotkit); 384 object_property_set_link(OBJECT(&mms->iotkit), OBJECT(system_memory), 385 "memory", &error_abort); 386 qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", MPS2TZ_NUMIRQ); 387 qdev_prop_set_uint32(iotkitdev, "MAINCLK", SYSCLK_FRQ); 388 object_property_set_bool(OBJECT(&mms->iotkit), true, "realized", 389 &error_fatal); 390 391 /* 392 * The AN521 needs us to create splitters to feed the IRQ inputs 393 * for each CPU in the SSE-200 from each device in the board. 394 */ 395 if (mmc->fpga_type == FPGA_AN521) { 396 for (i = 0; i < MPS2TZ_NUMIRQ; i++) { 397 char *name = g_strdup_printf("mps2-irq-splitter%d", i); 398 SplitIRQ *splitter = &mms->cpu_irq_splitter[i]; 399 400 object_initialize_child(OBJECT(machine), name, 401 splitter, sizeof(*splitter), 402 TYPE_SPLIT_IRQ, &error_fatal, NULL); 403 g_free(name); 404 405 object_property_set_int(OBJECT(splitter), 2, "num-lines", 406 &error_fatal); 407 object_property_set_bool(OBJECT(splitter), true, "realized", 408 &error_fatal); 409 qdev_connect_gpio_out(DEVICE(splitter), 0, 410 qdev_get_gpio_in_named(DEVICE(&mms->iotkit), 411 "EXP_IRQ", i)); 412 qdev_connect_gpio_out(DEVICE(splitter), 1, 413 qdev_get_gpio_in_named(DEVICE(&mms->iotkit), 414 "EXP_CPU1_IRQ", i)); 415 } 416 } 417 418 /* The sec_resp_cfg output from the IoTKit must be split into multiple 419 * lines, one for each of the PPCs we create here, plus one per MSC. 420 */ 421 object_initialize(&mms->sec_resp_splitter, sizeof(mms->sec_resp_splitter), 422 TYPE_SPLIT_IRQ); 423 object_property_add_child(OBJECT(machine), "sec-resp-splitter", 424 OBJECT(&mms->sec_resp_splitter), &error_abort); 425 object_property_set_int(OBJECT(&mms->sec_resp_splitter), 426 ARRAY_SIZE(mms->ppc) + ARRAY_SIZE(mms->msc), 427 "num-lines", &error_fatal); 428 object_property_set_bool(OBJECT(&mms->sec_resp_splitter), true, 429 "realized", &error_fatal); 430 dev_splitter = DEVICE(&mms->sec_resp_splitter); 431 qdev_connect_gpio_out_named(iotkitdev, "sec_resp_cfg", 0, 432 qdev_get_gpio_in(dev_splitter, 0)); 433 434 /* The IoTKit sets up much of the memory layout, including 435 * the aliases between secure and non-secure regions in the 436 * address space. The FPGA itself contains: 437 * 438 * 0x00000000..0x003fffff SSRAM1 439 * 0x00400000..0x007fffff alias of SSRAM1 440 * 0x28000000..0x283fffff 4MB SSRAM2 + SSRAM3 441 * 0x40100000..0x4fffffff AHB Master Expansion 1 interface devices 442 * 0x80000000..0x80ffffff 16MB PSRAM 443 */ 444 445 /* The FPGA images have an odd combination of different RAMs, 446 * because in hardware they are different implementations and 447 * connected to different buses, giving varying performance/size 448 * tradeoffs. For QEMU they're all just RAM, though. We arbitrarily 449 * call the 16MB our "system memory", as it's the largest lump. 450 */ 451 memory_region_allocate_system_memory(&mms->psram, 452 NULL, "mps.ram", 0x01000000); 453 memory_region_add_subregion(system_memory, 0x80000000, &mms->psram); 454 455 /* The overflow IRQs for all UARTs are ORed together. 456 * Tx, Rx and "combined" IRQs are sent to the NVIC separately. 457 * Create the OR gate for this. 458 */ 459 object_initialize(&mms->uart_irq_orgate, sizeof(mms->uart_irq_orgate), 460 TYPE_OR_IRQ); 461 object_property_add_child(OBJECT(mms), "uart-irq-orgate", 462 OBJECT(&mms->uart_irq_orgate), &error_abort); 463 object_property_set_int(OBJECT(&mms->uart_irq_orgate), 10, "num-lines", 464 &error_fatal); 465 object_property_set_bool(OBJECT(&mms->uart_irq_orgate), true, 466 "realized", &error_fatal); 467 qdev_connect_gpio_out(DEVICE(&mms->uart_irq_orgate), 0, 468 get_sse_irq_in(mms, 15)); 469 470 /* Most of the devices in the FPGA are behind Peripheral Protection 471 * Controllers. The required order for initializing things is: 472 * + initialize the PPC 473 * + initialize, configure and realize downstream devices 474 * + connect downstream device MemoryRegions to the PPC 475 * + realize the PPC 476 * + map the PPC's MemoryRegions to the places in the address map 477 * where the downstream devices should appear 478 * + wire up the PPC's control lines to the IoTKit object 479 */ 480 481 const PPCInfo ppcs[] = { { 482 .name = "apb_ppcexp0", 483 .ports = { 484 { "ssram-0", make_mpc, &mms->ssram_mpc[0], 0x58007000, 0x1000 }, 485 { "ssram-1", make_mpc, &mms->ssram_mpc[1], 0x58008000, 0x1000 }, 486 { "ssram-2", make_mpc, &mms->ssram_mpc[2], 0x58009000, 0x1000 }, 487 }, 488 }, { 489 .name = "apb_ppcexp1", 490 .ports = { 491 { "spi0", make_spi, &mms->spi[0], 0x40205000, 0x1000 }, 492 { "spi1", make_spi, &mms->spi[1], 0x40206000, 0x1000 }, 493 { "spi2", make_spi, &mms->spi[2], 0x40209000, 0x1000 }, 494 { "spi3", make_spi, &mms->spi[3], 0x4020a000, 0x1000 }, 495 { "spi4", make_spi, &mms->spi[4], 0x4020b000, 0x1000 }, 496 { "uart0", make_uart, &mms->uart[0], 0x40200000, 0x1000 }, 497 { "uart1", make_uart, &mms->uart[1], 0x40201000, 0x1000 }, 498 { "uart2", make_uart, &mms->uart[2], 0x40202000, 0x1000 }, 499 { "uart3", make_uart, &mms->uart[3], 0x40203000, 0x1000 }, 500 { "uart4", make_uart, &mms->uart[4], 0x40204000, 0x1000 }, 501 { "i2c0", make_unimp_dev, &mms->i2c[0], 0x40207000, 0x1000 }, 502 { "i2c1", make_unimp_dev, &mms->i2c[1], 0x40208000, 0x1000 }, 503 { "i2c2", make_unimp_dev, &mms->i2c[2], 0x4020c000, 0x1000 }, 504 { "i2c3", make_unimp_dev, &mms->i2c[3], 0x4020d000, 0x1000 }, 505 }, 506 }, { 507 .name = "apb_ppcexp2", 508 .ports = { 509 { "scc", make_scc, &mms->scc, 0x40300000, 0x1000 }, 510 { "i2s-audio", make_unimp_dev, &mms->i2s_audio, 511 0x40301000, 0x1000 }, 512 { "fpgaio", make_fpgaio, &mms->fpgaio, 0x40302000, 0x1000 }, 513 }, 514 }, { 515 .name = "ahb_ppcexp0", 516 .ports = { 517 { "gfx", make_unimp_dev, &mms->gfx, 0x41000000, 0x140000 }, 518 { "gpio0", make_unimp_dev, &mms->gpio[0], 0x40100000, 0x1000 }, 519 { "gpio1", make_unimp_dev, &mms->gpio[1], 0x40101000, 0x1000 }, 520 { "gpio2", make_unimp_dev, &mms->gpio[2], 0x40102000, 0x1000 }, 521 { "gpio3", make_unimp_dev, &mms->gpio[3], 0x40103000, 0x1000 }, 522 { "eth", make_eth_dev, NULL, 0x42000000, 0x100000 }, 523 }, 524 }, { 525 .name = "ahb_ppcexp1", 526 .ports = { 527 { "dma0", make_dma, &mms->dma[0], 0x40110000, 0x1000 }, 528 { "dma1", make_dma, &mms->dma[1], 0x40111000, 0x1000 }, 529 { "dma2", make_dma, &mms->dma[2], 0x40112000, 0x1000 }, 530 { "dma3", make_dma, &mms->dma[3], 0x40113000, 0x1000 }, 531 }, 532 }, 533 }; 534 535 for (i = 0; i < ARRAY_SIZE(ppcs); i++) { 536 const PPCInfo *ppcinfo = &ppcs[i]; 537 TZPPC *ppc = &mms->ppc[i]; 538 DeviceState *ppcdev; 539 int port; 540 char *gpioname; 541 542 sysbus_init_child_obj(OBJECT(machine), ppcinfo->name, ppc, 543 sizeof(TZPPC), TYPE_TZ_PPC); 544 ppcdev = DEVICE(ppc); 545 546 for (port = 0; port < TZ_NUM_PORTS; port++) { 547 const PPCPortInfo *pinfo = &ppcinfo->ports[port]; 548 MemoryRegion *mr; 549 char *portname; 550 551 if (!pinfo->devfn) { 552 continue; 553 } 554 555 mr = pinfo->devfn(mms, pinfo->opaque, pinfo->name, pinfo->size); 556 portname = g_strdup_printf("port[%d]", port); 557 object_property_set_link(OBJECT(ppc), OBJECT(mr), 558 portname, &error_fatal); 559 g_free(portname); 560 } 561 562 object_property_set_bool(OBJECT(ppc), true, "realized", &error_fatal); 563 564 for (port = 0; port < TZ_NUM_PORTS; port++) { 565 const PPCPortInfo *pinfo = &ppcinfo->ports[port]; 566 567 if (!pinfo->devfn) { 568 continue; 569 } 570 sysbus_mmio_map(SYS_BUS_DEVICE(ppc), port, pinfo->addr); 571 572 gpioname = g_strdup_printf("%s_nonsec", ppcinfo->name); 573 qdev_connect_gpio_out_named(iotkitdev, gpioname, port, 574 qdev_get_gpio_in_named(ppcdev, 575 "cfg_nonsec", 576 port)); 577 g_free(gpioname); 578 gpioname = g_strdup_printf("%s_ap", ppcinfo->name); 579 qdev_connect_gpio_out_named(iotkitdev, gpioname, port, 580 qdev_get_gpio_in_named(ppcdev, 581 "cfg_ap", port)); 582 g_free(gpioname); 583 } 584 585 gpioname = g_strdup_printf("%s_irq_enable", ppcinfo->name); 586 qdev_connect_gpio_out_named(iotkitdev, gpioname, 0, 587 qdev_get_gpio_in_named(ppcdev, 588 "irq_enable", 0)); 589 g_free(gpioname); 590 gpioname = g_strdup_printf("%s_irq_clear", ppcinfo->name); 591 qdev_connect_gpio_out_named(iotkitdev, gpioname, 0, 592 qdev_get_gpio_in_named(ppcdev, 593 "irq_clear", 0)); 594 g_free(gpioname); 595 gpioname = g_strdup_printf("%s_irq_status", ppcinfo->name); 596 qdev_connect_gpio_out_named(ppcdev, "irq", 0, 597 qdev_get_gpio_in_named(iotkitdev, 598 gpioname, 0)); 599 g_free(gpioname); 600 601 qdev_connect_gpio_out(dev_splitter, i, 602 qdev_get_gpio_in_named(ppcdev, 603 "cfg_sec_resp", 0)); 604 } 605 606 create_unimplemented_device("FPGA NS PC", 0x48007000, 0x1000); 607 608 armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 0x400000); 609 } 610 611 static void mps2_tz_idau_check(IDAUInterface *ii, uint32_t address, 612 int *iregion, bool *exempt, bool *ns, bool *nsc) 613 { 614 /* 615 * The MPS2 TZ FPGA images have IDAUs in them which are connected to 616 * the Master Security Controllers. Thes have the same logic as 617 * is used by the IoTKit for the IDAU connected to the CPU, except 618 * that MSCs don't care about the NSC attribute. 619 */ 620 int region = extract32(address, 28, 4); 621 622 *ns = !(region & 1); 623 *nsc = false; 624 /* 0xe0000000..0xe00fffff and 0xf0000000..0xf00fffff are exempt */ 625 *exempt = (address & 0xeff00000) == 0xe0000000; 626 *iregion = region; 627 } 628 629 static void mps2tz_class_init(ObjectClass *oc, void *data) 630 { 631 MachineClass *mc = MACHINE_CLASS(oc); 632 IDAUInterfaceClass *iic = IDAU_INTERFACE_CLASS(oc); 633 634 mc->init = mps2tz_common_init; 635 mc->max_cpus = 1; 636 iic->check = mps2_tz_idau_check; 637 } 638 639 static void mps2tz_an505_class_init(ObjectClass *oc, void *data) 640 { 641 MachineClass *mc = MACHINE_CLASS(oc); 642 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc); 643 644 mc->desc = "ARM MPS2 with AN505 FPGA image for Cortex-M33"; 645 mmc->fpga_type = FPGA_AN505; 646 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"); 647 mmc->scc_id = 0x41045050; 648 } 649 650 static const TypeInfo mps2tz_info = { 651 .name = TYPE_MPS2TZ_MACHINE, 652 .parent = TYPE_MACHINE, 653 .abstract = true, 654 .instance_size = sizeof(MPS2TZMachineState), 655 .class_size = sizeof(MPS2TZMachineClass), 656 .class_init = mps2tz_class_init, 657 .interfaces = (InterfaceInfo[]) { 658 { TYPE_IDAU_INTERFACE }, 659 { } 660 }, 661 }; 662 663 static const TypeInfo mps2tz_an505_info = { 664 .name = TYPE_MPS2TZ_AN505_MACHINE, 665 .parent = TYPE_MPS2TZ_MACHINE, 666 .class_init = mps2tz_an505_class_init, 667 }; 668 669 static void mps2tz_machine_init(void) 670 { 671 type_register_static(&mps2tz_info); 672 type_register_static(&mps2tz_an505_info); 673 } 674 675 type_init(mps2tz_machine_init); 676