1 /* 2 * ARM V2M MPS2 board emulation, trustzone aware FPGA images 3 * 4 * Copyright (c) 2017 Linaro Limited 5 * Written by Peter Maydell 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 or 9 * (at your option) any later version. 10 */ 11 12 /* The MPS2 and MPS2+ dev boards are FPGA based (the 2+ has a bigger 13 * FPGA but is otherwise the same as the 2). Since the CPU itself 14 * and most of the devices are in the FPGA, the details of the board 15 * as seen by the guest depend significantly on the FPGA image. 16 * This source file covers the following FPGA images, for TrustZone cores: 17 * "mps2-an505" -- Cortex-M33 as documented in ARM Application Note AN505 18 * "mps2-an521" -- Dual Cortex-M33 as documented in Application Note AN521 19 * "mps2-an524" -- Dual Cortex-M33 as documented in Application Note AN524 20 * "mps2-an547" -- Single Cortex-M55 as documented in Application Note AN547 21 * 22 * Links to the TRM for the board itself and to the various Application 23 * Notes which document the FPGA images can be found here: 24 * https://developer.arm.com/products/system-design/development-boards/fpga-prototyping-boards/mps2 25 * 26 * Board TRM: 27 * https://developer.arm.com/documentation/100112/latest/ 28 * Application Note AN505: 29 * https://developer.arm.com/documentation/dai0505/latest/ 30 * Application Note AN521: 31 * https://developer.arm.com/documentation/dai0521/latest/ 32 * Application Note AN524: 33 * https://developer.arm.com/documentation/dai0524/latest/ 34 * Application Note AN547: 35 * https://developer.arm.com/-/media/Arm%20Developer%20Community/PDF/DAI0547B_SSE300_PLUS_U55_FPGA_for_mps3.pdf 36 * 37 * The AN505 defers to the Cortex-M33 processor ARMv8M IoT Kit FVP User Guide 38 * (ARM ECM0601256) for the details of some of the device layout: 39 * https://developer.arm.com/documentation/ecm0601256/latest 40 * Similarly, the AN521 and AN524 use the SSE-200, and the SSE-200 TRM defines 41 * most of the device layout: 42 * https://developer.arm.com/documentation/101104/latest/ 43 * and the AN547 uses the SSE-300, whose layout is in the SSE-300 TRM: 44 * https://developer.arm.com/documentation/101773/latest/ 45 */ 46 47 #include "qemu/osdep.h" 48 #include "qemu/units.h" 49 #include "qemu/cutils.h" 50 #include "qapi/error.h" 51 #include "qemu/error-report.h" 52 #include "hw/arm/boot.h" 53 #include "hw/arm/armv7m.h" 54 #include "hw/or-irq.h" 55 #include "hw/boards.h" 56 #include "exec/address-spaces.h" 57 #include "sysemu/sysemu.h" 58 #include "sysemu/reset.h" 59 #include "hw/misc/unimp.h" 60 #include "hw/char/cmsdk-apb-uart.h" 61 #include "hw/timer/cmsdk-apb-timer.h" 62 #include "hw/misc/mps2-scc.h" 63 #include "hw/misc/mps2-fpgaio.h" 64 #include "hw/misc/tz-mpc.h" 65 #include "hw/misc/tz-msc.h" 66 #include "hw/arm/armsse.h" 67 #include "hw/dma/pl080.h" 68 #include "hw/rtc/pl031.h" 69 #include "hw/ssi/pl022.h" 70 #include "hw/i2c/arm_sbcon_i2c.h" 71 #include "hw/net/lan9118.h" 72 #include "net/net.h" 73 #include "hw/core/split-irq.h" 74 #include "hw/qdev-clock.h" 75 #include "qom/object.h" 76 #include "hw/irq.h" 77 78 #define MPS2TZ_NUMIRQ_MAX 96 79 #define MPS2TZ_RAM_MAX 5 80 81 typedef enum MPS2TZFPGAType { 82 FPGA_AN505, 83 FPGA_AN521, 84 FPGA_AN524, 85 FPGA_AN547, 86 } MPS2TZFPGAType; 87 88 /* 89 * Define the layout of RAM in a board, including which parts are 90 * behind which MPCs. 91 * mrindex specifies the index into mms->ram[] to use for the backing RAM; 92 * -1 means "use the system RAM". 93 */ 94 typedef struct RAMInfo { 95 const char *name; 96 uint32_t base; 97 uint32_t size; 98 int mpc; /* MPC number, -1 for "not behind an MPC" */ 99 int mrindex; 100 int flags; 101 } RAMInfo; 102 103 /* 104 * Flag values: 105 * IS_ALIAS: this RAM area is an alias to the upstream end of the 106 * MPC specified by its .mpc value 107 * IS_ROM: this RAM area is read-only 108 */ 109 #define IS_ALIAS 1 110 #define IS_ROM 2 111 112 struct MPS2TZMachineClass { 113 MachineClass parent; 114 MPS2TZFPGAType fpga_type; 115 uint32_t scc_id; 116 uint32_t sysclk_frq; /* Main SYSCLK frequency in Hz */ 117 uint32_t apb_periph_frq; /* APB peripheral frequency in Hz */ 118 uint32_t len_oscclk; 119 const uint32_t *oscclk; 120 uint32_t fpgaio_num_leds; /* Number of LEDs in FPGAIO LED0 register */ 121 bool fpgaio_has_switches; /* Does FPGAIO have SWITCH register? */ 122 bool fpgaio_has_dbgctrl; /* Does FPGAIO have DBGCTRL register? */ 123 int numirq; /* Number of external interrupts */ 124 int uart_overflow_irq; /* number of the combined UART overflow IRQ */ 125 uint32_t init_svtor; /* init-svtor setting for SSE */ 126 uint32_t sram_addr_width; /* SRAM_ADDR_WIDTH setting for SSE */ 127 const RAMInfo *raminfo; 128 const char *armsse_type; 129 uint32_t boot_ram_size; /* size of ram at address 0; 0 == find in raminfo */ 130 }; 131 132 struct MPS2TZMachineState { 133 MachineState parent; 134 135 ARMSSE iotkit; 136 MemoryRegion ram[MPS2TZ_RAM_MAX]; 137 MemoryRegion eth_usb_container; 138 139 MPS2SCC scc; 140 MPS2FPGAIO fpgaio; 141 TZPPC ppc[5]; 142 TZMPC mpc[3]; 143 PL022State spi[5]; 144 ArmSbconI2CState i2c[5]; 145 UnimplementedDeviceState i2s_audio; 146 UnimplementedDeviceState gpio[4]; 147 UnimplementedDeviceState gfx; 148 UnimplementedDeviceState cldc; 149 UnimplementedDeviceState usb; 150 PL031State rtc; 151 PL080State dma[4]; 152 TZMSC msc[4]; 153 CMSDKAPBUART uart[6]; 154 SplitIRQ sec_resp_splitter; 155 qemu_or_irq uart_irq_orgate; 156 DeviceState *lan9118; 157 SplitIRQ cpu_irq_splitter[MPS2TZ_NUMIRQ_MAX]; 158 Clock *sysclk; 159 Clock *s32kclk; 160 161 bool remap; 162 qemu_irq remap_irq; 163 }; 164 165 #define TYPE_MPS2TZ_MACHINE "mps2tz" 166 #define TYPE_MPS2TZ_AN505_MACHINE MACHINE_TYPE_NAME("mps2-an505") 167 #define TYPE_MPS2TZ_AN521_MACHINE MACHINE_TYPE_NAME("mps2-an521") 168 #define TYPE_MPS3TZ_AN524_MACHINE MACHINE_TYPE_NAME("mps3-an524") 169 #define TYPE_MPS3TZ_AN547_MACHINE MACHINE_TYPE_NAME("mps3-an547") 170 171 OBJECT_DECLARE_TYPE(MPS2TZMachineState, MPS2TZMachineClass, MPS2TZ_MACHINE) 172 173 /* Slow 32Khz S32KCLK frequency in Hz */ 174 #define S32KCLK_FRQ (32 * 1000) 175 176 /* 177 * The MPS3 DDR is 2GiB, but on a 32-bit host QEMU doesn't permit 178 * emulation of that much guest RAM, so artificially make it smaller. 179 */ 180 #if HOST_LONG_BITS == 32 181 #define MPS3_DDR_SIZE (1 * GiB) 182 #else 183 #define MPS3_DDR_SIZE (2 * GiB) 184 #endif 185 186 static const uint32_t an505_oscclk[] = { 187 40000000, 188 24580000, 189 25000000, 190 }; 191 192 static const uint32_t an524_oscclk[] = { 193 24000000, 194 32000000, 195 50000000, 196 50000000, 197 24576000, 198 23750000, 199 }; 200 201 static const RAMInfo an505_raminfo[] = { { 202 .name = "ssram-0", 203 .base = 0x00000000, 204 .size = 0x00400000, 205 .mpc = 0, 206 .mrindex = 0, 207 }, { 208 .name = "ssram-1", 209 .base = 0x28000000, 210 .size = 0x00200000, 211 .mpc = 1, 212 .mrindex = 1, 213 }, { 214 .name = "ssram-2", 215 .base = 0x28200000, 216 .size = 0x00200000, 217 .mpc = 2, 218 .mrindex = 2, 219 }, { 220 .name = "ssram-0-alias", 221 .base = 0x00400000, 222 .size = 0x00400000, 223 .mpc = 0, 224 .mrindex = 3, 225 .flags = IS_ALIAS, 226 }, { 227 /* Use the largest bit of contiguous RAM as our "system memory" */ 228 .name = "mps.ram", 229 .base = 0x80000000, 230 .size = 16 * MiB, 231 .mpc = -1, 232 .mrindex = -1, 233 }, { 234 .name = NULL, 235 }, 236 }; 237 238 /* 239 * Note that the addresses and MPC numbering here should match up 240 * with those used in remap_memory(), which can swap the BRAM and QSPI. 241 */ 242 static const RAMInfo an524_raminfo[] = { { 243 .name = "bram", 244 .base = 0x00000000, 245 .size = 512 * KiB, 246 .mpc = 0, 247 .mrindex = 0, 248 }, { 249 /* We don't model QSPI flash yet; for now expose it as simple ROM */ 250 .name = "QSPI", 251 .base = 0x28000000, 252 .size = 8 * MiB, 253 .mpc = 1, 254 .mrindex = 1, 255 .flags = IS_ROM, 256 }, { 257 .name = "DDR", 258 .base = 0x60000000, 259 .size = MPS3_DDR_SIZE, 260 .mpc = 2, 261 .mrindex = -1, 262 }, { 263 .name = NULL, 264 }, 265 }; 266 267 static const RAMInfo an547_raminfo[] = { { 268 .name = "itcm", 269 .base = 0x00000000, 270 .size = 512 * KiB, 271 .mpc = -1, 272 .mrindex = 0, 273 }, { 274 .name = "sram", 275 .base = 0x01000000, 276 .size = 2 * MiB, 277 .mpc = 0, 278 .mrindex = 1, 279 }, { 280 .name = "dtcm", 281 .base = 0x20000000, 282 .size = 4 * 128 * KiB, 283 .mpc = -1, 284 .mrindex = 2, 285 }, { 286 .name = "sram 2", 287 .base = 0x21000000, 288 .size = 4 * MiB, 289 .mpc = -1, 290 .mrindex = 3, 291 }, { 292 /* We don't model QSPI flash yet; for now expose it as simple ROM */ 293 .name = "QSPI", 294 .base = 0x28000000, 295 .size = 8 * MiB, 296 .mpc = 1, 297 .mrindex = 4, 298 .flags = IS_ROM, 299 }, { 300 .name = "DDR", 301 .base = 0x60000000, 302 .size = MPS3_DDR_SIZE, 303 .mpc = 2, 304 .mrindex = -1, 305 }, { 306 .name = NULL, 307 }, 308 }; 309 310 static const RAMInfo *find_raminfo_for_mpc(MPS2TZMachineState *mms, int mpc) 311 { 312 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); 313 const RAMInfo *p; 314 const RAMInfo *found = NULL; 315 316 for (p = mmc->raminfo; p->name; p++) { 317 if (p->mpc == mpc && !(p->flags & IS_ALIAS)) { 318 /* There should only be one entry in the array for this MPC */ 319 g_assert(!found); 320 found = p; 321 } 322 } 323 /* if raminfo array doesn't have an entry for each MPC this is a bug */ 324 assert(found); 325 return found; 326 } 327 328 static MemoryRegion *mr_for_raminfo(MPS2TZMachineState *mms, 329 const RAMInfo *raminfo) 330 { 331 /* Return an initialized MemoryRegion for the RAMInfo. */ 332 MemoryRegion *ram; 333 334 if (raminfo->mrindex < 0) { 335 /* Means this RAMInfo is for QEMU's "system memory" */ 336 MachineState *machine = MACHINE(mms); 337 assert(!(raminfo->flags & IS_ROM)); 338 return machine->ram; 339 } 340 341 assert(raminfo->mrindex < MPS2TZ_RAM_MAX); 342 ram = &mms->ram[raminfo->mrindex]; 343 344 memory_region_init_ram(ram, NULL, raminfo->name, 345 raminfo->size, &error_fatal); 346 if (raminfo->flags & IS_ROM) { 347 memory_region_set_readonly(ram, true); 348 } 349 return ram; 350 } 351 352 /* Create an alias of an entire original MemoryRegion @orig 353 * located at @base in the memory map. 354 */ 355 static void make_ram_alias(MemoryRegion *mr, const char *name, 356 MemoryRegion *orig, hwaddr base) 357 { 358 memory_region_init_alias(mr, NULL, name, orig, 0, 359 memory_region_size(orig)); 360 memory_region_add_subregion(get_system_memory(), base, mr); 361 } 362 363 static qemu_irq get_sse_irq_in(MPS2TZMachineState *mms, int irqno) 364 { 365 /* 366 * Return a qemu_irq which will signal IRQ n to all CPUs in the 367 * SSE. The irqno should be as the CPU sees it, so the first 368 * external-to-the-SSE interrupt is 32. 369 */ 370 MachineClass *mc = MACHINE_GET_CLASS(mms); 371 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); 372 373 assert(irqno >= 32 && irqno < (mmc->numirq + 32)); 374 375 /* 376 * Convert from "CPU irq number" (as listed in the FPGA image 377 * documentation) to the SSE external-interrupt number. 378 */ 379 irqno -= 32; 380 381 if (mc->max_cpus > 1) { 382 return qdev_get_gpio_in(DEVICE(&mms->cpu_irq_splitter[irqno]), 0); 383 } else { 384 return qdev_get_gpio_in_named(DEVICE(&mms->iotkit), "EXP_IRQ", irqno); 385 } 386 } 387 388 /* Most of the devices in the AN505 FPGA image sit behind 389 * Peripheral Protection Controllers. These data structures 390 * define the layout of which devices sit behind which PPCs. 391 * The devfn for each port is a function which creates, configures 392 * and initializes the device, returning the MemoryRegion which 393 * needs to be plugged into the downstream end of the PPC port. 394 */ 395 typedef MemoryRegion *MakeDevFn(MPS2TZMachineState *mms, void *opaque, 396 const char *name, hwaddr size, 397 const int *irqs); 398 399 typedef struct PPCPortInfo { 400 const char *name; 401 MakeDevFn *devfn; 402 void *opaque; 403 hwaddr addr; 404 hwaddr size; 405 int irqs[3]; /* currently no device needs more IRQ lines than this */ 406 } PPCPortInfo; 407 408 typedef struct PPCInfo { 409 const char *name; 410 PPCPortInfo ports[TZ_NUM_PORTS]; 411 } PPCInfo; 412 413 static MemoryRegion *make_unimp_dev(MPS2TZMachineState *mms, 414 void *opaque, 415 const char *name, hwaddr size, 416 const int *irqs) 417 { 418 /* Initialize, configure and realize a TYPE_UNIMPLEMENTED_DEVICE, 419 * and return a pointer to its MemoryRegion. 420 */ 421 UnimplementedDeviceState *uds = opaque; 422 423 object_initialize_child(OBJECT(mms), name, uds, TYPE_UNIMPLEMENTED_DEVICE); 424 qdev_prop_set_string(DEVICE(uds), "name", name); 425 qdev_prop_set_uint64(DEVICE(uds), "size", size); 426 sysbus_realize(SYS_BUS_DEVICE(uds), &error_fatal); 427 return sysbus_mmio_get_region(SYS_BUS_DEVICE(uds), 0); 428 } 429 430 static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque, 431 const char *name, hwaddr size, 432 const int *irqs) 433 { 434 /* The irq[] array is tx, rx, combined, in that order */ 435 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); 436 CMSDKAPBUART *uart = opaque; 437 int i = uart - &mms->uart[0]; 438 SysBusDevice *s; 439 DeviceState *orgate_dev = DEVICE(&mms->uart_irq_orgate); 440 441 object_initialize_child(OBJECT(mms), name, uart, TYPE_CMSDK_APB_UART); 442 qdev_prop_set_chr(DEVICE(uart), "chardev", serial_hd(i)); 443 qdev_prop_set_uint32(DEVICE(uart), "pclk-frq", mmc->apb_periph_frq); 444 sysbus_realize(SYS_BUS_DEVICE(uart), &error_fatal); 445 s = SYS_BUS_DEVICE(uart); 446 sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0])); 447 sysbus_connect_irq(s, 1, get_sse_irq_in(mms, irqs[1])); 448 sysbus_connect_irq(s, 2, qdev_get_gpio_in(orgate_dev, i * 2)); 449 sysbus_connect_irq(s, 3, qdev_get_gpio_in(orgate_dev, i * 2 + 1)); 450 sysbus_connect_irq(s, 4, get_sse_irq_in(mms, irqs[2])); 451 return sysbus_mmio_get_region(SYS_BUS_DEVICE(uart), 0); 452 } 453 454 static MemoryRegion *make_scc(MPS2TZMachineState *mms, void *opaque, 455 const char *name, hwaddr size, 456 const int *irqs) 457 { 458 MPS2SCC *scc = opaque; 459 DeviceState *sccdev; 460 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); 461 uint32_t i; 462 463 object_initialize_child(OBJECT(mms), "scc", scc, TYPE_MPS2_SCC); 464 sccdev = DEVICE(scc); 465 qdev_prop_set_uint32(sccdev, "scc-cfg0", mms->remap ? 1 : 0); 466 qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2); 467 qdev_prop_set_uint32(sccdev, "scc-aid", 0x00200008); 468 qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id); 469 qdev_prop_set_uint32(sccdev, "len-oscclk", mmc->len_oscclk); 470 for (i = 0; i < mmc->len_oscclk; i++) { 471 g_autofree char *propname = g_strdup_printf("oscclk[%u]", i); 472 qdev_prop_set_uint32(sccdev, propname, mmc->oscclk[i]); 473 } 474 sysbus_realize(SYS_BUS_DEVICE(scc), &error_fatal); 475 return sysbus_mmio_get_region(SYS_BUS_DEVICE(sccdev), 0); 476 } 477 478 static MemoryRegion *make_fpgaio(MPS2TZMachineState *mms, void *opaque, 479 const char *name, hwaddr size, 480 const int *irqs) 481 { 482 MPS2FPGAIO *fpgaio = opaque; 483 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); 484 485 object_initialize_child(OBJECT(mms), "fpgaio", fpgaio, TYPE_MPS2_FPGAIO); 486 qdev_prop_set_uint32(DEVICE(fpgaio), "num-leds", mmc->fpgaio_num_leds); 487 qdev_prop_set_bit(DEVICE(fpgaio), "has-switches", mmc->fpgaio_has_switches); 488 qdev_prop_set_bit(DEVICE(fpgaio), "has-dbgctrl", mmc->fpgaio_has_dbgctrl); 489 sysbus_realize(SYS_BUS_DEVICE(fpgaio), &error_fatal); 490 return sysbus_mmio_get_region(SYS_BUS_DEVICE(fpgaio), 0); 491 } 492 493 static MemoryRegion *make_eth_dev(MPS2TZMachineState *mms, void *opaque, 494 const char *name, hwaddr size, 495 const int *irqs) 496 { 497 SysBusDevice *s; 498 NICInfo *nd = &nd_table[0]; 499 500 /* In hardware this is a LAN9220; the LAN9118 is software compatible 501 * except that it doesn't support the checksum-offload feature. 502 */ 503 qemu_check_nic_model(nd, "lan9118"); 504 mms->lan9118 = qdev_new(TYPE_LAN9118); 505 qdev_set_nic_properties(mms->lan9118, nd); 506 507 s = SYS_BUS_DEVICE(mms->lan9118); 508 sysbus_realize_and_unref(s, &error_fatal); 509 sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0])); 510 return sysbus_mmio_get_region(s, 0); 511 } 512 513 static MemoryRegion *make_eth_usb(MPS2TZMachineState *mms, void *opaque, 514 const char *name, hwaddr size, 515 const int *irqs) 516 { 517 /* 518 * The AN524 makes the ethernet and USB share a PPC port. 519 * irqs[] is the ethernet IRQ. 520 */ 521 SysBusDevice *s; 522 NICInfo *nd = &nd_table[0]; 523 524 memory_region_init(&mms->eth_usb_container, OBJECT(mms), 525 "mps2-tz-eth-usb-container", 0x200000); 526 527 /* 528 * In hardware this is a LAN9220; the LAN9118 is software compatible 529 * except that it doesn't support the checksum-offload feature. 530 */ 531 qemu_check_nic_model(nd, "lan9118"); 532 mms->lan9118 = qdev_new(TYPE_LAN9118); 533 qdev_set_nic_properties(mms->lan9118, nd); 534 535 s = SYS_BUS_DEVICE(mms->lan9118); 536 sysbus_realize_and_unref(s, &error_fatal); 537 sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0])); 538 539 memory_region_add_subregion(&mms->eth_usb_container, 540 0, sysbus_mmio_get_region(s, 0)); 541 542 /* The USB OTG controller is an ISP1763; we don't have a model of it. */ 543 object_initialize_child(OBJECT(mms), "usb-otg", 544 &mms->usb, TYPE_UNIMPLEMENTED_DEVICE); 545 qdev_prop_set_string(DEVICE(&mms->usb), "name", "usb-otg"); 546 qdev_prop_set_uint64(DEVICE(&mms->usb), "size", 0x100000); 547 s = SYS_BUS_DEVICE(&mms->usb); 548 sysbus_realize(s, &error_fatal); 549 550 memory_region_add_subregion(&mms->eth_usb_container, 551 0x100000, sysbus_mmio_get_region(s, 0)); 552 553 return &mms->eth_usb_container; 554 } 555 556 static MemoryRegion *make_mpc(MPS2TZMachineState *mms, void *opaque, 557 const char *name, hwaddr size, 558 const int *irqs) 559 { 560 TZMPC *mpc = opaque; 561 int i = mpc - &mms->mpc[0]; 562 MemoryRegion *upstream; 563 const RAMInfo *raminfo = find_raminfo_for_mpc(mms, i); 564 MemoryRegion *ram = mr_for_raminfo(mms, raminfo); 565 566 object_initialize_child(OBJECT(mms), name, mpc, TYPE_TZ_MPC); 567 object_property_set_link(OBJECT(mpc), "downstream", OBJECT(ram), 568 &error_fatal); 569 sysbus_realize(SYS_BUS_DEVICE(mpc), &error_fatal); 570 /* Map the upstream end of the MPC into system memory */ 571 upstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 1); 572 memory_region_add_subregion(get_system_memory(), raminfo->base, upstream); 573 /* and connect its interrupt to the IoTKit */ 574 qdev_connect_gpio_out_named(DEVICE(mpc), "irq", 0, 575 qdev_get_gpio_in_named(DEVICE(&mms->iotkit), 576 "mpcexp_status", i)); 577 578 /* Return the register interface MR for our caller to map behind the PPC */ 579 return sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 0); 580 } 581 582 static hwaddr boot_mem_base(MPS2TZMachineState *mms) 583 { 584 /* 585 * Return the canonical address of the block which will be mapped 586 * at address 0x0 (i.e. where the vector table is). 587 * This is usually 0, but if the AN524 alternate memory map is 588 * enabled it will be the base address of the QSPI block. 589 */ 590 return mms->remap ? 0x28000000 : 0; 591 } 592 593 static void remap_memory(MPS2TZMachineState *mms, int map) 594 { 595 /* 596 * Remap the memory for the AN524. 'map' is the value of 597 * SCC CFG_REG0 bit 0, i.e. 0 for the default map and 1 598 * for the "option 1" mapping where QSPI is at address 0. 599 * 600 * Effectively we need to swap around the "upstream" ends of 601 * MPC 0 and MPC 1. 602 */ 603 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); 604 int i; 605 606 if (mmc->fpga_type != FPGA_AN524) { 607 return; 608 } 609 610 memory_region_transaction_begin(); 611 for (i = 0; i < 2; i++) { 612 TZMPC *mpc = &mms->mpc[i]; 613 MemoryRegion *upstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 1); 614 hwaddr addr = (i ^ map) ? 0x28000000 : 0; 615 616 memory_region_set_address(upstream, addr); 617 } 618 memory_region_transaction_commit(); 619 } 620 621 static void remap_irq_fn(void *opaque, int n, int level) 622 { 623 MPS2TZMachineState *mms = opaque; 624 625 remap_memory(mms, level); 626 } 627 628 static MemoryRegion *make_dma(MPS2TZMachineState *mms, void *opaque, 629 const char *name, hwaddr size, 630 const int *irqs) 631 { 632 /* The irq[] array is DMACINTR, DMACINTERR, DMACINTTC, in that order */ 633 PL080State *dma = opaque; 634 int i = dma - &mms->dma[0]; 635 SysBusDevice *s; 636 char *mscname = g_strdup_printf("%s-msc", name); 637 TZMSC *msc = &mms->msc[i]; 638 DeviceState *iotkitdev = DEVICE(&mms->iotkit); 639 MemoryRegion *msc_upstream; 640 MemoryRegion *msc_downstream; 641 642 /* 643 * Each DMA device is a PL081 whose transaction master interface 644 * is guarded by a Master Security Controller. The downstream end of 645 * the MSC connects to the IoTKit AHB Slave Expansion port, so the 646 * DMA devices can see all devices and memory that the CPU does. 647 */ 648 object_initialize_child(OBJECT(mms), mscname, msc, TYPE_TZ_MSC); 649 msc_downstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(&mms->iotkit), 0); 650 object_property_set_link(OBJECT(msc), "downstream", 651 OBJECT(msc_downstream), &error_fatal); 652 object_property_set_link(OBJECT(msc), "idau", OBJECT(mms), &error_fatal); 653 sysbus_realize(SYS_BUS_DEVICE(msc), &error_fatal); 654 655 qdev_connect_gpio_out_named(DEVICE(msc), "irq", 0, 656 qdev_get_gpio_in_named(iotkitdev, 657 "mscexp_status", i)); 658 qdev_connect_gpio_out_named(iotkitdev, "mscexp_clear", i, 659 qdev_get_gpio_in_named(DEVICE(msc), 660 "irq_clear", 0)); 661 qdev_connect_gpio_out_named(iotkitdev, "mscexp_ns", i, 662 qdev_get_gpio_in_named(DEVICE(msc), 663 "cfg_nonsec", 0)); 664 qdev_connect_gpio_out(DEVICE(&mms->sec_resp_splitter), 665 ARRAY_SIZE(mms->ppc) + i, 666 qdev_get_gpio_in_named(DEVICE(msc), 667 "cfg_sec_resp", 0)); 668 msc_upstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(msc), 0); 669 670 object_initialize_child(OBJECT(mms), name, dma, TYPE_PL081); 671 object_property_set_link(OBJECT(dma), "downstream", OBJECT(msc_upstream), 672 &error_fatal); 673 sysbus_realize(SYS_BUS_DEVICE(dma), &error_fatal); 674 675 s = SYS_BUS_DEVICE(dma); 676 /* Wire up DMACINTR, DMACINTERR, DMACINTTC */ 677 sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0])); 678 sysbus_connect_irq(s, 1, get_sse_irq_in(mms, irqs[1])); 679 sysbus_connect_irq(s, 2, get_sse_irq_in(mms, irqs[2])); 680 681 g_free(mscname); 682 return sysbus_mmio_get_region(s, 0); 683 } 684 685 static MemoryRegion *make_spi(MPS2TZMachineState *mms, void *opaque, 686 const char *name, hwaddr size, 687 const int *irqs) 688 { 689 /* 690 * The AN505 has five PL022 SPI controllers. 691 * One of these should have the LCD controller behind it; the others 692 * are connected only to the FPGA's "general purpose SPI connector" 693 * or "shield" expansion connectors. 694 * Note that if we do implement devices behind SPI, the chip select 695 * lines are set via the "MISC" register in the MPS2 FPGAIO device. 696 */ 697 PL022State *spi = opaque; 698 SysBusDevice *s; 699 700 object_initialize_child(OBJECT(mms), name, spi, TYPE_PL022); 701 sysbus_realize(SYS_BUS_DEVICE(spi), &error_fatal); 702 s = SYS_BUS_DEVICE(spi); 703 sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0])); 704 return sysbus_mmio_get_region(s, 0); 705 } 706 707 static MemoryRegion *make_i2c(MPS2TZMachineState *mms, void *opaque, 708 const char *name, hwaddr size, 709 const int *irqs) 710 { 711 ArmSbconI2CState *i2c = opaque; 712 SysBusDevice *s; 713 714 object_initialize_child(OBJECT(mms), name, i2c, TYPE_ARM_SBCON_I2C); 715 s = SYS_BUS_DEVICE(i2c); 716 sysbus_realize(s, &error_fatal); 717 return sysbus_mmio_get_region(s, 0); 718 } 719 720 static MemoryRegion *make_rtc(MPS2TZMachineState *mms, void *opaque, 721 const char *name, hwaddr size, 722 const int *irqs) 723 { 724 PL031State *pl031 = opaque; 725 SysBusDevice *s; 726 727 object_initialize_child(OBJECT(mms), name, pl031, TYPE_PL031); 728 s = SYS_BUS_DEVICE(pl031); 729 sysbus_realize(s, &error_fatal); 730 /* 731 * The board docs don't give an IRQ number for the PL031, so 732 * presumably it is not connected. 733 */ 734 return sysbus_mmio_get_region(s, 0); 735 } 736 737 static void create_non_mpc_ram(MPS2TZMachineState *mms) 738 { 739 /* 740 * Handle the RAMs which are either not behind MPCs or which are 741 * aliases to another MPC. 742 */ 743 const RAMInfo *p; 744 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); 745 746 for (p = mmc->raminfo; p->name; p++) { 747 if (p->flags & IS_ALIAS) { 748 SysBusDevice *mpc_sbd = SYS_BUS_DEVICE(&mms->mpc[p->mpc]); 749 MemoryRegion *upstream = sysbus_mmio_get_region(mpc_sbd, 1); 750 make_ram_alias(&mms->ram[p->mrindex], p->name, upstream, p->base); 751 } else if (p->mpc == -1) { 752 /* RAM not behind an MPC */ 753 MemoryRegion *mr = mr_for_raminfo(mms, p); 754 memory_region_add_subregion(get_system_memory(), p->base, mr); 755 } 756 } 757 } 758 759 static uint32_t boot_ram_size(MPS2TZMachineState *mms) 760 { 761 /* Return the size of the RAM block at guest address zero */ 762 const RAMInfo *p; 763 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); 764 765 /* 766 * Use a per-board specification (for when the boot RAM is in 767 * the SSE and so doesn't have a RAMInfo list entry) 768 */ 769 if (mmc->boot_ram_size) { 770 return mmc->boot_ram_size; 771 } 772 773 for (p = mmc->raminfo; p->name; p++) { 774 if (p->base == boot_mem_base(mms)) { 775 return p->size; 776 } 777 } 778 g_assert_not_reached(); 779 } 780 781 static void mps2tz_common_init(MachineState *machine) 782 { 783 MPS2TZMachineState *mms = MPS2TZ_MACHINE(machine); 784 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); 785 MachineClass *mc = MACHINE_GET_CLASS(machine); 786 MemoryRegion *system_memory = get_system_memory(); 787 DeviceState *iotkitdev; 788 DeviceState *dev_splitter; 789 const PPCInfo *ppcs; 790 int num_ppcs; 791 int i; 792 793 if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) { 794 error_report("This board can only be used with CPU %s", 795 mc->default_cpu_type); 796 exit(1); 797 } 798 799 if (machine->ram_size != mc->default_ram_size) { 800 char *sz = size_to_str(mc->default_ram_size); 801 error_report("Invalid RAM size, should be %s", sz); 802 g_free(sz); 803 exit(EXIT_FAILURE); 804 } 805 806 /* These clocks don't need migration because they are fixed-frequency */ 807 mms->sysclk = clock_new(OBJECT(machine), "SYSCLK"); 808 clock_set_hz(mms->sysclk, mmc->sysclk_frq); 809 mms->s32kclk = clock_new(OBJECT(machine), "S32KCLK"); 810 clock_set_hz(mms->s32kclk, S32KCLK_FRQ); 811 812 object_initialize_child(OBJECT(machine), TYPE_IOTKIT, &mms->iotkit, 813 mmc->armsse_type); 814 iotkitdev = DEVICE(&mms->iotkit); 815 object_property_set_link(OBJECT(&mms->iotkit), "memory", 816 OBJECT(system_memory), &error_abort); 817 qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", mmc->numirq); 818 qdev_prop_set_uint32(iotkitdev, "init-svtor", mmc->init_svtor); 819 qdev_prop_set_uint32(iotkitdev, "SRAM_ADDR_WIDTH", mmc->sram_addr_width); 820 qdev_connect_clock_in(iotkitdev, "MAINCLK", mms->sysclk); 821 qdev_connect_clock_in(iotkitdev, "S32KCLK", mms->s32kclk); 822 sysbus_realize(SYS_BUS_DEVICE(&mms->iotkit), &error_fatal); 823 824 /* 825 * If this board has more than one CPU, then we need to create splitters 826 * to feed the IRQ inputs for each CPU in the SSE from each device in the 827 * board. If there is only one CPU, we can just wire the device IRQ 828 * directly to the SSE's IRQ input. 829 */ 830 assert(mmc->numirq <= MPS2TZ_NUMIRQ_MAX); 831 if (mc->max_cpus > 1) { 832 for (i = 0; i < mmc->numirq; i++) { 833 char *name = g_strdup_printf("mps2-irq-splitter%d", i); 834 SplitIRQ *splitter = &mms->cpu_irq_splitter[i]; 835 836 object_initialize_child_with_props(OBJECT(machine), name, 837 splitter, sizeof(*splitter), 838 TYPE_SPLIT_IRQ, &error_fatal, 839 NULL); 840 g_free(name); 841 842 object_property_set_int(OBJECT(splitter), "num-lines", 2, 843 &error_fatal); 844 qdev_realize(DEVICE(splitter), NULL, &error_fatal); 845 qdev_connect_gpio_out(DEVICE(splitter), 0, 846 qdev_get_gpio_in_named(DEVICE(&mms->iotkit), 847 "EXP_IRQ", i)); 848 qdev_connect_gpio_out(DEVICE(splitter), 1, 849 qdev_get_gpio_in_named(DEVICE(&mms->iotkit), 850 "EXP_CPU1_IRQ", i)); 851 } 852 } 853 854 /* The sec_resp_cfg output from the IoTKit must be split into multiple 855 * lines, one for each of the PPCs we create here, plus one per MSC. 856 */ 857 object_initialize_child(OBJECT(machine), "sec-resp-splitter", 858 &mms->sec_resp_splitter, TYPE_SPLIT_IRQ); 859 object_property_set_int(OBJECT(&mms->sec_resp_splitter), "num-lines", 860 ARRAY_SIZE(mms->ppc) + ARRAY_SIZE(mms->msc), 861 &error_fatal); 862 qdev_realize(DEVICE(&mms->sec_resp_splitter), NULL, &error_fatal); 863 dev_splitter = DEVICE(&mms->sec_resp_splitter); 864 qdev_connect_gpio_out_named(iotkitdev, "sec_resp_cfg", 0, 865 qdev_get_gpio_in(dev_splitter, 0)); 866 867 /* 868 * The IoTKit sets up much of the memory layout, including 869 * the aliases between secure and non-secure regions in the 870 * address space, and also most of the devices in the system. 871 * The FPGA itself contains various RAMs and some additional devices. 872 * The FPGA images have an odd combination of different RAMs, 873 * because in hardware they are different implementations and 874 * connected to different buses, giving varying performance/size 875 * tradeoffs. For QEMU they're all just RAM, though. We arbitrarily 876 * call the largest lump our "system memory". 877 */ 878 879 /* 880 * The overflow IRQs for all UARTs are ORed together. 881 * Tx, Rx and "combined" IRQs are sent to the NVIC separately. 882 * Create the OR gate for this: it has one input for the TX overflow 883 * and one for the RX overflow for each UART we might have. 884 * (If the board has fewer than the maximum possible number of UARTs 885 * those inputs are never wired up and are treated as always-zero.) 886 */ 887 object_initialize_child(OBJECT(mms), "uart-irq-orgate", 888 &mms->uart_irq_orgate, TYPE_OR_IRQ); 889 object_property_set_int(OBJECT(&mms->uart_irq_orgate), "num-lines", 890 2 * ARRAY_SIZE(mms->uart), 891 &error_fatal); 892 qdev_realize(DEVICE(&mms->uart_irq_orgate), NULL, &error_fatal); 893 qdev_connect_gpio_out(DEVICE(&mms->uart_irq_orgate), 0, 894 get_sse_irq_in(mms, mmc->uart_overflow_irq)); 895 896 /* Most of the devices in the FPGA are behind Peripheral Protection 897 * Controllers. The required order for initializing things is: 898 * + initialize the PPC 899 * + initialize, configure and realize downstream devices 900 * + connect downstream device MemoryRegions to the PPC 901 * + realize the PPC 902 * + map the PPC's MemoryRegions to the places in the address map 903 * where the downstream devices should appear 904 * + wire up the PPC's control lines to the IoTKit object 905 */ 906 907 const PPCInfo an505_ppcs[] = { { 908 .name = "apb_ppcexp0", 909 .ports = { 910 { "ssram-0-mpc", make_mpc, &mms->mpc[0], 0x58007000, 0x1000 }, 911 { "ssram-1-mpc", make_mpc, &mms->mpc[1], 0x58008000, 0x1000 }, 912 { "ssram-2-mpc", make_mpc, &mms->mpc[2], 0x58009000, 0x1000 }, 913 }, 914 }, { 915 .name = "apb_ppcexp1", 916 .ports = { 917 { "spi0", make_spi, &mms->spi[0], 0x40205000, 0x1000, { 51 } }, 918 { "spi1", make_spi, &mms->spi[1], 0x40206000, 0x1000, { 52 } }, 919 { "spi2", make_spi, &mms->spi[2], 0x40209000, 0x1000, { 53 } }, 920 { "spi3", make_spi, &mms->spi[3], 0x4020a000, 0x1000, { 54 } }, 921 { "spi4", make_spi, &mms->spi[4], 0x4020b000, 0x1000, { 55 } }, 922 { "uart0", make_uart, &mms->uart[0], 0x40200000, 0x1000, { 32, 33, 42 } }, 923 { "uart1", make_uart, &mms->uart[1], 0x40201000, 0x1000, { 34, 35, 43 } }, 924 { "uart2", make_uart, &mms->uart[2], 0x40202000, 0x1000, { 36, 37, 44 } }, 925 { "uart3", make_uart, &mms->uart[3], 0x40203000, 0x1000, { 38, 39, 45 } }, 926 { "uart4", make_uart, &mms->uart[4], 0x40204000, 0x1000, { 40, 41, 46 } }, 927 { "i2c0", make_i2c, &mms->i2c[0], 0x40207000, 0x1000 }, 928 { "i2c1", make_i2c, &mms->i2c[1], 0x40208000, 0x1000 }, 929 { "i2c2", make_i2c, &mms->i2c[2], 0x4020c000, 0x1000 }, 930 { "i2c3", make_i2c, &mms->i2c[3], 0x4020d000, 0x1000 }, 931 }, 932 }, { 933 .name = "apb_ppcexp2", 934 .ports = { 935 { "scc", make_scc, &mms->scc, 0x40300000, 0x1000 }, 936 { "i2s-audio", make_unimp_dev, &mms->i2s_audio, 937 0x40301000, 0x1000 }, 938 { "fpgaio", make_fpgaio, &mms->fpgaio, 0x40302000, 0x1000 }, 939 }, 940 }, { 941 .name = "ahb_ppcexp0", 942 .ports = { 943 { "gfx", make_unimp_dev, &mms->gfx, 0x41000000, 0x140000 }, 944 { "gpio0", make_unimp_dev, &mms->gpio[0], 0x40100000, 0x1000 }, 945 { "gpio1", make_unimp_dev, &mms->gpio[1], 0x40101000, 0x1000 }, 946 { "gpio2", make_unimp_dev, &mms->gpio[2], 0x40102000, 0x1000 }, 947 { "gpio3", make_unimp_dev, &mms->gpio[3], 0x40103000, 0x1000 }, 948 { "eth", make_eth_dev, NULL, 0x42000000, 0x100000, { 48 } }, 949 }, 950 }, { 951 .name = "ahb_ppcexp1", 952 .ports = { 953 { "dma0", make_dma, &mms->dma[0], 0x40110000, 0x1000, { 58, 56, 57 } }, 954 { "dma1", make_dma, &mms->dma[1], 0x40111000, 0x1000, { 61, 59, 60 } }, 955 { "dma2", make_dma, &mms->dma[2], 0x40112000, 0x1000, { 64, 62, 63 } }, 956 { "dma3", make_dma, &mms->dma[3], 0x40113000, 0x1000, { 67, 65, 66 } }, 957 }, 958 }, 959 }; 960 961 const PPCInfo an524_ppcs[] = { { 962 .name = "apb_ppcexp0", 963 .ports = { 964 { "bram-mpc", make_mpc, &mms->mpc[0], 0x58007000, 0x1000 }, 965 { "qspi-mpc", make_mpc, &mms->mpc[1], 0x58008000, 0x1000 }, 966 { "ddr-mpc", make_mpc, &mms->mpc[2], 0x58009000, 0x1000 }, 967 }, 968 }, { 969 .name = "apb_ppcexp1", 970 .ports = { 971 { "i2c0", make_i2c, &mms->i2c[0], 0x41200000, 0x1000 }, 972 { "i2c1", make_i2c, &mms->i2c[1], 0x41201000, 0x1000 }, 973 { "spi0", make_spi, &mms->spi[0], 0x41202000, 0x1000, { 52 } }, 974 { "spi1", make_spi, &mms->spi[1], 0x41203000, 0x1000, { 53 } }, 975 { "spi2", make_spi, &mms->spi[2], 0x41204000, 0x1000, { 54 } }, 976 { "i2c2", make_i2c, &mms->i2c[2], 0x41205000, 0x1000 }, 977 { "i2c3", make_i2c, &mms->i2c[3], 0x41206000, 0x1000 }, 978 { /* port 7 reserved */ }, 979 { "i2c4", make_i2c, &mms->i2c[4], 0x41208000, 0x1000 }, 980 }, 981 }, { 982 .name = "apb_ppcexp2", 983 .ports = { 984 { "scc", make_scc, &mms->scc, 0x41300000, 0x1000 }, 985 { "i2s-audio", make_unimp_dev, &mms->i2s_audio, 986 0x41301000, 0x1000 }, 987 { "fpgaio", make_fpgaio, &mms->fpgaio, 0x41302000, 0x1000 }, 988 { "uart0", make_uart, &mms->uart[0], 0x41303000, 0x1000, { 32, 33, 42 } }, 989 { "uart1", make_uart, &mms->uart[1], 0x41304000, 0x1000, { 34, 35, 43 } }, 990 { "uart2", make_uart, &mms->uart[2], 0x41305000, 0x1000, { 36, 37, 44 } }, 991 { "uart3", make_uart, &mms->uart[3], 0x41306000, 0x1000, { 38, 39, 45 } }, 992 { "uart4", make_uart, &mms->uart[4], 0x41307000, 0x1000, { 40, 41, 46 } }, 993 { "uart5", make_uart, &mms->uart[5], 0x41308000, 0x1000, { 124, 125, 126 } }, 994 995 { /* port 9 reserved */ }, 996 { "clcd", make_unimp_dev, &mms->cldc, 0x4130a000, 0x1000 }, 997 { "rtc", make_rtc, &mms->rtc, 0x4130b000, 0x1000 }, 998 }, 999 }, { 1000 .name = "ahb_ppcexp0", 1001 .ports = { 1002 { "gpio0", make_unimp_dev, &mms->gpio[0], 0x41100000, 0x1000 }, 1003 { "gpio1", make_unimp_dev, &mms->gpio[1], 0x41101000, 0x1000 }, 1004 { "gpio2", make_unimp_dev, &mms->gpio[2], 0x41102000, 0x1000 }, 1005 { "gpio3", make_unimp_dev, &mms->gpio[3], 0x41103000, 0x1000 }, 1006 { "eth-usb", make_eth_usb, NULL, 0x41400000, 0x200000, { 48 } }, 1007 }, 1008 }, 1009 }; 1010 1011 const PPCInfo an547_ppcs[] = { { 1012 .name = "apb_ppcexp0", 1013 .ports = { 1014 { "ssram-mpc", make_mpc, &mms->mpc[0], 0x57000000, 0x1000 }, 1015 { "qspi-mpc", make_mpc, &mms->mpc[1], 0x57001000, 0x1000 }, 1016 { "ddr-mpc", make_mpc, &mms->mpc[2], 0x57002000, 0x1000 }, 1017 }, 1018 }, { 1019 .name = "apb_ppcexp1", 1020 .ports = { 1021 { "i2c0", make_i2c, &mms->i2c[0], 0x49200000, 0x1000 }, 1022 { "i2c1", make_i2c, &mms->i2c[1], 0x49201000, 0x1000 }, 1023 { "spi0", make_spi, &mms->spi[0], 0x49202000, 0x1000, { 53 } }, 1024 { "spi1", make_spi, &mms->spi[1], 0x49203000, 0x1000, { 54 } }, 1025 { "spi2", make_spi, &mms->spi[2], 0x49204000, 0x1000, { 55 } }, 1026 { "i2c2", make_i2c, &mms->i2c[2], 0x49205000, 0x1000 }, 1027 { "i2c3", make_i2c, &mms->i2c[3], 0x49206000, 0x1000 }, 1028 { /* port 7 reserved */ }, 1029 { "i2c4", make_i2c, &mms->i2c[4], 0x49208000, 0x1000 }, 1030 }, 1031 }, { 1032 .name = "apb_ppcexp2", 1033 .ports = { 1034 { "scc", make_scc, &mms->scc, 0x49300000, 0x1000 }, 1035 { "i2s-audio", make_unimp_dev, &mms->i2s_audio, 0x49301000, 0x1000 }, 1036 { "fpgaio", make_fpgaio, &mms->fpgaio, 0x49302000, 0x1000 }, 1037 { "uart0", make_uart, &mms->uart[0], 0x49303000, 0x1000, { 33, 34, 43 } }, 1038 { "uart1", make_uart, &mms->uart[1], 0x49304000, 0x1000, { 35, 36, 44 } }, 1039 { "uart2", make_uart, &mms->uart[2], 0x49305000, 0x1000, { 37, 38, 45 } }, 1040 { "uart3", make_uart, &mms->uart[3], 0x49306000, 0x1000, { 39, 40, 46 } }, 1041 { "uart4", make_uart, &mms->uart[4], 0x49307000, 0x1000, { 41, 42, 47 } }, 1042 { "uart5", make_uart, &mms->uart[5], 0x49308000, 0x1000, { 125, 126, 127 } }, 1043 1044 { /* port 9 reserved */ }, 1045 { "clcd", make_unimp_dev, &mms->cldc, 0x4930a000, 0x1000 }, 1046 { "rtc", make_rtc, &mms->rtc, 0x4930b000, 0x1000 }, 1047 }, 1048 }, { 1049 .name = "ahb_ppcexp0", 1050 .ports = { 1051 { "gpio0", make_unimp_dev, &mms->gpio[0], 0x41100000, 0x1000 }, 1052 { "gpio1", make_unimp_dev, &mms->gpio[1], 0x41101000, 0x1000 }, 1053 { "gpio2", make_unimp_dev, &mms->gpio[2], 0x41102000, 0x1000 }, 1054 { "gpio3", make_unimp_dev, &mms->gpio[3], 0x41103000, 0x1000 }, 1055 { "eth-usb", make_eth_usb, NULL, 0x41400000, 0x200000, { 49 } }, 1056 }, 1057 }, 1058 }; 1059 1060 switch (mmc->fpga_type) { 1061 case FPGA_AN505: 1062 case FPGA_AN521: 1063 ppcs = an505_ppcs; 1064 num_ppcs = ARRAY_SIZE(an505_ppcs); 1065 break; 1066 case FPGA_AN524: 1067 ppcs = an524_ppcs; 1068 num_ppcs = ARRAY_SIZE(an524_ppcs); 1069 break; 1070 case FPGA_AN547: 1071 ppcs = an547_ppcs; 1072 num_ppcs = ARRAY_SIZE(an547_ppcs); 1073 break; 1074 default: 1075 g_assert_not_reached(); 1076 } 1077 1078 for (i = 0; i < num_ppcs; i++) { 1079 const PPCInfo *ppcinfo = &ppcs[i]; 1080 TZPPC *ppc = &mms->ppc[i]; 1081 DeviceState *ppcdev; 1082 int port; 1083 char *gpioname; 1084 1085 object_initialize_child(OBJECT(machine), ppcinfo->name, ppc, 1086 TYPE_TZ_PPC); 1087 ppcdev = DEVICE(ppc); 1088 1089 for (port = 0; port < TZ_NUM_PORTS; port++) { 1090 const PPCPortInfo *pinfo = &ppcinfo->ports[port]; 1091 MemoryRegion *mr; 1092 char *portname; 1093 1094 if (!pinfo->devfn) { 1095 continue; 1096 } 1097 1098 mr = pinfo->devfn(mms, pinfo->opaque, pinfo->name, pinfo->size, 1099 pinfo->irqs); 1100 portname = g_strdup_printf("port[%d]", port); 1101 object_property_set_link(OBJECT(ppc), portname, OBJECT(mr), 1102 &error_fatal); 1103 g_free(portname); 1104 } 1105 1106 sysbus_realize(SYS_BUS_DEVICE(ppc), &error_fatal); 1107 1108 for (port = 0; port < TZ_NUM_PORTS; port++) { 1109 const PPCPortInfo *pinfo = &ppcinfo->ports[port]; 1110 1111 if (!pinfo->devfn) { 1112 continue; 1113 } 1114 sysbus_mmio_map(SYS_BUS_DEVICE(ppc), port, pinfo->addr); 1115 1116 gpioname = g_strdup_printf("%s_nonsec", ppcinfo->name); 1117 qdev_connect_gpio_out_named(iotkitdev, gpioname, port, 1118 qdev_get_gpio_in_named(ppcdev, 1119 "cfg_nonsec", 1120 port)); 1121 g_free(gpioname); 1122 gpioname = g_strdup_printf("%s_ap", ppcinfo->name); 1123 qdev_connect_gpio_out_named(iotkitdev, gpioname, port, 1124 qdev_get_gpio_in_named(ppcdev, 1125 "cfg_ap", port)); 1126 g_free(gpioname); 1127 } 1128 1129 gpioname = g_strdup_printf("%s_irq_enable", ppcinfo->name); 1130 qdev_connect_gpio_out_named(iotkitdev, gpioname, 0, 1131 qdev_get_gpio_in_named(ppcdev, 1132 "irq_enable", 0)); 1133 g_free(gpioname); 1134 gpioname = g_strdup_printf("%s_irq_clear", ppcinfo->name); 1135 qdev_connect_gpio_out_named(iotkitdev, gpioname, 0, 1136 qdev_get_gpio_in_named(ppcdev, 1137 "irq_clear", 0)); 1138 g_free(gpioname); 1139 gpioname = g_strdup_printf("%s_irq_status", ppcinfo->name); 1140 qdev_connect_gpio_out_named(ppcdev, "irq", 0, 1141 qdev_get_gpio_in_named(iotkitdev, 1142 gpioname, 0)); 1143 g_free(gpioname); 1144 1145 qdev_connect_gpio_out(dev_splitter, i, 1146 qdev_get_gpio_in_named(ppcdev, 1147 "cfg_sec_resp", 0)); 1148 } 1149 1150 create_unimplemented_device("FPGA NS PC", 0x48007000, 0x1000); 1151 1152 if (mmc->fpga_type == FPGA_AN547) { 1153 create_unimplemented_device("U55 timing adapter 0", 0x48102000, 0x1000); 1154 create_unimplemented_device("U55 timing adapter 1", 0x48103000, 0x1000); 1155 } 1156 1157 create_non_mpc_ram(mms); 1158 1159 if (mmc->fpga_type == FPGA_AN524) { 1160 /* 1161 * Connect the line from the SCC so that we can remap when the 1162 * guest updates that register. 1163 */ 1164 mms->remap_irq = qemu_allocate_irq(remap_irq_fn, mms, 0); 1165 qdev_connect_gpio_out_named(DEVICE(&mms->scc), "remap", 0, 1166 mms->remap_irq); 1167 } 1168 1169 armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 1170 boot_ram_size(mms)); 1171 } 1172 1173 static void mps2_tz_idau_check(IDAUInterface *ii, uint32_t address, 1174 int *iregion, bool *exempt, bool *ns, bool *nsc) 1175 { 1176 /* 1177 * The MPS2 TZ FPGA images have IDAUs in them which are connected to 1178 * the Master Security Controllers. Thes have the same logic as 1179 * is used by the IoTKit for the IDAU connected to the CPU, except 1180 * that MSCs don't care about the NSC attribute. 1181 */ 1182 int region = extract32(address, 28, 4); 1183 1184 *ns = !(region & 1); 1185 *nsc = false; 1186 /* 0xe0000000..0xe00fffff and 0xf0000000..0xf00fffff are exempt */ 1187 *exempt = (address & 0xeff00000) == 0xe0000000; 1188 *iregion = region; 1189 } 1190 1191 static char *mps2_get_remap(Object *obj, Error **errp) 1192 { 1193 MPS2TZMachineState *mms = MPS2TZ_MACHINE(obj); 1194 const char *val = mms->remap ? "QSPI" : "BRAM"; 1195 return g_strdup(val); 1196 } 1197 1198 static void mps2_set_remap(Object *obj, const char *value, Error **errp) 1199 { 1200 MPS2TZMachineState *mms = MPS2TZ_MACHINE(obj); 1201 1202 if (!strcmp(value, "BRAM")) { 1203 mms->remap = false; 1204 } else if (!strcmp(value, "QSPI")) { 1205 mms->remap = true; 1206 } else { 1207 error_setg(errp, "Invalid remap value"); 1208 error_append_hint(errp, "Valid values are BRAM and QSPI.\n"); 1209 } 1210 } 1211 1212 static void mps2_machine_reset(MachineState *machine) 1213 { 1214 MPS2TZMachineState *mms = MPS2TZ_MACHINE(machine); 1215 1216 /* 1217 * Set the initial memory mapping before triggering the reset of 1218 * the rest of the system, so that the guest image loader and CPU 1219 * reset see the correct mapping. 1220 */ 1221 remap_memory(mms, mms->remap); 1222 qemu_devices_reset(); 1223 } 1224 1225 static void mps2tz_class_init(ObjectClass *oc, void *data) 1226 { 1227 MachineClass *mc = MACHINE_CLASS(oc); 1228 IDAUInterfaceClass *iic = IDAU_INTERFACE_CLASS(oc); 1229 1230 mc->init = mps2tz_common_init; 1231 mc->reset = mps2_machine_reset; 1232 iic->check = mps2_tz_idau_check; 1233 } 1234 1235 static void mps2tz_set_default_ram_info(MPS2TZMachineClass *mmc) 1236 { 1237 /* 1238 * Set mc->default_ram_size and default_ram_id from the 1239 * information in mmc->raminfo. 1240 */ 1241 MachineClass *mc = MACHINE_CLASS(mmc); 1242 const RAMInfo *p; 1243 1244 for (p = mmc->raminfo; p->name; p++) { 1245 if (p->mrindex < 0) { 1246 /* Found the entry for "system memory" */ 1247 mc->default_ram_size = p->size; 1248 mc->default_ram_id = p->name; 1249 return; 1250 } 1251 } 1252 g_assert_not_reached(); 1253 } 1254 1255 static void mps2tz_an505_class_init(ObjectClass *oc, void *data) 1256 { 1257 MachineClass *mc = MACHINE_CLASS(oc); 1258 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc); 1259 1260 mc->desc = "ARM MPS2 with AN505 FPGA image for Cortex-M33"; 1261 mc->default_cpus = 1; 1262 mc->min_cpus = mc->default_cpus; 1263 mc->max_cpus = mc->default_cpus; 1264 mmc->fpga_type = FPGA_AN505; 1265 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"); 1266 mmc->scc_id = 0x41045050; 1267 mmc->sysclk_frq = 20 * 1000 * 1000; /* 20MHz */ 1268 mmc->apb_periph_frq = mmc->sysclk_frq; 1269 mmc->oscclk = an505_oscclk; 1270 mmc->len_oscclk = ARRAY_SIZE(an505_oscclk); 1271 mmc->fpgaio_num_leds = 2; 1272 mmc->fpgaio_has_switches = false; 1273 mmc->fpgaio_has_dbgctrl = false; 1274 mmc->numirq = 92; 1275 mmc->uart_overflow_irq = 47; 1276 mmc->init_svtor = 0x10000000; 1277 mmc->sram_addr_width = 15; 1278 mmc->raminfo = an505_raminfo; 1279 mmc->armsse_type = TYPE_IOTKIT; 1280 mmc->boot_ram_size = 0; 1281 mps2tz_set_default_ram_info(mmc); 1282 } 1283 1284 static void mps2tz_an521_class_init(ObjectClass *oc, void *data) 1285 { 1286 MachineClass *mc = MACHINE_CLASS(oc); 1287 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc); 1288 1289 mc->desc = "ARM MPS2 with AN521 FPGA image for dual Cortex-M33"; 1290 mc->default_cpus = 2; 1291 mc->min_cpus = mc->default_cpus; 1292 mc->max_cpus = mc->default_cpus; 1293 mmc->fpga_type = FPGA_AN521; 1294 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"); 1295 mmc->scc_id = 0x41045210; 1296 mmc->sysclk_frq = 20 * 1000 * 1000; /* 20MHz */ 1297 mmc->apb_periph_frq = mmc->sysclk_frq; 1298 mmc->oscclk = an505_oscclk; /* AN521 is the same as AN505 here */ 1299 mmc->len_oscclk = ARRAY_SIZE(an505_oscclk); 1300 mmc->fpgaio_num_leds = 2; 1301 mmc->fpgaio_has_switches = false; 1302 mmc->fpgaio_has_dbgctrl = false; 1303 mmc->numirq = 92; 1304 mmc->uart_overflow_irq = 47; 1305 mmc->init_svtor = 0x10000000; 1306 mmc->sram_addr_width = 15; 1307 mmc->raminfo = an505_raminfo; /* AN521 is the same as AN505 here */ 1308 mmc->armsse_type = TYPE_SSE200; 1309 mmc->boot_ram_size = 0; 1310 mps2tz_set_default_ram_info(mmc); 1311 } 1312 1313 static void mps3tz_an524_class_init(ObjectClass *oc, void *data) 1314 { 1315 MachineClass *mc = MACHINE_CLASS(oc); 1316 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc); 1317 1318 mc->desc = "ARM MPS3 with AN524 FPGA image for dual Cortex-M33"; 1319 mc->default_cpus = 2; 1320 mc->min_cpus = mc->default_cpus; 1321 mc->max_cpus = mc->default_cpus; 1322 mmc->fpga_type = FPGA_AN524; 1323 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"); 1324 mmc->scc_id = 0x41045240; 1325 mmc->sysclk_frq = 32 * 1000 * 1000; /* 32MHz */ 1326 mmc->apb_periph_frq = mmc->sysclk_frq; 1327 mmc->oscclk = an524_oscclk; 1328 mmc->len_oscclk = ARRAY_SIZE(an524_oscclk); 1329 mmc->fpgaio_num_leds = 10; 1330 mmc->fpgaio_has_switches = true; 1331 mmc->fpgaio_has_dbgctrl = false; 1332 mmc->numirq = 95; 1333 mmc->uart_overflow_irq = 47; 1334 mmc->init_svtor = 0x10000000; 1335 mmc->sram_addr_width = 15; 1336 mmc->raminfo = an524_raminfo; 1337 mmc->armsse_type = TYPE_SSE200; 1338 mmc->boot_ram_size = 0; 1339 mps2tz_set_default_ram_info(mmc); 1340 1341 object_class_property_add_str(oc, "remap", mps2_get_remap, mps2_set_remap); 1342 object_class_property_set_description(oc, "remap", 1343 "Set memory mapping. Valid values " 1344 "are BRAM (default) and QSPI."); 1345 } 1346 1347 static void mps3tz_an547_class_init(ObjectClass *oc, void *data) 1348 { 1349 MachineClass *mc = MACHINE_CLASS(oc); 1350 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc); 1351 1352 mc->desc = "ARM MPS3 with AN547 FPGA image for Cortex-M55"; 1353 mc->default_cpus = 1; 1354 mc->min_cpus = mc->default_cpus; 1355 mc->max_cpus = mc->default_cpus; 1356 mmc->fpga_type = FPGA_AN547; 1357 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m55"); 1358 mmc->scc_id = 0x41055470; 1359 mmc->sysclk_frq = 32 * 1000 * 1000; /* 32MHz */ 1360 mmc->apb_periph_frq = 25 * 1000 * 1000; /* 25MHz */ 1361 mmc->oscclk = an524_oscclk; /* same as AN524 */ 1362 mmc->len_oscclk = ARRAY_SIZE(an524_oscclk); 1363 mmc->fpgaio_num_leds = 10; 1364 mmc->fpgaio_has_switches = true; 1365 mmc->fpgaio_has_dbgctrl = true; 1366 mmc->numirq = 96; 1367 mmc->uart_overflow_irq = 48; 1368 mmc->init_svtor = 0x00000000; 1369 mmc->sram_addr_width = 21; 1370 mmc->raminfo = an547_raminfo; 1371 mmc->armsse_type = TYPE_SSE300; 1372 mmc->boot_ram_size = 512 * KiB; 1373 mps2tz_set_default_ram_info(mmc); 1374 } 1375 1376 static const TypeInfo mps2tz_info = { 1377 .name = TYPE_MPS2TZ_MACHINE, 1378 .parent = TYPE_MACHINE, 1379 .abstract = true, 1380 .instance_size = sizeof(MPS2TZMachineState), 1381 .class_size = sizeof(MPS2TZMachineClass), 1382 .class_init = mps2tz_class_init, 1383 .interfaces = (InterfaceInfo[]) { 1384 { TYPE_IDAU_INTERFACE }, 1385 { } 1386 }, 1387 }; 1388 1389 static const TypeInfo mps2tz_an505_info = { 1390 .name = TYPE_MPS2TZ_AN505_MACHINE, 1391 .parent = TYPE_MPS2TZ_MACHINE, 1392 .class_init = mps2tz_an505_class_init, 1393 }; 1394 1395 static const TypeInfo mps2tz_an521_info = { 1396 .name = TYPE_MPS2TZ_AN521_MACHINE, 1397 .parent = TYPE_MPS2TZ_MACHINE, 1398 .class_init = mps2tz_an521_class_init, 1399 }; 1400 1401 static const TypeInfo mps3tz_an524_info = { 1402 .name = TYPE_MPS3TZ_AN524_MACHINE, 1403 .parent = TYPE_MPS2TZ_MACHINE, 1404 .class_init = mps3tz_an524_class_init, 1405 }; 1406 1407 static const TypeInfo mps3tz_an547_info = { 1408 .name = TYPE_MPS3TZ_AN547_MACHINE, 1409 .parent = TYPE_MPS2TZ_MACHINE, 1410 .class_init = mps3tz_an547_class_init, 1411 }; 1412 1413 static void mps2tz_machine_init(void) 1414 { 1415 type_register_static(&mps2tz_info); 1416 type_register_static(&mps2tz_an505_info); 1417 type_register_static(&mps2tz_an521_info); 1418 type_register_static(&mps3tz_an524_info); 1419 type_register_static(&mps3tz_an547_info); 1420 } 1421 1422 type_init(mps2tz_machine_init); 1423