1 /* 2 * Copyright (c) 2015 Jean-Christophe Dubois <jcd@tribudubois.net> 3 * 4 * i.MX6 SOC emulation. 5 * 6 * Based on hw/arm/fsl-imx31.c 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, but WITHOUT 14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 16 * for more details. 17 * 18 * You should have received a copy of the GNU General Public License along 19 * with this program; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #include "qemu/osdep.h" 23 #include "qapi/error.h" 24 #include "hw/arm/fsl-imx6.h" 25 #include "hw/misc/unimp.h" 26 #include "hw/usb/imx-usb-phy.h" 27 #include "hw/boards.h" 28 #include "hw/qdev-properties.h" 29 #include "system/system.h" 30 #include "chardev/char.h" 31 #include "qemu/error-report.h" 32 #include "qemu/module.h" 33 #include "target/arm/cpu-qom.h" 34 35 #define IMX6_ESDHC_CAPABILITIES 0x057834b4 36 37 #define NAME_SIZE 20 38 39 static void fsl_imx6_init(Object *obj) 40 { 41 MachineState *ms = MACHINE(qdev_get_machine()); 42 FslIMX6State *s = FSL_IMX6(obj); 43 char name[NAME_SIZE]; 44 int i; 45 46 for (i = 0; i < MIN(ms->smp.cpus, FSL_IMX6_NUM_CPUS); i++) { 47 snprintf(name, NAME_SIZE, "cpu%d", i); 48 object_initialize_child(obj, name, &s->cpu[i], 49 ARM_CPU_TYPE_NAME("cortex-a9")); 50 } 51 52 object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV); 53 54 object_initialize_child(obj, "ccm", &s->ccm, TYPE_IMX6_CCM); 55 56 object_initialize_child(obj, "src", &s->src, TYPE_IMX6_SRC); 57 58 object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS); 59 60 for (i = 0; i < FSL_IMX6_NUM_UARTS; i++) { 61 snprintf(name, NAME_SIZE, "uart%d", i + 1); 62 object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL); 63 } 64 65 object_initialize_child(obj, "gpt", &s->gpt, TYPE_IMX6_GPT); 66 67 for (i = 0; i < FSL_IMX6_NUM_EPITS; i++) { 68 snprintf(name, NAME_SIZE, "epit%d", i + 1); 69 object_initialize_child(obj, name, &s->epit[i], TYPE_IMX_EPIT); 70 } 71 72 for (i = 0; i < FSL_IMX6_NUM_I2CS; i++) { 73 snprintf(name, NAME_SIZE, "i2c%d", i + 1); 74 object_initialize_child(obj, name, &s->i2c[i], TYPE_IMX_I2C); 75 } 76 77 for (i = 0; i < FSL_IMX6_NUM_GPIOS; i++) { 78 snprintf(name, NAME_SIZE, "gpio%d", i + 1); 79 object_initialize_child(obj, name, &s->gpio[i], TYPE_IMX_GPIO); 80 } 81 82 for (i = 0; i < FSL_IMX6_NUM_ESDHCS; i++) { 83 snprintf(name, NAME_SIZE, "sdhc%d", i + 1); 84 object_initialize_child(obj, name, &s->esdhc[i], TYPE_IMX_USDHC); 85 } 86 87 for (i = 0; i < FSL_IMX6_NUM_USB_PHYS; i++) { 88 snprintf(name, NAME_SIZE, "usbphy%d", i); 89 object_initialize_child(obj, name, &s->usbphy[i], TYPE_IMX_USBPHY); 90 } 91 for (i = 0; i < FSL_IMX6_NUM_USBS; i++) { 92 snprintf(name, NAME_SIZE, "usb%d", i); 93 object_initialize_child(obj, name, &s->usb[i], TYPE_CHIPIDEA); 94 } 95 96 for (i = 0; i < FSL_IMX6_NUM_ECSPIS; i++) { 97 snprintf(name, NAME_SIZE, "spi%d", i + 1); 98 object_initialize_child(obj, name, &s->spi[i], TYPE_IMX_SPI); 99 } 100 for (i = 0; i < FSL_IMX6_NUM_WDTS; i++) { 101 snprintf(name, NAME_SIZE, "wdt%d", i); 102 object_initialize_child(obj, name, &s->wdt[i], TYPE_IMX2_WDT); 103 } 104 105 106 object_initialize_child(obj, "eth", &s->eth, TYPE_IMX_ENET); 107 108 object_initialize_child(obj, "pcie", &s->pcie, TYPE_DESIGNWARE_PCIE_HOST); 109 object_initialize_child(obj, "pcie4-msi-irq", &s->pcie4_msi_irq, 110 TYPE_OR_IRQ); 111 } 112 113 static void fsl_imx6_realize(DeviceState *dev, Error **errp) 114 { 115 MachineState *ms = MACHINE(qdev_get_machine()); 116 FslIMX6State *s = FSL_IMX6(dev); 117 uint16_t i; 118 qemu_irq irq; 119 unsigned int smp_cpus = ms->smp.cpus; 120 121 if (smp_cpus > FSL_IMX6_NUM_CPUS) { 122 error_setg(errp, "%s: Only %d CPUs are supported (%d requested)", 123 TYPE_FSL_IMX6, FSL_IMX6_NUM_CPUS, smp_cpus); 124 return; 125 } 126 127 for (i = 0; i < smp_cpus; i++) { 128 129 /* On uniprocessor, the CBAR is set to 0 */ 130 if (smp_cpus > 1) { 131 object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar", 132 FSL_IMX6_A9MPCORE_ADDR, &error_abort); 133 } 134 135 /* All CPU but CPU 0 start in power off mode */ 136 if (i) { 137 object_property_set_bool(OBJECT(&s->cpu[i]), "start-powered-off", 138 true, &error_abort); 139 } 140 141 if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) { 142 return; 143 } 144 } 145 146 object_property_set_int(OBJECT(&s->a9mpcore), "num-cpu", smp_cpus, 147 &error_abort); 148 149 object_property_set_int(OBJECT(&s->a9mpcore), "num-irq", 150 FSL_IMX6_MAX_IRQ + GIC_INTERNAL, &error_abort); 151 152 if (!sysbus_realize(SYS_BUS_DEVICE(&s->a9mpcore), errp)) { 153 return; 154 } 155 sysbus_mmio_map(SYS_BUS_DEVICE(&s->a9mpcore), 0, FSL_IMX6_A9MPCORE_ADDR); 156 157 for (i = 0; i < smp_cpus; i++) { 158 sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i, 159 qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IRQ)); 160 sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i + smp_cpus, 161 qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_FIQ)); 162 } 163 164 /* L2 cache controller */ 165 sysbus_create_simple("l2x0", FSL_IMX6_PL310_ADDR, NULL); 166 167 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ccm), errp)) { 168 return; 169 } 170 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX6_CCM_ADDR); 171 172 if (!sysbus_realize(SYS_BUS_DEVICE(&s->src), errp)) { 173 return; 174 } 175 sysbus_mmio_map(SYS_BUS_DEVICE(&s->src), 0, FSL_IMX6_SRC_ADDR); 176 177 /* Initialize all UARTs */ 178 for (i = 0; i < FSL_IMX6_NUM_UARTS; i++) { 179 static const struct { 180 hwaddr addr; 181 unsigned int irq; 182 } serial_table[FSL_IMX6_NUM_UARTS] = { 183 { FSL_IMX6_UART1_ADDR, FSL_IMX6_UART1_IRQ }, 184 { FSL_IMX6_UART2_ADDR, FSL_IMX6_UART2_IRQ }, 185 { FSL_IMX6_UART3_ADDR, FSL_IMX6_UART3_IRQ }, 186 { FSL_IMX6_UART4_ADDR, FSL_IMX6_UART4_IRQ }, 187 { FSL_IMX6_UART5_ADDR, FSL_IMX6_UART5_IRQ }, 188 }; 189 190 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i)); 191 192 if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), errp)) { 193 return; 194 } 195 196 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr); 197 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, 198 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 199 serial_table[i].irq)); 200 } 201 202 s->gpt.ccm = IMX_CCM(&s->ccm); 203 204 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpt), errp)) { 205 return; 206 } 207 208 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt), 0, FSL_IMX6_GPT_ADDR); 209 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt), 0, 210 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 211 FSL_IMX6_GPT_IRQ)); 212 213 /* Initialize all EPIT timers */ 214 for (i = 0; i < FSL_IMX6_NUM_EPITS; i++) { 215 static const struct { 216 hwaddr addr; 217 unsigned int irq; 218 } epit_table[FSL_IMX6_NUM_EPITS] = { 219 { FSL_IMX6_EPIT1_ADDR, FSL_IMX6_EPIT1_IRQ }, 220 { FSL_IMX6_EPIT2_ADDR, FSL_IMX6_EPIT2_IRQ }, 221 }; 222 223 s->epit[i].ccm = IMX_CCM(&s->ccm); 224 225 if (!sysbus_realize(SYS_BUS_DEVICE(&s->epit[i]), errp)) { 226 return; 227 } 228 229 sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr); 230 sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0, 231 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 232 epit_table[i].irq)); 233 } 234 235 /* Initialize all I2C */ 236 for (i = 0; i < FSL_IMX6_NUM_I2CS; i++) { 237 static const struct { 238 hwaddr addr; 239 unsigned int irq; 240 } i2c_table[FSL_IMX6_NUM_I2CS] = { 241 { FSL_IMX6_I2C1_ADDR, FSL_IMX6_I2C1_IRQ }, 242 { FSL_IMX6_I2C2_ADDR, FSL_IMX6_I2C2_IRQ }, 243 { FSL_IMX6_I2C3_ADDR, FSL_IMX6_I2C3_IRQ } 244 }; 245 246 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c[i]), errp)) { 247 return; 248 } 249 250 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr); 251 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0, 252 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 253 i2c_table[i].irq)); 254 } 255 256 /* Initialize all GPIOs */ 257 for (i = 0; i < FSL_IMX6_NUM_GPIOS; i++) { 258 static const struct { 259 hwaddr addr; 260 unsigned int irq_low; 261 unsigned int irq_high; 262 } gpio_table[FSL_IMX6_NUM_GPIOS] = { 263 { 264 FSL_IMX6_GPIO1_ADDR, 265 FSL_IMX6_GPIO1_LOW_IRQ, 266 FSL_IMX6_GPIO1_HIGH_IRQ 267 }, 268 { 269 FSL_IMX6_GPIO2_ADDR, 270 FSL_IMX6_GPIO2_LOW_IRQ, 271 FSL_IMX6_GPIO2_HIGH_IRQ 272 }, 273 { 274 FSL_IMX6_GPIO3_ADDR, 275 FSL_IMX6_GPIO3_LOW_IRQ, 276 FSL_IMX6_GPIO3_HIGH_IRQ 277 }, 278 { 279 FSL_IMX6_GPIO4_ADDR, 280 FSL_IMX6_GPIO4_LOW_IRQ, 281 FSL_IMX6_GPIO4_HIGH_IRQ 282 }, 283 { 284 FSL_IMX6_GPIO5_ADDR, 285 FSL_IMX6_GPIO5_LOW_IRQ, 286 FSL_IMX6_GPIO5_HIGH_IRQ 287 }, 288 { 289 FSL_IMX6_GPIO6_ADDR, 290 FSL_IMX6_GPIO6_LOW_IRQ, 291 FSL_IMX6_GPIO6_HIGH_IRQ 292 }, 293 { 294 FSL_IMX6_GPIO7_ADDR, 295 FSL_IMX6_GPIO7_LOW_IRQ, 296 FSL_IMX6_GPIO7_HIGH_IRQ 297 }, 298 }; 299 300 object_property_set_bool(OBJECT(&s->gpio[i]), "has-edge-sel", true, 301 &error_abort); 302 object_property_set_bool(OBJECT(&s->gpio[i]), "has-upper-pin-irq", 303 true, &error_abort); 304 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), errp)) { 305 return; 306 } 307 308 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr); 309 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0, 310 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 311 gpio_table[i].irq_low)); 312 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1, 313 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 314 gpio_table[i].irq_high)); 315 } 316 317 /* Initialize all SDHC */ 318 for (i = 0; i < FSL_IMX6_NUM_ESDHCS; i++) { 319 static const struct { 320 hwaddr addr; 321 unsigned int irq; 322 } esdhc_table[FSL_IMX6_NUM_ESDHCS] = { 323 { FSL_IMX6_uSDHC1_ADDR, FSL_IMX6_uSDHC1_IRQ }, 324 { FSL_IMX6_uSDHC2_ADDR, FSL_IMX6_uSDHC2_IRQ }, 325 { FSL_IMX6_uSDHC3_ADDR, FSL_IMX6_uSDHC3_IRQ }, 326 { FSL_IMX6_uSDHC4_ADDR, FSL_IMX6_uSDHC4_IRQ }, 327 }; 328 329 /* UHS-I SDIO3.0 SDR104 1.8V ADMA */ 330 object_property_set_uint(OBJECT(&s->esdhc[i]), "sd-spec-version", 3, 331 &error_abort); 332 object_property_set_uint(OBJECT(&s->esdhc[i]), "capareg", 333 IMX6_ESDHC_CAPABILITIES, &error_abort); 334 object_property_set_uint(OBJECT(&s->esdhc[i]), "vendor", 335 SDHCI_VENDOR_IMX, &error_abort); 336 if (!sysbus_realize(SYS_BUS_DEVICE(&s->esdhc[i]), errp)) { 337 return; 338 } 339 sysbus_mmio_map(SYS_BUS_DEVICE(&s->esdhc[i]), 0, esdhc_table[i].addr); 340 sysbus_connect_irq(SYS_BUS_DEVICE(&s->esdhc[i]), 0, 341 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 342 esdhc_table[i].irq)); 343 } 344 345 /* USB */ 346 for (i = 0; i < FSL_IMX6_NUM_USB_PHYS; i++) { 347 sysbus_realize(SYS_BUS_DEVICE(&s->usbphy[i]), &error_abort); 348 sysbus_mmio_map(SYS_BUS_DEVICE(&s->usbphy[i]), 0, 349 FSL_IMX6_USBPHY1_ADDR + i * 0x1000); 350 } 351 for (i = 0; i < FSL_IMX6_NUM_USBS; i++) { 352 static const int FSL_IMX6_USBn_IRQ[] = { 353 FSL_IMX6_USB_OTG_IRQ, 354 FSL_IMX6_USB_HOST1_IRQ, 355 FSL_IMX6_USB_HOST2_IRQ, 356 FSL_IMX6_USB_HOST3_IRQ, 357 }; 358 359 sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), &error_abort); 360 sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0, 361 FSL_IMX6_USBOH3_USB_ADDR + i * 0x200); 362 sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0, 363 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 364 FSL_IMX6_USBn_IRQ[i])); 365 } 366 367 /* Initialize all ECSPI */ 368 for (i = 0; i < FSL_IMX6_NUM_ECSPIS; i++) { 369 static const struct { 370 hwaddr addr; 371 unsigned int irq; 372 } spi_table[FSL_IMX6_NUM_ECSPIS] = { 373 { FSL_IMX6_eCSPI1_ADDR, FSL_IMX6_ECSPI1_IRQ }, 374 { FSL_IMX6_eCSPI2_ADDR, FSL_IMX6_ECSPI2_IRQ }, 375 { FSL_IMX6_eCSPI3_ADDR, FSL_IMX6_ECSPI3_IRQ }, 376 { FSL_IMX6_eCSPI4_ADDR, FSL_IMX6_ECSPI4_IRQ }, 377 { FSL_IMX6_eCSPI5_ADDR, FSL_IMX6_ECSPI5_IRQ }, 378 }; 379 380 /* Initialize the SPI */ 381 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { 382 return; 383 } 384 385 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_table[i].addr); 386 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0, 387 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 388 spi_table[i].irq)); 389 } 390 391 object_property_set_uint(OBJECT(&s->eth), "phy-num", s->phy_num, 392 &error_abort); 393 qemu_configure_nic_device(DEVICE(&s->eth), true, NULL); 394 if (!sysbus_realize(SYS_BUS_DEVICE(&s->eth), errp)) { 395 return; 396 } 397 sysbus_mmio_map(SYS_BUS_DEVICE(&s->eth), 0, FSL_IMX6_ENET_ADDR); 398 sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth), 0, 399 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 400 FSL_IMX6_ENET_MAC_IRQ)); 401 sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth), 1, 402 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 403 FSL_IMX6_ENET_MAC_1588_IRQ)); 404 405 /* 406 * SNVS 407 */ 408 sysbus_realize(SYS_BUS_DEVICE(&s->snvs), &error_abort); 409 sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX6_SNVSHP_ADDR); 410 411 /* 412 * Watchdog 413 */ 414 for (i = 0; i < FSL_IMX6_NUM_WDTS; i++) { 415 static const hwaddr FSL_IMX6_WDOGn_ADDR[FSL_IMX6_NUM_WDTS] = { 416 FSL_IMX6_WDOG1_ADDR, 417 FSL_IMX6_WDOG2_ADDR, 418 }; 419 static const int FSL_IMX6_WDOGn_IRQ[FSL_IMX6_NUM_WDTS] = { 420 FSL_IMX6_WDOG1_IRQ, 421 FSL_IMX6_WDOG2_IRQ, 422 }; 423 424 object_property_set_bool(OBJECT(&s->wdt[i]), "pretimeout-support", 425 true, &error_abort); 426 sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), &error_abort); 427 428 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, FSL_IMX6_WDOGn_ADDR[i]); 429 sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[i]), 0, 430 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 431 FSL_IMX6_WDOGn_IRQ[i])); 432 } 433 434 /* 435 * PCIe 436 */ 437 sysbus_realize(SYS_BUS_DEVICE(&s->pcie), &error_abort); 438 sysbus_mmio_map(SYS_BUS_DEVICE(&s->pcie), 0, FSL_IMX6_PCIe_REG_ADDR); 439 440 object_property_set_int(OBJECT(&s->pcie4_msi_irq), "num-lines", 2, 441 &error_abort); 442 qdev_realize(DEVICE(&s->pcie4_msi_irq), NULL, &error_abort); 443 444 irq = qdev_get_gpio_in(DEVICE(&s->a9mpcore), FSL_IMX6_PCIE4_MSI_IRQ); 445 qdev_connect_gpio_out(DEVICE(&s->pcie4_msi_irq), 0, irq); 446 447 irq = qdev_get_gpio_in(DEVICE(&s->a9mpcore), FSL_IMX6_PCIE1_IRQ); 448 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 0, irq); 449 irq = qdev_get_gpio_in(DEVICE(&s->a9mpcore), FSL_IMX6_PCIE2_IRQ); 450 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 1, irq); 451 irq = qdev_get_gpio_in(DEVICE(&s->a9mpcore), FSL_IMX6_PCIE3_IRQ); 452 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 2, irq); 453 irq = qdev_get_gpio_in(DEVICE(&s->pcie4_msi_irq), 0); 454 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 3, irq); 455 irq = qdev_get_gpio_in(DEVICE(&s->pcie4_msi_irq), 1); 456 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 4, irq); 457 458 /* 459 * PCIe PHY 460 */ 461 create_unimplemented_device("pcie-phy", FSL_IMX6_PCIe_ADDR, 462 FSL_IMX6_PCIe_SIZE); 463 464 /* ROM memory */ 465 if (!memory_region_init_rom(&s->rom, OBJECT(dev), "imx6.rom", 466 FSL_IMX6_ROM_SIZE, errp)) { 467 return; 468 } 469 memory_region_add_subregion(get_system_memory(), FSL_IMX6_ROM_ADDR, 470 &s->rom); 471 472 /* CAAM memory */ 473 if (!memory_region_init_rom(&s->caam, OBJECT(dev), "imx6.caam", 474 FSL_IMX6_CAAM_MEM_SIZE, errp)) { 475 return; 476 } 477 memory_region_add_subregion(get_system_memory(), FSL_IMX6_CAAM_MEM_ADDR, 478 &s->caam); 479 480 /* OCRAM memory */ 481 if (!memory_region_init_ram(&s->ocram, NULL, "imx6.ocram", 482 FSL_IMX6_OCRAM_SIZE, errp)) { 483 return; 484 } 485 memory_region_add_subregion(get_system_memory(), FSL_IMX6_OCRAM_ADDR, 486 &s->ocram); 487 488 /* internal OCRAM (256 KB) is aliased over 1 MB */ 489 memory_region_init_alias(&s->ocram_alias, OBJECT(dev), "imx6.ocram_alias", 490 &s->ocram, 0, FSL_IMX6_OCRAM_ALIAS_SIZE); 491 memory_region_add_subregion(get_system_memory(), FSL_IMX6_OCRAM_ALIAS_ADDR, 492 &s->ocram_alias); 493 } 494 495 static const Property fsl_imx6_properties[] = { 496 DEFINE_PROP_UINT32("fec-phy-num", FslIMX6State, phy_num, 0), 497 }; 498 499 static void fsl_imx6_class_init(ObjectClass *oc, void *data) 500 { 501 DeviceClass *dc = DEVICE_CLASS(oc); 502 503 device_class_set_props(dc, fsl_imx6_properties); 504 dc->realize = fsl_imx6_realize; 505 dc->desc = "i.MX6 SOC"; 506 /* Reason: Uses serial_hd() in the realize() function */ 507 dc->user_creatable = false; 508 } 509 510 static const TypeInfo fsl_imx6_type_info = { 511 .name = TYPE_FSL_IMX6, 512 .parent = TYPE_DEVICE, 513 .instance_size = sizeof(FslIMX6State), 514 .instance_init = fsl_imx6_init, 515 .class_init = fsl_imx6_class_init, 516 }; 517 518 static void fsl_imx6_register_types(void) 519 { 520 type_register_static(&fsl_imx6_type_info); 521 } 522 523 type_init(fsl_imx6_register_types) 524