1 /* 2 * Samsung exynos4210 SoC emulation 3 * 4 * Copyright (c) 2011 Samsung Electronics Co., Ltd. All rights reserved. 5 * Maksim Kozlov <m.kozlov@samsung.com> 6 * Evgeny Voevodin <e.voevodin@samsung.com> 7 * Igor Mitsyanko <i.mitsyanko@samsung.com> 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License as published by the 11 * Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, but WITHOUT 15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 17 * for more details. 18 * 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, see <http://www.gnu.org/licenses/>. 21 * 22 */ 23 24 #include "qemu/osdep.h" 25 #include "qapi/error.h" 26 #include "exec/tswap.h" 27 #include "cpu.h" 28 #include "hw/cpu/a9mpcore.h" 29 #include "hw/irq.h" 30 #include "system/blockdev.h" 31 #include "system/system.h" 32 #include "hw/sysbus.h" 33 #include "hw/arm/boot.h" 34 #include "hw/loader.h" 35 #include "hw/qdev-properties.h" 36 #include "hw/arm/exynos4210.h" 37 #include "hw/sd/sdhci.h" 38 #include "hw/usb/hcd-ehci.h" 39 #include "target/arm/cpu-qom.h" 40 41 #define EXYNOS4210_CHIPID_ADDR 0x10000000 42 43 /* PWM */ 44 #define EXYNOS4210_PWM_BASE_ADDR 0x139D0000 45 46 /* RTC */ 47 #define EXYNOS4210_RTC_BASE_ADDR 0x10070000 48 49 /* MCT */ 50 #define EXYNOS4210_MCT_BASE_ADDR 0x10050000 51 52 /* I2C */ 53 #define EXYNOS4210_I2C_SHIFT 0x00010000 54 #define EXYNOS4210_I2C_BASE_ADDR 0x13860000 55 /* Interrupt Group of External Interrupt Combiner for I2C */ 56 #define EXYNOS4210_I2C_INTG 27 57 #define EXYNOS4210_HDMI_INTG 16 58 59 /* UART's definitions */ 60 #define EXYNOS4210_UART0_BASE_ADDR 0x13800000 61 #define EXYNOS4210_UART1_BASE_ADDR 0x13810000 62 #define EXYNOS4210_UART2_BASE_ADDR 0x13820000 63 #define EXYNOS4210_UART3_BASE_ADDR 0x13830000 64 #define EXYNOS4210_UART0_FIFO_SIZE 256 65 #define EXYNOS4210_UART1_FIFO_SIZE 64 66 #define EXYNOS4210_UART2_FIFO_SIZE 16 67 #define EXYNOS4210_UART3_FIFO_SIZE 16 68 /* Interrupt Group of External Interrupt Combiner for UART */ 69 #define EXYNOS4210_UART_INT_GRP 26 70 71 /* External GIC */ 72 #define EXYNOS4210_EXT_GIC_CPU_BASE_ADDR 0x10480000 73 #define EXYNOS4210_EXT_GIC_DIST_BASE_ADDR 0x10490000 74 75 /* Combiner */ 76 #define EXYNOS4210_EXT_COMBINER_BASE_ADDR 0x10440000 77 #define EXYNOS4210_INT_COMBINER_BASE_ADDR 0x10448000 78 79 /* SD/MMC host controllers */ 80 #define EXYNOS4210_SDHCI_CAPABILITIES 0x05E80080 81 #define EXYNOS4210_SDHCI_BASE_ADDR 0x12510000 82 #define EXYNOS4210_SDHCI_ADDR(n) (EXYNOS4210_SDHCI_BASE_ADDR + \ 83 0x00010000 * (n)) 84 #define EXYNOS4210_SDHCI_NUMBER 4 85 86 /* PMU SFR base address */ 87 #define EXYNOS4210_PMU_BASE_ADDR 0x10020000 88 89 /* Clock controller SFR base address */ 90 #define EXYNOS4210_CLK_BASE_ADDR 0x10030000 91 92 /* PRNG/HASH SFR base address */ 93 #define EXYNOS4210_RNG_BASE_ADDR 0x10830400 94 95 /* Display controllers (FIMD) */ 96 #define EXYNOS4210_FIMD0_BASE_ADDR 0x11C00000 97 98 /* EHCI */ 99 #define EXYNOS4210_EHCI_BASE_ADDR 0x12580000 100 101 /* DMA */ 102 #define EXYNOS4210_PL330_BASE0_ADDR 0x12680000 103 #define EXYNOS4210_PL330_BASE1_ADDR 0x12690000 104 #define EXYNOS4210_PL330_BASE2_ADDR 0x12850000 105 106 #define GIC_EXT_IRQS 64 /* FIXME: verify for this SoC */ 107 108 enum ExtGicId { 109 EXT_GIC_ID_MDMA_LCD0 = 66, 110 EXT_GIC_ID_PDMA0, 111 EXT_GIC_ID_PDMA1, 112 EXT_GIC_ID_TIMER0, 113 EXT_GIC_ID_TIMER1, 114 EXT_GIC_ID_TIMER2, 115 EXT_GIC_ID_TIMER3, 116 EXT_GIC_ID_TIMER4, 117 EXT_GIC_ID_MCT_L0, 118 EXT_GIC_ID_WDT, 119 EXT_GIC_ID_RTC_ALARM, 120 EXT_GIC_ID_RTC_TIC, 121 EXT_GIC_ID_GPIO_XB, 122 EXT_GIC_ID_GPIO_XA, 123 EXT_GIC_ID_MCT_L1, 124 EXT_GIC_ID_IEM_APC, 125 EXT_GIC_ID_IEM_IEC, 126 EXT_GIC_ID_NFC, 127 EXT_GIC_ID_UART0, 128 EXT_GIC_ID_UART1, 129 EXT_GIC_ID_UART2, 130 EXT_GIC_ID_UART3, 131 EXT_GIC_ID_UART4, 132 EXT_GIC_ID_MCT_G0, 133 EXT_GIC_ID_I2C0, 134 EXT_GIC_ID_I2C1, 135 EXT_GIC_ID_I2C2, 136 EXT_GIC_ID_I2C3, 137 EXT_GIC_ID_I2C4, 138 EXT_GIC_ID_I2C5, 139 EXT_GIC_ID_I2C6, 140 EXT_GIC_ID_I2C7, 141 EXT_GIC_ID_SPI0, 142 EXT_GIC_ID_SPI1, 143 EXT_GIC_ID_SPI2, 144 EXT_GIC_ID_MCT_G1, 145 EXT_GIC_ID_USB_HOST, 146 EXT_GIC_ID_USB_DEVICE, 147 EXT_GIC_ID_MODEMIF, 148 EXT_GIC_ID_HSMMC0, 149 EXT_GIC_ID_HSMMC1, 150 EXT_GIC_ID_HSMMC2, 151 EXT_GIC_ID_HSMMC3, 152 EXT_GIC_ID_SDMMC, 153 EXT_GIC_ID_MIPI_CSI_4LANE, 154 EXT_GIC_ID_MIPI_DSI_4LANE, 155 EXT_GIC_ID_MIPI_CSI_2LANE, 156 EXT_GIC_ID_MIPI_DSI_2LANE, 157 EXT_GIC_ID_ONENAND_AUDI, 158 EXT_GIC_ID_ROTATOR, 159 EXT_GIC_ID_FIMC0, 160 EXT_GIC_ID_FIMC1, 161 EXT_GIC_ID_FIMC2, 162 EXT_GIC_ID_FIMC3, 163 EXT_GIC_ID_JPEG, 164 EXT_GIC_ID_2D, 165 EXT_GIC_ID_PCIe, 166 EXT_GIC_ID_MIXER, 167 EXT_GIC_ID_HDMI, 168 EXT_GIC_ID_HDMI_I2C, 169 EXT_GIC_ID_MFC, 170 EXT_GIC_ID_TVENC, 171 }; 172 173 enum ExtInt { 174 EXT_GIC_ID_EXTINT0 = 48, 175 EXT_GIC_ID_EXTINT1, 176 EXT_GIC_ID_EXTINT2, 177 EXT_GIC_ID_EXTINT3, 178 EXT_GIC_ID_EXTINT4, 179 EXT_GIC_ID_EXTINT5, 180 EXT_GIC_ID_EXTINT6, 181 EXT_GIC_ID_EXTINT7, 182 EXT_GIC_ID_EXTINT8, 183 EXT_GIC_ID_EXTINT9, 184 EXT_GIC_ID_EXTINT10, 185 EXT_GIC_ID_EXTINT11, 186 EXT_GIC_ID_EXTINT12, 187 EXT_GIC_ID_EXTINT13, 188 EXT_GIC_ID_EXTINT14, 189 EXT_GIC_ID_EXTINT15 190 }; 191 192 /* 193 * External GIC sources which are not from External Interrupt Combiner or 194 * External Interrupts are starting from EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ, 195 * which is INTG16 in Internal Interrupt Combiner. 196 */ 197 198 static const uint32_t 199 combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = { 200 /* int combiner groups 16-19 */ 201 { }, { }, { }, { }, 202 /* int combiner group 20 */ 203 { 0, EXT_GIC_ID_MDMA_LCD0 }, 204 /* int combiner group 21 */ 205 { EXT_GIC_ID_PDMA0, EXT_GIC_ID_PDMA1 }, 206 /* int combiner group 22 */ 207 { EXT_GIC_ID_TIMER0, EXT_GIC_ID_TIMER1, EXT_GIC_ID_TIMER2, 208 EXT_GIC_ID_TIMER3, EXT_GIC_ID_TIMER4 }, 209 /* int combiner group 23 */ 210 { EXT_GIC_ID_RTC_ALARM, EXT_GIC_ID_RTC_TIC }, 211 /* int combiner group 24 */ 212 { EXT_GIC_ID_GPIO_XB, EXT_GIC_ID_GPIO_XA }, 213 /* int combiner group 25 */ 214 { EXT_GIC_ID_IEM_APC, EXT_GIC_ID_IEM_IEC }, 215 /* int combiner group 26 */ 216 { EXT_GIC_ID_UART0, EXT_GIC_ID_UART1, EXT_GIC_ID_UART2, EXT_GIC_ID_UART3, 217 EXT_GIC_ID_UART4 }, 218 /* int combiner group 27 */ 219 { EXT_GIC_ID_I2C0, EXT_GIC_ID_I2C1, EXT_GIC_ID_I2C2, EXT_GIC_ID_I2C3, 220 EXT_GIC_ID_I2C4, EXT_GIC_ID_I2C5, EXT_GIC_ID_I2C6, 221 EXT_GIC_ID_I2C7 }, 222 /* int combiner group 28 */ 223 { EXT_GIC_ID_SPI0, EXT_GIC_ID_SPI1, EXT_GIC_ID_SPI2 , EXT_GIC_ID_USB_HOST}, 224 /* int combiner group 29 */ 225 { EXT_GIC_ID_HSMMC0, EXT_GIC_ID_HSMMC1, EXT_GIC_ID_HSMMC2, 226 EXT_GIC_ID_HSMMC3, EXT_GIC_ID_SDMMC }, 227 /* int combiner group 30 */ 228 { EXT_GIC_ID_MIPI_CSI_4LANE, EXT_GIC_ID_MIPI_CSI_2LANE }, 229 /* int combiner group 31 */ 230 { EXT_GIC_ID_MIPI_DSI_4LANE, EXT_GIC_ID_MIPI_DSI_2LANE }, 231 /* int combiner group 32 */ 232 { EXT_GIC_ID_FIMC0, EXT_GIC_ID_FIMC1 }, 233 /* int combiner group 33 */ 234 { EXT_GIC_ID_FIMC2, EXT_GIC_ID_FIMC3 }, 235 /* int combiner group 34 */ 236 { EXT_GIC_ID_ONENAND_AUDI, EXT_GIC_ID_NFC }, 237 /* int combiner group 35 */ 238 { 0, 0, 0, EXT_GIC_ID_MCT_L1 }, 239 /* int combiner group 36 */ 240 { EXT_GIC_ID_MIXER }, 241 /* int combiner group 37 */ 242 { EXT_GIC_ID_EXTINT4, EXT_GIC_ID_EXTINT5, EXT_GIC_ID_EXTINT6, 243 EXT_GIC_ID_EXTINT7 }, 244 /* groups 38-50 */ 245 { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, 246 /* int combiner group 51 */ 247 { EXT_GIC_ID_MCT_L0 }, 248 /* group 52 */ 249 { }, 250 /* int combiner group 53 */ 251 { EXT_GIC_ID_WDT }, 252 /* groups 54-63 */ 253 { }, { }, { }, { }, { }, { }, { }, { }, { }, { } 254 }; 255 256 #define EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit) ((grp) * 8 + (bit)) 257 #define EXYNOS4210_COMBINER_GET_GRP_NUM(irq) ((irq) / 8) 258 #define EXYNOS4210_COMBINER_GET_BIT_NUM(irq) \ 259 ((irq) - 8 * EXYNOS4210_COMBINER_GET_GRP_NUM(irq)) 260 261 /* 262 * Some interrupt lines go to multiple combiner inputs. 263 * This data structure defines those: each array element is 264 * a list of combiner inputs which are connected together; 265 * the one with the smallest interrupt ID value must be first. 266 * As with combiner_grp_to_gic_id[], we rely on (0, 0) not being 267 * wired to anything so we can use 0 as a terminator. 268 */ 269 #define IRQNO(G, B) EXYNOS4210_COMBINER_GET_IRQ_NUM(G, B) 270 #define IRQNONE 0 271 272 #define COMBINERMAP_SIZE 16 273 274 static const int combinermap[COMBINERMAP_SIZE][6] = { 275 /* MDNIE_LCD1 */ 276 { IRQNO(0, 4), IRQNO(1, 0), IRQNONE }, 277 { IRQNO(0, 5), IRQNO(1, 1), IRQNONE }, 278 { IRQNO(0, 6), IRQNO(1, 2), IRQNONE }, 279 { IRQNO(0, 7), IRQNO(1, 3), IRQNONE }, 280 /* TMU */ 281 { IRQNO(2, 4), IRQNO(3, 4), IRQNONE }, 282 { IRQNO(2, 5), IRQNO(3, 5), IRQNONE }, 283 { IRQNO(2, 6), IRQNO(3, 6), IRQNONE }, 284 { IRQNO(2, 7), IRQNO(3, 7), IRQNONE }, 285 /* LCD1 */ 286 { IRQNO(11, 4), IRQNO(12, 0), IRQNONE }, 287 { IRQNO(11, 5), IRQNO(12, 1), IRQNONE }, 288 { IRQNO(11, 6), IRQNO(12, 2), IRQNONE }, 289 { IRQNO(11, 7), IRQNO(12, 3), IRQNONE }, 290 /* Multi-core timer */ 291 { IRQNO(1, 4), IRQNO(12, 4), IRQNO(35, 4), IRQNO(51, 4), IRQNO(53, 4), IRQNONE }, 292 { IRQNO(1, 5), IRQNO(12, 5), IRQNO(35, 5), IRQNO(51, 5), IRQNO(53, 5), IRQNONE }, 293 { IRQNO(1, 6), IRQNO(12, 6), IRQNO(35, 6), IRQNO(51, 6), IRQNO(53, 6), IRQNONE }, 294 { IRQNO(1, 7), IRQNO(12, 7), IRQNO(35, 7), IRQNO(51, 7), IRQNO(53, 7), IRQNONE }, 295 }; 296 297 #undef IRQNO 298 299 static const int *combinermap_entry(int irq) 300 { 301 /* 302 * If the interrupt number passed in is the first entry in some 303 * line of the combinermap, return a pointer to that line; 304 * otherwise return NULL. 305 */ 306 int i; 307 for (i = 0; i < COMBINERMAP_SIZE; i++) { 308 if (combinermap[i][0] == irq) { 309 return combinermap[i]; 310 } 311 } 312 return NULL; 313 } 314 315 static int mapline_size(const int *mapline) 316 { 317 /* Return number of entries in this mapline in total */ 318 int i = 0; 319 320 if (!mapline) { 321 /* Not in the map? IRQ goes to exactly one combiner input */ 322 return 1; 323 } 324 while (*mapline != IRQNONE) { 325 mapline++; 326 i++; 327 } 328 return i; 329 } 330 331 /* 332 * Initialize board IRQs. 333 * These IRQs contain split Int/External Combiner and External Gic IRQs. 334 */ 335 static void exynos4210_init_board_irqs(Exynos4210State *s) 336 { 337 uint32_t grp, bit, irq_id, n; 338 DeviceState *extgicdev = DEVICE(&s->ext_gic); 339 DeviceState *intcdev = DEVICE(&s->int_combiner); 340 DeviceState *extcdev = DEVICE(&s->ext_combiner); 341 int splitcount = 0; 342 DeviceState *splitter; 343 const int *mapline; 344 int numlines, splitin, in; 345 346 for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) { 347 irq_id = 0; 348 if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 4)) { 349 /* MCT_G0 is passed to External GIC */ 350 irq_id = EXT_GIC_ID_MCT_G0; 351 } 352 if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 5)) { 353 /* MCT_G1 is passed to External and GIC */ 354 irq_id = EXT_GIC_ID_MCT_G1; 355 } 356 357 if (s->irq_table[n]) { 358 /* 359 * This must be some non-first entry in a combinermap line, 360 * and we've already filled it in. 361 */ 362 continue; 363 } 364 mapline = combinermap_entry(n); 365 /* 366 * We need to connect the IRQ to multiple inputs on both combiners 367 * and possibly also to the external GIC. 368 */ 369 numlines = 2 * mapline_size(mapline); 370 if (irq_id) { 371 numlines++; 372 } 373 assert(splitcount < EXYNOS4210_NUM_SPLITTERS); 374 splitter = DEVICE(&s->splitter[splitcount]); 375 qdev_prop_set_uint16(splitter, "num-lines", numlines); 376 qdev_realize(splitter, NULL, &error_abort); 377 splitcount++; 378 379 in = n; 380 splitin = 0; 381 for (;;) { 382 s->irq_table[in] = qdev_get_gpio_in(splitter, 0); 383 qdev_connect_gpio_out(splitter, splitin, 384 qdev_get_gpio_in(intcdev, in)); 385 qdev_connect_gpio_out(splitter, splitin + 1, 386 qdev_get_gpio_in(extcdev, in)); 387 splitin += 2; 388 if (!mapline) { 389 break; 390 } 391 mapline++; 392 in = *mapline; 393 if (in == IRQNONE) { 394 break; 395 } 396 } 397 if (irq_id) { 398 qdev_connect_gpio_out(splitter, splitin, 399 qdev_get_gpio_in(extgicdev, 400 irq_id - GIC_INTERNAL)); 401 } 402 } 403 for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) { 404 /* these IDs are passed to Internal Combiner and External GIC */ 405 grp = EXYNOS4210_COMBINER_GET_GRP_NUM(n); 406 bit = EXYNOS4210_COMBINER_GET_BIT_NUM(n); 407 irq_id = combiner_grp_to_gic_id[grp - 408 EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][bit]; 409 410 if (s->irq_table[n]) { 411 /* 412 * This must be some non-first entry in a combinermap line, 413 * and we've already filled it in. 414 */ 415 continue; 416 } 417 418 if (irq_id) { 419 assert(splitcount < EXYNOS4210_NUM_SPLITTERS); 420 splitter = DEVICE(&s->splitter[splitcount]); 421 qdev_prop_set_uint16(splitter, "num-lines", 2); 422 qdev_realize(splitter, NULL, &error_abort); 423 splitcount++; 424 s->irq_table[n] = qdev_get_gpio_in(splitter, 0); 425 qdev_connect_gpio_out(splitter, 0, qdev_get_gpio_in(intcdev, n)); 426 qdev_connect_gpio_out(splitter, 1, 427 qdev_get_gpio_in(extgicdev, 428 irq_id - GIC_INTERNAL)); 429 } else { 430 s->irq_table[n] = qdev_get_gpio_in(intcdev, n); 431 } 432 } 433 /* 434 * We check this here to avoid a more obscure assert later when 435 * qdev_assert_realized_properly() checks that we realized every 436 * child object we initialized. 437 */ 438 assert(splitcount == EXYNOS4210_NUM_SPLITTERS); 439 } 440 441 /* 442 * Get IRQ number from exynos4210 IRQ subsystem stub. 443 * To identify IRQ source use internal combiner group and bit number 444 * grp - group number 445 * bit - bit number inside group 446 */ 447 uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit) 448 { 449 return EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit); 450 } 451 452 static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43, 453 0x09, 0x00, 0x00, 0x00 }; 454 455 static uint64_t exynos4210_chipid_and_omr_read(void *opaque, hwaddr offset, 456 unsigned size) 457 { 458 assert(offset < sizeof(chipid_and_omr)); 459 return chipid_and_omr[offset]; 460 } 461 462 static void exynos4210_chipid_and_omr_write(void *opaque, hwaddr offset, 463 uint64_t value, unsigned size) 464 { 465 return; 466 } 467 468 static const MemoryRegionOps exynos4210_chipid_and_omr_ops = { 469 .read = exynos4210_chipid_and_omr_read, 470 .write = exynos4210_chipid_and_omr_write, 471 .endianness = DEVICE_NATIVE_ENDIAN, 472 .impl = { 473 .max_access_size = 1, 474 } 475 }; 476 477 void exynos4210_write_secondary(ARMCPU *cpu, 478 const struct arm_boot_info *info) 479 { 480 int n; 481 uint32_t smpboot[] = { 482 0xe59f3034, /* ldr r3, External gic_cpu_if */ 483 0xe59f2034, /* ldr r2, Internal gic_cpu_if */ 484 0xe59f0034, /* ldr r0, startaddr */ 485 0xe3a01001, /* mov r1, #1 */ 486 0xe5821000, /* str r1, [r2] */ 487 0xe5831000, /* str r1, [r3] */ 488 0xe3a010ff, /* mov r1, #0xff */ 489 0xe5821004, /* str r1, [r2, #4] */ 490 0xe5831004, /* str r1, [r3, #4] */ 491 0xf57ff04f, /* dsb */ 492 0xe320f003, /* wfi */ 493 0xe5901000, /* ldr r1, [r0] */ 494 0xe1110001, /* tst r1, r1 */ 495 0x0afffffb, /* beq <wfi> */ 496 0xe12fff11, /* bx r1 */ 497 EXYNOS4210_EXT_GIC_CPU_BASE_ADDR, 498 0, /* gic_cpu_if: base address of Internal GIC CPU interface */ 499 0 /* bootreg: Boot register address is held here */ 500 }; 501 smpboot[ARRAY_SIZE(smpboot) - 1] = info->smp_bootreg_addr; 502 smpboot[ARRAY_SIZE(smpboot) - 2] = info->gic_cpu_if_addr; 503 for (n = 0; n < ARRAY_SIZE(smpboot); n++) { 504 smpboot[n] = tswap32(smpboot[n]); 505 } 506 rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot), 507 info->smp_loader_start); 508 } 509 510 static uint64_t exynos4210_calc_affinity(int cpu) 511 { 512 /* Exynos4210 has 0x9 as cluster ID */ 513 return (0x9 << ARM_AFF1_SHIFT) | cpu; 514 } 515 516 static DeviceState *pl330_create(uint32_t base, OrIRQState *orgate, 517 qemu_irq irq, int nreq, int nevents, int width) 518 { 519 SysBusDevice *busdev; 520 DeviceState *dev; 521 int i; 522 523 dev = qdev_new("pl330"); 524 object_property_set_link(OBJECT(dev), "memory", 525 OBJECT(get_system_memory()), 526 &error_fatal); 527 qdev_prop_set_uint8(dev, "num_events", nevents); 528 qdev_prop_set_uint8(dev, "num_chnls", 8); 529 qdev_prop_set_uint8(dev, "num_periph_req", nreq); 530 531 qdev_prop_set_uint8(dev, "wr_cap", 4); 532 qdev_prop_set_uint8(dev, "wr_q_dep", 8); 533 qdev_prop_set_uint8(dev, "rd_cap", 4); 534 qdev_prop_set_uint8(dev, "rd_q_dep", 8); 535 qdev_prop_set_uint8(dev, "data_width", width); 536 qdev_prop_set_uint16(dev, "data_buffer_dep", width); 537 busdev = SYS_BUS_DEVICE(dev); 538 sysbus_realize_and_unref(busdev, &error_fatal); 539 sysbus_mmio_map(busdev, 0, base); 540 541 object_property_set_int(OBJECT(orgate), "num-lines", nevents + 1, 542 &error_abort); 543 qdev_realize(DEVICE(orgate), NULL, &error_abort); 544 545 for (i = 0; i < nevents + 1; i++) { 546 sysbus_connect_irq(busdev, i, qdev_get_gpio_in(DEVICE(orgate), i)); 547 } 548 qdev_connect_gpio_out(DEVICE(orgate), 0, irq); 549 return dev; 550 } 551 552 static void exynos4210_realize(DeviceState *socdev, Error **errp) 553 { 554 Exynos4210State *s = EXYNOS4210_SOC(socdev); 555 MemoryRegion *system_mem = get_system_memory(); 556 SysBusDevice *busdev; 557 DeviceState *dev, *uart[4], *pl330[3]; 558 int i, n; 559 560 for (n = 0; n < EXYNOS4210_NCPUS; n++) { 561 Object *cpuobj = object_new(ARM_CPU_TYPE_NAME("cortex-a9")); 562 563 object_property_add_child(OBJECT(s), "cpu[*]", cpuobj); 564 /* By default A9 CPUs have EL3 enabled. This board does not currently 565 * support EL3 so the CPU EL3 property is disabled before realization. 566 */ 567 if (object_property_find(cpuobj, "has_el3")) { 568 object_property_set_bool(cpuobj, "has_el3", false, &error_fatal); 569 } 570 571 s->cpu[n] = ARM_CPU(cpuobj); 572 object_property_set_int(cpuobj, "mp-affinity", 573 exynos4210_calc_affinity(n), &error_abort); 574 object_property_set_int(cpuobj, "reset-cbar", 575 EXYNOS4210_SMP_PRIVATE_BASE_ADDR, 576 &error_abort); 577 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); 578 } 579 580 /* IRQ Gate */ 581 for (i = 0; i < EXYNOS4210_NCPUS; i++) { 582 DeviceState *orgate = DEVICE(&s->cpu_irq_orgate[i]); 583 object_property_set_int(OBJECT(orgate), "num-lines", 584 EXYNOS4210_IRQ_GATE_NINPUTS, 585 &error_abort); 586 qdev_realize(orgate, NULL, &error_abort); 587 qdev_connect_gpio_out(orgate, 0, 588 qdev_get_gpio_in(DEVICE(s->cpu[i]), ARM_CPU_IRQ)); 589 } 590 591 /* Private memory region and Internal GIC */ 592 qdev_prop_set_uint32(DEVICE(&s->a9mpcore), "num-cpu", EXYNOS4210_NCPUS); 593 qdev_prop_set_uint32(DEVICE(&s->a9mpcore), "num-irq", 594 GIC_EXT_IRQS + GIC_INTERNAL); 595 busdev = SYS_BUS_DEVICE(&s->a9mpcore); 596 sysbus_realize(busdev, &error_fatal); 597 sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR); 598 for (n = 0; n < EXYNOS4210_NCPUS; n++) { 599 sysbus_connect_irq(busdev, n, 600 qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 0)); 601 } 602 603 /* Cache controller */ 604 sysbus_create_simple("l2x0", EXYNOS4210_L2X0_BASE_ADDR, NULL); 605 606 /* External GIC */ 607 qdev_prop_set_uint32(DEVICE(&s->ext_gic), "num-cpu", EXYNOS4210_NCPUS); 608 busdev = SYS_BUS_DEVICE(&s->ext_gic); 609 sysbus_realize(busdev, &error_fatal); 610 /* Map CPU interface */ 611 sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_GIC_CPU_BASE_ADDR); 612 /* Map Distributer interface */ 613 sysbus_mmio_map(busdev, 1, EXYNOS4210_EXT_GIC_DIST_BASE_ADDR); 614 for (n = 0; n < EXYNOS4210_NCPUS; n++) { 615 sysbus_connect_irq(busdev, n, 616 qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 1)); 617 } 618 619 /* Internal Interrupt Combiner */ 620 busdev = SYS_BUS_DEVICE(&s->int_combiner); 621 sysbus_realize(busdev, &error_fatal); 622 for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) { 623 sysbus_connect_irq(busdev, n, 624 qdev_get_gpio_in(DEVICE(&s->a9mpcore), n)); 625 } 626 sysbus_mmio_map(busdev, 0, EXYNOS4210_INT_COMBINER_BASE_ADDR); 627 628 /* External Interrupt Combiner */ 629 qdev_prop_set_uint32(DEVICE(&s->ext_combiner), "external", 1); 630 busdev = SYS_BUS_DEVICE(&s->ext_combiner); 631 sysbus_realize(busdev, &error_fatal); 632 for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) { 633 sysbus_connect_irq(busdev, n, qdev_get_gpio_in(DEVICE(&s->ext_gic), n)); 634 } 635 sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR); 636 637 /* Initialize board IRQs. */ 638 exynos4210_init_board_irqs(s); 639 640 /*** Memory ***/ 641 642 /* Chip-ID and OMR */ 643 memory_region_init_io(&s->chipid_mem, OBJECT(socdev), 644 &exynos4210_chipid_and_omr_ops, NULL, 645 "exynos4210.chipid", sizeof(chipid_and_omr)); 646 memory_region_add_subregion(system_mem, EXYNOS4210_CHIPID_ADDR, 647 &s->chipid_mem); 648 649 /* Internal ROM */ 650 memory_region_init_rom(&s->irom_mem, OBJECT(socdev), "exynos4210.irom", 651 EXYNOS4210_IROM_SIZE, &error_fatal); 652 memory_region_add_subregion(system_mem, EXYNOS4210_IROM_BASE_ADDR, 653 &s->irom_mem); 654 /* mirror of iROM */ 655 memory_region_init_alias(&s->irom_alias_mem, OBJECT(socdev), 656 "exynos4210.irom_alias", &s->irom_mem, 0, 657 EXYNOS4210_IROM_SIZE); 658 memory_region_add_subregion(system_mem, EXYNOS4210_IROM_MIRROR_BASE_ADDR, 659 &s->irom_alias_mem); 660 661 /* Internal RAM */ 662 memory_region_init_ram(&s->iram_mem, NULL, "exynos4210.iram", 663 EXYNOS4210_IRAM_SIZE, &error_fatal); 664 memory_region_add_subregion(system_mem, EXYNOS4210_IRAM_BASE_ADDR, 665 &s->iram_mem); 666 667 /* PMU. 668 * The only reason of existence at the moment is that secondary CPU boot 669 * loader uses PMU INFORM5 register as a holding pen. 670 */ 671 sysbus_create_simple("exynos4210.pmu", EXYNOS4210_PMU_BASE_ADDR, NULL); 672 673 sysbus_create_simple("exynos4210.clk", EXYNOS4210_CLK_BASE_ADDR, NULL); 674 sysbus_create_simple("exynos4210.rng", EXYNOS4210_RNG_BASE_ADDR, NULL); 675 676 /* PWM */ 677 sysbus_create_varargs("exynos4210.pwm", EXYNOS4210_PWM_BASE_ADDR, 678 s->irq_table[exynos4210_get_irq(22, 0)], 679 s->irq_table[exynos4210_get_irq(22, 1)], 680 s->irq_table[exynos4210_get_irq(22, 2)], 681 s->irq_table[exynos4210_get_irq(22, 3)], 682 s->irq_table[exynos4210_get_irq(22, 4)], 683 NULL); 684 /* RTC */ 685 sysbus_create_varargs("exynos4210.rtc", EXYNOS4210_RTC_BASE_ADDR, 686 s->irq_table[exynos4210_get_irq(23, 0)], 687 s->irq_table[exynos4210_get_irq(23, 1)], 688 NULL); 689 690 /* Multi Core Timer */ 691 dev = qdev_new("exynos4210.mct"); 692 busdev = SYS_BUS_DEVICE(dev); 693 sysbus_realize_and_unref(busdev, &error_fatal); 694 for (n = 0; n < 4; n++) { 695 /* Connect global timer interrupts to Combiner gpio_in */ 696 sysbus_connect_irq(busdev, n, 697 s->irq_table[exynos4210_get_irq(1, 4 + n)]); 698 } 699 /* Connect local timer interrupts to Combiner gpio_in */ 700 sysbus_connect_irq(busdev, 4, 701 s->irq_table[exynos4210_get_irq(51, 0)]); 702 sysbus_connect_irq(busdev, 5, 703 s->irq_table[exynos4210_get_irq(35, 3)]); 704 sysbus_mmio_map(busdev, 0, EXYNOS4210_MCT_BASE_ADDR); 705 706 /*** I2C ***/ 707 for (n = 0; n < EXYNOS4210_I2C_NUMBER; n++) { 708 uint32_t addr = EXYNOS4210_I2C_BASE_ADDR + EXYNOS4210_I2C_SHIFT * n; 709 qemu_irq i2c_irq; 710 711 if (n < 8) { 712 i2c_irq = s->irq_table[exynos4210_get_irq(EXYNOS4210_I2C_INTG, n)]; 713 } else { 714 i2c_irq = s->irq_table[exynos4210_get_irq(EXYNOS4210_HDMI_INTG, 1)]; 715 } 716 717 dev = qdev_new("exynos4210.i2c"); 718 busdev = SYS_BUS_DEVICE(dev); 719 sysbus_realize_and_unref(busdev, &error_fatal); 720 sysbus_connect_irq(busdev, 0, i2c_irq); 721 sysbus_mmio_map(busdev, 0, addr); 722 s->i2c_if[n] = (I2CBus *)qdev_get_child_bus(dev, "i2c"); 723 } 724 725 726 /*** UARTs ***/ 727 uart[0] = exynos4210_uart_create(EXYNOS4210_UART0_BASE_ADDR, 728 EXYNOS4210_UART0_FIFO_SIZE, 0, serial_hd(0), 729 s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 0)]); 730 731 uart[1] = exynos4210_uart_create(EXYNOS4210_UART1_BASE_ADDR, 732 EXYNOS4210_UART1_FIFO_SIZE, 1, serial_hd(1), 733 s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 1)]); 734 735 uart[2] = exynos4210_uart_create(EXYNOS4210_UART2_BASE_ADDR, 736 EXYNOS4210_UART2_FIFO_SIZE, 2, serial_hd(2), 737 s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 2)]); 738 739 uart[3] = exynos4210_uart_create(EXYNOS4210_UART3_BASE_ADDR, 740 EXYNOS4210_UART3_FIFO_SIZE, 3, serial_hd(3), 741 s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 3)]); 742 743 /*** SD/MMC host controllers ***/ 744 for (n = 0; n < EXYNOS4210_SDHCI_NUMBER; n++) { 745 DeviceState *carddev; 746 BlockBackend *blk; 747 DriveInfo *di; 748 749 /* Compatible with: 750 * - SD Host Controller Specification Version 2.0 751 * - SDIO Specification Version 2.0 752 * - MMC Specification Version 4.3 753 * - SDMA 754 * - ADMA2 755 * 756 * As this part of the Exynos4210 is not publicly available, 757 * we used the "HS-MMC Controller S3C2416X RISC Microprocessor" 758 * public datasheet which is very similar (implementing 759 * MMC Specification Version 4.0 being the only difference noted) 760 */ 761 dev = qdev_new(TYPE_S3C_SDHCI); 762 qdev_prop_set_uint64(dev, "capareg", EXYNOS4210_SDHCI_CAPABILITIES); 763 764 busdev = SYS_BUS_DEVICE(dev); 765 sysbus_realize_and_unref(busdev, &error_fatal); 766 sysbus_mmio_map(busdev, 0, EXYNOS4210_SDHCI_ADDR(n)); 767 sysbus_connect_irq(busdev, 0, s->irq_table[exynos4210_get_irq(29, n)]); 768 769 di = drive_get(IF_SD, 0, n); 770 blk = di ? blk_by_legacy_dinfo(di) : NULL; 771 carddev = qdev_new(TYPE_SD_CARD); 772 qdev_prop_set_drive(carddev, "drive", blk); 773 qdev_realize_and_unref(carddev, qdev_get_child_bus(dev, "sd-bus"), 774 &error_fatal); 775 } 776 777 /*** Display controller (FIMD) ***/ 778 dev = qdev_new("exynos4210.fimd"); 779 object_property_set_link(OBJECT(dev), "framebuffer-memory", 780 OBJECT(system_mem), &error_fatal); 781 busdev = SYS_BUS_DEVICE(dev); 782 sysbus_realize_and_unref(busdev, &error_fatal); 783 sysbus_mmio_map(busdev, 0, EXYNOS4210_FIMD0_BASE_ADDR); 784 for (n = 0; n < 3; n++) { 785 sysbus_connect_irq(busdev, n, s->irq_table[exynos4210_get_irq(11, n)]); 786 } 787 788 sysbus_create_simple(TYPE_EXYNOS4210_EHCI, EXYNOS4210_EHCI_BASE_ADDR, 789 s->irq_table[exynos4210_get_irq(28, 3)]); 790 791 /*** DMA controllers ***/ 792 pl330[0] = pl330_create(EXYNOS4210_PL330_BASE0_ADDR, 793 &s->pl330_irq_orgate[0], 794 s->irq_table[exynos4210_get_irq(21, 0)], 795 32, 32, 32); 796 pl330[1] = pl330_create(EXYNOS4210_PL330_BASE1_ADDR, 797 &s->pl330_irq_orgate[1], 798 s->irq_table[exynos4210_get_irq(21, 1)], 799 32, 32, 32); 800 pl330[2] = pl330_create(EXYNOS4210_PL330_BASE2_ADDR, 801 &s->pl330_irq_orgate[2], 802 s->irq_table[exynos4210_get_irq(20, 1)], 803 1, 31, 64); 804 805 sysbus_connect_irq(SYS_BUS_DEVICE(uart[0]), 1, 806 qdev_get_gpio_in(pl330[0], 15)); 807 sysbus_connect_irq(SYS_BUS_DEVICE(uart[1]), 1, 808 qdev_get_gpio_in(pl330[1], 15)); 809 sysbus_connect_irq(SYS_BUS_DEVICE(uart[2]), 1, 810 qdev_get_gpio_in(pl330[0], 17)); 811 sysbus_connect_irq(SYS_BUS_DEVICE(uart[3]), 1, 812 qdev_get_gpio_in(pl330[1], 17)); 813 } 814 815 static void exynos4210_init(Object *obj) 816 { 817 Exynos4210State *s = EXYNOS4210_SOC(obj); 818 int i; 819 820 for (i = 0; i < ARRAY_SIZE(s->pl330_irq_orgate); i++) { 821 char *name = g_strdup_printf("pl330-irq-orgate%d", i); 822 OrIRQState *orgate = &s->pl330_irq_orgate[i]; 823 824 object_initialize_child(obj, name, orgate, TYPE_OR_IRQ); 825 g_free(name); 826 } 827 828 for (i = 0; i < ARRAY_SIZE(s->cpu_irq_orgate); i++) { 829 g_autofree char *name = g_strdup_printf("cpu-irq-orgate%d", i); 830 object_initialize_child(obj, name, &s->cpu_irq_orgate[i], TYPE_OR_IRQ); 831 } 832 833 for (i = 0; i < ARRAY_SIZE(s->splitter); i++) { 834 g_autofree char *name = g_strdup_printf("irq-splitter%d", i); 835 object_initialize_child(obj, name, &s->splitter[i], TYPE_SPLIT_IRQ); 836 } 837 838 object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV); 839 object_initialize_child(obj, "ext-gic", &s->ext_gic, TYPE_EXYNOS4210_GIC); 840 object_initialize_child(obj, "int-combiner", &s->int_combiner, 841 TYPE_EXYNOS4210_COMBINER); 842 object_initialize_child(obj, "ext-combiner", &s->ext_combiner, 843 TYPE_EXYNOS4210_COMBINER); 844 } 845 846 static void exynos4210_class_init(ObjectClass *klass, void *data) 847 { 848 DeviceClass *dc = DEVICE_CLASS(klass); 849 850 dc->realize = exynos4210_realize; 851 } 852 853 static const TypeInfo exynos4210_info = { 854 .name = TYPE_EXYNOS4210_SOC, 855 .parent = TYPE_SYS_BUS_DEVICE, 856 .instance_size = sizeof(Exynos4210State), 857 .instance_init = exynos4210_init, 858 .class_init = exynos4210_class_init, 859 }; 860 861 static void exynos4210_register_types(void) 862 { 863 type_register_static(&exynos4210_info); 864 } 865 866 type_init(exynos4210_register_types) 867