1 /* 2 * ARM kernel loader. 3 * 4 * Copyright (c) 2006-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/datadir.h" 12 #include "qemu/error-report.h" 13 #include "qapi/error.h" 14 #include <libfdt.h> 15 #include "hw/arm/boot.h" 16 #include "hw/arm/linux-boot-if.h" 17 #include "system/kvm.h" 18 #include "system/tcg.h" 19 #include "system/system.h" 20 #include "system/numa.h" 21 #include "hw/boards.h" 22 #include "system/reset.h" 23 #include "hw/loader.h" 24 #include "elf.h" 25 #include "system/device_tree.h" 26 #include "qemu/config-file.h" 27 #include "qemu/option.h" 28 #include "qemu/units.h" 29 30 /* Kernel boot protocol is specified in the kernel docs 31 * Documentation/arm/Booting and Documentation/arm64/booting.txt 32 * They have different preferred image load offsets from system RAM base. 33 */ 34 #define KERNEL_ARGS_ADDR 0x100 35 #define KERNEL_NOLOAD_ADDR 0x02000000 36 #define KERNEL_LOAD_ADDR 0x00010000 37 #define KERNEL64_LOAD_ADDR 0x00080000 38 39 #define ARM64_TEXT_OFFSET_OFFSET 8 40 #define ARM64_MAGIC_OFFSET 56 41 42 #define BOOTLOADER_MAX_SIZE (4 * KiB) 43 44 AddressSpace *arm_boot_address_space(ARMCPU *cpu, 45 const struct arm_boot_info *info) 46 { 47 /* Return the address space to use for bootloader reads and writes. 48 * We prefer the secure address space if the CPU has it and we're 49 * going to boot the guest into it. 50 */ 51 int asidx; 52 CPUState *cs = CPU(cpu); 53 54 if (arm_feature(&cpu->env, ARM_FEATURE_EL3) && info->secure_boot) { 55 asidx = ARMASIdx_S; 56 } else { 57 asidx = ARMASIdx_NS; 58 } 59 60 return cpu_get_address_space(cs, asidx); 61 } 62 63 static const ARMInsnFixup bootloader_aarch64[] = { 64 { 0x580000c0 }, /* ldr x0, arg ; Load the lower 32-bits of DTB */ 65 { 0xaa1f03e1 }, /* mov x1, xzr */ 66 { 0xaa1f03e2 }, /* mov x2, xzr */ 67 { 0xaa1f03e3 }, /* mov x3, xzr */ 68 { 0x58000084 }, /* ldr x4, entry ; Load the lower 32-bits of kernel entry */ 69 { 0xd61f0080 }, /* br x4 ; Jump to the kernel entry point */ 70 { 0, FIXUP_ARGPTR_LO }, /* arg: .word @DTB Lower 32-bits */ 71 { 0, FIXUP_ARGPTR_HI}, /* .word @DTB Higher 32-bits */ 72 { 0, FIXUP_ENTRYPOINT_LO }, /* entry: .word @Kernel Entry Lower 32-bits */ 73 { 0, FIXUP_ENTRYPOINT_HI }, /* .word @Kernel Entry Higher 32-bits */ 74 { 0, FIXUP_TERMINATOR } 75 }; 76 77 /* A very small bootloader: call the board-setup code (if needed), 78 * set r0-r2, then jump to the kernel. 79 * If we're not calling boot setup code then we don't copy across 80 * the first BOOTLOADER_NO_BOARD_SETUP_OFFSET insns in this array. 81 */ 82 83 static const ARMInsnFixup bootloader[] = { 84 { 0xe28fe004 }, /* add lr, pc, #4 */ 85 { 0xe51ff004 }, /* ldr pc, [pc, #-4] */ 86 { 0, FIXUP_BOARD_SETUP }, 87 #define BOOTLOADER_NO_BOARD_SETUP_OFFSET 3 88 { 0xe3a00000 }, /* mov r0, #0 */ 89 { 0xe59f1004 }, /* ldr r1, [pc, #4] */ 90 { 0xe59f2004 }, /* ldr r2, [pc, #4] */ 91 { 0xe59ff004 }, /* ldr pc, [pc, #4] */ 92 { 0, FIXUP_BOARDID }, 93 { 0, FIXUP_ARGPTR_LO }, 94 { 0, FIXUP_ENTRYPOINT_LO }, 95 { 0, FIXUP_TERMINATOR } 96 }; 97 98 /* Handling for secondary CPU boot in a multicore system. 99 * Unlike the uniprocessor/primary CPU boot, this is platform 100 * dependent. The default code here is based on the secondary 101 * CPU boot protocol used on realview/vexpress boards, with 102 * some parameterisation to increase its flexibility. 103 * QEMU platform models for which this code is not appropriate 104 * should override write_secondary_boot and secondary_cpu_reset_hook 105 * instead. 106 * 107 * This code enables the interrupt controllers for the secondary 108 * CPUs and then puts all the secondary CPUs into a loop waiting 109 * for an interprocessor interrupt and polling a configurable 110 * location for the kernel secondary CPU entry point. 111 */ 112 #define DSB_INSN 0xf57ff04f 113 #define CP15_DSB_INSN 0xee070f9a /* mcr cp15, 0, r0, c7, c10, 4 */ 114 115 static const ARMInsnFixup smpboot[] = { 116 { 0xe59f2028 }, /* ldr r2, gic_cpu_if */ 117 { 0xe59f0028 }, /* ldr r0, bootreg_addr */ 118 { 0xe3a01001 }, /* mov r1, #1 */ 119 { 0xe5821000 }, /* str r1, [r2] - set GICC_CTLR.Enable */ 120 { 0xe3a010ff }, /* mov r1, #0xff */ 121 { 0xe5821004 }, /* str r1, [r2, 4] - set GIC_PMR.Priority to 0xff */ 122 { 0, FIXUP_DSB }, /* dsb */ 123 { 0xe320f003 }, /* wfi */ 124 { 0xe5901000 }, /* ldr r1, [r0] */ 125 { 0xe1110001 }, /* tst r1, r1 */ 126 { 0x0afffffb }, /* beq <wfi> */ 127 { 0xe12fff11 }, /* bx r1 */ 128 { 0, FIXUP_GIC_CPU_IF }, /* gic_cpu_if: .word 0x.... */ 129 { 0, FIXUP_BOOTREG }, /* bootreg_addr: .word 0x.... */ 130 { 0, FIXUP_TERMINATOR } 131 }; 132 133 void arm_write_bootloader(const char *name, 134 AddressSpace *as, hwaddr addr, 135 const ARMInsnFixup *insns, 136 const uint32_t *fixupcontext) 137 { 138 /* Fix up the specified bootloader fragment and write it into 139 * guest memory using rom_add_blob_fixed(). fixupcontext is 140 * an array giving the values to write in for the fixup types 141 * which write a value into the code array. 142 */ 143 int i, len; 144 uint32_t *code; 145 146 len = 0; 147 while (insns[len].fixup != FIXUP_TERMINATOR) { 148 len++; 149 } 150 151 code = g_new0(uint32_t, len); 152 153 for (i = 0; i < len; i++) { 154 uint32_t insn = insns[i].insn; 155 FixupType fixup = insns[i].fixup; 156 157 switch (fixup) { 158 case FIXUP_NONE: 159 break; 160 case FIXUP_BOARDID: 161 case FIXUP_BOARD_SETUP: 162 case FIXUP_ARGPTR_LO: 163 case FIXUP_ARGPTR_HI: 164 case FIXUP_ENTRYPOINT_LO: 165 case FIXUP_ENTRYPOINT_HI: 166 case FIXUP_GIC_CPU_IF: 167 case FIXUP_BOOTREG: 168 case FIXUP_DSB: 169 insn = fixupcontext[fixup]; 170 break; 171 default: 172 abort(); 173 } 174 code[i] = tswap32(insn); 175 } 176 177 assert((len * sizeof(uint32_t)) < BOOTLOADER_MAX_SIZE); 178 179 rom_add_blob_fixed_as(name, code, len * sizeof(uint32_t), addr, as); 180 181 g_free(code); 182 } 183 184 static void default_write_secondary(ARMCPU *cpu, 185 const struct arm_boot_info *info) 186 { 187 uint32_t fixupcontext[FIXUP_MAX]; 188 AddressSpace *as = arm_boot_address_space(cpu, info); 189 190 fixupcontext[FIXUP_GIC_CPU_IF] = info->gic_cpu_if_addr; 191 fixupcontext[FIXUP_BOOTREG] = info->smp_bootreg_addr; 192 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 193 fixupcontext[FIXUP_DSB] = DSB_INSN; 194 } else { 195 fixupcontext[FIXUP_DSB] = CP15_DSB_INSN; 196 } 197 198 arm_write_bootloader("smpboot", as, info->smp_loader_start, 199 smpboot, fixupcontext); 200 } 201 202 void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu, 203 const struct arm_boot_info *info, 204 hwaddr mvbar_addr) 205 { 206 AddressSpace *as = arm_boot_address_space(cpu, info); 207 int n; 208 uint32_t mvbar_blob[] = { 209 /* mvbar_addr: secure monitor vectors 210 * Default unimplemented and unused vectors to spin. Makes it 211 * easier to debug (as opposed to the CPU running away). 212 */ 213 0xeafffffe, /* (spin) */ 214 0xeafffffe, /* (spin) */ 215 0xe1b0f00e, /* movs pc, lr ;SMC exception return */ 216 0xeafffffe, /* (spin) */ 217 0xeafffffe, /* (spin) */ 218 0xeafffffe, /* (spin) */ 219 0xeafffffe, /* (spin) */ 220 0xeafffffe, /* (spin) */ 221 }; 222 uint32_t board_setup_blob[] = { 223 /* board setup addr */ 224 0xee110f51, /* mrc p15, 0, r0, c1, c1, 2 ;read NSACR */ 225 0xe3800b03, /* orr r0, #0xc00 ;set CP11, CP10 */ 226 0xee010f51, /* mcr p15, 0, r0, c1, c1, 2 ;write NSACR */ 227 0xe3a00e00 + (mvbar_addr >> 4), /* mov r0, #mvbar_addr */ 228 0xee0c0f30, /* mcr p15, 0, r0, c12, c0, 1 ;set MVBAR */ 229 0xee110f11, /* mrc p15, 0, r0, c1 , c1, 0 ;read SCR */ 230 0xe3800031, /* orr r0, #0x31 ;enable AW, FW, NS */ 231 0xee010f11, /* mcr p15, 0, r0, c1, c1, 0 ;write SCR */ 232 0xe1a0100e, /* mov r1, lr ;save LR across SMC */ 233 0xe1600070, /* smc #0 ;call monitor to flush SCR */ 234 0xe1a0f001, /* mov pc, r1 ;return */ 235 }; 236 237 /* check that mvbar_addr is correctly aligned and relocatable (using MOV) */ 238 assert((mvbar_addr & 0x1f) == 0 && (mvbar_addr >> 4) < 0x100); 239 240 /* check that these blobs don't overlap */ 241 assert((mvbar_addr + sizeof(mvbar_blob) <= info->board_setup_addr) 242 || (info->board_setup_addr + sizeof(board_setup_blob) <= mvbar_addr)); 243 244 for (n = 0; n < ARRAY_SIZE(mvbar_blob); n++) { 245 mvbar_blob[n] = tswap32(mvbar_blob[n]); 246 } 247 rom_add_blob_fixed_as("board-setup-mvbar", mvbar_blob, sizeof(mvbar_blob), 248 mvbar_addr, as); 249 250 for (n = 0; n < ARRAY_SIZE(board_setup_blob); n++) { 251 board_setup_blob[n] = tswap32(board_setup_blob[n]); 252 } 253 rom_add_blob_fixed_as("board-setup", board_setup_blob, 254 sizeof(board_setup_blob), info->board_setup_addr, as); 255 } 256 257 static void default_reset_secondary(ARMCPU *cpu, 258 const struct arm_boot_info *info) 259 { 260 AddressSpace *as = arm_boot_address_space(cpu, info); 261 CPUState *cs = CPU(cpu); 262 263 address_space_stl_notdirty(as, info->smp_bootreg_addr, 264 0, MEMTXATTRS_UNSPECIFIED, NULL); 265 cpu_set_pc(cs, info->smp_loader_start); 266 } 267 268 static inline bool have_dtb(const struct arm_boot_info *info) 269 { 270 return info->dtb_filename || info->get_dtb; 271 } 272 273 #define WRITE_WORD(p, value) do { \ 274 address_space_stl_notdirty(as, p, value, \ 275 MEMTXATTRS_UNSPECIFIED, NULL); \ 276 p += 4; \ 277 } while (0) 278 279 static void set_kernel_args(const struct arm_boot_info *info, AddressSpace *as) 280 { 281 int initrd_size = info->initrd_size; 282 hwaddr base = info->loader_start; 283 hwaddr p; 284 285 p = base + KERNEL_ARGS_ADDR; 286 /* ATAG_CORE */ 287 WRITE_WORD(p, 5); 288 WRITE_WORD(p, 0x54410001); 289 WRITE_WORD(p, 1); 290 WRITE_WORD(p, 0x1000); 291 WRITE_WORD(p, 0); 292 /* ATAG_MEM */ 293 /* TODO: handle multiple chips on one ATAG list */ 294 WRITE_WORD(p, 4); 295 WRITE_WORD(p, 0x54410002); 296 WRITE_WORD(p, info->ram_size); 297 WRITE_WORD(p, info->loader_start); 298 if (initrd_size) { 299 /* ATAG_INITRD2 */ 300 WRITE_WORD(p, 4); 301 WRITE_WORD(p, 0x54420005); 302 WRITE_WORD(p, info->initrd_start); 303 WRITE_WORD(p, initrd_size); 304 } 305 if (info->kernel_cmdline && *info->kernel_cmdline) { 306 /* ATAG_CMDLINE */ 307 int cmdline_size; 308 309 cmdline_size = strlen(info->kernel_cmdline); 310 address_space_write(as, p + 8, MEMTXATTRS_UNSPECIFIED, 311 info->kernel_cmdline, cmdline_size + 1); 312 cmdline_size = (cmdline_size >> 2) + 1; 313 WRITE_WORD(p, cmdline_size + 2); 314 WRITE_WORD(p, 0x54410009); 315 p += cmdline_size * 4; 316 } 317 if (info->atag_board) { 318 /* ATAG_BOARD */ 319 int atag_board_len; 320 uint8_t atag_board_buf[0x1000]; 321 322 atag_board_len = (info->atag_board(info, atag_board_buf) + 3) & ~3; 323 WRITE_WORD(p, (atag_board_len + 8) >> 2); 324 WRITE_WORD(p, 0x414f4d50); 325 address_space_write(as, p, MEMTXATTRS_UNSPECIFIED, 326 atag_board_buf, atag_board_len); 327 p += atag_board_len; 328 } 329 /* ATAG_END */ 330 WRITE_WORD(p, 0); 331 WRITE_WORD(p, 0); 332 } 333 334 static void set_kernel_args_old(const struct arm_boot_info *info, 335 AddressSpace *as) 336 { 337 hwaddr p; 338 const char *s; 339 int initrd_size = info->initrd_size; 340 hwaddr base = info->loader_start; 341 342 /* see linux/include/asm-arm/setup.h */ 343 p = base + KERNEL_ARGS_ADDR; 344 /* page_size */ 345 WRITE_WORD(p, 4096); 346 /* nr_pages */ 347 WRITE_WORD(p, info->ram_size / 4096); 348 /* ramdisk_size */ 349 WRITE_WORD(p, 0); 350 #define FLAG_READONLY 1 351 #define FLAG_RDLOAD 4 352 #define FLAG_RDPROMPT 8 353 /* flags */ 354 WRITE_WORD(p, FLAG_READONLY | FLAG_RDLOAD | FLAG_RDPROMPT); 355 /* rootdev */ 356 WRITE_WORD(p, (31 << 8) | 0); /* /dev/mtdblock0 */ 357 /* video_num_cols */ 358 WRITE_WORD(p, 0); 359 /* video_num_rows */ 360 WRITE_WORD(p, 0); 361 /* video_x */ 362 WRITE_WORD(p, 0); 363 /* video_y */ 364 WRITE_WORD(p, 0); 365 /* memc_control_reg */ 366 WRITE_WORD(p, 0); 367 /* unsigned char sounddefault */ 368 /* unsigned char adfsdrives */ 369 /* unsigned char bytes_per_char_h */ 370 /* unsigned char bytes_per_char_v */ 371 WRITE_WORD(p, 0); 372 /* pages_in_bank[4] */ 373 WRITE_WORD(p, 0); 374 WRITE_WORD(p, 0); 375 WRITE_WORD(p, 0); 376 WRITE_WORD(p, 0); 377 /* pages_in_vram */ 378 WRITE_WORD(p, 0); 379 /* initrd_start */ 380 if (initrd_size) { 381 WRITE_WORD(p, info->initrd_start); 382 } else { 383 WRITE_WORD(p, 0); 384 } 385 /* initrd_size */ 386 WRITE_WORD(p, initrd_size); 387 /* rd_start */ 388 WRITE_WORD(p, 0); 389 /* system_rev */ 390 WRITE_WORD(p, 0); 391 /* system_serial_low */ 392 WRITE_WORD(p, 0); 393 /* system_serial_high */ 394 WRITE_WORD(p, 0); 395 /* mem_fclk_21285 */ 396 WRITE_WORD(p, 0); 397 /* zero unused fields */ 398 while (p < base + KERNEL_ARGS_ADDR + 256 + 1024) { 399 WRITE_WORD(p, 0); 400 } 401 s = info->kernel_cmdline; 402 if (s) { 403 address_space_write(as, p, MEMTXATTRS_UNSPECIFIED, s, strlen(s) + 1); 404 } else { 405 WRITE_WORD(p, 0); 406 } 407 } 408 409 static int fdt_add_memory_node(void *fdt, uint32_t acells, hwaddr mem_base, 410 uint32_t scells, hwaddr mem_len, 411 int numa_node_id) 412 { 413 char *nodename; 414 int ret; 415 416 nodename = g_strdup_printf("/memory@%" PRIx64, mem_base); 417 qemu_fdt_add_subnode(fdt, nodename); 418 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); 419 ret = qemu_fdt_setprop_sized_cells(fdt, nodename, "reg", acells, mem_base, 420 scells, mem_len); 421 if (ret < 0) { 422 goto out; 423 } 424 425 /* only set the NUMA ID if it is specified */ 426 if (numa_node_id >= 0) { 427 ret = qemu_fdt_setprop_cell(fdt, nodename, 428 "numa-node-id", numa_node_id); 429 } 430 out: 431 g_free(nodename); 432 return ret; 433 } 434 435 static void fdt_add_psci_node(void *fdt, ARMCPU *armcpu) 436 { 437 uint32_t cpu_suspend_fn; 438 uint32_t cpu_off_fn; 439 uint32_t cpu_on_fn; 440 uint32_t migrate_fn; 441 const char *psci_method; 442 int64_t psci_conduit; 443 int rc; 444 445 psci_conduit = object_property_get_int(OBJECT(armcpu), 446 "psci-conduit", 447 &error_abort); 448 switch (psci_conduit) { 449 case QEMU_PSCI_CONDUIT_DISABLED: 450 return; 451 case QEMU_PSCI_CONDUIT_HVC: 452 psci_method = "hvc"; 453 break; 454 case QEMU_PSCI_CONDUIT_SMC: 455 psci_method = "smc"; 456 break; 457 default: 458 g_assert_not_reached(); 459 } 460 461 /* 462 * A pre-existing /psci node might specify function ID values 463 * that don't match QEMU's PSCI implementation. Delete the whole 464 * node and put our own in instead. 465 */ 466 rc = fdt_path_offset(fdt, "/psci"); 467 if (rc >= 0) { 468 qemu_fdt_nop_node(fdt, "/psci"); 469 } 470 471 qemu_fdt_add_subnode(fdt, "/psci"); 472 if (armcpu->psci_version >= QEMU_PSCI_VERSION_0_2) { 473 if (armcpu->psci_version < QEMU_PSCI_VERSION_1_0) { 474 const char comp[] = "arm,psci-0.2\0arm,psci"; 475 qemu_fdt_setprop(fdt, "/psci", "compatible", comp, sizeof(comp)); 476 } else { 477 const char comp[] = "arm,psci-1.0\0arm,psci-0.2\0arm,psci"; 478 qemu_fdt_setprop(fdt, "/psci", "compatible", comp, sizeof(comp)); 479 } 480 481 cpu_off_fn = QEMU_PSCI_0_2_FN_CPU_OFF; 482 if (arm_feature(&armcpu->env, ARM_FEATURE_AARCH64)) { 483 cpu_suspend_fn = QEMU_PSCI_0_2_FN64_CPU_SUSPEND; 484 cpu_on_fn = QEMU_PSCI_0_2_FN64_CPU_ON; 485 migrate_fn = QEMU_PSCI_0_2_FN64_MIGRATE; 486 } else { 487 cpu_suspend_fn = QEMU_PSCI_0_2_FN_CPU_SUSPEND; 488 cpu_on_fn = QEMU_PSCI_0_2_FN_CPU_ON; 489 migrate_fn = QEMU_PSCI_0_2_FN_MIGRATE; 490 } 491 } else { 492 qemu_fdt_setprop_string(fdt, "/psci", "compatible", "arm,psci"); 493 494 cpu_suspend_fn = QEMU_PSCI_0_1_FN_CPU_SUSPEND; 495 cpu_off_fn = QEMU_PSCI_0_1_FN_CPU_OFF; 496 cpu_on_fn = QEMU_PSCI_0_1_FN_CPU_ON; 497 migrate_fn = QEMU_PSCI_0_1_FN_MIGRATE; 498 } 499 500 /* We adopt the PSCI spec's nomenclature, and use 'conduit' to refer 501 * to the instruction that should be used to invoke PSCI functions. 502 * However, the device tree binding uses 'method' instead, so that is 503 * what we should use here. 504 */ 505 qemu_fdt_setprop_string(fdt, "/psci", "method", psci_method); 506 507 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_suspend", cpu_suspend_fn); 508 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_off", cpu_off_fn); 509 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_on", cpu_on_fn); 510 qemu_fdt_setprop_cell(fdt, "/psci", "migrate", migrate_fn); 511 } 512 513 int arm_load_dtb(hwaddr addr, const struct arm_boot_info *binfo, 514 hwaddr addr_limit, AddressSpace *as, MachineState *ms, 515 ARMCPU *cpu) 516 { 517 void *fdt = NULL; 518 int size, rc, n = 0; 519 uint32_t acells, scells; 520 unsigned int i; 521 hwaddr mem_base, mem_len; 522 char **node_path; 523 Error *err = NULL; 524 525 if (binfo->dtb_filename) { 526 char *filename; 527 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, binfo->dtb_filename); 528 if (!filename) { 529 fprintf(stderr, "Couldn't open dtb file %s\n", binfo->dtb_filename); 530 goto fail; 531 } 532 533 fdt = load_device_tree(filename, &size); 534 if (!fdt) { 535 fprintf(stderr, "Couldn't open dtb file %s\n", filename); 536 g_free(filename); 537 goto fail; 538 } 539 g_free(filename); 540 } else { 541 fdt = binfo->get_dtb(binfo, &size); 542 if (!fdt) { 543 fprintf(stderr, "Board was unable to create a dtb blob\n"); 544 goto fail; 545 } 546 } 547 548 if (addr_limit > addr && size > (addr_limit - addr)) { 549 /* Installing the device tree blob at addr would exceed addr_limit. 550 * Whether this constitutes failure is up to the caller to decide, 551 * so just return 0 as size, i.e., no error. 552 */ 553 g_free(fdt); 554 return 0; 555 } 556 557 acells = qemu_fdt_getprop_cell(fdt, "/", "#address-cells", 558 NULL, &error_fatal); 559 scells = qemu_fdt_getprop_cell(fdt, "/", "#size-cells", 560 NULL, &error_fatal); 561 if (acells == 0 || scells == 0) { 562 fprintf(stderr, "dtb file invalid (#address-cells or #size-cells 0)\n"); 563 goto fail; 564 } 565 566 if (scells < 2 && binfo->ram_size >= 4 * GiB) { 567 /* This is user error so deserves a friendlier error message 568 * than the failure of setprop_sized_cells would provide 569 */ 570 fprintf(stderr, "qemu: dtb file not compatible with " 571 "RAM size > 4GB\n"); 572 goto fail; 573 } 574 575 /* nop all root nodes matching /memory or /memory@unit-address */ 576 node_path = qemu_fdt_node_unit_path(fdt, "memory", &err); 577 if (err) { 578 error_report_err(err); 579 goto fail; 580 } 581 while (node_path[n]) { 582 if (g_str_has_prefix(node_path[n], "/memory")) { 583 qemu_fdt_nop_node(fdt, node_path[n]); 584 } 585 n++; 586 } 587 g_strfreev(node_path); 588 589 /* 590 * We drop all the memory nodes which correspond to empty NUMA nodes 591 * from the device tree, because the Linux NUMA binding document 592 * states they should not be generated. Linux will get the NUMA node 593 * IDs of the empty NUMA nodes from the distance map if they are needed. 594 * This means QEMU users may be obliged to provide command lines which 595 * configure distance maps when the empty NUMA node IDs are needed and 596 * Linux's default distance map isn't sufficient. 597 */ 598 if (ms->numa_state != NULL && ms->numa_state->num_nodes > 0) { 599 mem_base = binfo->loader_start; 600 for (i = 0; i < ms->numa_state->num_nodes; i++) { 601 mem_len = ms->numa_state->nodes[i].node_mem; 602 if (!mem_len) { 603 continue; 604 } 605 606 rc = fdt_add_memory_node(fdt, acells, mem_base, 607 scells, mem_len, i); 608 if (rc < 0) { 609 fprintf(stderr, "couldn't add /memory@%"PRIx64" node\n", 610 mem_base); 611 goto fail; 612 } 613 614 mem_base += mem_len; 615 } 616 } else { 617 rc = fdt_add_memory_node(fdt, acells, binfo->loader_start, 618 scells, binfo->ram_size, -1); 619 if (rc < 0) { 620 fprintf(stderr, "couldn't add /memory@%"PRIx64" node\n", 621 binfo->loader_start); 622 goto fail; 623 } 624 } 625 626 rc = fdt_path_offset(fdt, "/chosen"); 627 if (rc < 0) { 628 qemu_fdt_add_subnode(fdt, "/chosen"); 629 } 630 631 if (ms->kernel_cmdline && *ms->kernel_cmdline) { 632 rc = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", 633 ms->kernel_cmdline); 634 if (rc < 0) { 635 fprintf(stderr, "couldn't set /chosen/bootargs\n"); 636 goto fail; 637 } 638 } 639 640 if (binfo->initrd_size) { 641 rc = qemu_fdt_setprop_sized_cells(fdt, "/chosen", "linux,initrd-start", 642 acells, binfo->initrd_start); 643 if (rc < 0) { 644 fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n"); 645 goto fail; 646 } 647 648 rc = qemu_fdt_setprop_sized_cells(fdt, "/chosen", "linux,initrd-end", 649 acells, 650 binfo->initrd_start + 651 binfo->initrd_size); 652 if (rc < 0) { 653 fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n"); 654 goto fail; 655 } 656 } 657 658 fdt_add_psci_node(fdt, cpu); 659 660 if (binfo->modify_dtb) { 661 binfo->modify_dtb(binfo, fdt); 662 } 663 664 /* Put the DTB into the memory map as a ROM image: this will ensure 665 * the DTB is copied again upon reset, even if addr points into RAM. 666 */ 667 rom_add_blob_fixed_as("dtb", fdt, size, addr, as); 668 qemu_register_reset_nosnapshotload(qemu_fdt_randomize_seeds, 669 rom_ptr_for_as(as, addr, size)); 670 671 if (fdt != ms->fdt) { 672 g_free(ms->fdt); 673 ms->fdt = fdt; 674 } 675 676 return size; 677 678 fail: 679 g_free(fdt); 680 return -1; 681 } 682 683 static void do_cpu_reset(void *opaque) 684 { 685 ARMCPU *cpu = opaque; 686 CPUState *cs = CPU(cpu); 687 CPUARMState *env = &cpu->env; 688 const struct arm_boot_info *info = env->boot_info; 689 690 cpu_reset(cs); 691 if (info) { 692 if (!info->is_linux) { 693 int i; 694 /* Jump to the entry point. */ 695 uint64_t entry = info->entry; 696 697 switch (info->endianness) { 698 case ARM_ENDIANNESS_LE: 699 env->cp15.sctlr_el[1] &= ~SCTLR_E0E; 700 for (i = 1; i < 4; ++i) { 701 env->cp15.sctlr_el[i] &= ~SCTLR_EE; 702 } 703 env->uncached_cpsr &= ~CPSR_E; 704 break; 705 case ARM_ENDIANNESS_BE8: 706 env->cp15.sctlr_el[1] |= SCTLR_E0E; 707 for (i = 1; i < 4; ++i) { 708 env->cp15.sctlr_el[i] |= SCTLR_EE; 709 } 710 env->uncached_cpsr |= CPSR_E; 711 break; 712 case ARM_ENDIANNESS_BE32: 713 env->cp15.sctlr_el[1] |= SCTLR_B; 714 break; 715 case ARM_ENDIANNESS_UNKNOWN: 716 break; /* Board's decision */ 717 default: 718 g_assert_not_reached(); 719 } 720 721 cpu_set_pc(cs, entry); 722 } else { 723 /* 724 * If we are booting Linux then we might need to do so at: 725 * - AArch64 NS EL2 or NS EL1 726 * - AArch32 Secure SVC (EL3) 727 * - AArch32 NS Hyp (EL2) 728 * - AArch32 NS SVC (EL1) 729 * Configure the CPU in the way boot firmware would do to 730 * drop us down to the appropriate level. 731 */ 732 int target_el = arm_feature(env, ARM_FEATURE_EL2) ? 2 : 1; 733 734 if (env->aarch64) { 735 /* 736 * AArch64 kernels never boot in secure mode, and we don't 737 * support the secure_board_setup hook for AArch64. 738 */ 739 assert(!info->secure_boot); 740 assert(!info->secure_board_setup); 741 } else { 742 if (arm_feature(env, ARM_FEATURE_EL3) && 743 (info->secure_boot || 744 (info->secure_board_setup && cs == first_cpu))) { 745 /* Start this CPU in Secure SVC */ 746 target_el = 3; 747 } 748 } 749 750 arm_emulate_firmware_reset(cs, target_el); 751 752 if (cs == first_cpu) { 753 AddressSpace *as = arm_boot_address_space(cpu, info); 754 755 cpu_set_pc(cs, info->loader_start); 756 757 if (!have_dtb(info)) { 758 if (old_param) { 759 set_kernel_args_old(info, as); 760 } else { 761 set_kernel_args(info, as); 762 } 763 } 764 } else if (info->secondary_cpu_reset_hook) { 765 info->secondary_cpu_reset_hook(cpu, info); 766 } 767 } 768 769 if (tcg_enabled()) { 770 arm_rebuild_hflags(env); 771 } 772 } 773 } 774 775 static int do_arm_linux_init(Object *obj, void *opaque) 776 { 777 if (object_dynamic_cast(obj, TYPE_ARM_LINUX_BOOT_IF)) { 778 ARMLinuxBootIf *albif = ARM_LINUX_BOOT_IF(obj); 779 ARMLinuxBootIfClass *albifc = ARM_LINUX_BOOT_IF_GET_CLASS(obj); 780 struct arm_boot_info *info = opaque; 781 782 if (albifc->arm_linux_init) { 783 albifc->arm_linux_init(albif, info->secure_boot); 784 } 785 } 786 return 0; 787 } 788 789 static ssize_t arm_load_elf(struct arm_boot_info *info, uint64_t *pentry, 790 uint64_t *lowaddr, uint64_t *highaddr, 791 int elf_machine, AddressSpace *as) 792 { 793 bool elf_is64; 794 union { 795 Elf32_Ehdr h32; 796 Elf64_Ehdr h64; 797 } elf_header; 798 int data_swab = 0; 799 int elf_data_order; 800 ssize_t ret; 801 Error *err = NULL; 802 803 804 load_elf_hdr(info->kernel_filename, &elf_header, &elf_is64, &err); 805 if (err) { 806 /* 807 * If the file is not an ELF file we silently return. 808 * The caller will fall back to try other formats. 809 */ 810 error_free(err); 811 return -1; 812 } 813 814 if (elf_is64) { 815 elf_data_order = elf_header.h64.e_ident[EI_DATA]; 816 info->endianness = elf_data_order == ELFDATA2MSB ? ARM_ENDIANNESS_BE8 817 : ARM_ENDIANNESS_LE; 818 } else { 819 elf_data_order = elf_header.h32.e_ident[EI_DATA]; 820 if (elf_data_order == ELFDATA2MSB) { 821 if (bswap32(elf_header.h32.e_flags) & EF_ARM_BE8) { 822 info->endianness = ARM_ENDIANNESS_BE8; 823 } else { 824 info->endianness = ARM_ENDIANNESS_BE32; 825 /* In BE32, the CPU has a different view of the per-byte 826 * address map than the rest of the system. BE32 ELF files 827 * are organised such that they can be programmed through 828 * the CPU's per-word byte-reversed view of the world. QEMU 829 * however loads ELF files independently of the CPU. So 830 * tell the ELF loader to byte reverse the data for us. 831 */ 832 data_swab = 2; 833 } 834 } else { 835 info->endianness = ARM_ENDIANNESS_LE; 836 } 837 } 838 839 ret = load_elf_as(info->kernel_filename, NULL, NULL, NULL, 840 pentry, lowaddr, highaddr, NULL, elf_data_order, 841 elf_machine, 1, data_swab, as); 842 if (ret <= 0) { 843 /* The header loaded but the image didn't */ 844 error_report("Couldn't load elf '%s': %s", 845 info->kernel_filename, load_elf_strerror(ret)); 846 exit(1); 847 } 848 849 return ret; 850 } 851 852 static uint64_t load_aarch64_image(const char *filename, hwaddr mem_base, 853 hwaddr *entry, AddressSpace *as) 854 { 855 hwaddr kernel_load_offset = KERNEL64_LOAD_ADDR; 856 uint64_t kernel_size = 0; 857 uint8_t *buffer; 858 ssize_t size; 859 860 /* On aarch64, it's the bootloader's job to uncompress the kernel. */ 861 size = load_image_gzipped_buffer(filename, LOAD_IMAGE_MAX_GUNZIP_BYTES, 862 &buffer); 863 864 if (size < 0) { 865 gsize len; 866 867 /* Load as raw file otherwise */ 868 if (!g_file_get_contents(filename, (char **)&buffer, &len, NULL)) { 869 return -1; 870 } 871 size = len; 872 873 /* Unpack the image if it is a EFI zboot image */ 874 if (unpack_efi_zboot_image(&buffer, &size) < 0) { 875 g_free(buffer); 876 return -1; 877 } 878 } 879 880 /* check the arm64 magic header value -- very old kernels may not have it */ 881 if (size > ARM64_MAGIC_OFFSET + 4 && 882 memcmp(buffer + ARM64_MAGIC_OFFSET, "ARM\x64", 4) == 0) { 883 uint64_t hdrvals[2]; 884 885 /* The arm64 Image header has text_offset and image_size fields at 8 and 886 * 16 bytes into the Image header, respectively. The text_offset field 887 * is only valid if the image_size is non-zero. 888 */ 889 memcpy(&hdrvals, buffer + ARM64_TEXT_OFFSET_OFFSET, sizeof(hdrvals)); 890 891 kernel_size = le64_to_cpu(hdrvals[1]); 892 893 if (kernel_size != 0) { 894 kernel_load_offset = le64_to_cpu(hdrvals[0]); 895 896 /* 897 * We write our startup "bootloader" at the very bottom of RAM, 898 * so that bit can't be used for the image. Luckily the Image 899 * format specification is that the image requests only an offset 900 * from a 2MB boundary, not an absolute load address. So if the 901 * image requests an offset that might mean it overlaps with the 902 * bootloader, we can just load it starting at 2MB+offset rather 903 * than 0MB + offset. 904 */ 905 if (kernel_load_offset < BOOTLOADER_MAX_SIZE) { 906 kernel_load_offset += 2 * MiB; 907 } 908 } 909 } 910 911 /* 912 * Kernels before v3.17 don't populate the image_size field, and 913 * raw images have no header. For those our best guess at the size 914 * is the size of the Image file itself. 915 */ 916 if (kernel_size == 0) { 917 kernel_size = size; 918 } 919 920 *entry = mem_base + kernel_load_offset; 921 rom_add_blob_fixed_as(filename, buffer, size, *entry, as); 922 923 g_free(buffer); 924 925 return kernel_size; 926 } 927 928 static void arm_setup_direct_kernel_boot(ARMCPU *cpu, 929 struct arm_boot_info *info) 930 { 931 /* Set up for a direct boot of a kernel image file. */ 932 CPUState *cs; 933 AddressSpace *as = arm_boot_address_space(cpu, info); 934 ssize_t kernel_size; 935 int initrd_size; 936 int is_linux = 0; 937 uint64_t elf_entry; 938 /* Addresses of first byte used and first byte not used by the image */ 939 uint64_t image_low_addr = 0, image_high_addr = 0; 940 int elf_machine; 941 hwaddr entry; 942 static const ARMInsnFixup *primary_loader; 943 uint64_t ram_end = info->loader_start + info->ram_size; 944 945 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 946 primary_loader = bootloader_aarch64; 947 elf_machine = EM_AARCH64; 948 } else { 949 primary_loader = bootloader; 950 if (!info->write_board_setup) { 951 primary_loader += BOOTLOADER_NO_BOARD_SETUP_OFFSET; 952 } 953 elf_machine = EM_ARM; 954 } 955 956 /* Assume that raw images are linux kernels, and ELF images are not. */ 957 kernel_size = arm_load_elf(info, &elf_entry, &image_low_addr, 958 &image_high_addr, elf_machine, as); 959 if (kernel_size > 0 && have_dtb(info)) { 960 /* 961 * If there is still some room left at the base of RAM, try and put 962 * the DTB there like we do for images loaded with -bios or -pflash. 963 */ 964 if (image_low_addr > info->loader_start 965 || image_high_addr < info->loader_start) { 966 /* 967 * Set image_low_addr as address limit for arm_load_dtb if it may be 968 * pointing into RAM, otherwise pass '0' (no limit) 969 */ 970 if (image_low_addr < info->loader_start) { 971 image_low_addr = 0; 972 } 973 info->dtb_start = info->loader_start; 974 info->dtb_limit = image_low_addr; 975 } 976 } 977 entry = elf_entry; 978 if (kernel_size < 0) { 979 uint64_t loadaddr = info->loader_start + KERNEL_NOLOAD_ADDR; 980 kernel_size = load_uimage_as(info->kernel_filename, &entry, &loadaddr, 981 &is_linux, NULL, NULL, as); 982 if (kernel_size >= 0) { 983 image_low_addr = loadaddr; 984 image_high_addr = image_low_addr + kernel_size; 985 } 986 } 987 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && kernel_size < 0) { 988 kernel_size = load_aarch64_image(info->kernel_filename, 989 info->loader_start, &entry, as); 990 is_linux = 1; 991 if (kernel_size >= 0) { 992 image_low_addr = entry; 993 image_high_addr = image_low_addr + kernel_size; 994 } 995 } else if (kernel_size < 0) { 996 /* 32-bit ARM */ 997 entry = info->loader_start + KERNEL_LOAD_ADDR; 998 kernel_size = load_image_targphys_as(info->kernel_filename, entry, 999 ram_end - KERNEL_LOAD_ADDR, as); 1000 is_linux = 1; 1001 if (kernel_size >= 0) { 1002 image_low_addr = entry; 1003 image_high_addr = image_low_addr + kernel_size; 1004 } 1005 } 1006 if (kernel_size < 0) { 1007 error_report("could not load kernel '%s'", info->kernel_filename); 1008 exit(1); 1009 } 1010 1011 if (kernel_size > info->ram_size) { 1012 error_report("kernel '%s' is too large to fit in RAM " 1013 "(kernel size %zd, RAM size %" PRId64 ")", 1014 info->kernel_filename, kernel_size, info->ram_size); 1015 exit(1); 1016 } 1017 1018 info->entry = entry; 1019 1020 /* 1021 * We want to put the initrd far enough into RAM that when the 1022 * kernel is uncompressed it will not clobber the initrd. However 1023 * on boards without much RAM we must ensure that we still leave 1024 * enough room for a decent sized initrd, and on boards with large 1025 * amounts of RAM we must avoid the initrd being so far up in RAM 1026 * that it is outside lowmem and inaccessible to the kernel. 1027 * So for boards with less than 256MB of RAM we put the initrd 1028 * halfway into RAM, and for boards with 256MB of RAM or more we put 1029 * the initrd at 128MB. 1030 * We also refuse to put the initrd somewhere that will definitely 1031 * overlay the kernel we just loaded, though for kernel formats which 1032 * don't tell us their exact size (eg self-decompressing 32-bit kernels) 1033 * we might still make a bad choice here. 1034 */ 1035 info->initrd_start = info->loader_start + 1036 MIN(info->ram_size / 2, 128 * MiB); 1037 if (image_high_addr) { 1038 info->initrd_start = MAX(info->initrd_start, image_high_addr); 1039 } 1040 info->initrd_start = TARGET_PAGE_ALIGN(info->initrd_start); 1041 1042 if (is_linux) { 1043 uint32_t fixupcontext[FIXUP_MAX]; 1044 1045 if (info->initrd_filename) { 1046 1047 if (info->initrd_start >= ram_end) { 1048 error_report("not enough space after kernel to load initrd"); 1049 exit(1); 1050 } 1051 1052 initrd_size = load_ramdisk_as(info->initrd_filename, 1053 info->initrd_start, 1054 ram_end - info->initrd_start, as); 1055 if (initrd_size < 0) { 1056 initrd_size = load_image_targphys_as(info->initrd_filename, 1057 info->initrd_start, 1058 ram_end - 1059 info->initrd_start, 1060 as); 1061 } 1062 if (initrd_size < 0) { 1063 error_report("could not load initrd '%s'", 1064 info->initrd_filename); 1065 exit(1); 1066 } 1067 if (info->initrd_start + initrd_size > ram_end) { 1068 error_report("could not load initrd '%s': " 1069 "too big to fit into RAM after the kernel", 1070 info->initrd_filename); 1071 exit(1); 1072 } 1073 } else { 1074 initrd_size = 0; 1075 } 1076 info->initrd_size = initrd_size; 1077 1078 fixupcontext[FIXUP_BOARDID] = info->board_id; 1079 fixupcontext[FIXUP_BOARD_SETUP] = info->board_setup_addr; 1080 1081 /* 1082 * for device tree boot, we pass the DTB directly in r2. Otherwise 1083 * we point to the kernel args. 1084 */ 1085 if (have_dtb(info)) { 1086 hwaddr align; 1087 1088 if (elf_machine == EM_AARCH64) { 1089 /* 1090 * Some AArch64 kernels on early bootup map the fdt region as 1091 * 1092 * [ ALIGN_DOWN(fdt, 2MB) ... ALIGN_DOWN(fdt, 2MB) + 2MB ] 1093 * 1094 * Let's play safe and prealign it to 2MB to give us some space. 1095 */ 1096 align = 2 * MiB; 1097 } else { 1098 /* 1099 * Some 32bit kernels will trash anything in the 4K page the 1100 * initrd ends in, so make sure the DTB isn't caught up in that. 1101 */ 1102 align = 4 * KiB; 1103 } 1104 1105 /* Place the DTB after the initrd in memory with alignment. */ 1106 info->dtb_start = QEMU_ALIGN_UP(info->initrd_start + initrd_size, 1107 align); 1108 if (info->dtb_start >= ram_end) { 1109 error_report("Not enough space for DTB after kernel/initrd"); 1110 exit(1); 1111 } 1112 fixupcontext[FIXUP_ARGPTR_LO] = info->dtb_start; 1113 fixupcontext[FIXUP_ARGPTR_HI] = info->dtb_start >> 32; 1114 } else { 1115 fixupcontext[FIXUP_ARGPTR_LO] = 1116 info->loader_start + KERNEL_ARGS_ADDR; 1117 fixupcontext[FIXUP_ARGPTR_HI] = 1118 (info->loader_start + KERNEL_ARGS_ADDR) >> 32; 1119 if (info->ram_size >= 4 * GiB) { 1120 error_report("RAM size must be less than 4GB to boot" 1121 " Linux kernel using ATAGS (try passing a device tree" 1122 " using -dtb)"); 1123 exit(1); 1124 } 1125 } 1126 fixupcontext[FIXUP_ENTRYPOINT_LO] = entry; 1127 fixupcontext[FIXUP_ENTRYPOINT_HI] = entry >> 32; 1128 1129 arm_write_bootloader("bootloader", as, info->loader_start, 1130 primary_loader, fixupcontext); 1131 1132 if (info->write_board_setup) { 1133 info->write_board_setup(cpu, info); 1134 } 1135 1136 /* 1137 * Notify devices which need to fake up firmware initialization 1138 * that we're doing a direct kernel boot. 1139 */ 1140 object_child_foreach_recursive(object_get_root(), 1141 do_arm_linux_init, info); 1142 } 1143 info->is_linux = is_linux; 1144 1145 for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) { 1146 ARM_CPU(cs)->env.boot_info = info; 1147 } 1148 } 1149 1150 static void arm_setup_firmware_boot(ARMCPU *cpu, struct arm_boot_info *info) 1151 { 1152 /* Set up for booting firmware (which might load a kernel via fw_cfg) */ 1153 1154 if (have_dtb(info)) { 1155 /* 1156 * If we have a device tree blob, but no kernel to supply it to (or 1157 * the kernel is supposed to be loaded by the bootloader), copy the 1158 * DTB to the base of RAM for the bootloader to pick up. 1159 */ 1160 info->dtb_start = info->loader_start; 1161 } 1162 1163 if (info->kernel_filename) { 1164 FWCfgState *fw_cfg; 1165 bool try_decompressing_kernel; 1166 1167 fw_cfg = fw_cfg_find(); 1168 1169 if (!fw_cfg) { 1170 error_report("This machine type does not support loading both " 1171 "a guest firmware/BIOS image and a guest kernel at " 1172 "the same time. You should change your QEMU command " 1173 "line to specify one or the other, but not both."); 1174 exit(1); 1175 } 1176 1177 try_decompressing_kernel = arm_feature(&cpu->env, 1178 ARM_FEATURE_AARCH64); 1179 1180 /* 1181 * Expose the kernel, the command line, and the initrd in fw_cfg. 1182 * We don't process them here at all, it's all left to the 1183 * firmware. 1184 */ 1185 load_image_to_fw_cfg(fw_cfg, 1186 FW_CFG_KERNEL_SIZE, FW_CFG_KERNEL_DATA, 1187 info->kernel_filename, 1188 try_decompressing_kernel); 1189 load_image_to_fw_cfg(fw_cfg, 1190 FW_CFG_INITRD_SIZE, FW_CFG_INITRD_DATA, 1191 info->initrd_filename, false); 1192 1193 if (info->kernel_cmdline) { 1194 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 1195 strlen(info->kernel_cmdline) + 1); 1196 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, 1197 info->kernel_cmdline); 1198 } 1199 } 1200 1201 /* 1202 * We will start from address 0 (typically a boot ROM image) in the 1203 * same way as hardware. Leave env->boot_info NULL, so that 1204 * do_cpu_reset() knows it does not need to alter the PC on reset. 1205 */ 1206 } 1207 1208 void arm_load_kernel(ARMCPU *cpu, MachineState *ms, struct arm_boot_info *info) 1209 { 1210 CPUState *cs; 1211 AddressSpace *as = arm_boot_address_space(cpu, info); 1212 int boot_el; 1213 CPUARMState *env = &cpu->env; 1214 int nb_cpus = 0; 1215 1216 /* 1217 * CPU objects (unlike devices) are not automatically reset on system 1218 * reset, so we must always register a handler to do so. If we're 1219 * actually loading a kernel, the handler is also responsible for 1220 * arranging that we start it correctly. 1221 */ 1222 for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) { 1223 qemu_register_reset(do_cpu_reset, ARM_CPU(cs)); 1224 nb_cpus++; 1225 } 1226 1227 /* 1228 * The board code is not supposed to set secure_board_setup unless 1229 * running its code in secure mode is actually possible, and KVM 1230 * doesn't support secure. 1231 */ 1232 assert(!(info->secure_board_setup && kvm_enabled())); 1233 info->kernel_filename = ms->kernel_filename; 1234 info->kernel_cmdline = ms->kernel_cmdline; 1235 info->initrd_filename = ms->initrd_filename; 1236 info->dtb_filename = ms->dtb; 1237 info->dtb_limit = 0; 1238 1239 /* Load the kernel. */ 1240 if (!info->kernel_filename || info->firmware_loaded) { 1241 arm_setup_firmware_boot(cpu, info); 1242 } else { 1243 arm_setup_direct_kernel_boot(cpu, info); 1244 } 1245 1246 /* 1247 * Disable the PSCI conduit if it is set up to target the same 1248 * or a lower EL than the one we're going to start the guest code in. 1249 * This logic needs to agree with the code in do_cpu_reset() which 1250 * decides whether we're going to boot the guest in the highest 1251 * supported exception level or in a lower one. 1252 */ 1253 1254 /* 1255 * If PSCI is enabled, then SMC calls all go to the PSCI handler and 1256 * are never emulated to trap into guest code. It therefore does not 1257 * make sense for the board to have a setup code fragment that runs 1258 * in Secure, because this will probably need to itself issue an SMC of some 1259 * kind as part of its operation. 1260 */ 1261 assert(info->psci_conduit == QEMU_PSCI_CONDUIT_DISABLED || 1262 !info->secure_board_setup); 1263 1264 /* Boot into highest supported EL ... */ 1265 if (arm_feature(env, ARM_FEATURE_EL3)) { 1266 boot_el = 3; 1267 } else if (arm_feature(env, ARM_FEATURE_EL2)) { 1268 boot_el = 2; 1269 } else { 1270 boot_el = 1; 1271 } 1272 /* ...except that if we're booting Linux we adjust the EL we boot into */ 1273 if (info->is_linux && !info->secure_boot) { 1274 boot_el = arm_feature(env, ARM_FEATURE_EL2) ? 2 : 1; 1275 } 1276 1277 if ((info->psci_conduit == QEMU_PSCI_CONDUIT_HVC && boot_el >= 2) || 1278 (info->psci_conduit == QEMU_PSCI_CONDUIT_SMC && boot_el == 3)) { 1279 info->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; 1280 } 1281 1282 if (info->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED) { 1283 for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) { 1284 Object *cpuobj = OBJECT(cs); 1285 1286 object_property_set_int(cpuobj, "psci-conduit", info->psci_conduit, 1287 &error_abort); 1288 /* 1289 * Secondary CPUs start in PSCI powered-down state. Like the 1290 * code in do_cpu_reset(), we assume first_cpu is the primary 1291 * CPU. 1292 */ 1293 if (cs != first_cpu) { 1294 object_property_set_bool(cpuobj, "start-powered-off", true, 1295 &error_abort); 1296 } 1297 } 1298 } 1299 1300 if (info->psci_conduit == QEMU_PSCI_CONDUIT_DISABLED && 1301 info->is_linux && nb_cpus > 1) { 1302 /* 1303 * We're booting Linux but not using PSCI, so for SMP we need 1304 * to write a custom secondary CPU boot loader stub, and arrange 1305 * for the secondary CPU reset to make the accompanying initialization. 1306 */ 1307 if (!info->secondary_cpu_reset_hook) { 1308 info->secondary_cpu_reset_hook = default_reset_secondary; 1309 } 1310 if (!info->write_secondary_boot) { 1311 info->write_secondary_boot = default_write_secondary; 1312 } 1313 info->write_secondary_boot(cpu, info); 1314 } else { 1315 /* 1316 * No secondary boot stub; don't use the reset hook that would 1317 * have set the CPU up to call it 1318 */ 1319 info->write_secondary_boot = NULL; 1320 info->secondary_cpu_reset_hook = NULL; 1321 } 1322 1323 /* 1324 * arm_load_dtb() may add a PSCI node so it must be called after we have 1325 * decided whether to enable PSCI and set the psci-conduit CPU properties. 1326 */ 1327 if (!info->skip_dtb_autoload && have_dtb(info)) { 1328 if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, 1329 as, ms, cpu) < 0) { 1330 exit(1); 1331 } 1332 } 1333 } 1334 1335 static const TypeInfo arm_linux_boot_if_info = { 1336 .name = TYPE_ARM_LINUX_BOOT_IF, 1337 .parent = TYPE_INTERFACE, 1338 .class_size = sizeof(ARMLinuxBootIfClass), 1339 }; 1340 1341 static void arm_linux_boot_register_types(void) 1342 { 1343 type_register_static(&arm_linux_boot_if_info); 1344 } 1345 1346 type_init(arm_linux_boot_register_types) 1347