1 /* 2 * Raspberry Pi emulation (c) 2012 Gregory Estrade 3 * Upstreaming code cleanup [including bcm2835_*] (c) 2013 Jan Petrous 4 * 5 * Rasperry Pi 2 emulation and refactoring Copyright (c) 2015, Microsoft 6 * Written by Andrew Baumann 7 * 8 * This work is licensed under the terms of the GNU GPL, version 2 or later. 9 * See the COPYING file in the top-level directory. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "qemu/module.h" 15 #include "hw/arm/bcm2836.h" 16 #include "hw/arm/raspi_platform.h" 17 #include "hw/sysbus.h" 18 #include "target/arm/cpu-qom.h" 19 #include "target/arm/gtimer.h" 20 21 struct BCM283XClass { 22 /*< private >*/ 23 DeviceClass parent_class; 24 /*< public >*/ 25 const char *name; 26 const char *cpu_type; 27 unsigned core_count; 28 hwaddr peri_base; /* Peripheral base address seen by the CPU */ 29 hwaddr ctrl_base; /* Interrupt controller and mailboxes etc. */ 30 int clusterid; 31 }; 32 33 static Property bcm2836_enabled_cores_property = 34 DEFINE_PROP_UINT32("enabled-cpus", BCM283XBaseState, enabled_cpus, 0); 35 36 static void bcm283x_base_init(Object *obj) 37 { 38 BCM283XBaseState *s = BCM283X_BASE(obj); 39 BCM283XBaseClass *bc = BCM283X_BASE_GET_CLASS(obj); 40 int n; 41 42 for (n = 0; n < bc->core_count; n++) { 43 object_initialize_child(obj, "cpu[*]", &s->cpu[n].core, 44 bc->cpu_type); 45 } 46 if (bc->core_count > 1) { 47 qdev_property_add_static(DEVICE(obj), &bcm2836_enabled_cores_property); 48 qdev_prop_set_uint32(DEVICE(obj), "enabled-cpus", bc->core_count); 49 } 50 51 if (bc->ctrl_base) { 52 object_initialize_child(obj, "control", &s->control, 53 TYPE_BCM2836_CONTROL); 54 } 55 } 56 57 static void bcm283x_init(Object *obj) 58 { 59 BCM283XState *s = BCM283X(obj); 60 61 object_initialize_child(obj, "peripherals", &s->peripherals, 62 TYPE_BCM2835_PERIPHERALS); 63 object_property_add_alias(obj, "board-rev", OBJECT(&s->peripherals), 64 "board-rev"); 65 object_property_add_alias(obj, "command-line", OBJECT(&s->peripherals), 66 "command-line"); 67 object_property_add_alias(obj, "vcram-size", OBJECT(&s->peripherals), 68 "vcram-size"); 69 } 70 71 bool bcm283x_common_realize(DeviceState *dev, Error **errp) 72 { 73 BCM283XState *s = BCM283X(dev); 74 BCM283XBaseState *s_base = BCM283X_BASE(dev); 75 BCM283XBaseClass *bc = BCM283X_BASE_GET_CLASS(dev); 76 Object *obj; 77 78 /* common peripherals from bcm2835 */ 79 80 obj = object_property_get_link(OBJECT(dev), "ram", &error_abort); 81 82 object_property_add_const_link(OBJECT(&s->peripherals), "ram", obj); 83 84 if (!sysbus_realize(SYS_BUS_DEVICE(&s->peripherals), errp)) { 85 return false; 86 } 87 88 object_property_add_alias(OBJECT(s_base), "sd-bus", 89 OBJECT(&s->peripherals), "sd-bus"); 90 91 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->peripherals), 92 0, bc->peri_base, 1); 93 return true; 94 } 95 96 static void bcm2835_realize(DeviceState *dev, Error **errp) 97 { 98 BCM283XState *s = BCM283X(dev); 99 BCM283XBaseState *s_base = BCM283X_BASE(dev); 100 101 if (!bcm283x_common_realize(dev, errp)) { 102 return; 103 } 104 105 if (!qdev_realize(DEVICE(&s_base->cpu[0].core), NULL, errp)) { 106 return; 107 } 108 109 /* Connect irq/fiq outputs from the interrupt controller. */ 110 sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 0, 111 qdev_get_gpio_in(DEVICE(&s_base->cpu[0].core), ARM_CPU_IRQ)); 112 sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1, 113 qdev_get_gpio_in(DEVICE(&s_base->cpu[0].core), ARM_CPU_FIQ)); 114 } 115 116 static void bcm2836_realize(DeviceState *dev, Error **errp) 117 { 118 int n; 119 BCM283XState *s = BCM283X(dev); 120 BCM283XBaseState *s_base = BCM283X_BASE(dev); 121 BCM283XBaseClass *bc = BCM283X_BASE_GET_CLASS(dev); 122 123 if (!bcm283x_common_realize(dev, errp)) { 124 return; 125 } 126 127 /* bcm2836 interrupt controller (and mailboxes, etc.) */ 128 if (!sysbus_realize(SYS_BUS_DEVICE(&s_base->control), errp)) { 129 return; 130 } 131 132 sysbus_mmio_map(SYS_BUS_DEVICE(&s_base->control), 0, bc->ctrl_base); 133 134 sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 0, 135 qdev_get_gpio_in_named(DEVICE(&s_base->control), "gpu-irq", 0)); 136 sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1, 137 qdev_get_gpio_in_named(DEVICE(&s_base->control), "gpu-fiq", 0)); 138 139 for (n = 0; n < BCM283X_NCPUS; n++) { 140 object_property_set_int(OBJECT(&s_base->cpu[n].core), "mp-affinity", 141 (bc->clusterid << 8) | n, &error_abort); 142 143 /* set periphbase/CBAR value for CPU-local registers */ 144 object_property_set_int(OBJECT(&s_base->cpu[n].core), "reset-cbar", 145 bc->peri_base, &error_abort); 146 147 /* start powered off if not enabled */ 148 object_property_set_bool(OBJECT(&s_base->cpu[n].core), 149 "start-powered-off", 150 n >= s_base->enabled_cpus, &error_abort); 151 152 if (!qdev_realize(DEVICE(&s_base->cpu[n].core), NULL, errp)) { 153 return; 154 } 155 156 /* Connect irq/fiq outputs from the interrupt controller. */ 157 qdev_connect_gpio_out_named(DEVICE(&s_base->control), "irq", n, 158 qdev_get_gpio_in(DEVICE(&s_base->cpu[n].core), ARM_CPU_IRQ)); 159 qdev_connect_gpio_out_named(DEVICE(&s_base->control), "fiq", n, 160 qdev_get_gpio_in(DEVICE(&s_base->cpu[n].core), ARM_CPU_FIQ)); 161 162 /* Connect timers from the CPU to the interrupt controller */ 163 qdev_connect_gpio_out(DEVICE(&s_base->cpu[n].core), GTIMER_PHYS, 164 qdev_get_gpio_in_named(DEVICE(&s_base->control), "cntpnsirq", n)); 165 qdev_connect_gpio_out(DEVICE(&s_base->cpu[n].core), GTIMER_VIRT, 166 qdev_get_gpio_in_named(DEVICE(&s_base->control), "cntvirq", n)); 167 qdev_connect_gpio_out(DEVICE(&s_base->cpu[n].core), GTIMER_HYP, 168 qdev_get_gpio_in_named(DEVICE(&s_base->control), "cnthpirq", n)); 169 qdev_connect_gpio_out(DEVICE(&s_base->cpu[n].core), GTIMER_SEC, 170 qdev_get_gpio_in_named(DEVICE(&s_base->control), "cntpsirq", n)); 171 } 172 } 173 174 static void bcm283x_base_class_init(ObjectClass *oc, void *data) 175 { 176 DeviceClass *dc = DEVICE_CLASS(oc); 177 178 /* Reason: Must be wired up in code (see raspi_init() function) */ 179 dc->user_creatable = false; 180 } 181 182 static void bcm2835_class_init(ObjectClass *oc, void *data) 183 { 184 DeviceClass *dc = DEVICE_CLASS(oc); 185 BCM283XBaseClass *bc = BCM283X_BASE_CLASS(oc); 186 187 bc->cpu_type = ARM_CPU_TYPE_NAME("arm1176"); 188 bc->core_count = 1; 189 bc->peri_base = 0x20000000; 190 dc->realize = bcm2835_realize; 191 }; 192 193 static void bcm2836_class_init(ObjectClass *oc, void *data) 194 { 195 DeviceClass *dc = DEVICE_CLASS(oc); 196 BCM283XBaseClass *bc = BCM283X_BASE_CLASS(oc); 197 198 bc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7"); 199 bc->core_count = BCM283X_NCPUS; 200 bc->peri_base = 0x3f000000; 201 bc->ctrl_base = 0x40000000; 202 bc->clusterid = 0xf; 203 dc->realize = bcm2836_realize; 204 }; 205 206 #ifdef TARGET_AARCH64 207 static void bcm2837_class_init(ObjectClass *oc, void *data) 208 { 209 DeviceClass *dc = DEVICE_CLASS(oc); 210 BCM283XBaseClass *bc = BCM283X_BASE_CLASS(oc); 211 212 bc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a53"); 213 bc->core_count = BCM283X_NCPUS; 214 bc->peri_base = 0x3f000000; 215 bc->ctrl_base = 0x40000000; 216 bc->clusterid = 0x0; 217 dc->realize = bcm2836_realize; 218 }; 219 #endif 220 221 static const TypeInfo bcm283x_types[] = { 222 { 223 .name = TYPE_BCM2835, 224 .parent = TYPE_BCM283X, 225 .class_init = bcm2835_class_init, 226 }, { 227 .name = TYPE_BCM2836, 228 .parent = TYPE_BCM283X, 229 .class_init = bcm2836_class_init, 230 #ifdef TARGET_AARCH64 231 }, { 232 .name = TYPE_BCM2837, 233 .parent = TYPE_BCM283X, 234 .class_init = bcm2837_class_init, 235 #endif 236 }, { 237 .name = TYPE_BCM283X, 238 .parent = TYPE_BCM283X_BASE, 239 .instance_size = sizeof(BCM283XState), 240 .instance_init = bcm283x_init, 241 .abstract = true, 242 }, { 243 .name = TYPE_BCM283X_BASE, 244 .parent = TYPE_DEVICE, 245 .instance_size = sizeof(BCM283XBaseState), 246 .instance_init = bcm283x_base_init, 247 .class_size = sizeof(BCM283XBaseClass), 248 .class_init = bcm283x_base_class_init, 249 .abstract = true, 250 } 251 }; 252 253 DEFINE_TYPES(bcm283x_types) 254