1 /* 2 * Raspberry Pi emulation (c) 2012 Gregory Estrade 3 * Upstreaming code cleanup [including bcm2835_*] (c) 2013 Jan Petrous 4 * 5 * Rasperry Pi 2 emulation and refactoring Copyright (c) 2015, Microsoft 6 * Written by Andrew Baumann 7 * 8 * This work is licensed under the terms of the GNU GPL, version 2 or later. 9 * See the COPYING file in the top-level directory. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "qemu/module.h" 15 #include "hw/arm/bcm2836.h" 16 #include "hw/arm/raspi_platform.h" 17 #include "hw/sysbus.h" 18 #include "target/arm/cpu-qom.h" 19 #include "target/arm/gtimer.h" 20 21 struct BCM283XClass { 22 /*< private >*/ 23 DeviceClass parent_class; 24 /*< public >*/ 25 const char *name; 26 const char *cpu_type; 27 unsigned core_count; 28 hwaddr peri_base; /* Peripheral base address seen by the CPU */ 29 hwaddr ctrl_base; /* Interrupt controller and mailboxes etc. */ 30 int clusterid; 31 }; 32 33 static Property bcm2836_enabled_cores_property = 34 DEFINE_PROP_UINT32("enabled-cpus", BCM283XBaseState, enabled_cpus, 0); 35 36 static void bcm283x_base_init(Object *obj) 37 { 38 BCM283XBaseState *s = BCM283X_BASE(obj); 39 BCM283XBaseClass *bc = BCM283X_BASE_GET_CLASS(obj); 40 int n; 41 42 for (n = 0; n < bc->core_count; n++) { 43 object_initialize_child(obj, "cpu[*]", &s->cpu[n].core, 44 bc->cpu_type); 45 } 46 if (bc->core_count > 1) { 47 qdev_property_add_static(DEVICE(obj), &bcm2836_enabled_cores_property); 48 qdev_prop_set_uint32(DEVICE(obj), "enabled-cpus", bc->core_count); 49 } 50 51 if (bc->ctrl_base) { 52 object_initialize_child(obj, "control", &s->control, 53 TYPE_BCM2836_CONTROL); 54 } 55 } 56 57 static void bcm283x_init(Object *obj) 58 { 59 BCM283XState *s = BCM283X(obj); 60 61 object_initialize_child(obj, "peripherals", &s->peripherals, 62 TYPE_BCM2835_PERIPHERALS); 63 object_property_add_alias(obj, "board-rev", OBJECT(&s->peripherals), 64 "board-rev"); 65 object_property_add_alias(obj, "command-line", OBJECT(&s->peripherals), 66 "command-line"); 67 object_property_add_alias(obj, "vcram-size", OBJECT(&s->peripherals), 68 "vcram-size"); 69 } 70 71 bool bcm283x_common_realize(DeviceState *dev, BCMSocPeripheralBaseState *ps, 72 Error **errp) 73 { 74 BCM283XBaseState *s = BCM283X_BASE(dev); 75 BCM283XBaseClass *bc = BCM283X_BASE_GET_CLASS(dev); 76 Object *obj; 77 78 /* common peripherals from bcm2835 */ 79 80 obj = object_property_get_link(OBJECT(dev), "ram", &error_abort); 81 82 object_property_add_const_link(OBJECT(ps), "ram", obj); 83 84 if (!sysbus_realize(SYS_BUS_DEVICE(ps), errp)) { 85 return false; 86 } 87 88 object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(ps), "sd-bus"); 89 90 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(ps), 0, bc->peri_base, 1); 91 return true; 92 } 93 94 static void bcm2835_realize(DeviceState *dev, Error **errp) 95 { 96 BCM283XState *s = BCM283X(dev); 97 BCM283XBaseState *s_base = BCM283X_BASE(dev); 98 BCMSocPeripheralBaseState *ps_base 99 = BCM_SOC_PERIPHERALS_BASE(&s->peripherals); 100 101 if (!bcm283x_common_realize(dev, ps_base, errp)) { 102 return; 103 } 104 105 if (!qdev_realize(DEVICE(&s_base->cpu[0].core), NULL, errp)) { 106 return; 107 } 108 109 /* Connect irq/fiq outputs from the interrupt controller. */ 110 sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 0, 111 qdev_get_gpio_in(DEVICE(&s_base->cpu[0].core), ARM_CPU_IRQ)); 112 sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1, 113 qdev_get_gpio_in(DEVICE(&s_base->cpu[0].core), ARM_CPU_FIQ)); 114 } 115 116 static void bcm2836_realize(DeviceState *dev, Error **errp) 117 { 118 int n; 119 BCM283XState *s = BCM283X(dev); 120 BCM283XBaseState *s_base = BCM283X_BASE(dev); 121 BCM283XBaseClass *bc = BCM283X_BASE_GET_CLASS(dev); 122 BCMSocPeripheralBaseState *ps_base 123 = BCM_SOC_PERIPHERALS_BASE(&s->peripherals); 124 125 if (!bcm283x_common_realize(dev, ps_base, errp)) { 126 return; 127 } 128 129 /* bcm2836 interrupt controller (and mailboxes, etc.) */ 130 if (!sysbus_realize(SYS_BUS_DEVICE(&s_base->control), errp)) { 131 return; 132 } 133 134 sysbus_mmio_map(SYS_BUS_DEVICE(&s_base->control), 0, bc->ctrl_base); 135 136 sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 0, 137 qdev_get_gpio_in_named(DEVICE(&s_base->control), "gpu-irq", 0)); 138 sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1, 139 qdev_get_gpio_in_named(DEVICE(&s_base->control), "gpu-fiq", 0)); 140 141 for (n = 0; n < BCM283X_NCPUS; n++) { 142 object_property_set_int(OBJECT(&s_base->cpu[n].core), "mp-affinity", 143 (bc->clusterid << 8) | n, &error_abort); 144 145 /* set periphbase/CBAR value for CPU-local registers */ 146 object_property_set_int(OBJECT(&s_base->cpu[n].core), "reset-cbar", 147 bc->peri_base, &error_abort); 148 149 /* start powered off if not enabled */ 150 object_property_set_bool(OBJECT(&s_base->cpu[n].core), 151 "start-powered-off", 152 n >= s_base->enabled_cpus, &error_abort); 153 154 if (!qdev_realize(DEVICE(&s_base->cpu[n].core), NULL, errp)) { 155 return; 156 } 157 158 /* Connect irq/fiq outputs from the interrupt controller. */ 159 qdev_connect_gpio_out_named(DEVICE(&s_base->control), "irq", n, 160 qdev_get_gpio_in(DEVICE(&s_base->cpu[n].core), ARM_CPU_IRQ)); 161 qdev_connect_gpio_out_named(DEVICE(&s_base->control), "fiq", n, 162 qdev_get_gpio_in(DEVICE(&s_base->cpu[n].core), ARM_CPU_FIQ)); 163 164 /* Connect timers from the CPU to the interrupt controller */ 165 qdev_connect_gpio_out(DEVICE(&s_base->cpu[n].core), GTIMER_PHYS, 166 qdev_get_gpio_in_named(DEVICE(&s_base->control), "cntpnsirq", n)); 167 qdev_connect_gpio_out(DEVICE(&s_base->cpu[n].core), GTIMER_VIRT, 168 qdev_get_gpio_in_named(DEVICE(&s_base->control), "cntvirq", n)); 169 qdev_connect_gpio_out(DEVICE(&s_base->cpu[n].core), GTIMER_HYP, 170 qdev_get_gpio_in_named(DEVICE(&s_base->control), "cnthpirq", n)); 171 qdev_connect_gpio_out(DEVICE(&s_base->cpu[n].core), GTIMER_SEC, 172 qdev_get_gpio_in_named(DEVICE(&s_base->control), "cntpsirq", n)); 173 } 174 } 175 176 static void bcm283x_base_class_init(ObjectClass *oc, void *data) 177 { 178 DeviceClass *dc = DEVICE_CLASS(oc); 179 180 /* Reason: Must be wired up in code (see raspi_init() function) */ 181 dc->user_creatable = false; 182 } 183 184 static void bcm2835_class_init(ObjectClass *oc, void *data) 185 { 186 DeviceClass *dc = DEVICE_CLASS(oc); 187 BCM283XBaseClass *bc = BCM283X_BASE_CLASS(oc); 188 189 bc->cpu_type = ARM_CPU_TYPE_NAME("arm1176"); 190 bc->core_count = 1; 191 bc->peri_base = 0x20000000; 192 dc->realize = bcm2835_realize; 193 }; 194 195 static void bcm2836_class_init(ObjectClass *oc, void *data) 196 { 197 DeviceClass *dc = DEVICE_CLASS(oc); 198 BCM283XBaseClass *bc = BCM283X_BASE_CLASS(oc); 199 200 bc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7"); 201 bc->core_count = BCM283X_NCPUS; 202 bc->peri_base = 0x3f000000; 203 bc->ctrl_base = 0x40000000; 204 bc->clusterid = 0xf; 205 dc->realize = bcm2836_realize; 206 }; 207 208 #ifdef TARGET_AARCH64 209 static void bcm2837_class_init(ObjectClass *oc, void *data) 210 { 211 DeviceClass *dc = DEVICE_CLASS(oc); 212 BCM283XBaseClass *bc = BCM283X_BASE_CLASS(oc); 213 214 bc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a53"); 215 bc->core_count = BCM283X_NCPUS; 216 bc->peri_base = 0x3f000000; 217 bc->ctrl_base = 0x40000000; 218 bc->clusterid = 0x0; 219 dc->realize = bcm2836_realize; 220 }; 221 #endif 222 223 static const TypeInfo bcm283x_types[] = { 224 { 225 .name = TYPE_BCM2835, 226 .parent = TYPE_BCM283X, 227 .class_init = bcm2835_class_init, 228 }, { 229 .name = TYPE_BCM2836, 230 .parent = TYPE_BCM283X, 231 .class_init = bcm2836_class_init, 232 #ifdef TARGET_AARCH64 233 }, { 234 .name = TYPE_BCM2837, 235 .parent = TYPE_BCM283X, 236 .class_init = bcm2837_class_init, 237 #endif 238 }, { 239 .name = TYPE_BCM283X, 240 .parent = TYPE_BCM283X_BASE, 241 .instance_size = sizeof(BCM283XState), 242 .instance_init = bcm283x_init, 243 .abstract = true, 244 }, { 245 .name = TYPE_BCM283X_BASE, 246 .parent = TYPE_DEVICE, 247 .instance_size = sizeof(BCM283XBaseState), 248 .instance_init = bcm283x_base_init, 249 .class_size = sizeof(BCM283XBaseClass), 250 .class_init = bcm283x_base_class_init, 251 .abstract = true, 252 } 253 }; 254 255 DEFINE_TYPES(bcm283x_types) 256