1 /* 2 * Raspberry Pi emulation (c) 2012 Gregory Estrade 3 * Upstreaming code cleanup [including bcm2835_*] (c) 2013 Jan Petrous 4 * 5 * Rasperry Pi 2 emulation and refactoring Copyright (c) 2015, Microsoft 6 * Written by Andrew Baumann 7 * 8 * This work is licensed under the terms of the GNU GPL, version 2 or later. 9 * See the COPYING file in the top-level directory. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "qemu/module.h" 15 #include "hw/arm/bcm2835_peripherals.h" 16 #include "hw/misc/bcm2835_mbox_defs.h" 17 #include "hw/arm/raspi_platform.h" 18 #include "sysemu/sysemu.h" 19 20 /* Peripheral base address on the VC (GPU) system bus */ 21 #define BCM2835_VC_PERI_BASE 0x7e000000 22 23 /* Capabilities for SD controller: no DMA, high-speed, default clocks etc. */ 24 #define BCM2835_SDHC_CAPAREG 0x52134b4 25 26 /* 27 * According to Linux driver & DTS, dma channels 0--10 have separate IRQ, 28 * while channels 11--14 share one IRQ: 29 */ 30 #define SEPARATE_DMA_IRQ_MAX 10 31 #define ORGATED_DMA_IRQ_COUNT 4 32 33 /* All three I2C controllers share the same IRQ */ 34 #define ORGATED_I2C_IRQ_COUNT 3 35 36 void create_unimp(BCMSocPeripheralBaseState *ps, 37 UnimplementedDeviceState *uds, 38 const char *name, hwaddr ofs, hwaddr size) 39 { 40 object_initialize_child(OBJECT(ps), name, uds, TYPE_UNIMPLEMENTED_DEVICE); 41 qdev_prop_set_string(DEVICE(uds), "name", name); 42 qdev_prop_set_uint64(DEVICE(uds), "size", size); 43 sysbus_realize(SYS_BUS_DEVICE(uds), &error_fatal); 44 memory_region_add_subregion_overlap(&ps->peri_mr, ofs, 45 sysbus_mmio_get_region(SYS_BUS_DEVICE(uds), 0), -1000); 46 } 47 48 static void bcm2835_peripherals_init(Object *obj) 49 { 50 BCM2835PeripheralState *s = BCM2835_PERIPHERALS(obj); 51 BCMSocPeripheralBaseState *s_base = BCM_SOC_PERIPHERALS_BASE(obj); 52 53 /* Random Number Generator */ 54 object_initialize_child(obj, "rng", &s->rng, TYPE_BCM2835_RNG); 55 56 /* Thermal */ 57 object_initialize_child(obj, "thermal", &s->thermal, TYPE_BCM2835_THERMAL); 58 59 /* GPIO */ 60 object_initialize_child(obj, "gpio", &s->gpio, TYPE_BCM2835_GPIO); 61 62 object_property_add_const_link(OBJECT(&s->gpio), "sdbus-sdhci", 63 OBJECT(&s_base->sdhci.sdbus)); 64 object_property_add_const_link(OBJECT(&s->gpio), "sdbus-sdhost", 65 OBJECT(&s_base->sdhost.sdbus)); 66 67 /* Gated DMA interrupts */ 68 object_initialize_child(obj, "orgated-dma-irq", 69 &s_base->orgated_dma_irq, TYPE_OR_IRQ); 70 object_property_set_int(OBJECT(&s_base->orgated_dma_irq), "num-lines", 71 ORGATED_DMA_IRQ_COUNT, &error_abort); 72 } 73 74 static void raspi_peripherals_base_init(Object *obj) 75 { 76 BCMSocPeripheralBaseState *s = BCM_SOC_PERIPHERALS_BASE(obj); 77 BCMSocPeripheralBaseClass *bc = BCM_SOC_PERIPHERALS_BASE_GET_CLASS(obj); 78 79 /* Memory region for peripheral devices, which we export to our parent */ 80 memory_region_init(&s->peri_mr, obj, "bcm2835-peripherals", bc->peri_size); 81 sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->peri_mr); 82 83 /* Internal memory region for peripheral bus addresses (not exported) */ 84 memory_region_init(&s->gpu_bus_mr, obj, "bcm2835-gpu", (uint64_t)1 << 32); 85 86 /* Internal memory region for request/response communication with 87 * mailbox-addressable peripherals (not exported) 88 */ 89 memory_region_init(&s->mbox_mr, obj, "bcm2835-mbox", 90 MBOX_CHAN_COUNT << MBOX_AS_CHAN_SHIFT); 91 92 /* Interrupt Controller */ 93 object_initialize_child(obj, "ic", &s->ic, TYPE_BCM2835_IC); 94 95 /* SYS Timer */ 96 object_initialize_child(obj, "systimer", &s->systmr, 97 TYPE_BCM2835_SYSTIMER); 98 99 /* UART0 */ 100 object_initialize_child(obj, "uart0", &s->uart0, TYPE_PL011); 101 102 /* AUX / UART1 */ 103 object_initialize_child(obj, "aux", &s->aux, TYPE_BCM2835_AUX); 104 105 /* Mailboxes */ 106 object_initialize_child(obj, "mbox", &s->mboxes, TYPE_BCM2835_MBOX); 107 108 object_property_add_const_link(OBJECT(&s->mboxes), "mbox-mr", 109 OBJECT(&s->mbox_mr)); 110 111 /* Framebuffer */ 112 object_initialize_child(obj, "fb", &s->fb, TYPE_BCM2835_FB); 113 object_property_add_alias(obj, "vcram-size", OBJECT(&s->fb), "vcram-size"); 114 object_property_add_alias(obj, "vcram-base", OBJECT(&s->fb), "vcram-base"); 115 116 object_property_add_const_link(OBJECT(&s->fb), "dma-mr", 117 OBJECT(&s->gpu_bus_mr)); 118 119 /* OTP */ 120 object_initialize_child(obj, "bcm2835-otp", &s->otp, 121 TYPE_BCM2835_OTP); 122 123 /* Property channel */ 124 object_initialize_child(obj, "property", &s->property, 125 TYPE_BCM2835_PROPERTY); 126 object_property_add_alias(obj, "board-rev", OBJECT(&s->property), 127 "board-rev"); 128 object_property_add_alias(obj, "command-line", OBJECT(&s->property), 129 "command-line"); 130 131 object_property_add_const_link(OBJECT(&s->property), "fb", 132 OBJECT(&s->fb)); 133 object_property_add_const_link(OBJECT(&s->property), "dma-mr", 134 OBJECT(&s->gpu_bus_mr)); 135 136 /* Extended Mass Media Controller */ 137 object_initialize_child(obj, "sdhci", &s->sdhci, TYPE_SYSBUS_SDHCI); 138 139 /* SDHOST */ 140 object_initialize_child(obj, "sdhost", &s->sdhost, TYPE_BCM2835_SDHOST); 141 142 /* DMA Channels */ 143 object_initialize_child(obj, "dma", &s->dma, TYPE_BCM2835_DMA); 144 145 object_property_add_const_link(OBJECT(&s->dma), "dma-mr", 146 OBJECT(&s->gpu_bus_mr)); 147 148 /* Mphi */ 149 object_initialize_child(obj, "mphi", &s->mphi, TYPE_BCM2835_MPHI); 150 151 /* DWC2 */ 152 object_initialize_child(obj, "dwc2", &s->dwc2, TYPE_DWC2_USB); 153 154 /* CPRMAN clock manager */ 155 object_initialize_child(obj, "cprman", &s->cprman, TYPE_BCM2835_CPRMAN); 156 157 object_property_add_const_link(OBJECT(&s->dwc2), "dma-mr", 158 OBJECT(&s->gpu_bus_mr)); 159 160 /* Power Management */ 161 object_initialize_child(obj, "powermgt", &s->powermgt, 162 TYPE_BCM2835_POWERMGT); 163 164 /* SPI */ 165 object_initialize_child(obj, "bcm2835-spi0", &s->spi[0], 166 TYPE_BCM2835_SPI); 167 168 /* I2C */ 169 object_initialize_child(obj, "bcm2835-i2c0", &s->i2c[0], 170 TYPE_BCM2835_I2C); 171 object_initialize_child(obj, "bcm2835-i2c1", &s->i2c[1], 172 TYPE_BCM2835_I2C); 173 object_initialize_child(obj, "bcm2835-i2c2", &s->i2c[2], 174 TYPE_BCM2835_I2C); 175 176 object_initialize_child(obj, "orgated-i2c-irq", 177 &s->orgated_i2c_irq, TYPE_OR_IRQ); 178 object_property_set_int(OBJECT(&s->orgated_i2c_irq), "num-lines", 179 ORGATED_I2C_IRQ_COUNT, &error_abort); 180 } 181 182 static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp) 183 { 184 MemoryRegion *mphi_mr; 185 BCM2835PeripheralState *s = BCM2835_PERIPHERALS(dev); 186 BCMSocPeripheralBaseState *s_base = BCM_SOC_PERIPHERALS_BASE(dev); 187 int n; 188 189 bcm_soc_peripherals_common_realize(dev, errp); 190 191 /* Extended Mass Media Controller */ 192 sysbus_connect_irq(SYS_BUS_DEVICE(&s_base->sdhci), 0, 193 qdev_get_gpio_in_named(DEVICE(&s_base->ic), BCM2835_IC_GPU_IRQ, 194 INTERRUPT_ARASANSDIO)); 195 196 /* Connect DMA 0-12 to the interrupt controller */ 197 for (n = 0; n <= SEPARATE_DMA_IRQ_MAX; n++) { 198 sysbus_connect_irq(SYS_BUS_DEVICE(&s_base->dma), n, 199 qdev_get_gpio_in_named(DEVICE(&s_base->ic), 200 BCM2835_IC_GPU_IRQ, 201 INTERRUPT_DMA0 + n)); 202 } 203 204 if (!qdev_realize(DEVICE(&s_base->orgated_dma_irq), NULL, errp)) { 205 return; 206 } 207 for (n = 0; n < ORGATED_DMA_IRQ_COUNT; n++) { 208 sysbus_connect_irq(SYS_BUS_DEVICE(&s_base->dma), 209 SEPARATE_DMA_IRQ_MAX + 1 + n, 210 qdev_get_gpio_in(DEVICE(&s_base->orgated_dma_irq), n)); 211 } 212 qdev_connect_gpio_out(DEVICE(&s_base->orgated_dma_irq), 0, 213 qdev_get_gpio_in_named(DEVICE(&s_base->ic), 214 BCM2835_IC_GPU_IRQ, 215 INTERRUPT_DMA0 + SEPARATE_DMA_IRQ_MAX + 1)); 216 217 /* Random Number Generator */ 218 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rng), errp)) { 219 return; 220 } 221 memory_region_add_subregion( 222 &s_base->peri_mr, RNG_OFFSET, 223 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->rng), 0)); 224 225 /* THERMAL */ 226 if (!sysbus_realize(SYS_BUS_DEVICE(&s->thermal), errp)) { 227 return; 228 } 229 memory_region_add_subregion(&s_base->peri_mr, THERMAL_OFFSET, 230 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->thermal), 0)); 231 232 /* Map MPHI to the peripherals memory map */ 233 mphi_mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s_base->mphi), 0); 234 memory_region_add_subregion(&s_base->peri_mr, MPHI_OFFSET, mphi_mr); 235 236 /* GPIO */ 237 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { 238 return; 239 } 240 memory_region_add_subregion( 241 &s_base->peri_mr, GPIO_OFFSET, 242 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gpio), 0)); 243 244 object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->gpio), "sd-bus"); 245 } 246 247 void bcm_soc_peripherals_common_realize(DeviceState *dev, Error **errp) 248 { 249 BCMSocPeripheralBaseState *s = BCM_SOC_PERIPHERALS_BASE(dev); 250 Object *obj; 251 MemoryRegion *ram; 252 Error *err = NULL; 253 uint64_t ram_size, vcram_size, vcram_base; 254 int n; 255 256 obj = object_property_get_link(OBJECT(dev), "ram", &error_abort); 257 258 ram = MEMORY_REGION(obj); 259 ram_size = memory_region_size(ram); 260 261 /* Map peripherals and RAM into the GPU address space. */ 262 memory_region_init_alias(&s->peri_mr_alias, OBJECT(s), 263 "bcm2835-peripherals", &s->peri_mr, 0, 264 memory_region_size(&s->peri_mr)); 265 266 memory_region_add_subregion_overlap(&s->gpu_bus_mr, BCM2835_VC_PERI_BASE, 267 &s->peri_mr_alias, 1); 268 269 /* RAM is aliased four times (different cache configurations) on the GPU */ 270 for (n = 0; n < 4; n++) { 271 memory_region_init_alias(&s->ram_alias[n], OBJECT(s), 272 "bcm2835-gpu-ram-alias[*]", ram, 0, ram_size); 273 memory_region_add_subregion_overlap(&s->gpu_bus_mr, (hwaddr)n << 30, 274 &s->ram_alias[n], 0); 275 } 276 277 /* Interrupt Controller */ 278 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ic), errp)) { 279 return; 280 } 281 282 /* CPRMAN clock manager */ 283 if (!sysbus_realize(SYS_BUS_DEVICE(&s->cprman), errp)) { 284 return; 285 } 286 memory_region_add_subregion(&s->peri_mr, CPRMAN_OFFSET, 287 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cprman), 0)); 288 qdev_connect_clock_in(DEVICE(&s->uart0), "clk", 289 qdev_get_clock_out(DEVICE(&s->cprman), "uart-out")); 290 291 memory_region_add_subregion(&s->peri_mr, ARMCTRL_IC_OFFSET, 292 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->ic), 0)); 293 sysbus_pass_irq(SYS_BUS_DEVICE(s), SYS_BUS_DEVICE(&s->ic)); 294 295 /* Sys Timer */ 296 if (!sysbus_realize(SYS_BUS_DEVICE(&s->systmr), errp)) { 297 return; 298 } 299 memory_region_add_subregion(&s->peri_mr, ST_OFFSET, 300 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->systmr), 0)); 301 sysbus_connect_irq(SYS_BUS_DEVICE(&s->systmr), 0, 302 qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, 303 INTERRUPT_TIMER0)); 304 sysbus_connect_irq(SYS_BUS_DEVICE(&s->systmr), 1, 305 qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, 306 INTERRUPT_TIMER1)); 307 sysbus_connect_irq(SYS_BUS_DEVICE(&s->systmr), 2, 308 qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, 309 INTERRUPT_TIMER2)); 310 sysbus_connect_irq(SYS_BUS_DEVICE(&s->systmr), 3, 311 qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, 312 INTERRUPT_TIMER3)); 313 314 /* UART0 */ 315 qdev_prop_set_chr(DEVICE(&s->uart0), "chardev", serial_hd(0)); 316 if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart0), errp)) { 317 return; 318 } 319 320 memory_region_add_subregion(&s->peri_mr, UART0_OFFSET, 321 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->uart0), 0)); 322 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart0), 0, 323 qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, 324 INTERRUPT_UART0)); 325 326 /* AUX / UART1 */ 327 qdev_prop_set_chr(DEVICE(&s->aux), "chardev", serial_hd(1)); 328 329 if (!sysbus_realize(SYS_BUS_DEVICE(&s->aux), errp)) { 330 return; 331 } 332 333 memory_region_add_subregion(&s->peri_mr, AUX_OFFSET, 334 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->aux), 0)); 335 sysbus_connect_irq(SYS_BUS_DEVICE(&s->aux), 0, 336 qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, 337 INTERRUPT_AUX)); 338 339 /* Mailboxes */ 340 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mboxes), errp)) { 341 return; 342 } 343 344 memory_region_add_subregion(&s->peri_mr, ARMCTRL_0_SBM_OFFSET, 345 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->mboxes), 0)); 346 sysbus_connect_irq(SYS_BUS_DEVICE(&s->mboxes), 0, 347 qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_ARM_IRQ, 348 INTERRUPT_ARM_MAILBOX)); 349 350 /* Framebuffer */ 351 vcram_size = object_property_get_uint(OBJECT(s), "vcram-size", &err); 352 if (err) { 353 error_propagate(errp, err); 354 return; 355 } 356 357 vcram_base = object_property_get_uint(OBJECT(s), "vcram-base", &err); 358 if (err) { 359 error_propagate(errp, err); 360 return; 361 } 362 363 if (vcram_base == 0) { 364 vcram_base = ram_size - vcram_size; 365 } 366 vcram_base = MIN(vcram_base, UPPER_RAM_BASE - vcram_size); 367 368 if (!object_property_set_uint(OBJECT(&s->fb), "vcram-base", vcram_base, 369 errp)) { 370 return; 371 } 372 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fb), errp)) { 373 return; 374 } 375 376 memory_region_add_subregion(&s->mbox_mr, MBOX_CHAN_FB << MBOX_AS_CHAN_SHIFT, 377 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->fb), 0)); 378 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fb), 0, 379 qdev_get_gpio_in(DEVICE(&s->mboxes), MBOX_CHAN_FB)); 380 381 /* OTP */ 382 if (!sysbus_realize(SYS_BUS_DEVICE(&s->otp), errp)) { 383 return; 384 } 385 386 memory_region_add_subregion(&s->peri_mr, OTP_OFFSET, 387 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->otp), 0)); 388 389 /* Property channel */ 390 if (!sysbus_realize(SYS_BUS_DEVICE(&s->property), errp)) { 391 return; 392 } 393 394 memory_region_add_subregion(&s->mbox_mr, 395 MBOX_CHAN_PROPERTY << MBOX_AS_CHAN_SHIFT, 396 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->property), 0)); 397 sysbus_connect_irq(SYS_BUS_DEVICE(&s->property), 0, 398 qdev_get_gpio_in(DEVICE(&s->mboxes), MBOX_CHAN_PROPERTY)); 399 400 /* Extended Mass Media Controller 401 * 402 * Compatible with: 403 * - SD Host Controller Specification Version 3.0 Draft 1.0 404 * - SDIO Specification Version 3.0 405 * - MMC Specification Version 4.4 406 * 407 * For the exact details please refer to the Arasan documentation: 408 * SD3.0_Host_AHB_eMMC4.4_Usersguide_ver5.9_jan11_10.pdf 409 */ 410 object_property_set_uint(OBJECT(&s->sdhci), "sd-spec-version", 3, 411 &error_abort); 412 object_property_set_uint(OBJECT(&s->sdhci), "capareg", 413 BCM2835_SDHC_CAPAREG, &error_abort); 414 object_property_set_bool(OBJECT(&s->sdhci), "pending-insert-quirk", true, 415 &error_abort); 416 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) { 417 return; 418 } 419 420 memory_region_add_subregion(&s->peri_mr, EMMC1_OFFSET, 421 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->sdhci), 0)); 422 423 /* SDHOST */ 424 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhost), errp)) { 425 return; 426 } 427 428 memory_region_add_subregion(&s->peri_mr, MMCI0_OFFSET, 429 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->sdhost), 0)); 430 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhost), 0, 431 qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, 432 INTERRUPT_SDIO)); 433 434 /* DMA Channels */ 435 if (!sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp)) { 436 return; 437 } 438 439 memory_region_add_subregion(&s->peri_mr, DMA_OFFSET, 440 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->dma), 0)); 441 memory_region_add_subregion(&s->peri_mr, DMA15_OFFSET, 442 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->dma), 1)); 443 444 /* Mphi */ 445 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mphi), errp)) { 446 return; 447 } 448 449 sysbus_connect_irq(SYS_BUS_DEVICE(&s->mphi), 0, 450 qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, 451 INTERRUPT_HOSTPORT)); 452 453 /* DWC2 */ 454 if (!sysbus_realize(SYS_BUS_DEVICE(&s->dwc2), errp)) { 455 return; 456 } 457 458 memory_region_add_subregion(&s->peri_mr, USB_OTG_OFFSET, 459 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->dwc2), 0)); 460 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dwc2), 0, 461 qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, 462 INTERRUPT_USB)); 463 464 /* Power Management */ 465 if (!sysbus_realize(SYS_BUS_DEVICE(&s->powermgt), errp)) { 466 return; 467 } 468 469 memory_region_add_subregion(&s->peri_mr, PM_OFFSET, 470 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->powermgt), 0)); 471 472 /* SPI */ 473 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[0]), errp)) { 474 return; 475 } 476 477 memory_region_add_subregion(&s->peri_mr, SPI0_OFFSET, 478 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->spi[0]), 0)); 479 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[0]), 0, 480 qdev_get_gpio_in_named(DEVICE(&s->ic), 481 BCM2835_IC_GPU_IRQ, 482 INTERRUPT_SPI)); 483 484 /* I2C */ 485 for (n = 0; n < 3; n++) { 486 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c[n]), errp)) { 487 return; 488 } 489 } 490 491 memory_region_add_subregion(&s->peri_mr, BSC0_OFFSET, 492 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->i2c[0]), 0)); 493 memory_region_add_subregion(&s->peri_mr, BSC1_OFFSET, 494 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->i2c[1]), 0)); 495 memory_region_add_subregion(&s->peri_mr, BSC2_OFFSET, 496 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->i2c[2]), 0)); 497 498 if (!qdev_realize(DEVICE(&s->orgated_i2c_irq), NULL, errp)) { 499 return; 500 } 501 for (n = 0; n < ORGATED_I2C_IRQ_COUNT; n++) { 502 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[n]), 0, 503 qdev_get_gpio_in(DEVICE(&s->orgated_i2c_irq), n)); 504 } 505 qdev_connect_gpio_out(DEVICE(&s->orgated_i2c_irq), 0, 506 qdev_get_gpio_in_named(DEVICE(&s->ic), 507 BCM2835_IC_GPU_IRQ, 508 INTERRUPT_I2C)); 509 510 create_unimp(s, &s->txp, "bcm2835-txp", TXP_OFFSET, 0x1000); 511 create_unimp(s, &s->armtmr, "bcm2835-sp804", ARMCTRL_TIMER0_1_OFFSET, 0x40); 512 create_unimp(s, &s->i2s, "bcm2835-i2s", I2S_OFFSET, 0x100); 513 create_unimp(s, &s->smi, "bcm2835-smi", SMI_OFFSET, 0x100); 514 create_unimp(s, &s->bscsl, "bcm2835-spis", BSC_SL_OFFSET, 0x100); 515 create_unimp(s, &s->dbus, "bcm2835-dbus", DBUS_OFFSET, 0x8000); 516 create_unimp(s, &s->ave0, "bcm2835-ave0", AVE0_OFFSET, 0x8000); 517 create_unimp(s, &s->v3d, "bcm2835-v3d", V3D_OFFSET, 0x1000); 518 create_unimp(s, &s->sdramc, "bcm2835-sdramc", SDRAMC_OFFSET, 0x100); 519 } 520 521 static void bcm2835_peripherals_class_init(ObjectClass *oc, void *data) 522 { 523 DeviceClass *dc = DEVICE_CLASS(oc); 524 BCMSocPeripheralBaseClass *bc = BCM_SOC_PERIPHERALS_BASE_CLASS(oc); 525 526 bc->peri_size = 0x1000000; 527 dc->realize = bcm2835_peripherals_realize; 528 } 529 530 static const TypeInfo bcm2835_peripherals_types[] = { 531 { 532 .name = TYPE_BCM2835_PERIPHERALS, 533 .parent = TYPE_BCM_SOC_PERIPHERALS_BASE, 534 .instance_size = sizeof(BCM2835PeripheralState), 535 .instance_init = bcm2835_peripherals_init, 536 .class_init = bcm2835_peripherals_class_init, 537 }, { 538 .name = TYPE_BCM_SOC_PERIPHERALS_BASE, 539 .parent = TYPE_SYS_BUS_DEVICE, 540 .instance_size = sizeof(BCMSocPeripheralBaseState), 541 .instance_init = raspi_peripherals_base_init, 542 .class_size = sizeof(BCMSocPeripheralBaseClass), 543 .abstract = true, 544 } 545 }; 546 547 DEFINE_TYPES(bcm2835_peripherals_types) 548