1 /* 2 * ASPEED SoC family 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * Jeremy Kerr <jk@ozlabs.org> 6 * 7 * Copyright 2016 IBM Corp. 8 * 9 * This code is licensed under the GPL version 2 or later. See 10 * the COPYING file in the top-level directory. 11 */ 12 13 #include "qemu/osdep.h" 14 #include "qapi/error.h" 15 #include "hw/misc/unimp.h" 16 #include "hw/arm/aspeed_soc.h" 17 #include "hw/char/serial.h" 18 19 20 qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev) 21 { 22 return ASPEED_SOC_GET_CLASS(s)->get_irq(s, dev); 23 } 24 25 bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp) 26 { 27 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 28 SerialMM *smm; 29 30 for (int i = 0, uart = ASPEED_DEV_UART1; i < sc->uarts_num; i++, uart++) { 31 smm = &s->uart[i]; 32 33 /* Chardev property is set by the machine. */ 34 qdev_prop_set_uint8(DEVICE(smm), "regshift", 2); 35 qdev_prop_set_uint32(DEVICE(smm), "baudbase", 38400); 36 qdev_set_legacy_instance_id(DEVICE(smm), sc->memmap[uart], 2); 37 qdev_prop_set_uint8(DEVICE(smm), "endianness", DEVICE_LITTLE_ENDIAN); 38 if (!sysbus_realize(SYS_BUS_DEVICE(smm), errp)) { 39 return false; 40 } 41 42 sysbus_connect_irq(SYS_BUS_DEVICE(smm), 0, aspeed_soc_get_irq(s, uart)); 43 aspeed_mmio_map(s, SYS_BUS_DEVICE(smm), 0, sc->memmap[uart]); 44 } 45 46 return true; 47 } 48 49 void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr) 50 { 51 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 52 int i = dev - ASPEED_DEV_UART1; 53 54 g_assert(0 <= i && i < ARRAY_SIZE(s->uart) && i < sc->uarts_num); 55 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", chr); 56 } 57 58 /* 59 * SDMC should be realized first to get correct RAM size and max size 60 * values 61 */ 62 bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp) 63 { 64 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 65 ram_addr_t ram_size, max_ram_size; 66 67 ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size", 68 &error_abort); 69 max_ram_size = object_property_get_uint(OBJECT(&s->sdmc), "max-ram-size", 70 &error_abort); 71 72 memory_region_init(&s->dram_container, OBJECT(s), "ram-container", 73 max_ram_size); 74 memory_region_add_subregion(&s->dram_container, 0, s->dram_mr); 75 76 /* 77 * Add a memory region beyond the RAM region to let firmwares scan 78 * the address space with load/store and guess how much RAM the 79 * SoC has. 80 */ 81 if (ram_size < max_ram_size) { 82 DeviceState *dev = qdev_new(TYPE_UNIMPLEMENTED_DEVICE); 83 84 qdev_prop_set_string(dev, "name", "ram-empty"); 85 qdev_prop_set_uint64(dev, "size", max_ram_size - ram_size); 86 if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp)) { 87 return false; 88 } 89 90 memory_region_add_subregion_overlap(&s->dram_container, ram_size, 91 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0), -1000); 92 } 93 94 memory_region_add_subregion(s->memory, 95 sc->memmap[ASPEED_DEV_SDRAM], &s->dram_container); 96 return true; 97 } 98 99 void aspeed_mmio_map(AspeedSoCState *s, SysBusDevice *dev, int n, hwaddr addr) 100 { 101 memory_region_add_subregion(s->memory, addr, 102 sysbus_mmio_get_region(dev, n)); 103 } 104 105 void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev, 106 const char *name, hwaddr addr, uint64_t size) 107 { 108 qdev_prop_set_string(DEVICE(dev), "name", name); 109 qdev_prop_set_uint64(DEVICE(dev), "size", size); 110 sysbus_realize(dev, &error_abort); 111 112 memory_region_add_subregion_overlap(s->memory, addr, 113 sysbus_mmio_get_region(dev, 0), -1000); 114 } 115