1 /* 2 * ASPEED SoC 2600 family 3 * 4 * Copyright (c) 2016-2019, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See 7 * the COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qapi/error.h" 12 #include "hw/misc/unimp.h" 13 #include "hw/arm/aspeed_soc.h" 14 #include "hw/char/serial.h" 15 #include "qemu/module.h" 16 #include "qemu/error-report.h" 17 #include "hw/i2c/aspeed_i2c.h" 18 #include "net/net.h" 19 #include "sysemu/sysemu.h" 20 21 #define ASPEED_SOC_IOMEM_SIZE 0x00200000 22 23 static const hwaddr aspeed_soc_ast2600_memmap[] = { 24 [ASPEED_DEV_SRAM] = 0x10000000, 25 /* 0x16000000 0x17FFFFFF : AHB BUS do LPC Bus bridge */ 26 [ASPEED_DEV_IOMEM] = 0x1E600000, 27 [ASPEED_DEV_PWM] = 0x1E610000, 28 [ASPEED_DEV_FMC] = 0x1E620000, 29 [ASPEED_DEV_SPI1] = 0x1E630000, 30 [ASPEED_DEV_SPI2] = 0x1E641000, 31 [ASPEED_DEV_EHCI1] = 0x1E6A1000, 32 [ASPEED_DEV_EHCI2] = 0x1E6A3000, 33 [ASPEED_DEV_MII1] = 0x1E650000, 34 [ASPEED_DEV_MII2] = 0x1E650008, 35 [ASPEED_DEV_MII3] = 0x1E650010, 36 [ASPEED_DEV_MII4] = 0x1E650018, 37 [ASPEED_DEV_ETH1] = 0x1E660000, 38 [ASPEED_DEV_ETH3] = 0x1E670000, 39 [ASPEED_DEV_ETH2] = 0x1E680000, 40 [ASPEED_DEV_ETH4] = 0x1E690000, 41 [ASPEED_DEV_VIC] = 0x1E6C0000, 42 [ASPEED_DEV_SDMC] = 0x1E6E0000, 43 [ASPEED_DEV_SCU] = 0x1E6E2000, 44 [ASPEED_DEV_XDMA] = 0x1E6E7000, 45 [ASPEED_DEV_ADC] = 0x1E6E9000, 46 [ASPEED_DEV_VIDEO] = 0x1E700000, 47 [ASPEED_DEV_SDHCI] = 0x1E740000, 48 [ASPEED_DEV_EMMC] = 0x1E750000, 49 [ASPEED_DEV_GPIO] = 0x1E780000, 50 [ASPEED_DEV_GPIO_1_8V] = 0x1E780800, 51 [ASPEED_DEV_RTC] = 0x1E781000, 52 [ASPEED_DEV_TIMER1] = 0x1E782000, 53 [ASPEED_DEV_WDT] = 0x1E785000, 54 [ASPEED_DEV_LPC] = 0x1E789000, 55 [ASPEED_DEV_IBT] = 0x1E789140, 56 [ASPEED_DEV_I2C] = 0x1E78A000, 57 [ASPEED_DEV_UART1] = 0x1E783000, 58 [ASPEED_DEV_UART5] = 0x1E784000, 59 [ASPEED_DEV_VUART] = 0x1E787000, 60 [ASPEED_DEV_SDRAM] = 0x80000000, 61 }; 62 63 #define ASPEED_A7MPCORE_ADDR 0x40460000 64 65 #define AST2600_MAX_IRQ 197 66 67 /* Shared Peripheral Interrupt values below are offset by -32 from datasheet */ 68 static const int aspeed_soc_ast2600_irqmap[] = { 69 [ASPEED_DEV_UART1] = 47, 70 [ASPEED_DEV_UART2] = 48, 71 [ASPEED_DEV_UART3] = 49, 72 [ASPEED_DEV_UART4] = 50, 73 [ASPEED_DEV_UART5] = 8, 74 [ASPEED_DEV_VUART] = 8, 75 [ASPEED_DEV_FMC] = 39, 76 [ASPEED_DEV_SDMC] = 0, 77 [ASPEED_DEV_SCU] = 12, 78 [ASPEED_DEV_ADC] = 78, 79 [ASPEED_DEV_XDMA] = 6, 80 [ASPEED_DEV_SDHCI] = 43, 81 [ASPEED_DEV_EHCI1] = 5, 82 [ASPEED_DEV_EHCI2] = 9, 83 [ASPEED_DEV_EMMC] = 15, 84 [ASPEED_DEV_GPIO] = 40, 85 [ASPEED_DEV_GPIO_1_8V] = 11, 86 [ASPEED_DEV_RTC] = 13, 87 [ASPEED_DEV_TIMER1] = 16, 88 [ASPEED_DEV_TIMER2] = 17, 89 [ASPEED_DEV_TIMER3] = 18, 90 [ASPEED_DEV_TIMER4] = 19, 91 [ASPEED_DEV_TIMER5] = 20, 92 [ASPEED_DEV_TIMER6] = 21, 93 [ASPEED_DEV_TIMER7] = 22, 94 [ASPEED_DEV_TIMER8] = 23, 95 [ASPEED_DEV_WDT] = 24, 96 [ASPEED_DEV_PWM] = 44, 97 [ASPEED_DEV_LPC] = 35, 98 [ASPEED_DEV_IBT] = 143, 99 [ASPEED_DEV_I2C] = 110, /* 110 -> 125 */ 100 [ASPEED_DEV_ETH1] = 2, 101 [ASPEED_DEV_ETH2] = 3, 102 [ASPEED_DEV_ETH3] = 32, 103 [ASPEED_DEV_ETH4] = 33, 104 [ASPEED_DEV_KCS] = 138, /* 138 -> 142 */ 105 }; 106 107 static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl) 108 { 109 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 110 111 return qdev_get_gpio_in(DEVICE(&s->a7mpcore), sc->irqmap[ctrl]); 112 } 113 114 static void aspeed_soc_ast2600_init(Object *obj) 115 { 116 AspeedSoCState *s = ASPEED_SOC(obj); 117 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 118 int i; 119 char socname[8]; 120 char typename[64]; 121 122 if (sscanf(sc->name, "%7s", socname) != 1) { 123 g_assert_not_reached(); 124 } 125 126 for (i = 0; i < sc->num_cpus; i++) { 127 object_initialize_child(obj, "cpu[*]", &s->cpu[i], sc->cpu_type); 128 } 129 130 snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname); 131 object_initialize_child(obj, "scu", &s->scu, typename); 132 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", 133 sc->silicon_rev); 134 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), 135 "hw-strap1"); 136 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), 137 "hw-strap2"); 138 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), 139 "hw-prot-key"); 140 141 object_initialize_child(obj, "a7mpcore", &s->a7mpcore, 142 TYPE_A15MPCORE_PRIV); 143 144 object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC); 145 146 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); 147 object_initialize_child(obj, "timerctrl", &s->timerctrl, typename); 148 149 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); 150 object_initialize_child(obj, "i2c", &s->i2c, typename); 151 152 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); 153 object_initialize_child(obj, "fmc", &s->fmc, typename); 154 object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs"); 155 156 for (i = 0; i < sc->spis_num; i++) { 157 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname); 158 object_initialize_child(obj, "spi[*]", &s->spi[i], typename); 159 } 160 161 for (i = 0; i < sc->ehcis_num; i++) { 162 object_initialize_child(obj, "ehci[*]", &s->ehci[i], 163 TYPE_PLATFORM_EHCI); 164 } 165 166 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname); 167 object_initialize_child(obj, "sdmc", &s->sdmc, typename); 168 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), 169 "ram-size"); 170 object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc), 171 "max-ram-size"); 172 173 for (i = 0; i < sc->wdts_num; i++) { 174 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); 175 object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename); 176 } 177 178 for (i = 0; i < sc->macs_num; i++) { 179 object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i], 180 TYPE_FTGMAC100); 181 182 object_initialize_child(obj, "mii[*]", &s->mii[i], TYPE_ASPEED_MII); 183 } 184 185 object_initialize_child(obj, "xdma", &s->xdma, TYPE_ASPEED_XDMA); 186 187 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); 188 object_initialize_child(obj, "gpio", &s->gpio, typename); 189 190 snprintf(typename, sizeof(typename), "aspeed.gpio-%s-1_8v", socname); 191 object_initialize_child(obj, "gpio_1_8v", &s->gpio_1_8v, typename); 192 193 object_initialize_child(obj, "sd-controller", &s->sdhci, 194 TYPE_ASPEED_SDHCI); 195 196 object_property_set_int(OBJECT(&s->sdhci), "num-slots", 2, &error_abort); 197 198 /* Init sd card slot class here so that they're under the correct parent */ 199 for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { 200 object_initialize_child(obj, "sd-controller.sdhci[*]", 201 &s->sdhci.slots[i], TYPE_SYSBUS_SDHCI); 202 } 203 204 object_initialize_child(obj, "emmc-controller", &s->emmc, 205 TYPE_ASPEED_SDHCI); 206 207 object_property_set_int(OBJECT(&s->emmc), "num-slots", 1, &error_abort); 208 209 object_initialize_child(obj, "emmc-controller.sdhci", &s->emmc.slots[0], 210 TYPE_SYSBUS_SDHCI); 211 212 object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC); 213 } 214 215 /* 216 * ASPEED ast2600 has 0xf as cluster ID 217 * 218 * https://developer.arm.com/documentation/ddi0388/e/the-system-control-coprocessors/summary-of-system-control-coprocessor-registers/multiprocessor-affinity-register 219 */ 220 static uint64_t aspeed_calc_affinity(int cpu) 221 { 222 return (0xf << ARM_AFF1_SHIFT) | cpu; 223 } 224 225 static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) 226 { 227 int i; 228 AspeedSoCState *s = ASPEED_SOC(dev); 229 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 230 Error *err = NULL; 231 qemu_irq irq; 232 233 /* IO space */ 234 create_unimplemented_device("aspeed_soc.io", sc->memmap[ASPEED_DEV_IOMEM], 235 ASPEED_SOC_IOMEM_SIZE); 236 237 /* Video engine stub */ 238 create_unimplemented_device("aspeed.video", sc->memmap[ASPEED_DEV_VIDEO], 239 0x1000); 240 241 /* CPU */ 242 for (i = 0; i < sc->num_cpus; i++) { 243 if (sc->num_cpus > 1) { 244 object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar", 245 ASPEED_A7MPCORE_ADDR, &error_abort); 246 } 247 object_property_set_int(OBJECT(&s->cpu[i]), "mp-affinity", 248 aspeed_calc_affinity(i), &error_abort); 249 250 object_property_set_int(OBJECT(&s->cpu[i]), "cntfrq", 1125000000, 251 &error_abort); 252 253 if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) { 254 return; 255 } 256 } 257 258 /* A7MPCORE */ 259 object_property_set_int(OBJECT(&s->a7mpcore), "num-cpu", sc->num_cpus, 260 &error_abort); 261 object_property_set_int(OBJECT(&s->a7mpcore), "num-irq", 262 ROUND_UP(AST2600_MAX_IRQ + GIC_INTERNAL, 32), 263 &error_abort); 264 265 sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort); 266 sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, ASPEED_A7MPCORE_ADDR); 267 268 for (i = 0; i < sc->num_cpus; i++) { 269 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore); 270 DeviceState *d = DEVICE(qemu_get_cpu(i)); 271 272 irq = qdev_get_gpio_in(d, ARM_CPU_IRQ); 273 sysbus_connect_irq(sbd, i, irq); 274 irq = qdev_get_gpio_in(d, ARM_CPU_FIQ); 275 sysbus_connect_irq(sbd, i + sc->num_cpus, irq); 276 irq = qdev_get_gpio_in(d, ARM_CPU_VIRQ); 277 sysbus_connect_irq(sbd, i + 2 * sc->num_cpus, irq); 278 irq = qdev_get_gpio_in(d, ARM_CPU_VFIQ); 279 sysbus_connect_irq(sbd, i + 3 * sc->num_cpus, irq); 280 } 281 282 /* SRAM */ 283 memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram", 284 sc->sram_size, &err); 285 if (err) { 286 error_propagate(errp, err); 287 return; 288 } 289 memory_region_add_subregion(get_system_memory(), 290 sc->memmap[ASPEED_DEV_SRAM], &s->sram); 291 292 /* SCU */ 293 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { 294 return; 295 } 296 sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]); 297 298 /* RTC */ 299 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) { 300 return; 301 } 302 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]); 303 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, 304 aspeed_soc_get_irq(s, ASPEED_DEV_RTC)); 305 306 /* Timer */ 307 object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), 308 &error_abort); 309 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) { 310 return; 311 } 312 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0, 313 sc->memmap[ASPEED_DEV_TIMER1]); 314 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { 315 qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i); 316 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); 317 } 318 319 /* UART - attach an 8250 to the IO space as our UART5 */ 320 serial_mm_init(get_system_memory(), sc->memmap[ASPEED_DEV_UART5], 2, 321 aspeed_soc_get_irq(s, ASPEED_DEV_UART5), 322 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN); 323 324 /* I2C */ 325 object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr), 326 &error_abort); 327 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) { 328 return; 329 } 330 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]); 331 for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) { 332 qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), 333 sc->irqmap[ASPEED_DEV_I2C] + i); 334 /* 335 * The AST2600 SoC has one IRQ per I2C bus. Skip the common 336 * IRQ (AST2400 and AST2500) and connect all bussses. 337 */ 338 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), i + 1, irq); 339 } 340 341 /* FMC, The number of CS is set at the board level */ 342 object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr), 343 &error_abort); 344 if (!object_property_set_int(OBJECT(&s->fmc), "sdram-base", 345 sc->memmap[ASPEED_DEV_SDRAM], errp)) { 346 return; 347 } 348 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) { 349 return; 350 } 351 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]); 352 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1, 353 s->fmc.ctrl->flash_window_base); 354 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, 355 aspeed_soc_get_irq(s, ASPEED_DEV_FMC)); 356 357 /* SPI */ 358 for (i = 0; i < sc->spis_num; i++) { 359 object_property_set_link(OBJECT(&s->spi[i]), "dram", 360 OBJECT(s->dram_mr), &error_abort); 361 object_property_set_int(OBJECT(&s->spi[i]), "num-cs", 1, &error_abort); 362 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { 363 return; 364 } 365 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, 366 sc->memmap[ASPEED_DEV_SPI1 + i]); 367 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1, 368 s->spi[i].ctrl->flash_window_base); 369 } 370 371 /* EHCI */ 372 for (i = 0; i < sc->ehcis_num; i++) { 373 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) { 374 return; 375 } 376 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0, 377 sc->memmap[ASPEED_DEV_EHCI1 + i]); 378 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, 379 aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i)); 380 } 381 382 /* SDMC - SDRAM Memory Controller */ 383 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) { 384 return; 385 } 386 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->memmap[ASPEED_DEV_SDMC]); 387 388 /* Watch dog */ 389 for (i = 0; i < sc->wdts_num; i++) { 390 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); 391 392 object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu), 393 &error_abort); 394 if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { 395 return; 396 } 397 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, 398 sc->memmap[ASPEED_DEV_WDT] + i * awc->offset); 399 } 400 401 /* Net */ 402 for (i = 0; i < sc->macs_num; i++) { 403 object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true, 404 &error_abort); 405 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) { 406 return; 407 } 408 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 409 sc->memmap[ASPEED_DEV_ETH1 + i]); 410 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 411 aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i)); 412 413 object_property_set_link(OBJECT(&s->mii[i]), "nic", 414 OBJECT(&s->ftgmac100[i]), &error_abort); 415 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mii[i]), errp)) { 416 return; 417 } 418 419 sysbus_mmio_map(SYS_BUS_DEVICE(&s->mii[i]), 0, 420 sc->memmap[ASPEED_DEV_MII1 + i]); 421 } 422 423 /* XDMA */ 424 if (!sysbus_realize(SYS_BUS_DEVICE(&s->xdma), errp)) { 425 return; 426 } 427 sysbus_mmio_map(SYS_BUS_DEVICE(&s->xdma), 0, 428 sc->memmap[ASPEED_DEV_XDMA]); 429 sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0, 430 aspeed_soc_get_irq(s, ASPEED_DEV_XDMA)); 431 432 /* GPIO */ 433 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { 434 return; 435 } 436 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_DEV_GPIO]); 437 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, 438 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO)); 439 440 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio_1_8v), errp)) { 441 return; 442 } 443 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio_1_8v), 0, 444 sc->memmap[ASPEED_DEV_GPIO_1_8V]); 445 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio_1_8v), 0, 446 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO_1_8V)); 447 448 /* SDHCI */ 449 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) { 450 return; 451 } 452 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0, 453 sc->memmap[ASPEED_DEV_SDHCI]); 454 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, 455 aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI)); 456 457 /* eMMC */ 458 if (!sysbus_realize(SYS_BUS_DEVICE(&s->emmc), errp)) { 459 return; 460 } 461 sysbus_mmio_map(SYS_BUS_DEVICE(&s->emmc), 0, sc->memmap[ASPEED_DEV_EMMC]); 462 sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0, 463 aspeed_soc_get_irq(s, ASPEED_DEV_EMMC)); 464 465 /* LPC */ 466 if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) { 467 return; 468 } 469 sysbus_mmio_map(SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]); 470 471 /* Connect the LPC IRQ to the GIC. It is otherwise unused. */ 472 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0, 473 aspeed_soc_get_irq(s, ASPEED_DEV_LPC)); 474 475 /* 476 * On the AST2600 LPC subdevice IRQs are connected straight to the GIC. 477 * 478 * LPC subdevice IRQ sources are offset from 1 because the LPC model caters 479 * to the AST2400 and AST2500. SoCs before the AST2600 have one LPC IRQ 480 * shared across the subdevices, and the shared IRQ output to the VIC is at 481 * offset 0. 482 */ 483 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1, 484 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 485 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1)); 486 487 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2, 488 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 489 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2)); 490 491 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3, 492 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 493 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3)); 494 495 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4, 496 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 497 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4)); 498 } 499 500 static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) 501 { 502 DeviceClass *dc = DEVICE_CLASS(oc); 503 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); 504 505 dc->realize = aspeed_soc_ast2600_realize; 506 507 sc->name = "ast2600-a1"; 508 sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7"); 509 sc->silicon_rev = AST2600_A1_SILICON_REV; 510 sc->sram_size = 0x16400; 511 sc->spis_num = 2; 512 sc->ehcis_num = 2; 513 sc->wdts_num = 4; 514 sc->macs_num = 4; 515 sc->irqmap = aspeed_soc_ast2600_irqmap; 516 sc->memmap = aspeed_soc_ast2600_memmap; 517 sc->num_cpus = 2; 518 } 519 520 static const TypeInfo aspeed_soc_ast2600_type_info = { 521 .name = "ast2600-a1", 522 .parent = TYPE_ASPEED_SOC, 523 .instance_size = sizeof(AspeedSoCState), 524 .instance_init = aspeed_soc_ast2600_init, 525 .class_init = aspeed_soc_ast2600_class_init, 526 .class_size = sizeof(AspeedSoCClass), 527 }; 528 529 static void aspeed_soc_register_types(void) 530 { 531 type_register_static(&aspeed_soc_ast2600_type_info); 532 }; 533 534 type_init(aspeed_soc_register_types) 535