1 /* 2 * ASPEED SoC 2600 family 3 * 4 * Copyright (c) 2016-2019, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See 7 * the COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qapi/error.h" 12 #include "cpu.h" 13 #include "exec/address-spaces.h" 14 #include "hw/misc/unimp.h" 15 #include "hw/arm/aspeed_soc.h" 16 #include "hw/char/serial.h" 17 #include "qemu/log.h" 18 #include "qemu/module.h" 19 #include "qemu/error-report.h" 20 #include "hw/i2c/aspeed_i2c.h" 21 #include "net/net.h" 22 #include "sysemu/sysemu.h" 23 24 #define ASPEED_SOC_IOMEM_SIZE 0x00200000 25 26 static const hwaddr aspeed_soc_ast2600_memmap[] = { 27 [ASPEED_SRAM] = 0x10000000, 28 /* 0x16000000 0x17FFFFFF : AHB BUS do LPC Bus bridge */ 29 [ASPEED_IOMEM] = 0x1E600000, 30 [ASPEED_PWM] = 0x1E610000, 31 [ASPEED_FMC] = 0x1E620000, 32 [ASPEED_SPI1] = 0x1E630000, 33 [ASPEED_SPI2] = 0x1E641000, 34 [ASPEED_EHCI1] = 0x1E6A1000, 35 [ASPEED_EHCI2] = 0x1E6A3000, 36 [ASPEED_MII1] = 0x1E650000, 37 [ASPEED_MII2] = 0x1E650008, 38 [ASPEED_MII3] = 0x1E650010, 39 [ASPEED_MII4] = 0x1E650018, 40 [ASPEED_ETH1] = 0x1E660000, 41 [ASPEED_ETH3] = 0x1E670000, 42 [ASPEED_ETH2] = 0x1E680000, 43 [ASPEED_ETH4] = 0x1E690000, 44 [ASPEED_VIC] = 0x1E6C0000, 45 [ASPEED_SDMC] = 0x1E6E0000, 46 [ASPEED_SCU] = 0x1E6E2000, 47 [ASPEED_XDMA] = 0x1E6E7000, 48 [ASPEED_ADC] = 0x1E6E9000, 49 [ASPEED_VIDEO] = 0x1E700000, 50 [ASPEED_SDHCI] = 0x1E740000, 51 [ASPEED_EMMC] = 0x1E750000, 52 [ASPEED_GPIO] = 0x1E780000, 53 [ASPEED_GPIO_1_8V] = 0x1E780800, 54 [ASPEED_RTC] = 0x1E781000, 55 [ASPEED_TIMER1] = 0x1E782000, 56 [ASPEED_WDT] = 0x1E785000, 57 [ASPEED_LPC] = 0x1E789000, 58 [ASPEED_IBT] = 0x1E789140, 59 [ASPEED_I2C] = 0x1E78A000, 60 [ASPEED_UART1] = 0x1E783000, 61 [ASPEED_UART5] = 0x1E784000, 62 [ASPEED_VUART] = 0x1E787000, 63 [ASPEED_SDRAM] = 0x80000000, 64 }; 65 66 #define ASPEED_A7MPCORE_ADDR 0x40460000 67 68 #define ASPEED_SOC_AST2600_MAX_IRQ 128 69 70 /* Shared Peripheral Interrupt values below are offset by -32 from datasheet */ 71 static const int aspeed_soc_ast2600_irqmap[] = { 72 [ASPEED_UART1] = 47, 73 [ASPEED_UART2] = 48, 74 [ASPEED_UART3] = 49, 75 [ASPEED_UART4] = 50, 76 [ASPEED_UART5] = 8, 77 [ASPEED_VUART] = 8, 78 [ASPEED_FMC] = 39, 79 [ASPEED_SDMC] = 0, 80 [ASPEED_SCU] = 12, 81 [ASPEED_ADC] = 78, 82 [ASPEED_XDMA] = 6, 83 [ASPEED_SDHCI] = 43, 84 [ASPEED_EHCI1] = 5, 85 [ASPEED_EHCI2] = 9, 86 [ASPEED_EMMC] = 15, 87 [ASPEED_GPIO] = 40, 88 [ASPEED_GPIO_1_8V] = 11, 89 [ASPEED_RTC] = 13, 90 [ASPEED_TIMER1] = 16, 91 [ASPEED_TIMER2] = 17, 92 [ASPEED_TIMER3] = 18, 93 [ASPEED_TIMER4] = 19, 94 [ASPEED_TIMER5] = 20, 95 [ASPEED_TIMER6] = 21, 96 [ASPEED_TIMER7] = 22, 97 [ASPEED_TIMER8] = 23, 98 [ASPEED_WDT] = 24, 99 [ASPEED_PWM] = 44, 100 [ASPEED_LPC] = 35, 101 [ASPEED_IBT] = 35, /* LPC */ 102 [ASPEED_I2C] = 110, /* 110 -> 125 */ 103 [ASPEED_ETH1] = 2, 104 [ASPEED_ETH2] = 3, 105 [ASPEED_ETH3] = 32, 106 [ASPEED_ETH4] = 33, 107 108 }; 109 110 static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl) 111 { 112 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 113 114 return qdev_get_gpio_in(DEVICE(&s->a7mpcore), sc->irqmap[ctrl]); 115 } 116 117 static void aspeed_soc_ast2600_init(Object *obj) 118 { 119 AspeedSoCState *s = ASPEED_SOC(obj); 120 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 121 int i; 122 char socname[8]; 123 char typename[64]; 124 125 if (sscanf(sc->name, "%7s", socname) != 1) { 126 g_assert_not_reached(); 127 } 128 129 for (i = 0; i < sc->num_cpus; i++) { 130 object_initialize_child(obj, "cpu[*]", &s->cpu[i], sc->cpu_type); 131 } 132 133 snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname); 134 object_initialize_child(obj, "scu", &s->scu, typename); 135 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", 136 sc->silicon_rev); 137 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), 138 "hw-strap1"); 139 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), 140 "hw-strap2"); 141 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), 142 "hw-prot-key"); 143 144 object_initialize_child(obj, "a7mpcore", &s->a7mpcore, 145 TYPE_A15MPCORE_PRIV); 146 147 object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC); 148 149 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); 150 object_initialize_child(obj, "timerctrl", &s->timerctrl, typename); 151 152 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); 153 object_initialize_child(obj, "i2c", &s->i2c, typename); 154 155 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); 156 object_initialize_child(obj, "fmc", &s->fmc, typename); 157 object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs"); 158 159 for (i = 0; i < sc->spis_num; i++) { 160 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname); 161 object_initialize_child(obj, "spi[*]", &s->spi[i], typename); 162 } 163 164 for (i = 0; i < sc->ehcis_num; i++) { 165 object_initialize_child(obj, "ehci[*]", &s->ehci[i], 166 TYPE_PLATFORM_EHCI); 167 } 168 169 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname); 170 object_initialize_child(obj, "sdmc", &s->sdmc, typename); 171 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), 172 "ram-size"); 173 object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc), 174 "max-ram-size"); 175 176 for (i = 0; i < sc->wdts_num; i++) { 177 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); 178 object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename); 179 } 180 181 for (i = 0; i < sc->macs_num; i++) { 182 object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i], 183 TYPE_FTGMAC100); 184 185 object_initialize_child(obj, "mii[*]", &s->mii[i], TYPE_ASPEED_MII); 186 } 187 188 object_initialize_child(obj, "xdma", &s->xdma, TYPE_ASPEED_XDMA); 189 190 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); 191 object_initialize_child(obj, "gpio", &s->gpio, typename); 192 193 snprintf(typename, sizeof(typename), "aspeed.gpio-%s-1_8v", socname); 194 object_initialize_child(obj, "gpio_1_8v", &s->gpio_1_8v, typename); 195 196 object_initialize_child(obj, "sd-controller", &s->sdhci, 197 TYPE_ASPEED_SDHCI); 198 199 object_property_set_int(OBJECT(&s->sdhci), 2, "num-slots", &error_abort); 200 201 /* Init sd card slot class here so that they're under the correct parent */ 202 for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { 203 sysbus_init_child_obj(obj, "sd-controller.sdhci[*]", 204 &s->sdhci.slots[i], 205 sizeof(s->sdhci.slots[i]), TYPE_SYSBUS_SDHCI); 206 } 207 208 object_initialize_child(obj, "emmc-controller", &s->emmc, 209 TYPE_ASPEED_SDHCI); 210 211 object_property_set_int(OBJECT(&s->emmc), 1, "num-slots", &error_abort); 212 213 sysbus_init_child_obj(obj, "emmc-controller.sdhci", 214 &s->emmc.slots[0], sizeof(s->emmc.slots[0]), 215 TYPE_SYSBUS_SDHCI); 216 } 217 218 /* 219 * ASPEED ast2600 has 0xf as cluster ID 220 * 221 * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0388e/CIHEBGFG.html 222 */ 223 static uint64_t aspeed_calc_affinity(int cpu) 224 { 225 return (0xf << ARM_AFF1_SHIFT) | cpu; 226 } 227 228 static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) 229 { 230 int i; 231 AspeedSoCState *s = ASPEED_SOC(dev); 232 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 233 Error *err = NULL, *local_err = NULL; 234 qemu_irq irq; 235 236 /* IO space */ 237 create_unimplemented_device("aspeed_soc.io", sc->memmap[ASPEED_IOMEM], 238 ASPEED_SOC_IOMEM_SIZE); 239 240 /* Video engine stub */ 241 create_unimplemented_device("aspeed.video", sc->memmap[ASPEED_VIDEO], 242 0x1000); 243 244 /* CPU */ 245 for (i = 0; i < sc->num_cpus; i++) { 246 object_property_set_int(OBJECT(&s->cpu[i]), QEMU_PSCI_CONDUIT_SMC, 247 "psci-conduit", &error_abort); 248 if (sc->num_cpus > 1) { 249 object_property_set_int(OBJECT(&s->cpu[i]), 250 ASPEED_A7MPCORE_ADDR, 251 "reset-cbar", &error_abort); 252 } 253 object_property_set_int(OBJECT(&s->cpu[i]), aspeed_calc_affinity(i), 254 "mp-affinity", &error_abort); 255 256 object_property_set_int(OBJECT(&s->cpu[i]), 1125000000, "cntfrq", 257 &error_abort); 258 259 /* 260 * TODO: the secondary CPUs are started and a boot helper 261 * is needed when using -kernel 262 */ 263 264 object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err); 265 if (err) { 266 error_propagate(errp, err); 267 return; 268 } 269 } 270 271 /* A7MPCORE */ 272 object_property_set_int(OBJECT(&s->a7mpcore), sc->num_cpus, "num-cpu", 273 &error_abort); 274 object_property_set_int(OBJECT(&s->a7mpcore), 275 ASPEED_SOC_AST2600_MAX_IRQ + GIC_INTERNAL, 276 "num-irq", &error_abort); 277 278 sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort); 279 sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, ASPEED_A7MPCORE_ADDR); 280 281 for (i = 0; i < sc->num_cpus; i++) { 282 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore); 283 DeviceState *d = DEVICE(qemu_get_cpu(i)); 284 285 irq = qdev_get_gpio_in(d, ARM_CPU_IRQ); 286 sysbus_connect_irq(sbd, i, irq); 287 irq = qdev_get_gpio_in(d, ARM_CPU_FIQ); 288 sysbus_connect_irq(sbd, i + sc->num_cpus, irq); 289 irq = qdev_get_gpio_in(d, ARM_CPU_VIRQ); 290 sysbus_connect_irq(sbd, i + 2 * sc->num_cpus, irq); 291 irq = qdev_get_gpio_in(d, ARM_CPU_VFIQ); 292 sysbus_connect_irq(sbd, i + 3 * sc->num_cpus, irq); 293 } 294 295 /* SRAM */ 296 memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram", 297 sc->sram_size, &err); 298 if (err) { 299 error_propagate(errp, err); 300 return; 301 } 302 memory_region_add_subregion(get_system_memory(), 303 sc->memmap[ASPEED_SRAM], &s->sram); 304 305 /* SCU */ 306 sysbus_realize(SYS_BUS_DEVICE(&s->scu), &err); 307 if (err) { 308 error_propagate(errp, err); 309 return; 310 } 311 sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_SCU]); 312 313 /* RTC */ 314 sysbus_realize(SYS_BUS_DEVICE(&s->rtc), &err); 315 if (err) { 316 error_propagate(errp, err); 317 return; 318 } 319 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_RTC]); 320 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, 321 aspeed_soc_get_irq(s, ASPEED_RTC)); 322 323 /* Timer */ 324 object_property_set_link(OBJECT(&s->timerctrl), 325 OBJECT(&s->scu), "scu", &error_abort); 326 sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), &err); 327 if (err) { 328 error_propagate(errp, err); 329 return; 330 } 331 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0, 332 sc->memmap[ASPEED_TIMER1]); 333 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { 334 qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_TIMER1 + i); 335 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); 336 } 337 338 /* UART - attach an 8250 to the IO space as our UART5 */ 339 if (serial_hd(0)) { 340 qemu_irq uart5 = aspeed_soc_get_irq(s, ASPEED_UART5); 341 serial_mm_init(get_system_memory(), sc->memmap[ASPEED_UART5], 2, 342 uart5, 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN); 343 } 344 345 /* I2C */ 346 object_property_set_link(OBJECT(&s->i2c), OBJECT(s->dram_mr), "dram", &err); 347 if (err) { 348 error_propagate(errp, err); 349 return; 350 } 351 sysbus_realize(SYS_BUS_DEVICE(&s->i2c), &err); 352 if (err) { 353 error_propagate(errp, err); 354 return; 355 } 356 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_I2C]); 357 for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) { 358 qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), 359 sc->irqmap[ASPEED_I2C] + i); 360 /* 361 * The AST2600 SoC has one IRQ per I2C bus. Skip the common 362 * IRQ (AST2400 and AST2500) and connect all bussses. 363 */ 364 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), i + 1, irq); 365 } 366 367 /* FMC, The number of CS is set at the board level */ 368 object_property_set_link(OBJECT(&s->fmc), OBJECT(s->dram_mr), "dram", &err); 369 if (err) { 370 error_propagate(errp, err); 371 return; 372 } 373 object_property_set_int(OBJECT(&s->fmc), sc->memmap[ASPEED_SDRAM], 374 "sdram-base", &err); 375 if (err) { 376 error_propagate(errp, err); 377 return; 378 } 379 sysbus_realize(SYS_BUS_DEVICE(&s->fmc), &err); 380 if (err) { 381 error_propagate(errp, err); 382 return; 383 } 384 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_FMC]); 385 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1, 386 s->fmc.ctrl->flash_window_base); 387 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, 388 aspeed_soc_get_irq(s, ASPEED_FMC)); 389 390 /* SPI */ 391 for (i = 0; i < sc->spis_num; i++) { 392 object_property_set_link(OBJECT(&s->spi[i]), OBJECT(s->dram_mr), 393 "dram", &err); 394 if (err) { 395 error_propagate(errp, err); 396 return; 397 } 398 object_property_set_int(OBJECT(&s->spi[i]), 1, "num-cs", &err); 399 sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), &local_err); 400 error_propagate(&err, local_err); 401 if (err) { 402 error_propagate(errp, err); 403 return; 404 } 405 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, 406 sc->memmap[ASPEED_SPI1 + i]); 407 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1, 408 s->spi[i].ctrl->flash_window_base); 409 } 410 411 /* EHCI */ 412 for (i = 0; i < sc->ehcis_num; i++) { 413 sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), &err); 414 if (err) { 415 error_propagate(errp, err); 416 return; 417 } 418 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0, 419 sc->memmap[ASPEED_EHCI1 + i]); 420 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, 421 aspeed_soc_get_irq(s, ASPEED_EHCI1 + i)); 422 } 423 424 /* SDMC - SDRAM Memory Controller */ 425 sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), &err); 426 if (err) { 427 error_propagate(errp, err); 428 return; 429 } 430 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->memmap[ASPEED_SDMC]); 431 432 /* Watch dog */ 433 for (i = 0; i < sc->wdts_num; i++) { 434 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); 435 436 object_property_set_link(OBJECT(&s->wdt[i]), 437 OBJECT(&s->scu), "scu", &error_abort); 438 sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), &err); 439 if (err) { 440 error_propagate(errp, err); 441 return; 442 } 443 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, 444 sc->memmap[ASPEED_WDT] + i * awc->offset); 445 } 446 447 /* Net */ 448 for (i = 0; i < sc->macs_num; i++) { 449 object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "aspeed", 450 &err); 451 sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), &local_err); 452 error_propagate(&err, local_err); 453 if (err) { 454 error_propagate(errp, err); 455 return; 456 } 457 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 458 sc->memmap[ASPEED_ETH1 + i]); 459 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 460 aspeed_soc_get_irq(s, ASPEED_ETH1 + i)); 461 462 object_property_set_link(OBJECT(&s->mii[i]), OBJECT(&s->ftgmac100[i]), 463 "nic", &error_abort); 464 sysbus_realize(SYS_BUS_DEVICE(&s->mii[i]), &err); 465 if (err) { 466 error_propagate(errp, err); 467 return; 468 } 469 470 sysbus_mmio_map(SYS_BUS_DEVICE(&s->mii[i]), 0, 471 sc->memmap[ASPEED_MII1 + i]); 472 } 473 474 /* XDMA */ 475 sysbus_realize(SYS_BUS_DEVICE(&s->xdma), &err); 476 if (err) { 477 error_propagate(errp, err); 478 return; 479 } 480 sysbus_mmio_map(SYS_BUS_DEVICE(&s->xdma), 0, 481 sc->memmap[ASPEED_XDMA]); 482 sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0, 483 aspeed_soc_get_irq(s, ASPEED_XDMA)); 484 485 /* GPIO */ 486 sysbus_realize(SYS_BUS_DEVICE(&s->gpio), &err); 487 if (err) { 488 error_propagate(errp, err); 489 return; 490 } 491 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_GPIO]); 492 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, 493 aspeed_soc_get_irq(s, ASPEED_GPIO)); 494 495 sysbus_realize(SYS_BUS_DEVICE(&s->gpio_1_8v), &err); 496 if (err) { 497 error_propagate(errp, err); 498 return; 499 } 500 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio_1_8v), 0, 501 sc->memmap[ASPEED_GPIO_1_8V]); 502 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio_1_8v), 0, 503 aspeed_soc_get_irq(s, ASPEED_GPIO_1_8V)); 504 505 /* SDHCI */ 506 sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), &err); 507 if (err) { 508 error_propagate(errp, err); 509 return; 510 } 511 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0, 512 sc->memmap[ASPEED_SDHCI]); 513 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, 514 aspeed_soc_get_irq(s, ASPEED_SDHCI)); 515 516 /* eMMC */ 517 sysbus_realize(SYS_BUS_DEVICE(&s->emmc), &err); 518 if (err) { 519 error_propagate(errp, err); 520 return; 521 } 522 sysbus_mmio_map(SYS_BUS_DEVICE(&s->emmc), 0, sc->memmap[ASPEED_EMMC]); 523 sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0, 524 aspeed_soc_get_irq(s, ASPEED_EMMC)); 525 } 526 527 static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) 528 { 529 DeviceClass *dc = DEVICE_CLASS(oc); 530 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); 531 532 dc->realize = aspeed_soc_ast2600_realize; 533 534 sc->name = "ast2600-a1"; 535 sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7"); 536 sc->silicon_rev = AST2600_A1_SILICON_REV; 537 sc->sram_size = 0x10000; 538 sc->spis_num = 2; 539 sc->ehcis_num = 2; 540 sc->wdts_num = 4; 541 sc->macs_num = 4; 542 sc->irqmap = aspeed_soc_ast2600_irqmap; 543 sc->memmap = aspeed_soc_ast2600_memmap; 544 sc->num_cpus = 2; 545 } 546 547 static const TypeInfo aspeed_soc_ast2600_type_info = { 548 .name = "ast2600-a1", 549 .parent = TYPE_ASPEED_SOC, 550 .instance_size = sizeof(AspeedSoCState), 551 .instance_init = aspeed_soc_ast2600_init, 552 .class_init = aspeed_soc_ast2600_class_init, 553 .class_size = sizeof(AspeedSoCClass), 554 }; 555 556 static void aspeed_soc_register_types(void) 557 { 558 type_register_static(&aspeed_soc_ast2600_type_info); 559 }; 560 561 type_init(aspeed_soc_register_types) 562