1 /* 2 * ASPEED SoC 2600 family 3 * 4 * Copyright (c) 2016-2019, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See 7 * the COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qapi/error.h" 12 #include "cpu.h" 13 #include "exec/address-spaces.h" 14 #include "hw/misc/unimp.h" 15 #include "hw/arm/aspeed_soc.h" 16 #include "hw/char/serial.h" 17 #include "qemu/log.h" 18 #include "qemu/module.h" 19 #include "qemu/error-report.h" 20 #include "hw/i2c/aspeed_i2c.h" 21 #include "net/net.h" 22 #include "sysemu/sysemu.h" 23 24 #define ASPEED_SOC_IOMEM_SIZE 0x00200000 25 26 static const hwaddr aspeed_soc_ast2600_memmap[] = { 27 [ASPEED_SRAM] = 0x10000000, 28 /* 0x16000000 0x17FFFFFF : AHB BUS do LPC Bus bridge */ 29 [ASPEED_IOMEM] = 0x1E600000, 30 [ASPEED_PWM] = 0x1E610000, 31 [ASPEED_FMC] = 0x1E620000, 32 [ASPEED_SPI1] = 0x1E630000, 33 [ASPEED_SPI2] = 0x1E641000, 34 [ASPEED_EHCI1] = 0x1E6A1000, 35 [ASPEED_EHCI2] = 0x1E6A3000, 36 [ASPEED_MII1] = 0x1E650000, 37 [ASPEED_MII2] = 0x1E650008, 38 [ASPEED_MII3] = 0x1E650010, 39 [ASPEED_MII4] = 0x1E650018, 40 [ASPEED_ETH1] = 0x1E660000, 41 [ASPEED_ETH3] = 0x1E670000, 42 [ASPEED_ETH2] = 0x1E680000, 43 [ASPEED_ETH4] = 0x1E690000, 44 [ASPEED_VIC] = 0x1E6C0000, 45 [ASPEED_SDMC] = 0x1E6E0000, 46 [ASPEED_SCU] = 0x1E6E2000, 47 [ASPEED_XDMA] = 0x1E6E7000, 48 [ASPEED_ADC] = 0x1E6E9000, 49 [ASPEED_VIDEO] = 0x1E700000, 50 [ASPEED_SDHCI] = 0x1E740000, 51 [ASPEED_EMMC] = 0x1E750000, 52 [ASPEED_GPIO] = 0x1E780000, 53 [ASPEED_GPIO_1_8V] = 0x1E780800, 54 [ASPEED_RTC] = 0x1E781000, 55 [ASPEED_TIMER1] = 0x1E782000, 56 [ASPEED_WDT] = 0x1E785000, 57 [ASPEED_LPC] = 0x1E789000, 58 [ASPEED_IBT] = 0x1E789140, 59 [ASPEED_I2C] = 0x1E78A000, 60 [ASPEED_UART1] = 0x1E783000, 61 [ASPEED_UART5] = 0x1E784000, 62 [ASPEED_VUART] = 0x1E787000, 63 [ASPEED_SDRAM] = 0x80000000, 64 }; 65 66 #define ASPEED_A7MPCORE_ADDR 0x40460000 67 68 #define ASPEED_SOC_AST2600_MAX_IRQ 128 69 70 /* Shared Peripheral Interrupt values below are offset by -32 from datasheet */ 71 static const int aspeed_soc_ast2600_irqmap[] = { 72 [ASPEED_UART1] = 47, 73 [ASPEED_UART2] = 48, 74 [ASPEED_UART3] = 49, 75 [ASPEED_UART4] = 50, 76 [ASPEED_UART5] = 8, 77 [ASPEED_VUART] = 8, 78 [ASPEED_FMC] = 39, 79 [ASPEED_SDMC] = 0, 80 [ASPEED_SCU] = 12, 81 [ASPEED_ADC] = 78, 82 [ASPEED_XDMA] = 6, 83 [ASPEED_SDHCI] = 43, 84 [ASPEED_EHCI1] = 5, 85 [ASPEED_EHCI2] = 9, 86 [ASPEED_EMMC] = 15, 87 [ASPEED_GPIO] = 40, 88 [ASPEED_GPIO_1_8V] = 11, 89 [ASPEED_RTC] = 13, 90 [ASPEED_TIMER1] = 16, 91 [ASPEED_TIMER2] = 17, 92 [ASPEED_TIMER3] = 18, 93 [ASPEED_TIMER4] = 19, 94 [ASPEED_TIMER5] = 20, 95 [ASPEED_TIMER6] = 21, 96 [ASPEED_TIMER7] = 22, 97 [ASPEED_TIMER8] = 23, 98 [ASPEED_WDT] = 24, 99 [ASPEED_PWM] = 44, 100 [ASPEED_LPC] = 35, 101 [ASPEED_IBT] = 35, /* LPC */ 102 [ASPEED_I2C] = 110, /* 110 -> 125 */ 103 [ASPEED_ETH1] = 2, 104 [ASPEED_ETH2] = 3, 105 [ASPEED_ETH3] = 32, 106 [ASPEED_ETH4] = 33, 107 108 }; 109 110 static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl) 111 { 112 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 113 114 return qdev_get_gpio_in(DEVICE(&s->a7mpcore), sc->irqmap[ctrl]); 115 } 116 117 static void aspeed_soc_ast2600_init(Object *obj) 118 { 119 AspeedSoCState *s = ASPEED_SOC(obj); 120 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 121 int i; 122 char socname[8]; 123 char typename[64]; 124 125 if (sscanf(sc->name, "%7s", socname) != 1) { 126 g_assert_not_reached(); 127 } 128 129 for (i = 0; i < sc->num_cpus; i++) { 130 object_initialize_child(obj, "cpu[*]", &s->cpu[i], sc->cpu_type); 131 } 132 133 snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname); 134 sysbus_init_child_obj(obj, "scu", OBJECT(&s->scu), sizeof(s->scu), 135 typename); 136 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", 137 sc->silicon_rev); 138 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), 139 "hw-strap1"); 140 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), 141 "hw-strap2"); 142 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), 143 "hw-prot-key"); 144 145 sysbus_init_child_obj(obj, "a7mpcore", &s->a7mpcore, 146 sizeof(s->a7mpcore), TYPE_A15MPCORE_PRIV); 147 148 sysbus_init_child_obj(obj, "rtc", OBJECT(&s->rtc), sizeof(s->rtc), 149 TYPE_ASPEED_RTC); 150 151 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); 152 sysbus_init_child_obj(obj, "timerctrl", OBJECT(&s->timerctrl), 153 sizeof(s->timerctrl), typename); 154 155 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); 156 sysbus_init_child_obj(obj, "i2c", OBJECT(&s->i2c), sizeof(s->i2c), 157 typename); 158 159 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); 160 sysbus_init_child_obj(obj, "fmc", OBJECT(&s->fmc), sizeof(s->fmc), 161 typename); 162 object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs"); 163 164 for (i = 0; i < sc->spis_num; i++) { 165 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname); 166 sysbus_init_child_obj(obj, "spi[*]", OBJECT(&s->spi[i]), 167 sizeof(s->spi[i]), typename); 168 } 169 170 for (i = 0; i < sc->ehcis_num; i++) { 171 sysbus_init_child_obj(obj, "ehci[*]", OBJECT(&s->ehci[i]), 172 sizeof(s->ehci[i]), TYPE_PLATFORM_EHCI); 173 } 174 175 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname); 176 sysbus_init_child_obj(obj, "sdmc", OBJECT(&s->sdmc), sizeof(s->sdmc), 177 typename); 178 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), 179 "ram-size"); 180 object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc), 181 "max-ram-size"); 182 183 for (i = 0; i < sc->wdts_num; i++) { 184 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); 185 sysbus_init_child_obj(obj, "wdt[*]", OBJECT(&s->wdt[i]), 186 sizeof(s->wdt[i]), typename); 187 } 188 189 for (i = 0; i < sc->macs_num; i++) { 190 sysbus_init_child_obj(obj, "ftgmac100[*]", OBJECT(&s->ftgmac100[i]), 191 sizeof(s->ftgmac100[i]), TYPE_FTGMAC100); 192 193 sysbus_init_child_obj(obj, "mii[*]", &s->mii[i], sizeof(s->mii[i]), 194 TYPE_ASPEED_MII); 195 } 196 197 sysbus_init_child_obj(obj, "xdma", OBJECT(&s->xdma), sizeof(s->xdma), 198 TYPE_ASPEED_XDMA); 199 200 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); 201 sysbus_init_child_obj(obj, "gpio", OBJECT(&s->gpio), sizeof(s->gpio), 202 typename); 203 204 snprintf(typename, sizeof(typename), "aspeed.gpio-%s-1_8v", socname); 205 sysbus_init_child_obj(obj, "gpio_1_8v", OBJECT(&s->gpio_1_8v), 206 sizeof(s->gpio_1_8v), typename); 207 208 sysbus_init_child_obj(obj, "sd-controller", OBJECT(&s->sdhci), 209 sizeof(s->sdhci), TYPE_ASPEED_SDHCI); 210 211 object_property_set_int(OBJECT(&s->sdhci), 2, "num-slots", &error_abort); 212 213 /* Init sd card slot class here so that they're under the correct parent */ 214 for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { 215 sysbus_init_child_obj(obj, "sd-controller.sdhci[*]", 216 OBJECT(&s->sdhci.slots[i]), 217 sizeof(s->sdhci.slots[i]), TYPE_SYSBUS_SDHCI); 218 } 219 220 sysbus_init_child_obj(obj, "emmc-controller", OBJECT(&s->emmc), 221 sizeof(s->emmc), TYPE_ASPEED_SDHCI); 222 223 object_property_set_int(OBJECT(&s->emmc), 1, "num-slots", &error_abort); 224 225 sysbus_init_child_obj(obj, "emmc-controller.sdhci", 226 OBJECT(&s->emmc.slots[0]), sizeof(s->emmc.slots[0]), 227 TYPE_SYSBUS_SDHCI); 228 } 229 230 /* 231 * ASPEED ast2600 has 0xf as cluster ID 232 * 233 * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0388e/CIHEBGFG.html 234 */ 235 static uint64_t aspeed_calc_affinity(int cpu) 236 { 237 return (0xf << ARM_AFF1_SHIFT) | cpu; 238 } 239 240 static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) 241 { 242 int i; 243 AspeedSoCState *s = ASPEED_SOC(dev); 244 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 245 Error *err = NULL, *local_err = NULL; 246 qemu_irq irq; 247 248 /* IO space */ 249 create_unimplemented_device("aspeed_soc.io", sc->memmap[ASPEED_IOMEM], 250 ASPEED_SOC_IOMEM_SIZE); 251 252 /* Video engine stub */ 253 create_unimplemented_device("aspeed.video", sc->memmap[ASPEED_VIDEO], 254 0x1000); 255 256 /* CPU */ 257 for (i = 0; i < sc->num_cpus; i++) { 258 object_property_set_int(OBJECT(&s->cpu[i]), QEMU_PSCI_CONDUIT_SMC, 259 "psci-conduit", &error_abort); 260 if (sc->num_cpus > 1) { 261 object_property_set_int(OBJECT(&s->cpu[i]), 262 ASPEED_A7MPCORE_ADDR, 263 "reset-cbar", &error_abort); 264 } 265 object_property_set_int(OBJECT(&s->cpu[i]), aspeed_calc_affinity(i), 266 "mp-affinity", &error_abort); 267 268 object_property_set_int(OBJECT(&s->cpu[i]), 1125000000, "cntfrq", 269 &error_abort); 270 271 /* 272 * TODO: the secondary CPUs are started and a boot helper 273 * is needed when using -kernel 274 */ 275 276 object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err); 277 if (err) { 278 error_propagate(errp, err); 279 return; 280 } 281 } 282 283 /* A7MPCORE */ 284 object_property_set_int(OBJECT(&s->a7mpcore), sc->num_cpus, "num-cpu", 285 &error_abort); 286 object_property_set_int(OBJECT(&s->a7mpcore), 287 ASPEED_SOC_AST2600_MAX_IRQ + GIC_INTERNAL, 288 "num-irq", &error_abort); 289 290 object_property_set_bool(OBJECT(&s->a7mpcore), true, "realized", 291 &error_abort); 292 sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, ASPEED_A7MPCORE_ADDR); 293 294 for (i = 0; i < sc->num_cpus; i++) { 295 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore); 296 DeviceState *d = DEVICE(qemu_get_cpu(i)); 297 298 irq = qdev_get_gpio_in(d, ARM_CPU_IRQ); 299 sysbus_connect_irq(sbd, i, irq); 300 irq = qdev_get_gpio_in(d, ARM_CPU_FIQ); 301 sysbus_connect_irq(sbd, i + sc->num_cpus, irq); 302 irq = qdev_get_gpio_in(d, ARM_CPU_VIRQ); 303 sysbus_connect_irq(sbd, i + 2 * sc->num_cpus, irq); 304 irq = qdev_get_gpio_in(d, ARM_CPU_VFIQ); 305 sysbus_connect_irq(sbd, i + 3 * sc->num_cpus, irq); 306 } 307 308 /* SRAM */ 309 memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram", 310 sc->sram_size, &err); 311 if (err) { 312 error_propagate(errp, err); 313 return; 314 } 315 memory_region_add_subregion(get_system_memory(), 316 sc->memmap[ASPEED_SRAM], &s->sram); 317 318 /* SCU */ 319 object_property_set_bool(OBJECT(&s->scu), true, "realized", &err); 320 if (err) { 321 error_propagate(errp, err); 322 return; 323 } 324 sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_SCU]); 325 326 /* RTC */ 327 object_property_set_bool(OBJECT(&s->rtc), true, "realized", &err); 328 if (err) { 329 error_propagate(errp, err); 330 return; 331 } 332 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_RTC]); 333 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, 334 aspeed_soc_get_irq(s, ASPEED_RTC)); 335 336 /* Timer */ 337 object_property_set_link(OBJECT(&s->timerctrl), 338 OBJECT(&s->scu), "scu", &error_abort); 339 object_property_set_bool(OBJECT(&s->timerctrl), true, "realized", &err); 340 if (err) { 341 error_propagate(errp, err); 342 return; 343 } 344 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0, 345 sc->memmap[ASPEED_TIMER1]); 346 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { 347 qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_TIMER1 + i); 348 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); 349 } 350 351 /* UART - attach an 8250 to the IO space as our UART5 */ 352 if (serial_hd(0)) { 353 qemu_irq uart5 = aspeed_soc_get_irq(s, ASPEED_UART5); 354 serial_mm_init(get_system_memory(), sc->memmap[ASPEED_UART5], 2, 355 uart5, 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN); 356 } 357 358 /* I2C */ 359 object_property_set_link(OBJECT(&s->i2c), OBJECT(s->dram_mr), "dram", &err); 360 if (err) { 361 error_propagate(errp, err); 362 return; 363 } 364 object_property_set_bool(OBJECT(&s->i2c), true, "realized", &err); 365 if (err) { 366 error_propagate(errp, err); 367 return; 368 } 369 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_I2C]); 370 for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) { 371 qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), 372 sc->irqmap[ASPEED_I2C] + i); 373 /* 374 * The AST2600 SoC has one IRQ per I2C bus. Skip the common 375 * IRQ (AST2400 and AST2500) and connect all bussses. 376 */ 377 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), i + 1, irq); 378 } 379 380 /* FMC, The number of CS is set at the board level */ 381 object_property_set_link(OBJECT(&s->fmc), OBJECT(s->dram_mr), "dram", &err); 382 if (err) { 383 error_propagate(errp, err); 384 return; 385 } 386 object_property_set_int(OBJECT(&s->fmc), sc->memmap[ASPEED_SDRAM], 387 "sdram-base", &err); 388 if (err) { 389 error_propagate(errp, err); 390 return; 391 } 392 object_property_set_bool(OBJECT(&s->fmc), true, "realized", &err); 393 if (err) { 394 error_propagate(errp, err); 395 return; 396 } 397 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_FMC]); 398 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1, 399 s->fmc.ctrl->flash_window_base); 400 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, 401 aspeed_soc_get_irq(s, ASPEED_FMC)); 402 403 /* SPI */ 404 for (i = 0; i < sc->spis_num; i++) { 405 object_property_set_link(OBJECT(&s->spi[i]), OBJECT(s->dram_mr), 406 "dram", &err); 407 if (err) { 408 error_propagate(errp, err); 409 return; 410 } 411 object_property_set_int(OBJECT(&s->spi[i]), 1, "num-cs", &err); 412 object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", 413 &local_err); 414 error_propagate(&err, local_err); 415 if (err) { 416 error_propagate(errp, err); 417 return; 418 } 419 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, 420 sc->memmap[ASPEED_SPI1 + i]); 421 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1, 422 s->spi[i].ctrl->flash_window_base); 423 } 424 425 /* EHCI */ 426 for (i = 0; i < sc->ehcis_num; i++) { 427 object_property_set_bool(OBJECT(&s->ehci[i]), true, "realized", &err); 428 if (err) { 429 error_propagate(errp, err); 430 return; 431 } 432 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0, 433 sc->memmap[ASPEED_EHCI1 + i]); 434 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, 435 aspeed_soc_get_irq(s, ASPEED_EHCI1 + i)); 436 } 437 438 /* SDMC - SDRAM Memory Controller */ 439 object_property_set_bool(OBJECT(&s->sdmc), true, "realized", &err); 440 if (err) { 441 error_propagate(errp, err); 442 return; 443 } 444 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->memmap[ASPEED_SDMC]); 445 446 /* Watch dog */ 447 for (i = 0; i < sc->wdts_num; i++) { 448 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); 449 450 object_property_set_link(OBJECT(&s->wdt[i]), 451 OBJECT(&s->scu), "scu", &error_abort); 452 object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized", &err); 453 if (err) { 454 error_propagate(errp, err); 455 return; 456 } 457 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, 458 sc->memmap[ASPEED_WDT] + i * awc->offset); 459 } 460 461 /* Net */ 462 for (i = 0; i < sc->macs_num; i++) { 463 object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "aspeed", 464 &err); 465 object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "realized", 466 &local_err); 467 error_propagate(&err, local_err); 468 if (err) { 469 error_propagate(errp, err); 470 return; 471 } 472 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 473 sc->memmap[ASPEED_ETH1 + i]); 474 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 475 aspeed_soc_get_irq(s, ASPEED_ETH1 + i)); 476 477 object_property_set_link(OBJECT(&s->mii[i]), OBJECT(&s->ftgmac100[i]), 478 "nic", &error_abort); 479 object_property_set_bool(OBJECT(&s->mii[i]), true, "realized", 480 &err); 481 if (err) { 482 error_propagate(errp, err); 483 return; 484 } 485 486 sysbus_mmio_map(SYS_BUS_DEVICE(&s->mii[i]), 0, 487 sc->memmap[ASPEED_MII1 + i]); 488 } 489 490 /* XDMA */ 491 object_property_set_bool(OBJECT(&s->xdma), true, "realized", &err); 492 if (err) { 493 error_propagate(errp, err); 494 return; 495 } 496 sysbus_mmio_map(SYS_BUS_DEVICE(&s->xdma), 0, 497 sc->memmap[ASPEED_XDMA]); 498 sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0, 499 aspeed_soc_get_irq(s, ASPEED_XDMA)); 500 501 /* GPIO */ 502 object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err); 503 if (err) { 504 error_propagate(errp, err); 505 return; 506 } 507 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_GPIO]); 508 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, 509 aspeed_soc_get_irq(s, ASPEED_GPIO)); 510 511 object_property_set_bool(OBJECT(&s->gpio_1_8v), true, "realized", &err); 512 if (err) { 513 error_propagate(errp, err); 514 return; 515 } 516 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio_1_8v), 0, 517 sc->memmap[ASPEED_GPIO_1_8V]); 518 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio_1_8v), 0, 519 aspeed_soc_get_irq(s, ASPEED_GPIO_1_8V)); 520 521 /* SDHCI */ 522 object_property_set_bool(OBJECT(&s->sdhci), true, "realized", &err); 523 if (err) { 524 error_propagate(errp, err); 525 return; 526 } 527 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0, 528 sc->memmap[ASPEED_SDHCI]); 529 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, 530 aspeed_soc_get_irq(s, ASPEED_SDHCI)); 531 532 /* eMMC */ 533 object_property_set_bool(OBJECT(&s->emmc), true, "realized", &err); 534 if (err) { 535 error_propagate(errp, err); 536 return; 537 } 538 sysbus_mmio_map(SYS_BUS_DEVICE(&s->emmc), 0, sc->memmap[ASPEED_EMMC]); 539 sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0, 540 aspeed_soc_get_irq(s, ASPEED_EMMC)); 541 } 542 543 static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) 544 { 545 DeviceClass *dc = DEVICE_CLASS(oc); 546 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); 547 548 dc->realize = aspeed_soc_ast2600_realize; 549 550 sc->name = "ast2600-a1"; 551 sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7"); 552 sc->silicon_rev = AST2600_A1_SILICON_REV; 553 sc->sram_size = 0x10000; 554 sc->spis_num = 2; 555 sc->ehcis_num = 2; 556 sc->wdts_num = 4; 557 sc->macs_num = 4; 558 sc->irqmap = aspeed_soc_ast2600_irqmap; 559 sc->memmap = aspeed_soc_ast2600_memmap; 560 sc->num_cpus = 2; 561 } 562 563 static const TypeInfo aspeed_soc_ast2600_type_info = { 564 .name = "ast2600-a1", 565 .parent = TYPE_ASPEED_SOC, 566 .instance_size = sizeof(AspeedSoCState), 567 .instance_init = aspeed_soc_ast2600_init, 568 .class_init = aspeed_soc_ast2600_class_init, 569 .class_size = sizeof(AspeedSoCClass), 570 }; 571 572 static void aspeed_soc_register_types(void) 573 { 574 type_register_static(&aspeed_soc_ast2600_type_info); 575 }; 576 577 type_init(aspeed_soc_register_types) 578