1 /* 2 * ASPEED SoC 2600 family 3 * 4 * Copyright (c) 2016-2019, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See 7 * the COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qapi/error.h" 12 #include "hw/misc/unimp.h" 13 #include "hw/arm/aspeed_soc.h" 14 #include "qemu/module.h" 15 #include "qemu/error-report.h" 16 #include "hw/i2c/aspeed_i2c.h" 17 #include "net/net.h" 18 #include "sysemu/sysemu.h" 19 20 #define ASPEED_SOC_IOMEM_SIZE 0x00200000 21 #define ASPEED_SOC_DPMCU_SIZE 0x00040000 22 23 static const hwaddr aspeed_soc_ast2600_memmap[] = { 24 [ASPEED_DEV_SRAM] = 0x10000000, 25 [ASPEED_DEV_DPMCU] = 0x18000000, 26 /* 0x16000000 0x17FFFFFF : AHB BUS do LPC Bus bridge */ 27 [ASPEED_DEV_IOMEM] = 0x1E600000, 28 [ASPEED_DEV_PWM] = 0x1E610000, 29 [ASPEED_DEV_FMC] = 0x1E620000, 30 [ASPEED_DEV_SPI1] = 0x1E630000, 31 [ASPEED_DEV_SPI2] = 0x1E631000, 32 [ASPEED_DEV_EHCI1] = 0x1E6A1000, 33 [ASPEED_DEV_EHCI2] = 0x1E6A3000, 34 [ASPEED_DEV_MII1] = 0x1E650000, 35 [ASPEED_DEV_MII2] = 0x1E650008, 36 [ASPEED_DEV_MII3] = 0x1E650010, 37 [ASPEED_DEV_MII4] = 0x1E650018, 38 [ASPEED_DEV_ETH1] = 0x1E660000, 39 [ASPEED_DEV_ETH3] = 0x1E670000, 40 [ASPEED_DEV_ETH2] = 0x1E680000, 41 [ASPEED_DEV_ETH4] = 0x1E690000, 42 [ASPEED_DEV_VIC] = 0x1E6C0000, 43 [ASPEED_DEV_HACE] = 0x1E6D0000, 44 [ASPEED_DEV_SDMC] = 0x1E6E0000, 45 [ASPEED_DEV_SCU] = 0x1E6E2000, 46 [ASPEED_DEV_XDMA] = 0x1E6E7000, 47 [ASPEED_DEV_ADC] = 0x1E6E9000, 48 [ASPEED_DEV_DP] = 0x1E6EB000, 49 [ASPEED_DEV_SBC] = 0x1E6F2000, 50 [ASPEED_DEV_EMMC_BC] = 0x1E6f5000, 51 [ASPEED_DEV_VIDEO] = 0x1E700000, 52 [ASPEED_DEV_SDHCI] = 0x1E740000, 53 [ASPEED_DEV_EMMC] = 0x1E750000, 54 [ASPEED_DEV_GPIO] = 0x1E780000, 55 [ASPEED_DEV_GPIO_1_8V] = 0x1E780800, 56 [ASPEED_DEV_RTC] = 0x1E781000, 57 [ASPEED_DEV_TIMER1] = 0x1E782000, 58 [ASPEED_DEV_WDT] = 0x1E785000, 59 [ASPEED_DEV_LPC] = 0x1E789000, 60 [ASPEED_DEV_IBT] = 0x1E789140, 61 [ASPEED_DEV_I2C] = 0x1E78A000, 62 [ASPEED_DEV_PECI] = 0x1E78B000, 63 [ASPEED_DEV_UART1] = 0x1E783000, 64 [ASPEED_DEV_UART2] = 0x1E78D000, 65 [ASPEED_DEV_UART3] = 0x1E78E000, 66 [ASPEED_DEV_UART4] = 0x1E78F000, 67 [ASPEED_DEV_UART5] = 0x1E784000, 68 [ASPEED_DEV_UART6] = 0x1E790000, 69 [ASPEED_DEV_UART7] = 0x1E790100, 70 [ASPEED_DEV_UART8] = 0x1E790200, 71 [ASPEED_DEV_UART9] = 0x1E790300, 72 [ASPEED_DEV_UART10] = 0x1E790400, 73 [ASPEED_DEV_UART11] = 0x1E790500, 74 [ASPEED_DEV_UART12] = 0x1E790600, 75 [ASPEED_DEV_UART13] = 0x1E790700, 76 [ASPEED_DEV_VUART] = 0x1E787000, 77 [ASPEED_DEV_I3C] = 0x1E7A0000, 78 [ASPEED_DEV_SDRAM] = 0x80000000, 79 }; 80 81 #define ASPEED_A7MPCORE_ADDR 0x40460000 82 83 #define AST2600_MAX_IRQ 197 84 85 /* Shared Peripheral Interrupt values below are offset by -32 from datasheet */ 86 static const int aspeed_soc_ast2600_irqmap[] = { 87 [ASPEED_DEV_UART1] = 47, 88 [ASPEED_DEV_UART2] = 48, 89 [ASPEED_DEV_UART3] = 49, 90 [ASPEED_DEV_UART4] = 50, 91 [ASPEED_DEV_UART5] = 8, 92 [ASPEED_DEV_UART6] = 57, 93 [ASPEED_DEV_UART7] = 58, 94 [ASPEED_DEV_UART8] = 59, 95 [ASPEED_DEV_UART9] = 60, 96 [ASPEED_DEV_UART10] = 61, 97 [ASPEED_DEV_UART11] = 62, 98 [ASPEED_DEV_UART12] = 63, 99 [ASPEED_DEV_UART13] = 64, 100 [ASPEED_DEV_VUART] = 8, 101 [ASPEED_DEV_FMC] = 39, 102 [ASPEED_DEV_SDMC] = 0, 103 [ASPEED_DEV_SCU] = 12, 104 [ASPEED_DEV_ADC] = 78, 105 [ASPEED_DEV_XDMA] = 6, 106 [ASPEED_DEV_SDHCI] = 43, 107 [ASPEED_DEV_EHCI1] = 5, 108 [ASPEED_DEV_EHCI2] = 9, 109 [ASPEED_DEV_EMMC] = 15, 110 [ASPEED_DEV_GPIO] = 40, 111 [ASPEED_DEV_GPIO_1_8V] = 11, 112 [ASPEED_DEV_RTC] = 13, 113 [ASPEED_DEV_TIMER1] = 16, 114 [ASPEED_DEV_TIMER2] = 17, 115 [ASPEED_DEV_TIMER3] = 18, 116 [ASPEED_DEV_TIMER4] = 19, 117 [ASPEED_DEV_TIMER5] = 20, 118 [ASPEED_DEV_TIMER6] = 21, 119 [ASPEED_DEV_TIMER7] = 22, 120 [ASPEED_DEV_TIMER8] = 23, 121 [ASPEED_DEV_WDT] = 24, 122 [ASPEED_DEV_PWM] = 44, 123 [ASPEED_DEV_LPC] = 35, 124 [ASPEED_DEV_IBT] = 143, 125 [ASPEED_DEV_I2C] = 110, /* 110 -> 125 */ 126 [ASPEED_DEV_PECI] = 38, 127 [ASPEED_DEV_ETH1] = 2, 128 [ASPEED_DEV_ETH2] = 3, 129 [ASPEED_DEV_HACE] = 4, 130 [ASPEED_DEV_ETH3] = 32, 131 [ASPEED_DEV_ETH4] = 33, 132 [ASPEED_DEV_KCS] = 138, /* 138 -> 142 */ 133 [ASPEED_DEV_DP] = 62, 134 [ASPEED_DEV_I3C] = 102, /* 102 -> 107 */ 135 }; 136 137 static qemu_irq aspeed_soc_ast2600_get_irq(AspeedSoCState *s, int dev) 138 { 139 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 140 141 return qdev_get_gpio_in(DEVICE(&s->a7mpcore), sc->irqmap[dev]); 142 } 143 144 static void aspeed_soc_ast2600_init(Object *obj) 145 { 146 AspeedSoCState *s = ASPEED_SOC(obj); 147 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 148 int i; 149 char socname[8]; 150 char typename[64]; 151 152 if (sscanf(sc->name, "%7s", socname) != 1) { 153 g_assert_not_reached(); 154 } 155 156 for (i = 0; i < sc->num_cpus; i++) { 157 object_initialize_child(obj, "cpu[*]", &s->cpu[i], sc->cpu_type); 158 } 159 160 snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname); 161 object_initialize_child(obj, "scu", &s->scu, typename); 162 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", 163 sc->silicon_rev); 164 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), 165 "hw-strap1"); 166 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), 167 "hw-strap2"); 168 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), 169 "hw-prot-key"); 170 171 object_initialize_child(obj, "a7mpcore", &s->a7mpcore, 172 TYPE_A15MPCORE_PRIV); 173 174 object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC); 175 176 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); 177 object_initialize_child(obj, "timerctrl", &s->timerctrl, typename); 178 179 snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname); 180 object_initialize_child(obj, "adc", &s->adc, typename); 181 182 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); 183 object_initialize_child(obj, "i2c", &s->i2c, typename); 184 185 object_initialize_child(obj, "peci", &s->peci, TYPE_ASPEED_PECI); 186 187 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); 188 object_initialize_child(obj, "fmc", &s->fmc, typename); 189 190 for (i = 0; i < sc->spis_num; i++) { 191 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname); 192 object_initialize_child(obj, "spi[*]", &s->spi[i], typename); 193 } 194 195 for (i = 0; i < sc->ehcis_num; i++) { 196 object_initialize_child(obj, "ehci[*]", &s->ehci[i], 197 TYPE_PLATFORM_EHCI); 198 } 199 200 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname); 201 object_initialize_child(obj, "sdmc", &s->sdmc, typename); 202 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), 203 "ram-size"); 204 205 for (i = 0; i < sc->wdts_num; i++) { 206 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); 207 object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename); 208 } 209 210 for (i = 0; i < sc->macs_num; i++) { 211 object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i], 212 TYPE_FTGMAC100); 213 214 object_initialize_child(obj, "mii[*]", &s->mii[i], TYPE_ASPEED_MII); 215 } 216 217 snprintf(typename, sizeof(typename), TYPE_ASPEED_XDMA "-%s", socname); 218 object_initialize_child(obj, "xdma", &s->xdma, typename); 219 220 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); 221 object_initialize_child(obj, "gpio", &s->gpio, typename); 222 223 snprintf(typename, sizeof(typename), "aspeed.gpio-%s-1_8v", socname); 224 object_initialize_child(obj, "gpio_1_8v", &s->gpio_1_8v, typename); 225 226 object_initialize_child(obj, "sd-controller", &s->sdhci, 227 TYPE_ASPEED_SDHCI); 228 229 object_property_set_int(OBJECT(&s->sdhci), "num-slots", 2, &error_abort); 230 231 /* Init sd card slot class here so that they're under the correct parent */ 232 for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { 233 object_initialize_child(obj, "sd-controller.sdhci[*]", 234 &s->sdhci.slots[i], TYPE_SYSBUS_SDHCI); 235 } 236 237 object_initialize_child(obj, "emmc-controller", &s->emmc, 238 TYPE_ASPEED_SDHCI); 239 240 object_property_set_int(OBJECT(&s->emmc), "num-slots", 1, &error_abort); 241 242 object_initialize_child(obj, "emmc-controller.sdhci", &s->emmc.slots[0], 243 TYPE_SYSBUS_SDHCI); 244 245 object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC); 246 247 snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname); 248 object_initialize_child(obj, "hace", &s->hace, typename); 249 250 object_initialize_child(obj, "i3c", &s->i3c, TYPE_ASPEED_I3C); 251 252 object_initialize_child(obj, "sbc", &s->sbc, TYPE_ASPEED_SBC); 253 254 object_initialize_child(obj, "iomem", &s->iomem, TYPE_UNIMPLEMENTED_DEVICE); 255 object_initialize_child(obj, "video", &s->video, TYPE_UNIMPLEMENTED_DEVICE); 256 object_initialize_child(obj, "dpmcu", &s->dpmcu, TYPE_UNIMPLEMENTED_DEVICE); 257 object_initialize_child(obj, "emmc-boot-controller", 258 &s->emmc_boot_controller, 259 TYPE_UNIMPLEMENTED_DEVICE); 260 } 261 262 /* 263 * ASPEED ast2600 has 0xf as cluster ID 264 * 265 * https://developer.arm.com/documentation/ddi0388/e/the-system-control-coprocessors/summary-of-system-control-coprocessor-registers/multiprocessor-affinity-register 266 */ 267 static uint64_t aspeed_calc_affinity(int cpu) 268 { 269 return (0xf << ARM_AFF1_SHIFT) | cpu; 270 } 271 272 static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) 273 { 274 int i; 275 AspeedSoCState *s = ASPEED_SOC(dev); 276 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 277 Error *err = NULL; 278 qemu_irq irq; 279 g_autofree char *sram_name = NULL; 280 281 /* IO space */ 282 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem), "aspeed.io", 283 sc->memmap[ASPEED_DEV_IOMEM], 284 ASPEED_SOC_IOMEM_SIZE); 285 286 /* Video engine stub */ 287 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->video), "aspeed.video", 288 sc->memmap[ASPEED_DEV_VIDEO], 0x1000); 289 290 /* eMMC Boot Controller stub */ 291 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->emmc_boot_controller), 292 "aspeed.emmc-boot-controller", 293 sc->memmap[ASPEED_DEV_EMMC_BC], 0x1000); 294 295 /* CPU */ 296 for (i = 0; i < sc->num_cpus; i++) { 297 if (sc->num_cpus > 1) { 298 object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar", 299 ASPEED_A7MPCORE_ADDR, &error_abort); 300 } 301 object_property_set_int(OBJECT(&s->cpu[i]), "mp-affinity", 302 aspeed_calc_affinity(i), &error_abort); 303 304 object_property_set_int(OBJECT(&s->cpu[i]), "cntfrq", 1125000000, 305 &error_abort); 306 object_property_set_link(OBJECT(&s->cpu[i]), "memory", 307 OBJECT(s->memory), &error_abort); 308 309 if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) { 310 return; 311 } 312 } 313 314 /* A7MPCORE */ 315 object_property_set_int(OBJECT(&s->a7mpcore), "num-cpu", sc->num_cpus, 316 &error_abort); 317 object_property_set_int(OBJECT(&s->a7mpcore), "num-irq", 318 ROUND_UP(AST2600_MAX_IRQ + GIC_INTERNAL, 32), 319 &error_abort); 320 321 sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort); 322 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->a7mpcore), 0, ASPEED_A7MPCORE_ADDR); 323 324 for (i = 0; i < sc->num_cpus; i++) { 325 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore); 326 DeviceState *d = DEVICE(&s->cpu[i]); 327 328 irq = qdev_get_gpio_in(d, ARM_CPU_IRQ); 329 sysbus_connect_irq(sbd, i, irq); 330 irq = qdev_get_gpio_in(d, ARM_CPU_FIQ); 331 sysbus_connect_irq(sbd, i + sc->num_cpus, irq); 332 irq = qdev_get_gpio_in(d, ARM_CPU_VIRQ); 333 sysbus_connect_irq(sbd, i + 2 * sc->num_cpus, irq); 334 irq = qdev_get_gpio_in(d, ARM_CPU_VFIQ); 335 sysbus_connect_irq(sbd, i + 3 * sc->num_cpus, irq); 336 } 337 338 /* SRAM */ 339 sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&s->cpu[0])->cpu_index); 340 memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, &err); 341 if (err) { 342 error_propagate(errp, err); 343 return; 344 } 345 memory_region_add_subregion(s->memory, 346 sc->memmap[ASPEED_DEV_SRAM], &s->sram); 347 348 /* DPMCU */ 349 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->dpmcu), "aspeed.dpmcu", 350 sc->memmap[ASPEED_DEV_DPMCU], 351 ASPEED_SOC_DPMCU_SIZE); 352 353 /* SCU */ 354 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { 355 return; 356 } 357 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]); 358 359 /* RTC */ 360 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) { 361 return; 362 } 363 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]); 364 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, 365 aspeed_soc_get_irq(s, ASPEED_DEV_RTC)); 366 367 /* Timer */ 368 object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), 369 &error_abort); 370 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) { 371 return; 372 } 373 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->timerctrl), 0, 374 sc->memmap[ASPEED_DEV_TIMER1]); 375 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { 376 qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i); 377 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); 378 } 379 380 /* ADC */ 381 if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) { 382 return; 383 } 384 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]); 385 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, 386 aspeed_soc_get_irq(s, ASPEED_DEV_ADC)); 387 388 /* UART */ 389 aspeed_soc_uart_init(s); 390 391 /* I2C */ 392 object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr), 393 &error_abort); 394 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) { 395 return; 396 } 397 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]); 398 for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) { 399 qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), 400 sc->irqmap[ASPEED_DEV_I2C] + i); 401 /* The AST2600 I2C controller has one IRQ per bus. */ 402 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq); 403 } 404 405 /* PECI */ 406 if (!sysbus_realize(SYS_BUS_DEVICE(&s->peci), errp)) { 407 return; 408 } 409 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->peci), 0, 410 sc->memmap[ASPEED_DEV_PECI]); 411 sysbus_connect_irq(SYS_BUS_DEVICE(&s->peci), 0, 412 aspeed_soc_get_irq(s, ASPEED_DEV_PECI)); 413 414 /* FMC, The number of CS is set at the board level */ 415 object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr), 416 &error_abort); 417 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) { 418 return; 419 } 420 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]); 421 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 1, 422 ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base); 423 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, 424 aspeed_soc_get_irq(s, ASPEED_DEV_FMC)); 425 426 /* SPI */ 427 for (i = 0; i < sc->spis_num; i++) { 428 object_property_set_link(OBJECT(&s->spi[i]), "dram", 429 OBJECT(s->dram_mr), &error_abort); 430 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { 431 return; 432 } 433 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 0, 434 sc->memmap[ASPEED_DEV_SPI1 + i]); 435 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 1, 436 ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base); 437 } 438 439 /* EHCI */ 440 for (i = 0; i < sc->ehcis_num; i++) { 441 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) { 442 return; 443 } 444 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ehci[i]), 0, 445 sc->memmap[ASPEED_DEV_EHCI1 + i]); 446 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, 447 aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i)); 448 } 449 450 /* SDMC - SDRAM Memory Controller */ 451 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) { 452 return; 453 } 454 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdmc), 0, 455 sc->memmap[ASPEED_DEV_SDMC]); 456 457 /* Watch dog */ 458 for (i = 0; i < sc->wdts_num; i++) { 459 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); 460 461 object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu), 462 &error_abort); 463 if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { 464 return; 465 } 466 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, 467 sc->memmap[ASPEED_DEV_WDT] + i * awc->offset); 468 } 469 470 /* RAM */ 471 if (!aspeed_soc_dram_init(s, errp)) { 472 return; 473 } 474 475 /* Net */ 476 for (i = 0; i < sc->macs_num; i++) { 477 object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true, 478 &error_abort); 479 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) { 480 return; 481 } 482 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 483 sc->memmap[ASPEED_DEV_ETH1 + i]); 484 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 485 aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i)); 486 487 object_property_set_link(OBJECT(&s->mii[i]), "nic", 488 OBJECT(&s->ftgmac100[i]), &error_abort); 489 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mii[i]), errp)) { 490 return; 491 } 492 493 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->mii[i]), 0, 494 sc->memmap[ASPEED_DEV_MII1 + i]); 495 } 496 497 /* XDMA */ 498 if (!sysbus_realize(SYS_BUS_DEVICE(&s->xdma), errp)) { 499 return; 500 } 501 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->xdma), 0, 502 sc->memmap[ASPEED_DEV_XDMA]); 503 sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0, 504 aspeed_soc_get_irq(s, ASPEED_DEV_XDMA)); 505 506 /* GPIO */ 507 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { 508 return; 509 } 510 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_DEV_GPIO]); 511 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, 512 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO)); 513 514 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio_1_8v), errp)) { 515 return; 516 } 517 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio_1_8v), 0, 518 sc->memmap[ASPEED_DEV_GPIO_1_8V]); 519 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio_1_8v), 0, 520 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO_1_8V)); 521 522 /* SDHCI */ 523 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) { 524 return; 525 } 526 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdhci), 0, 527 sc->memmap[ASPEED_DEV_SDHCI]); 528 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, 529 aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI)); 530 531 /* eMMC */ 532 if (!sysbus_realize(SYS_BUS_DEVICE(&s->emmc), errp)) { 533 return; 534 } 535 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->emmc), 0, 536 sc->memmap[ASPEED_DEV_EMMC]); 537 sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0, 538 aspeed_soc_get_irq(s, ASPEED_DEV_EMMC)); 539 540 /* LPC */ 541 if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) { 542 return; 543 } 544 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]); 545 546 /* Connect the LPC IRQ to the GIC. It is otherwise unused. */ 547 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0, 548 aspeed_soc_get_irq(s, ASPEED_DEV_LPC)); 549 550 /* 551 * On the AST2600 LPC subdevice IRQs are connected straight to the GIC. 552 * 553 * LPC subdevice IRQ sources are offset from 1 because the LPC model caters 554 * to the AST2400 and AST2500. SoCs before the AST2600 have one LPC IRQ 555 * shared across the subdevices, and the shared IRQ output to the VIC is at 556 * offset 0. 557 */ 558 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1, 559 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 560 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1)); 561 562 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2, 563 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 564 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2)); 565 566 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3, 567 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 568 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3)); 569 570 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4, 571 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 572 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4)); 573 574 /* HACE */ 575 object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(s->dram_mr), 576 &error_abort); 577 if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) { 578 return; 579 } 580 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->hace), 0, 581 sc->memmap[ASPEED_DEV_HACE]); 582 sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0, 583 aspeed_soc_get_irq(s, ASPEED_DEV_HACE)); 584 585 /* I3C */ 586 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i3c), errp)) { 587 return; 588 } 589 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i3c), 0, sc->memmap[ASPEED_DEV_I3C]); 590 for (i = 0; i < ASPEED_I3C_NR_DEVICES; i++) { 591 qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), 592 sc->irqmap[ASPEED_DEV_I3C] + i); 593 /* The AST2600 I3C controller has one IRQ per bus. */ 594 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq); 595 } 596 597 /* Secure Boot Controller */ 598 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sbc), errp)) { 599 return; 600 } 601 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sbc), 0, sc->memmap[ASPEED_DEV_SBC]); 602 } 603 604 static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) 605 { 606 DeviceClass *dc = DEVICE_CLASS(oc); 607 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); 608 609 dc->realize = aspeed_soc_ast2600_realize; 610 611 sc->name = "ast2600-a3"; 612 sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7"); 613 sc->silicon_rev = AST2600_A3_SILICON_REV; 614 sc->sram_size = 0x16400; 615 sc->spis_num = 2; 616 sc->ehcis_num = 2; 617 sc->wdts_num = 4; 618 sc->macs_num = 4; 619 sc->uarts_num = 13; 620 sc->irqmap = aspeed_soc_ast2600_irqmap; 621 sc->memmap = aspeed_soc_ast2600_memmap; 622 sc->num_cpus = 2; 623 sc->get_irq = aspeed_soc_ast2600_get_irq; 624 } 625 626 static const TypeInfo aspeed_soc_ast2600_type_info = { 627 .name = "ast2600-a3", 628 .parent = TYPE_ASPEED_SOC, 629 .instance_size = sizeof(AspeedSoCState), 630 .instance_init = aspeed_soc_ast2600_init, 631 .class_init = aspeed_soc_ast2600_class_init, 632 .class_size = sizeof(AspeedSoCClass), 633 }; 634 635 static void aspeed_soc_register_types(void) 636 { 637 type_register_static(&aspeed_soc_ast2600_type_info); 638 }; 639 640 type_init(aspeed_soc_register_types) 641