1 /* 2 * ASPEED SoC 2600 family 3 * 4 * Copyright (c) 2016-2019, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See 7 * the COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qapi/error.h" 12 #include "hw/misc/unimp.h" 13 #include "hw/arm/aspeed_soc.h" 14 #include "qemu/module.h" 15 #include "qemu/error-report.h" 16 #include "hw/i2c/aspeed_i2c.h" 17 #include "net/net.h" 18 #include "sysemu/sysemu.h" 19 20 #define ASPEED_SOC_IOMEM_SIZE 0x00200000 21 #define ASPEED_SOC_DPMCU_SIZE 0x00040000 22 23 static const hwaddr aspeed_soc_ast2600_memmap[] = { 24 [ASPEED_DEV_SRAM] = 0x10000000, 25 [ASPEED_DEV_DPMCU] = 0x18000000, 26 /* 0x16000000 0x17FFFFFF : AHB BUS do LPC Bus bridge */ 27 [ASPEED_DEV_IOMEM] = 0x1E600000, 28 [ASPEED_DEV_PWM] = 0x1E610000, 29 [ASPEED_DEV_FMC] = 0x1E620000, 30 [ASPEED_DEV_SPI1] = 0x1E630000, 31 [ASPEED_DEV_SPI2] = 0x1E631000, 32 [ASPEED_DEV_EHCI1] = 0x1E6A1000, 33 [ASPEED_DEV_EHCI2] = 0x1E6A3000, 34 [ASPEED_DEV_MII1] = 0x1E650000, 35 [ASPEED_DEV_MII2] = 0x1E650008, 36 [ASPEED_DEV_MII3] = 0x1E650010, 37 [ASPEED_DEV_MII4] = 0x1E650018, 38 [ASPEED_DEV_ETH1] = 0x1E660000, 39 [ASPEED_DEV_ETH3] = 0x1E670000, 40 [ASPEED_DEV_ETH2] = 0x1E680000, 41 [ASPEED_DEV_ETH4] = 0x1E690000, 42 [ASPEED_DEV_VIC] = 0x1E6C0000, 43 [ASPEED_DEV_HACE] = 0x1E6D0000, 44 [ASPEED_DEV_SDMC] = 0x1E6E0000, 45 [ASPEED_DEV_SCU] = 0x1E6E2000, 46 [ASPEED_DEV_XDMA] = 0x1E6E7000, 47 [ASPEED_DEV_ADC] = 0x1E6E9000, 48 [ASPEED_DEV_DP] = 0x1E6EB000, 49 [ASPEED_DEV_SBC] = 0x1E6F2000, 50 [ASPEED_DEV_EMMC_BC] = 0x1E6f5000, 51 [ASPEED_DEV_VIDEO] = 0x1E700000, 52 [ASPEED_DEV_SDHCI] = 0x1E740000, 53 [ASPEED_DEV_EMMC] = 0x1E750000, 54 [ASPEED_DEV_GPIO] = 0x1E780000, 55 [ASPEED_DEV_GPIO_1_8V] = 0x1E780800, 56 [ASPEED_DEV_RTC] = 0x1E781000, 57 [ASPEED_DEV_TIMER1] = 0x1E782000, 58 [ASPEED_DEV_WDT] = 0x1E785000, 59 [ASPEED_DEV_LPC] = 0x1E789000, 60 [ASPEED_DEV_IBT] = 0x1E789140, 61 [ASPEED_DEV_I2C] = 0x1E78A000, 62 [ASPEED_DEV_UART1] = 0x1E783000, 63 [ASPEED_DEV_UART2] = 0x1E78D000, 64 [ASPEED_DEV_UART3] = 0x1E78E000, 65 [ASPEED_DEV_UART4] = 0x1E78F000, 66 [ASPEED_DEV_UART5] = 0x1E784000, 67 [ASPEED_DEV_UART6] = 0x1E790000, 68 [ASPEED_DEV_UART7] = 0x1E790100, 69 [ASPEED_DEV_UART8] = 0x1E790200, 70 [ASPEED_DEV_UART9] = 0x1E790300, 71 [ASPEED_DEV_UART10] = 0x1E790400, 72 [ASPEED_DEV_UART11] = 0x1E790500, 73 [ASPEED_DEV_UART12] = 0x1E790600, 74 [ASPEED_DEV_UART13] = 0x1E790700, 75 [ASPEED_DEV_VUART] = 0x1E787000, 76 [ASPEED_DEV_I3C] = 0x1E7A0000, 77 [ASPEED_DEV_SDRAM] = 0x80000000, 78 }; 79 80 #define ASPEED_A7MPCORE_ADDR 0x40460000 81 82 #define AST2600_MAX_IRQ 197 83 84 /* Shared Peripheral Interrupt values below are offset by -32 from datasheet */ 85 static const int aspeed_soc_ast2600_irqmap[] = { 86 [ASPEED_DEV_UART1] = 47, 87 [ASPEED_DEV_UART2] = 48, 88 [ASPEED_DEV_UART3] = 49, 89 [ASPEED_DEV_UART4] = 50, 90 [ASPEED_DEV_UART5] = 8, 91 [ASPEED_DEV_UART6] = 57, 92 [ASPEED_DEV_UART7] = 58, 93 [ASPEED_DEV_UART8] = 59, 94 [ASPEED_DEV_UART9] = 60, 95 [ASPEED_DEV_UART10] = 61, 96 [ASPEED_DEV_UART11] = 62, 97 [ASPEED_DEV_UART12] = 63, 98 [ASPEED_DEV_UART13] = 64, 99 [ASPEED_DEV_VUART] = 8, 100 [ASPEED_DEV_FMC] = 39, 101 [ASPEED_DEV_SDMC] = 0, 102 [ASPEED_DEV_SCU] = 12, 103 [ASPEED_DEV_ADC] = 78, 104 [ASPEED_DEV_XDMA] = 6, 105 [ASPEED_DEV_SDHCI] = 43, 106 [ASPEED_DEV_EHCI1] = 5, 107 [ASPEED_DEV_EHCI2] = 9, 108 [ASPEED_DEV_EMMC] = 15, 109 [ASPEED_DEV_GPIO] = 40, 110 [ASPEED_DEV_GPIO_1_8V] = 11, 111 [ASPEED_DEV_RTC] = 13, 112 [ASPEED_DEV_TIMER1] = 16, 113 [ASPEED_DEV_TIMER2] = 17, 114 [ASPEED_DEV_TIMER3] = 18, 115 [ASPEED_DEV_TIMER4] = 19, 116 [ASPEED_DEV_TIMER5] = 20, 117 [ASPEED_DEV_TIMER6] = 21, 118 [ASPEED_DEV_TIMER7] = 22, 119 [ASPEED_DEV_TIMER8] = 23, 120 [ASPEED_DEV_WDT] = 24, 121 [ASPEED_DEV_PWM] = 44, 122 [ASPEED_DEV_LPC] = 35, 123 [ASPEED_DEV_IBT] = 143, 124 [ASPEED_DEV_I2C] = 110, /* 110 -> 125 */ 125 [ASPEED_DEV_ETH1] = 2, 126 [ASPEED_DEV_ETH2] = 3, 127 [ASPEED_DEV_HACE] = 4, 128 [ASPEED_DEV_ETH3] = 32, 129 [ASPEED_DEV_ETH4] = 33, 130 [ASPEED_DEV_KCS] = 138, /* 138 -> 142 */ 131 [ASPEED_DEV_DP] = 62, 132 [ASPEED_DEV_I3C] = 102, /* 102 -> 107 */ 133 }; 134 135 static qemu_irq aspeed_soc_ast2600_get_irq(AspeedSoCState *s, int dev) 136 { 137 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 138 139 return qdev_get_gpio_in(DEVICE(&s->a7mpcore), sc->irqmap[dev]); 140 } 141 142 static void aspeed_soc_ast2600_init(Object *obj) 143 { 144 AspeedSoCState *s = ASPEED_SOC(obj); 145 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 146 int i; 147 char socname[8]; 148 char typename[64]; 149 150 if (sscanf(sc->name, "%7s", socname) != 1) { 151 g_assert_not_reached(); 152 } 153 154 for (i = 0; i < sc->num_cpus; i++) { 155 object_initialize_child(obj, "cpu[*]", &s->cpu[i], sc->cpu_type); 156 } 157 158 snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname); 159 object_initialize_child(obj, "scu", &s->scu, typename); 160 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", 161 sc->silicon_rev); 162 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), 163 "hw-strap1"); 164 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), 165 "hw-strap2"); 166 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), 167 "hw-prot-key"); 168 169 object_initialize_child(obj, "a7mpcore", &s->a7mpcore, 170 TYPE_A15MPCORE_PRIV); 171 172 object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC); 173 174 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); 175 object_initialize_child(obj, "timerctrl", &s->timerctrl, typename); 176 177 snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname); 178 object_initialize_child(obj, "adc", &s->adc, typename); 179 180 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); 181 object_initialize_child(obj, "i2c", &s->i2c, typename); 182 183 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); 184 object_initialize_child(obj, "fmc", &s->fmc, typename); 185 186 for (i = 0; i < sc->spis_num; i++) { 187 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname); 188 object_initialize_child(obj, "spi[*]", &s->spi[i], typename); 189 } 190 191 for (i = 0; i < sc->ehcis_num; i++) { 192 object_initialize_child(obj, "ehci[*]", &s->ehci[i], 193 TYPE_PLATFORM_EHCI); 194 } 195 196 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname); 197 object_initialize_child(obj, "sdmc", &s->sdmc, typename); 198 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), 199 "ram-size"); 200 201 for (i = 0; i < sc->wdts_num; i++) { 202 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); 203 object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename); 204 } 205 206 for (i = 0; i < sc->macs_num; i++) { 207 object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i], 208 TYPE_FTGMAC100); 209 210 object_initialize_child(obj, "mii[*]", &s->mii[i], TYPE_ASPEED_MII); 211 } 212 213 snprintf(typename, sizeof(typename), TYPE_ASPEED_XDMA "-%s", socname); 214 object_initialize_child(obj, "xdma", &s->xdma, typename); 215 216 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); 217 object_initialize_child(obj, "gpio", &s->gpio, typename); 218 219 snprintf(typename, sizeof(typename), "aspeed.gpio-%s-1_8v", socname); 220 object_initialize_child(obj, "gpio_1_8v", &s->gpio_1_8v, typename); 221 222 object_initialize_child(obj, "sd-controller", &s->sdhci, 223 TYPE_ASPEED_SDHCI); 224 225 object_property_set_int(OBJECT(&s->sdhci), "num-slots", 2, &error_abort); 226 227 /* Init sd card slot class here so that they're under the correct parent */ 228 for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { 229 object_initialize_child(obj, "sd-controller.sdhci[*]", 230 &s->sdhci.slots[i], TYPE_SYSBUS_SDHCI); 231 } 232 233 object_initialize_child(obj, "emmc-controller", &s->emmc, 234 TYPE_ASPEED_SDHCI); 235 236 object_property_set_int(OBJECT(&s->emmc), "num-slots", 1, &error_abort); 237 238 object_initialize_child(obj, "emmc-controller.sdhci", &s->emmc.slots[0], 239 TYPE_SYSBUS_SDHCI); 240 241 object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC); 242 243 snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname); 244 object_initialize_child(obj, "hace", &s->hace, typename); 245 246 object_initialize_child(obj, "i3c", &s->i3c, TYPE_ASPEED_I3C); 247 248 object_initialize_child(obj, "sbc", &s->sbc, TYPE_ASPEED_SBC); 249 } 250 251 /* 252 * ASPEED ast2600 has 0xf as cluster ID 253 * 254 * https://developer.arm.com/documentation/ddi0388/e/the-system-control-coprocessors/summary-of-system-control-coprocessor-registers/multiprocessor-affinity-register 255 */ 256 static uint64_t aspeed_calc_affinity(int cpu) 257 { 258 return (0xf << ARM_AFF1_SHIFT) | cpu; 259 } 260 261 static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) 262 { 263 int i; 264 AspeedSoCState *s = ASPEED_SOC(dev); 265 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 266 Error *err = NULL; 267 qemu_irq irq; 268 269 /* IO space */ 270 create_unimplemented_device("aspeed_soc.io", sc->memmap[ASPEED_DEV_IOMEM], 271 ASPEED_SOC_IOMEM_SIZE); 272 273 /* Video engine stub */ 274 create_unimplemented_device("aspeed.video", sc->memmap[ASPEED_DEV_VIDEO], 275 0x1000); 276 277 /* eMMC Boot Controller stub */ 278 create_unimplemented_device("aspeed.emmc-boot-controller", 279 sc->memmap[ASPEED_DEV_EMMC_BC], 280 0x1000); 281 282 /* CPU */ 283 for (i = 0; i < sc->num_cpus; i++) { 284 if (sc->num_cpus > 1) { 285 object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar", 286 ASPEED_A7MPCORE_ADDR, &error_abort); 287 } 288 object_property_set_int(OBJECT(&s->cpu[i]), "mp-affinity", 289 aspeed_calc_affinity(i), &error_abort); 290 291 object_property_set_int(OBJECT(&s->cpu[i]), "cntfrq", 1125000000, 292 &error_abort); 293 294 if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) { 295 return; 296 } 297 } 298 299 /* A7MPCORE */ 300 object_property_set_int(OBJECT(&s->a7mpcore), "num-cpu", sc->num_cpus, 301 &error_abort); 302 object_property_set_int(OBJECT(&s->a7mpcore), "num-irq", 303 ROUND_UP(AST2600_MAX_IRQ + GIC_INTERNAL, 32), 304 &error_abort); 305 306 sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort); 307 sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, ASPEED_A7MPCORE_ADDR); 308 309 for (i = 0; i < sc->num_cpus; i++) { 310 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore); 311 DeviceState *d = DEVICE(qemu_get_cpu(i)); 312 313 irq = qdev_get_gpio_in(d, ARM_CPU_IRQ); 314 sysbus_connect_irq(sbd, i, irq); 315 irq = qdev_get_gpio_in(d, ARM_CPU_FIQ); 316 sysbus_connect_irq(sbd, i + sc->num_cpus, irq); 317 irq = qdev_get_gpio_in(d, ARM_CPU_VIRQ); 318 sysbus_connect_irq(sbd, i + 2 * sc->num_cpus, irq); 319 irq = qdev_get_gpio_in(d, ARM_CPU_VFIQ); 320 sysbus_connect_irq(sbd, i + 3 * sc->num_cpus, irq); 321 } 322 323 /* SRAM */ 324 memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram", 325 sc->sram_size, &err); 326 if (err) { 327 error_propagate(errp, err); 328 return; 329 } 330 memory_region_add_subregion(get_system_memory(), 331 sc->memmap[ASPEED_DEV_SRAM], &s->sram); 332 333 /* DPMCU */ 334 create_unimplemented_device("aspeed.dpmcu", sc->memmap[ASPEED_DEV_DPMCU], 335 ASPEED_SOC_DPMCU_SIZE); 336 337 /* SCU */ 338 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { 339 return; 340 } 341 sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]); 342 343 /* RTC */ 344 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) { 345 return; 346 } 347 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]); 348 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, 349 aspeed_soc_get_irq(s, ASPEED_DEV_RTC)); 350 351 /* Timer */ 352 object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), 353 &error_abort); 354 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) { 355 return; 356 } 357 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0, 358 sc->memmap[ASPEED_DEV_TIMER1]); 359 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { 360 qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i); 361 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); 362 } 363 364 /* ADC */ 365 if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) { 366 return; 367 } 368 sysbus_mmio_map(SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]); 369 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, 370 aspeed_soc_get_irq(s, ASPEED_DEV_ADC)); 371 372 /* UART */ 373 aspeed_soc_uart_init(s); 374 375 /* I2C */ 376 object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr), 377 &error_abort); 378 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) { 379 return; 380 } 381 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]); 382 for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) { 383 qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), 384 sc->irqmap[ASPEED_DEV_I2C] + i); 385 /* The AST2600 I2C controller has one IRQ per bus. */ 386 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq); 387 } 388 389 /* FMC, The number of CS is set at the board level */ 390 object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr), 391 &error_abort); 392 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) { 393 return; 394 } 395 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]); 396 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1, 397 ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base); 398 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, 399 aspeed_soc_get_irq(s, ASPEED_DEV_FMC)); 400 401 /* SPI */ 402 for (i = 0; i < sc->spis_num; i++) { 403 object_property_set_link(OBJECT(&s->spi[i]), "dram", 404 OBJECT(s->dram_mr), &error_abort); 405 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { 406 return; 407 } 408 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, 409 sc->memmap[ASPEED_DEV_SPI1 + i]); 410 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1, 411 ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base); 412 } 413 414 /* EHCI */ 415 for (i = 0; i < sc->ehcis_num; i++) { 416 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) { 417 return; 418 } 419 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0, 420 sc->memmap[ASPEED_DEV_EHCI1 + i]); 421 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, 422 aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i)); 423 } 424 425 /* SDMC - SDRAM Memory Controller */ 426 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) { 427 return; 428 } 429 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->memmap[ASPEED_DEV_SDMC]); 430 431 /* Watch dog */ 432 for (i = 0; i < sc->wdts_num; i++) { 433 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); 434 435 object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu), 436 &error_abort); 437 if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { 438 return; 439 } 440 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, 441 sc->memmap[ASPEED_DEV_WDT] + i * awc->offset); 442 } 443 444 /* RAM */ 445 if (!aspeed_soc_dram_init(s, errp)) { 446 return; 447 } 448 449 /* Net */ 450 for (i = 0; i < sc->macs_num; i++) { 451 object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true, 452 &error_abort); 453 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) { 454 return; 455 } 456 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 457 sc->memmap[ASPEED_DEV_ETH1 + i]); 458 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 459 aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i)); 460 461 object_property_set_link(OBJECT(&s->mii[i]), "nic", 462 OBJECT(&s->ftgmac100[i]), &error_abort); 463 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mii[i]), errp)) { 464 return; 465 } 466 467 sysbus_mmio_map(SYS_BUS_DEVICE(&s->mii[i]), 0, 468 sc->memmap[ASPEED_DEV_MII1 + i]); 469 } 470 471 /* XDMA */ 472 if (!sysbus_realize(SYS_BUS_DEVICE(&s->xdma), errp)) { 473 return; 474 } 475 sysbus_mmio_map(SYS_BUS_DEVICE(&s->xdma), 0, 476 sc->memmap[ASPEED_DEV_XDMA]); 477 sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0, 478 aspeed_soc_get_irq(s, ASPEED_DEV_XDMA)); 479 480 /* GPIO */ 481 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { 482 return; 483 } 484 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_DEV_GPIO]); 485 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, 486 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO)); 487 488 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio_1_8v), errp)) { 489 return; 490 } 491 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio_1_8v), 0, 492 sc->memmap[ASPEED_DEV_GPIO_1_8V]); 493 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio_1_8v), 0, 494 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO_1_8V)); 495 496 /* SDHCI */ 497 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) { 498 return; 499 } 500 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0, 501 sc->memmap[ASPEED_DEV_SDHCI]); 502 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, 503 aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI)); 504 505 /* eMMC */ 506 if (!sysbus_realize(SYS_BUS_DEVICE(&s->emmc), errp)) { 507 return; 508 } 509 sysbus_mmio_map(SYS_BUS_DEVICE(&s->emmc), 0, sc->memmap[ASPEED_DEV_EMMC]); 510 sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0, 511 aspeed_soc_get_irq(s, ASPEED_DEV_EMMC)); 512 513 /* LPC */ 514 if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) { 515 return; 516 } 517 sysbus_mmio_map(SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]); 518 519 /* Connect the LPC IRQ to the GIC. It is otherwise unused. */ 520 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0, 521 aspeed_soc_get_irq(s, ASPEED_DEV_LPC)); 522 523 /* 524 * On the AST2600 LPC subdevice IRQs are connected straight to the GIC. 525 * 526 * LPC subdevice IRQ sources are offset from 1 because the LPC model caters 527 * to the AST2400 and AST2500. SoCs before the AST2600 have one LPC IRQ 528 * shared across the subdevices, and the shared IRQ output to the VIC is at 529 * offset 0. 530 */ 531 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1, 532 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 533 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1)); 534 535 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2, 536 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 537 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2)); 538 539 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3, 540 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 541 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3)); 542 543 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4, 544 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 545 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4)); 546 547 /* HACE */ 548 object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(s->dram_mr), 549 &error_abort); 550 if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) { 551 return; 552 } 553 sysbus_mmio_map(SYS_BUS_DEVICE(&s->hace), 0, sc->memmap[ASPEED_DEV_HACE]); 554 sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0, 555 aspeed_soc_get_irq(s, ASPEED_DEV_HACE)); 556 557 /* I3C */ 558 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i3c), errp)) { 559 return; 560 } 561 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i3c), 0, sc->memmap[ASPEED_DEV_I3C]); 562 for (i = 0; i < ASPEED_I3C_NR_DEVICES; i++) { 563 qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), 564 sc->irqmap[ASPEED_DEV_I3C] + i); 565 /* The AST2600 I3C controller has one IRQ per bus. */ 566 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq); 567 } 568 569 /* Secure Boot Controller */ 570 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sbc), errp)) { 571 return; 572 } 573 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sbc), 0, sc->memmap[ASPEED_DEV_SBC]); 574 } 575 576 static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) 577 { 578 DeviceClass *dc = DEVICE_CLASS(oc); 579 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); 580 581 dc->realize = aspeed_soc_ast2600_realize; 582 583 sc->name = "ast2600-a3"; 584 sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7"); 585 sc->silicon_rev = AST2600_A3_SILICON_REV; 586 sc->sram_size = 0x16400; 587 sc->spis_num = 2; 588 sc->ehcis_num = 2; 589 sc->wdts_num = 4; 590 sc->macs_num = 4; 591 sc->uarts_num = 13; 592 sc->irqmap = aspeed_soc_ast2600_irqmap; 593 sc->memmap = aspeed_soc_ast2600_memmap; 594 sc->num_cpus = 2; 595 sc->get_irq = aspeed_soc_ast2600_get_irq; 596 } 597 598 static const TypeInfo aspeed_soc_ast2600_type_info = { 599 .name = "ast2600-a3", 600 .parent = TYPE_ASPEED_SOC, 601 .instance_size = sizeof(AspeedSoCState), 602 .instance_init = aspeed_soc_ast2600_init, 603 .class_init = aspeed_soc_ast2600_class_init, 604 .class_size = sizeof(AspeedSoCClass), 605 }; 606 607 static void aspeed_soc_register_types(void) 608 { 609 type_register_static(&aspeed_soc_ast2600_type_info); 610 }; 611 612 type_init(aspeed_soc_register_types) 613