1 /* 2 * ASPEED SoC 2600 family 3 * 4 * Copyright (c) 2016-2019, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See 7 * the COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qapi/error.h" 12 #include "cpu.h" 13 #include "exec/address-spaces.h" 14 #include "hw/misc/unimp.h" 15 #include "hw/arm/aspeed_soc.h" 16 #include "hw/char/serial.h" 17 #include "qemu/log.h" 18 #include "qemu/module.h" 19 #include "qemu/error-report.h" 20 #include "hw/i2c/aspeed_i2c.h" 21 #include "net/net.h" 22 #include "sysemu/sysemu.h" 23 24 #define ASPEED_SOC_IOMEM_SIZE 0x00200000 25 26 static const hwaddr aspeed_soc_ast2600_memmap[] = { 27 [ASPEED_SRAM] = 0x10000000, 28 /* 0x16000000 0x17FFFFFF : AHB BUS do LPC Bus bridge */ 29 [ASPEED_IOMEM] = 0x1E600000, 30 [ASPEED_PWM] = 0x1E610000, 31 [ASPEED_FMC] = 0x1E620000, 32 [ASPEED_SPI1] = 0x1E630000, 33 [ASPEED_SPI2] = 0x1E641000, 34 [ASPEED_MII1] = 0x1E650000, 35 [ASPEED_MII2] = 0x1E650008, 36 [ASPEED_MII3] = 0x1E650010, 37 [ASPEED_MII4] = 0x1E650018, 38 [ASPEED_ETH1] = 0x1E660000, 39 [ASPEED_ETH3] = 0x1E670000, 40 [ASPEED_ETH2] = 0x1E680000, 41 [ASPEED_ETH4] = 0x1E690000, 42 [ASPEED_VIC] = 0x1E6C0000, 43 [ASPEED_SDMC] = 0x1E6E0000, 44 [ASPEED_SCU] = 0x1E6E2000, 45 [ASPEED_XDMA] = 0x1E6E7000, 46 [ASPEED_ADC] = 0x1E6E9000, 47 [ASPEED_SDHCI] = 0x1E740000, 48 [ASPEED_GPIO] = 0x1E780000, 49 [ASPEED_GPIO_1_8V] = 0x1E780800, 50 [ASPEED_RTC] = 0x1E781000, 51 [ASPEED_TIMER1] = 0x1E782000, 52 [ASPEED_WDT] = 0x1E785000, 53 [ASPEED_LPC] = 0x1E789000, 54 [ASPEED_IBT] = 0x1E789140, 55 [ASPEED_I2C] = 0x1E78A000, 56 [ASPEED_UART1] = 0x1E783000, 57 [ASPEED_UART5] = 0x1E784000, 58 [ASPEED_VUART] = 0x1E787000, 59 [ASPEED_SDRAM] = 0x80000000, 60 }; 61 62 #define ASPEED_A7MPCORE_ADDR 0x40460000 63 64 #define ASPEED_SOC_AST2600_MAX_IRQ 128 65 66 static const int aspeed_soc_ast2600_irqmap[] = { 67 [ASPEED_UART1] = 47, 68 [ASPEED_UART2] = 48, 69 [ASPEED_UART3] = 49, 70 [ASPEED_UART4] = 50, 71 [ASPEED_UART5] = 8, 72 [ASPEED_VUART] = 8, 73 [ASPEED_FMC] = 39, 74 [ASPEED_SDMC] = 0, 75 [ASPEED_SCU] = 12, 76 [ASPEED_ADC] = 78, 77 [ASPEED_XDMA] = 6, 78 [ASPEED_SDHCI] = 43, 79 [ASPEED_GPIO] = 40, 80 [ASPEED_GPIO_1_8V] = 11, 81 [ASPEED_RTC] = 13, 82 [ASPEED_TIMER1] = 16, 83 [ASPEED_TIMER2] = 17, 84 [ASPEED_TIMER3] = 18, 85 [ASPEED_TIMER4] = 19, 86 [ASPEED_TIMER5] = 20, 87 [ASPEED_TIMER6] = 21, 88 [ASPEED_TIMER7] = 22, 89 [ASPEED_TIMER8] = 23, 90 [ASPEED_WDT] = 24, 91 [ASPEED_PWM] = 44, 92 [ASPEED_LPC] = 35, 93 [ASPEED_IBT] = 35, /* LPC */ 94 [ASPEED_I2C] = 110, /* 110 -> 125 */ 95 [ASPEED_ETH1] = 2, 96 [ASPEED_ETH2] = 3, 97 [ASPEED_ETH3] = 32, 98 [ASPEED_ETH4] = 33, 99 100 }; 101 102 static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl) 103 { 104 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 105 106 return qdev_get_gpio_in(DEVICE(&s->a7mpcore), sc->irqmap[ctrl]); 107 } 108 109 static void aspeed_soc_ast2600_init(Object *obj) 110 { 111 AspeedSoCState *s = ASPEED_SOC(obj); 112 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 113 int i; 114 char socname[8]; 115 char typename[64]; 116 117 if (sscanf(sc->name, "%7s", socname) != 1) { 118 g_assert_not_reached(); 119 } 120 121 for (i = 0; i < sc->num_cpus; i++) { 122 object_initialize_child(obj, "cpu[*]", OBJECT(&s->cpu[i]), 123 sizeof(s->cpu[i]), sc->cpu_type, 124 &error_abort, NULL); 125 } 126 127 snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname); 128 sysbus_init_child_obj(obj, "scu", OBJECT(&s->scu), sizeof(s->scu), 129 typename); 130 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", 131 sc->silicon_rev); 132 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), 133 "hw-strap1", &error_abort); 134 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), 135 "hw-strap2", &error_abort); 136 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), 137 "hw-prot-key", &error_abort); 138 139 sysbus_init_child_obj(obj, "a7mpcore", &s->a7mpcore, 140 sizeof(s->a7mpcore), TYPE_A15MPCORE_PRIV); 141 142 sysbus_init_child_obj(obj, "rtc", OBJECT(&s->rtc), sizeof(s->rtc), 143 TYPE_ASPEED_RTC); 144 145 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); 146 sysbus_init_child_obj(obj, "timerctrl", OBJECT(&s->timerctrl), 147 sizeof(s->timerctrl), typename); 148 object_property_add_const_link(OBJECT(&s->timerctrl), "scu", 149 OBJECT(&s->scu), &error_abort); 150 151 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); 152 sysbus_init_child_obj(obj, "i2c", OBJECT(&s->i2c), sizeof(s->i2c), 153 typename); 154 155 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); 156 sysbus_init_child_obj(obj, "fmc", OBJECT(&s->fmc), sizeof(s->fmc), 157 typename); 158 object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs", 159 &error_abort); 160 object_property_add_alias(obj, "dram", OBJECT(&s->fmc), "dram", 161 &error_abort); 162 163 for (i = 0; i < sc->spis_num; i++) { 164 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname); 165 sysbus_init_child_obj(obj, "spi[*]", OBJECT(&s->spi[i]), 166 sizeof(s->spi[i]), typename); 167 } 168 169 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname); 170 sysbus_init_child_obj(obj, "sdmc", OBJECT(&s->sdmc), sizeof(s->sdmc), 171 typename); 172 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), 173 "ram-size", &error_abort); 174 object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc), 175 "max-ram-size", &error_abort); 176 177 for (i = 0; i < sc->wdts_num; i++) { 178 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); 179 sysbus_init_child_obj(obj, "wdt[*]", OBJECT(&s->wdt[i]), 180 sizeof(s->wdt[i]), typename); 181 object_property_add_const_link(OBJECT(&s->wdt[i]), "scu", 182 OBJECT(&s->scu), &error_abort); 183 } 184 185 for (i = 0; i < sc->macs_num; i++) { 186 sysbus_init_child_obj(obj, "ftgmac100[*]", OBJECT(&s->ftgmac100[i]), 187 sizeof(s->ftgmac100[i]), TYPE_FTGMAC100); 188 189 sysbus_init_child_obj(obj, "mii[*]", &s->mii[i], sizeof(s->mii[i]), 190 TYPE_ASPEED_MII); 191 object_property_add_const_link(OBJECT(&s->mii[i]), "nic", 192 OBJECT(&s->ftgmac100[i]), 193 &error_abort); 194 } 195 196 sysbus_init_child_obj(obj, "xdma", OBJECT(&s->xdma), sizeof(s->xdma), 197 TYPE_ASPEED_XDMA); 198 199 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); 200 sysbus_init_child_obj(obj, "gpio", OBJECT(&s->gpio), sizeof(s->gpio), 201 typename); 202 203 snprintf(typename, sizeof(typename), "aspeed.gpio-%s-1_8v", socname); 204 sysbus_init_child_obj(obj, "gpio_1_8v", OBJECT(&s->gpio_1_8v), 205 sizeof(s->gpio_1_8v), typename); 206 207 sysbus_init_child_obj(obj, "sdc", OBJECT(&s->sdhci), sizeof(s->sdhci), 208 TYPE_ASPEED_SDHCI); 209 210 /* Init sd card slot class here so that they're under the correct parent */ 211 for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { 212 sysbus_init_child_obj(obj, "sdhci[*]", OBJECT(&s->sdhci.slots[i]), 213 sizeof(s->sdhci.slots[i]), TYPE_SYSBUS_SDHCI); 214 } 215 } 216 217 /* 218 * ASPEED ast2600 has 0xf as cluster ID 219 * 220 * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0388e/CIHEBGFG.html 221 */ 222 static uint64_t aspeed_calc_affinity(int cpu) 223 { 224 return (0xf << ARM_AFF1_SHIFT) | cpu; 225 } 226 227 static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) 228 { 229 int i; 230 AspeedSoCState *s = ASPEED_SOC(dev); 231 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 232 Error *err = NULL, *local_err = NULL; 233 qemu_irq irq; 234 235 /* IO space */ 236 create_unimplemented_device("aspeed_soc.io", sc->memmap[ASPEED_IOMEM], 237 ASPEED_SOC_IOMEM_SIZE); 238 239 if (s->num_cpus > sc->num_cpus) { 240 warn_report("%s: invalid number of CPUs %d, using default %d", 241 sc->name, s->num_cpus, sc->num_cpus); 242 s->num_cpus = sc->num_cpus; 243 } 244 245 /* CPU */ 246 for (i = 0; i < s->num_cpus; i++) { 247 object_property_set_int(OBJECT(&s->cpu[i]), QEMU_PSCI_CONDUIT_SMC, 248 "psci-conduit", &error_abort); 249 if (s->num_cpus > 1) { 250 object_property_set_int(OBJECT(&s->cpu[i]), 251 ASPEED_A7MPCORE_ADDR, 252 "reset-cbar", &error_abort); 253 } 254 object_property_set_int(OBJECT(&s->cpu[i]), aspeed_calc_affinity(i), 255 "mp-affinity", &error_abort); 256 257 /* 258 * TODO: the secondary CPUs are started and a boot helper 259 * is needed when using -kernel 260 */ 261 262 object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err); 263 if (err) { 264 error_propagate(errp, err); 265 return; 266 } 267 } 268 269 /* A7MPCORE */ 270 object_property_set_int(OBJECT(&s->a7mpcore), s->num_cpus, "num-cpu", 271 &error_abort); 272 object_property_set_int(OBJECT(&s->a7mpcore), 273 ASPEED_SOC_AST2600_MAX_IRQ + GIC_INTERNAL, 274 "num-irq", &error_abort); 275 276 object_property_set_bool(OBJECT(&s->a7mpcore), true, "realized", 277 &error_abort); 278 sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, ASPEED_A7MPCORE_ADDR); 279 280 for (i = 0; i < s->num_cpus; i++) { 281 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore); 282 DeviceState *d = DEVICE(qemu_get_cpu(i)); 283 284 irq = qdev_get_gpio_in(d, ARM_CPU_IRQ); 285 sysbus_connect_irq(sbd, i, irq); 286 irq = qdev_get_gpio_in(d, ARM_CPU_FIQ); 287 sysbus_connect_irq(sbd, i + s->num_cpus, irq); 288 irq = qdev_get_gpio_in(d, ARM_CPU_VIRQ); 289 sysbus_connect_irq(sbd, i + 2 * s->num_cpus, irq); 290 irq = qdev_get_gpio_in(d, ARM_CPU_VFIQ); 291 sysbus_connect_irq(sbd, i + 3 * s->num_cpus, irq); 292 } 293 294 /* SRAM */ 295 memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram", 296 sc->sram_size, &err); 297 if (err) { 298 error_propagate(errp, err); 299 return; 300 } 301 memory_region_add_subregion(get_system_memory(), 302 sc->memmap[ASPEED_SRAM], &s->sram); 303 304 /* SCU */ 305 object_property_set_bool(OBJECT(&s->scu), true, "realized", &err); 306 if (err) { 307 error_propagate(errp, err); 308 return; 309 } 310 sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_SCU]); 311 312 /* RTC */ 313 object_property_set_bool(OBJECT(&s->rtc), true, "realized", &err); 314 if (err) { 315 error_propagate(errp, err); 316 return; 317 } 318 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_RTC]); 319 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, 320 aspeed_soc_get_irq(s, ASPEED_RTC)); 321 322 /* Timer */ 323 object_property_set_bool(OBJECT(&s->timerctrl), true, "realized", &err); 324 if (err) { 325 error_propagate(errp, err); 326 return; 327 } 328 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0, 329 sc->memmap[ASPEED_TIMER1]); 330 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { 331 qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_TIMER1 + i); 332 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); 333 } 334 335 /* UART - attach an 8250 to the IO space as our UART5 */ 336 if (serial_hd(0)) { 337 qemu_irq uart5 = aspeed_soc_get_irq(s, ASPEED_UART5); 338 serial_mm_init(get_system_memory(), sc->memmap[ASPEED_UART5], 2, 339 uart5, 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN); 340 } 341 342 /* I2C */ 343 object_property_set_bool(OBJECT(&s->i2c), true, "realized", &err); 344 if (err) { 345 error_propagate(errp, err); 346 return; 347 } 348 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_I2C]); 349 for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) { 350 qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), 351 sc->irqmap[ASPEED_I2C] + i); 352 /* 353 * The AST2600 SoC has one IRQ per I2C bus. Skip the common 354 * IRQ (AST2400 and AST2500) and connect all bussses. 355 */ 356 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), i + 1, irq); 357 } 358 359 /* FMC, The number of CS is set at the board level */ 360 object_property_set_int(OBJECT(&s->fmc), sc->memmap[ASPEED_SDRAM], 361 "sdram-base", &err); 362 if (err) { 363 error_propagate(errp, err); 364 return; 365 } 366 object_property_set_bool(OBJECT(&s->fmc), true, "realized", &err); 367 if (err) { 368 error_propagate(errp, err); 369 return; 370 } 371 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_FMC]); 372 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1, 373 s->fmc.ctrl->flash_window_base); 374 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, 375 aspeed_soc_get_irq(s, ASPEED_FMC)); 376 377 /* SPI */ 378 for (i = 0; i < sc->spis_num; i++) { 379 object_property_set_int(OBJECT(&s->spi[i]), 1, "num-cs", &err); 380 object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", 381 &local_err); 382 error_propagate(&err, local_err); 383 if (err) { 384 error_propagate(errp, err); 385 return; 386 } 387 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, 388 sc->memmap[ASPEED_SPI1 + i]); 389 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1, 390 s->spi[i].ctrl->flash_window_base); 391 } 392 393 /* SDMC - SDRAM Memory Controller */ 394 object_property_set_bool(OBJECT(&s->sdmc), true, "realized", &err); 395 if (err) { 396 error_propagate(errp, err); 397 return; 398 } 399 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->memmap[ASPEED_SDMC]); 400 401 /* Watch dog */ 402 for (i = 0; i < sc->wdts_num; i++) { 403 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); 404 405 object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized", &err); 406 if (err) { 407 error_propagate(errp, err); 408 return; 409 } 410 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, 411 sc->memmap[ASPEED_WDT] + i * awc->offset); 412 } 413 414 /* Net */ 415 for (i = 0; i < nb_nics && i < sc->macs_num; i++) { 416 qdev_set_nic_properties(DEVICE(&s->ftgmac100[i]), &nd_table[i]); 417 object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "aspeed", 418 &err); 419 object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "realized", 420 &local_err); 421 error_propagate(&err, local_err); 422 if (err) { 423 error_propagate(errp, err); 424 return; 425 } 426 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 427 sc->memmap[ASPEED_ETH1 + i]); 428 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 429 aspeed_soc_get_irq(s, ASPEED_ETH1 + i)); 430 431 object_property_set_bool(OBJECT(&s->mii[i]), true, "realized", 432 &err); 433 if (err) { 434 error_propagate(errp, err); 435 return; 436 } 437 438 sysbus_mmio_map(SYS_BUS_DEVICE(&s->mii[i]), 0, 439 sc->memmap[ASPEED_MII1 + i]); 440 } 441 442 /* XDMA */ 443 object_property_set_bool(OBJECT(&s->xdma), true, "realized", &err); 444 if (err) { 445 error_propagate(errp, err); 446 return; 447 } 448 sysbus_mmio_map(SYS_BUS_DEVICE(&s->xdma), 0, 449 sc->memmap[ASPEED_XDMA]); 450 sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0, 451 aspeed_soc_get_irq(s, ASPEED_XDMA)); 452 453 /* GPIO */ 454 object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err); 455 if (err) { 456 error_propagate(errp, err); 457 return; 458 } 459 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_GPIO]); 460 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, 461 aspeed_soc_get_irq(s, ASPEED_GPIO)); 462 463 object_property_set_bool(OBJECT(&s->gpio_1_8v), true, "realized", &err); 464 if (err) { 465 error_propagate(errp, err); 466 return; 467 } 468 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio_1_8v), 0, 469 sc->memmap[ASPEED_GPIO_1_8V]); 470 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio_1_8v), 0, 471 aspeed_soc_get_irq(s, ASPEED_GPIO_1_8V)); 472 473 /* SDHCI */ 474 object_property_set_bool(OBJECT(&s->sdhci), true, "realized", &err); 475 if (err) { 476 error_propagate(errp, err); 477 return; 478 } 479 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0, 480 sc->memmap[ASPEED_SDHCI]); 481 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, 482 aspeed_soc_get_irq(s, ASPEED_SDHCI)); 483 } 484 485 static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) 486 { 487 DeviceClass *dc = DEVICE_CLASS(oc); 488 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); 489 490 dc->realize = aspeed_soc_ast2600_realize; 491 492 sc->name = "ast2600-a0"; 493 sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7"); 494 sc->silicon_rev = AST2600_A0_SILICON_REV; 495 sc->sram_size = 0x10000; 496 sc->spis_num = 2; 497 sc->wdts_num = 4; 498 sc->macs_num = 4; 499 sc->irqmap = aspeed_soc_ast2600_irqmap; 500 sc->memmap = aspeed_soc_ast2600_memmap; 501 sc->num_cpus = 2; 502 } 503 504 static const TypeInfo aspeed_soc_ast2600_type_info = { 505 .name = "ast2600-a0", 506 .parent = TYPE_ASPEED_SOC, 507 .instance_size = sizeof(AspeedSoCState), 508 .instance_init = aspeed_soc_ast2600_init, 509 .class_init = aspeed_soc_ast2600_class_init, 510 .class_size = sizeof(AspeedSoCClass), 511 }; 512 513 static void aspeed_soc_register_types(void) 514 { 515 type_register_static(&aspeed_soc_ast2600_type_info); 516 }; 517 518 type_init(aspeed_soc_register_types) 519