1 /* 2 * ASPEED SoC 2600 family 3 * 4 * Copyright (c) 2016-2019, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See 7 * the COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qapi/error.h" 12 #include "exec/address-spaces.h" 13 #include "hw/misc/unimp.h" 14 #include "hw/arm/aspeed_soc.h" 15 #include "hw/char/serial.h" 16 #include "qemu/module.h" 17 #include "qemu/error-report.h" 18 #include "hw/i2c/aspeed_i2c.h" 19 #include "net/net.h" 20 #include "sysemu/sysemu.h" 21 22 #define ASPEED_SOC_IOMEM_SIZE 0x00200000 23 24 static const hwaddr aspeed_soc_ast2600_memmap[] = { 25 [ASPEED_DEV_SRAM] = 0x10000000, 26 /* 0x16000000 0x17FFFFFF : AHB BUS do LPC Bus bridge */ 27 [ASPEED_DEV_IOMEM] = 0x1E600000, 28 [ASPEED_DEV_PWM] = 0x1E610000, 29 [ASPEED_DEV_FMC] = 0x1E620000, 30 [ASPEED_DEV_SPI1] = 0x1E630000, 31 [ASPEED_DEV_SPI2] = 0x1E641000, 32 [ASPEED_DEV_EHCI1] = 0x1E6A1000, 33 [ASPEED_DEV_EHCI2] = 0x1E6A3000, 34 [ASPEED_DEV_MII1] = 0x1E650000, 35 [ASPEED_DEV_MII2] = 0x1E650008, 36 [ASPEED_DEV_MII3] = 0x1E650010, 37 [ASPEED_DEV_MII4] = 0x1E650018, 38 [ASPEED_DEV_ETH1] = 0x1E660000, 39 [ASPEED_DEV_ETH3] = 0x1E670000, 40 [ASPEED_DEV_ETH2] = 0x1E680000, 41 [ASPEED_DEV_ETH4] = 0x1E690000, 42 [ASPEED_DEV_VIC] = 0x1E6C0000, 43 [ASPEED_DEV_SDMC] = 0x1E6E0000, 44 [ASPEED_DEV_SCU] = 0x1E6E2000, 45 [ASPEED_DEV_XDMA] = 0x1E6E7000, 46 [ASPEED_DEV_ADC] = 0x1E6E9000, 47 [ASPEED_DEV_VIDEO] = 0x1E700000, 48 [ASPEED_DEV_SDHCI] = 0x1E740000, 49 [ASPEED_DEV_EMMC] = 0x1E750000, 50 [ASPEED_DEV_GPIO] = 0x1E780000, 51 [ASPEED_DEV_GPIO_1_8V] = 0x1E780800, 52 [ASPEED_DEV_RTC] = 0x1E781000, 53 [ASPEED_DEV_TIMER1] = 0x1E782000, 54 [ASPEED_DEV_WDT] = 0x1E785000, 55 [ASPEED_DEV_LPC] = 0x1E789000, 56 [ASPEED_DEV_IBT] = 0x1E789140, 57 [ASPEED_DEV_I2C] = 0x1E78A000, 58 [ASPEED_DEV_UART1] = 0x1E783000, 59 [ASPEED_DEV_UART5] = 0x1E784000, 60 [ASPEED_DEV_VUART] = 0x1E787000, 61 [ASPEED_DEV_SDRAM] = 0x80000000, 62 }; 63 64 #define ASPEED_A7MPCORE_ADDR 0x40460000 65 66 #define AST2600_MAX_IRQ 197 67 68 /* Shared Peripheral Interrupt values below are offset by -32 from datasheet */ 69 static const int aspeed_soc_ast2600_irqmap[] = { 70 [ASPEED_DEV_UART1] = 47, 71 [ASPEED_DEV_UART2] = 48, 72 [ASPEED_DEV_UART3] = 49, 73 [ASPEED_DEV_UART4] = 50, 74 [ASPEED_DEV_UART5] = 8, 75 [ASPEED_DEV_VUART] = 8, 76 [ASPEED_DEV_FMC] = 39, 77 [ASPEED_DEV_SDMC] = 0, 78 [ASPEED_DEV_SCU] = 12, 79 [ASPEED_DEV_ADC] = 78, 80 [ASPEED_DEV_XDMA] = 6, 81 [ASPEED_DEV_SDHCI] = 43, 82 [ASPEED_DEV_EHCI1] = 5, 83 [ASPEED_DEV_EHCI2] = 9, 84 [ASPEED_DEV_EMMC] = 15, 85 [ASPEED_DEV_GPIO] = 40, 86 [ASPEED_DEV_GPIO_1_8V] = 11, 87 [ASPEED_DEV_RTC] = 13, 88 [ASPEED_DEV_TIMER1] = 16, 89 [ASPEED_DEV_TIMER2] = 17, 90 [ASPEED_DEV_TIMER3] = 18, 91 [ASPEED_DEV_TIMER4] = 19, 92 [ASPEED_DEV_TIMER5] = 20, 93 [ASPEED_DEV_TIMER6] = 21, 94 [ASPEED_DEV_TIMER7] = 22, 95 [ASPEED_DEV_TIMER8] = 23, 96 [ASPEED_DEV_WDT] = 24, 97 [ASPEED_DEV_PWM] = 44, 98 [ASPEED_DEV_LPC] = 35, 99 [ASPEED_DEV_IBT] = 143, 100 [ASPEED_DEV_I2C] = 110, /* 110 -> 125 */ 101 [ASPEED_DEV_ETH1] = 2, 102 [ASPEED_DEV_ETH2] = 3, 103 [ASPEED_DEV_ETH3] = 32, 104 [ASPEED_DEV_ETH4] = 33, 105 [ASPEED_DEV_KCS] = 138, /* 138 -> 142 */ 106 }; 107 108 static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl) 109 { 110 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 111 112 return qdev_get_gpio_in(DEVICE(&s->a7mpcore), sc->irqmap[ctrl]); 113 } 114 115 static void aspeed_soc_ast2600_init(Object *obj) 116 { 117 AspeedSoCState *s = ASPEED_SOC(obj); 118 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 119 int i; 120 char socname[8]; 121 char typename[64]; 122 123 if (sscanf(sc->name, "%7s", socname) != 1) { 124 g_assert_not_reached(); 125 } 126 127 for (i = 0; i < sc->num_cpus; i++) { 128 object_initialize_child(obj, "cpu[*]", &s->cpu[i], sc->cpu_type); 129 } 130 131 snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname); 132 object_initialize_child(obj, "scu", &s->scu, typename); 133 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", 134 sc->silicon_rev); 135 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), 136 "hw-strap1"); 137 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), 138 "hw-strap2"); 139 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), 140 "hw-prot-key"); 141 142 object_initialize_child(obj, "a7mpcore", &s->a7mpcore, 143 TYPE_A15MPCORE_PRIV); 144 145 object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC); 146 147 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); 148 object_initialize_child(obj, "timerctrl", &s->timerctrl, typename); 149 150 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); 151 object_initialize_child(obj, "i2c", &s->i2c, typename); 152 153 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); 154 object_initialize_child(obj, "fmc", &s->fmc, typename); 155 object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs"); 156 157 for (i = 0; i < sc->spis_num; i++) { 158 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname); 159 object_initialize_child(obj, "spi[*]", &s->spi[i], typename); 160 } 161 162 for (i = 0; i < sc->ehcis_num; i++) { 163 object_initialize_child(obj, "ehci[*]", &s->ehci[i], 164 TYPE_PLATFORM_EHCI); 165 } 166 167 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname); 168 object_initialize_child(obj, "sdmc", &s->sdmc, typename); 169 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), 170 "ram-size"); 171 object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc), 172 "max-ram-size"); 173 174 for (i = 0; i < sc->wdts_num; i++) { 175 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); 176 object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename); 177 } 178 179 for (i = 0; i < sc->macs_num; i++) { 180 object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i], 181 TYPE_FTGMAC100); 182 183 object_initialize_child(obj, "mii[*]", &s->mii[i], TYPE_ASPEED_MII); 184 } 185 186 object_initialize_child(obj, "xdma", &s->xdma, TYPE_ASPEED_XDMA); 187 188 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); 189 object_initialize_child(obj, "gpio", &s->gpio, typename); 190 191 snprintf(typename, sizeof(typename), "aspeed.gpio-%s-1_8v", socname); 192 object_initialize_child(obj, "gpio_1_8v", &s->gpio_1_8v, typename); 193 194 object_initialize_child(obj, "sd-controller", &s->sdhci, 195 TYPE_ASPEED_SDHCI); 196 197 object_property_set_int(OBJECT(&s->sdhci), "num-slots", 2, &error_abort); 198 199 /* Init sd card slot class here so that they're under the correct parent */ 200 for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { 201 object_initialize_child(obj, "sd-controller.sdhci[*]", 202 &s->sdhci.slots[i], TYPE_SYSBUS_SDHCI); 203 } 204 205 object_initialize_child(obj, "emmc-controller", &s->emmc, 206 TYPE_ASPEED_SDHCI); 207 208 object_property_set_int(OBJECT(&s->emmc), "num-slots", 1, &error_abort); 209 210 object_initialize_child(obj, "emmc-controller.sdhci", &s->emmc.slots[0], 211 TYPE_SYSBUS_SDHCI); 212 213 object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC); 214 } 215 216 /* 217 * ASPEED ast2600 has 0xf as cluster ID 218 * 219 * https://developer.arm.com/documentation/ddi0388/e/the-system-control-coprocessors/summary-of-system-control-coprocessor-registers/multiprocessor-affinity-register 220 */ 221 static uint64_t aspeed_calc_affinity(int cpu) 222 { 223 return (0xf << ARM_AFF1_SHIFT) | cpu; 224 } 225 226 static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) 227 { 228 int i; 229 AspeedSoCState *s = ASPEED_SOC(dev); 230 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 231 Error *err = NULL; 232 qemu_irq irq; 233 234 /* IO space */ 235 create_unimplemented_device("aspeed_soc.io", sc->memmap[ASPEED_DEV_IOMEM], 236 ASPEED_SOC_IOMEM_SIZE); 237 238 /* Video engine stub */ 239 create_unimplemented_device("aspeed.video", sc->memmap[ASPEED_DEV_VIDEO], 240 0x1000); 241 242 /* CPU */ 243 for (i = 0; i < sc->num_cpus; i++) { 244 if (sc->num_cpus > 1) { 245 object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar", 246 ASPEED_A7MPCORE_ADDR, &error_abort); 247 } 248 object_property_set_int(OBJECT(&s->cpu[i]), "mp-affinity", 249 aspeed_calc_affinity(i), &error_abort); 250 251 object_property_set_int(OBJECT(&s->cpu[i]), "cntfrq", 1125000000, 252 &error_abort); 253 254 if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) { 255 return; 256 } 257 } 258 259 /* A7MPCORE */ 260 object_property_set_int(OBJECT(&s->a7mpcore), "num-cpu", sc->num_cpus, 261 &error_abort); 262 object_property_set_int(OBJECT(&s->a7mpcore), "num-irq", 263 ROUND_UP(AST2600_MAX_IRQ + GIC_INTERNAL, 32), 264 &error_abort); 265 266 sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort); 267 sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, ASPEED_A7MPCORE_ADDR); 268 269 for (i = 0; i < sc->num_cpus; i++) { 270 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore); 271 DeviceState *d = DEVICE(qemu_get_cpu(i)); 272 273 irq = qdev_get_gpio_in(d, ARM_CPU_IRQ); 274 sysbus_connect_irq(sbd, i, irq); 275 irq = qdev_get_gpio_in(d, ARM_CPU_FIQ); 276 sysbus_connect_irq(sbd, i + sc->num_cpus, irq); 277 irq = qdev_get_gpio_in(d, ARM_CPU_VIRQ); 278 sysbus_connect_irq(sbd, i + 2 * sc->num_cpus, irq); 279 irq = qdev_get_gpio_in(d, ARM_CPU_VFIQ); 280 sysbus_connect_irq(sbd, i + 3 * sc->num_cpus, irq); 281 } 282 283 /* SRAM */ 284 memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram", 285 sc->sram_size, &err); 286 if (err) { 287 error_propagate(errp, err); 288 return; 289 } 290 memory_region_add_subregion(get_system_memory(), 291 sc->memmap[ASPEED_DEV_SRAM], &s->sram); 292 293 /* SCU */ 294 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { 295 return; 296 } 297 sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]); 298 299 /* RTC */ 300 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) { 301 return; 302 } 303 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]); 304 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, 305 aspeed_soc_get_irq(s, ASPEED_DEV_RTC)); 306 307 /* Timer */ 308 object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), 309 &error_abort); 310 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) { 311 return; 312 } 313 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0, 314 sc->memmap[ASPEED_DEV_TIMER1]); 315 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { 316 qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i); 317 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); 318 } 319 320 /* UART - attach an 8250 to the IO space as our UART5 */ 321 serial_mm_init(get_system_memory(), sc->memmap[ASPEED_DEV_UART5], 2, 322 aspeed_soc_get_irq(s, ASPEED_DEV_UART5), 323 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN); 324 325 /* I2C */ 326 object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr), 327 &error_abort); 328 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) { 329 return; 330 } 331 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]); 332 for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) { 333 qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), 334 sc->irqmap[ASPEED_DEV_I2C] + i); 335 /* 336 * The AST2600 SoC has one IRQ per I2C bus. Skip the common 337 * IRQ (AST2400 and AST2500) and connect all bussses. 338 */ 339 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), i + 1, irq); 340 } 341 342 /* FMC, The number of CS is set at the board level */ 343 object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr), 344 &error_abort); 345 if (!object_property_set_int(OBJECT(&s->fmc), "sdram-base", 346 sc->memmap[ASPEED_DEV_SDRAM], errp)) { 347 return; 348 } 349 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) { 350 return; 351 } 352 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]); 353 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1, 354 s->fmc.ctrl->flash_window_base); 355 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, 356 aspeed_soc_get_irq(s, ASPEED_DEV_FMC)); 357 358 /* SPI */ 359 for (i = 0; i < sc->spis_num; i++) { 360 object_property_set_link(OBJECT(&s->spi[i]), "dram", 361 OBJECT(s->dram_mr), &error_abort); 362 object_property_set_int(OBJECT(&s->spi[i]), "num-cs", 1, &error_abort); 363 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { 364 return; 365 } 366 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, 367 sc->memmap[ASPEED_DEV_SPI1 + i]); 368 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1, 369 s->spi[i].ctrl->flash_window_base); 370 } 371 372 /* EHCI */ 373 for (i = 0; i < sc->ehcis_num; i++) { 374 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) { 375 return; 376 } 377 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0, 378 sc->memmap[ASPEED_DEV_EHCI1 + i]); 379 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, 380 aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i)); 381 } 382 383 /* SDMC - SDRAM Memory Controller */ 384 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) { 385 return; 386 } 387 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->memmap[ASPEED_DEV_SDMC]); 388 389 /* Watch dog */ 390 for (i = 0; i < sc->wdts_num; i++) { 391 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); 392 393 object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu), 394 &error_abort); 395 if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { 396 return; 397 } 398 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, 399 sc->memmap[ASPEED_DEV_WDT] + i * awc->offset); 400 } 401 402 /* Net */ 403 for (i = 0; i < sc->macs_num; i++) { 404 object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true, 405 &error_abort); 406 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) { 407 return; 408 } 409 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 410 sc->memmap[ASPEED_DEV_ETH1 + i]); 411 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 412 aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i)); 413 414 object_property_set_link(OBJECT(&s->mii[i]), "nic", 415 OBJECT(&s->ftgmac100[i]), &error_abort); 416 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mii[i]), errp)) { 417 return; 418 } 419 420 sysbus_mmio_map(SYS_BUS_DEVICE(&s->mii[i]), 0, 421 sc->memmap[ASPEED_DEV_MII1 + i]); 422 } 423 424 /* XDMA */ 425 if (!sysbus_realize(SYS_BUS_DEVICE(&s->xdma), errp)) { 426 return; 427 } 428 sysbus_mmio_map(SYS_BUS_DEVICE(&s->xdma), 0, 429 sc->memmap[ASPEED_DEV_XDMA]); 430 sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0, 431 aspeed_soc_get_irq(s, ASPEED_DEV_XDMA)); 432 433 /* GPIO */ 434 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { 435 return; 436 } 437 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_DEV_GPIO]); 438 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, 439 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO)); 440 441 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio_1_8v), errp)) { 442 return; 443 } 444 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio_1_8v), 0, 445 sc->memmap[ASPEED_DEV_GPIO_1_8V]); 446 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio_1_8v), 0, 447 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO_1_8V)); 448 449 /* SDHCI */ 450 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) { 451 return; 452 } 453 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0, 454 sc->memmap[ASPEED_DEV_SDHCI]); 455 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, 456 aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI)); 457 458 /* eMMC */ 459 if (!sysbus_realize(SYS_BUS_DEVICE(&s->emmc), errp)) { 460 return; 461 } 462 sysbus_mmio_map(SYS_BUS_DEVICE(&s->emmc), 0, sc->memmap[ASPEED_DEV_EMMC]); 463 sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0, 464 aspeed_soc_get_irq(s, ASPEED_DEV_EMMC)); 465 466 /* LPC */ 467 if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) { 468 return; 469 } 470 sysbus_mmio_map(SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]); 471 472 /* Connect the LPC IRQ to the GIC. It is otherwise unused. */ 473 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0, 474 aspeed_soc_get_irq(s, ASPEED_DEV_LPC)); 475 476 /* 477 * On the AST2600 LPC subdevice IRQs are connected straight to the GIC. 478 * 479 * LPC subdevice IRQ sources are offset from 1 because the LPC model caters 480 * to the AST2400 and AST2500. SoCs before the AST2600 have one LPC IRQ 481 * shared across the subdevices, and the shared IRQ output to the VIC is at 482 * offset 0. 483 */ 484 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1, 485 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 486 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1)); 487 488 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2, 489 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 490 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2)); 491 492 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3, 493 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 494 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3)); 495 496 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4, 497 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 498 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4)); 499 } 500 501 static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) 502 { 503 DeviceClass *dc = DEVICE_CLASS(oc); 504 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); 505 506 dc->realize = aspeed_soc_ast2600_realize; 507 508 sc->name = "ast2600-a1"; 509 sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7"); 510 sc->silicon_rev = AST2600_A1_SILICON_REV; 511 sc->sram_size = 0x16400; 512 sc->spis_num = 2; 513 sc->ehcis_num = 2; 514 sc->wdts_num = 4; 515 sc->macs_num = 4; 516 sc->irqmap = aspeed_soc_ast2600_irqmap; 517 sc->memmap = aspeed_soc_ast2600_memmap; 518 sc->num_cpus = 2; 519 } 520 521 static const TypeInfo aspeed_soc_ast2600_type_info = { 522 .name = "ast2600-a1", 523 .parent = TYPE_ASPEED_SOC, 524 .instance_size = sizeof(AspeedSoCState), 525 .instance_init = aspeed_soc_ast2600_init, 526 .class_init = aspeed_soc_ast2600_class_init, 527 .class_size = sizeof(AspeedSoCClass), 528 }; 529 530 static void aspeed_soc_register_types(void) 531 { 532 type_register_static(&aspeed_soc_ast2600_type_info); 533 }; 534 535 type_init(aspeed_soc_register_types) 536