1 /* 2 * ASPEED SoC family 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * Jeremy Kerr <jk@ozlabs.org> 6 * 7 * Copyright 2016 IBM Corp. 8 * 9 * This code is licensed under the GPL version 2 or later. See 10 * the COPYING file in the top-level directory. 11 */ 12 13 #include "qemu/osdep.h" 14 #include "qemu/units.h" 15 #include "qapi/error.h" 16 #include "hw/misc/unimp.h" 17 #include "hw/arm/aspeed_soc.h" 18 #include "hw/char/serial-mm.h" 19 #include "qemu/module.h" 20 #include "qemu/error-report.h" 21 #include "hw/i2c/aspeed_i2c.h" 22 #include "net/net.h" 23 #include "system/system.h" 24 #include "target/arm/cpu-qom.h" 25 26 #define ASPEED_SOC_IOMEM_SIZE 0x00200000 27 28 static const hwaddr aspeed_soc_ast2400_memmap[] = { 29 [ASPEED_DEV_SPI_BOOT] = 0x00000000, 30 [ASPEED_DEV_IOMEM] = 0x1E600000, 31 [ASPEED_DEV_FMC] = 0x1E620000, 32 [ASPEED_DEV_SPI1] = 0x1E630000, 33 [ASPEED_DEV_EHCI1] = 0x1E6A1000, 34 [ASPEED_DEV_VIC] = 0x1E6C0000, 35 [ASPEED_DEV_SDMC] = 0x1E6E0000, 36 [ASPEED_DEV_SCU] = 0x1E6E2000, 37 [ASPEED_DEV_HACE] = 0x1E6E3000, 38 [ASPEED_DEV_XDMA] = 0x1E6E7000, 39 [ASPEED_DEV_VIDEO] = 0x1E700000, 40 [ASPEED_DEV_ADC] = 0x1E6E9000, 41 [ASPEED_DEV_SRAM] = 0x1E720000, 42 [ASPEED_DEV_SDHCI] = 0x1E740000, 43 [ASPEED_DEV_GPIO] = 0x1E780000, 44 [ASPEED_DEV_RTC] = 0x1E781000, 45 [ASPEED_DEV_TIMER1] = 0x1E782000, 46 [ASPEED_DEV_WDT] = 0x1E785000, 47 [ASPEED_DEV_PWM] = 0x1E786000, 48 [ASPEED_DEV_LPC] = 0x1E789000, 49 [ASPEED_DEV_IBT] = 0x1E789140, 50 [ASPEED_DEV_I2C] = 0x1E78A000, 51 [ASPEED_DEV_PECI] = 0x1E78B000, 52 [ASPEED_DEV_ETH1] = 0x1E660000, 53 [ASPEED_DEV_ETH2] = 0x1E680000, 54 [ASPEED_DEV_UART1] = 0x1E783000, 55 [ASPEED_DEV_UART2] = 0x1E78D000, 56 [ASPEED_DEV_UART3] = 0x1E78E000, 57 [ASPEED_DEV_UART4] = 0x1E78F000, 58 [ASPEED_DEV_UART5] = 0x1E784000, 59 [ASPEED_DEV_VUART] = 0x1E787000, 60 [ASPEED_DEV_SDRAM] = 0x40000000, 61 }; 62 63 static const hwaddr aspeed_soc_ast2500_memmap[] = { 64 [ASPEED_DEV_SPI_BOOT] = 0x00000000, 65 [ASPEED_DEV_IOMEM] = 0x1E600000, 66 [ASPEED_DEV_FMC] = 0x1E620000, 67 [ASPEED_DEV_SPI1] = 0x1E630000, 68 [ASPEED_DEV_SPI2] = 0x1E631000, 69 [ASPEED_DEV_EHCI1] = 0x1E6A1000, 70 [ASPEED_DEV_EHCI2] = 0x1E6A3000, 71 [ASPEED_DEV_VIC] = 0x1E6C0000, 72 [ASPEED_DEV_SDMC] = 0x1E6E0000, 73 [ASPEED_DEV_SCU] = 0x1E6E2000, 74 [ASPEED_DEV_HACE] = 0x1E6E3000, 75 [ASPEED_DEV_XDMA] = 0x1E6E7000, 76 [ASPEED_DEV_ADC] = 0x1E6E9000, 77 [ASPEED_DEV_VIDEO] = 0x1E700000, 78 [ASPEED_DEV_SRAM] = 0x1E720000, 79 [ASPEED_DEV_SDHCI] = 0x1E740000, 80 [ASPEED_DEV_GPIO] = 0x1E780000, 81 [ASPEED_DEV_RTC] = 0x1E781000, 82 [ASPEED_DEV_TIMER1] = 0x1E782000, 83 [ASPEED_DEV_WDT] = 0x1E785000, 84 [ASPEED_DEV_PWM] = 0x1E786000, 85 [ASPEED_DEV_LPC] = 0x1E789000, 86 [ASPEED_DEV_IBT] = 0x1E789140, 87 [ASPEED_DEV_I2C] = 0x1E78A000, 88 [ASPEED_DEV_PECI] = 0x1E78B000, 89 [ASPEED_DEV_ETH1] = 0x1E660000, 90 [ASPEED_DEV_ETH2] = 0x1E680000, 91 [ASPEED_DEV_UART1] = 0x1E783000, 92 [ASPEED_DEV_UART2] = 0x1E78D000, 93 [ASPEED_DEV_UART3] = 0x1E78E000, 94 [ASPEED_DEV_UART4] = 0x1E78F000, 95 [ASPEED_DEV_UART5] = 0x1E784000, 96 [ASPEED_DEV_VUART] = 0x1E787000, 97 [ASPEED_DEV_SDRAM] = 0x80000000, 98 }; 99 100 static const int aspeed_soc_ast2400_irqmap[] = { 101 [ASPEED_DEV_UART1] = 9, 102 [ASPEED_DEV_UART2] = 32, 103 [ASPEED_DEV_UART3] = 33, 104 [ASPEED_DEV_UART4] = 34, 105 [ASPEED_DEV_UART5] = 10, 106 [ASPEED_DEV_VUART] = 8, 107 [ASPEED_DEV_FMC] = 19, 108 [ASPEED_DEV_EHCI1] = 5, 109 [ASPEED_DEV_EHCI2] = 13, 110 [ASPEED_DEV_SDMC] = 0, 111 [ASPEED_DEV_SCU] = 21, 112 [ASPEED_DEV_ADC] = 31, 113 [ASPEED_DEV_GPIO] = 20, 114 [ASPEED_DEV_RTC] = 22, 115 [ASPEED_DEV_TIMER1] = 16, 116 [ASPEED_DEV_TIMER2] = 17, 117 [ASPEED_DEV_TIMER3] = 18, 118 [ASPEED_DEV_TIMER4] = 35, 119 [ASPEED_DEV_TIMER5] = 36, 120 [ASPEED_DEV_TIMER6] = 37, 121 [ASPEED_DEV_TIMER7] = 38, 122 [ASPEED_DEV_TIMER8] = 39, 123 [ASPEED_DEV_WDT] = 27, 124 [ASPEED_DEV_PWM] = 28, 125 [ASPEED_DEV_LPC] = 8, 126 [ASPEED_DEV_I2C] = 12, 127 [ASPEED_DEV_PECI] = 15, 128 [ASPEED_DEV_ETH1] = 2, 129 [ASPEED_DEV_ETH2] = 3, 130 [ASPEED_DEV_XDMA] = 6, 131 [ASPEED_DEV_SDHCI] = 26, 132 [ASPEED_DEV_HACE] = 4, 133 }; 134 135 #define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap 136 137 static qemu_irq aspeed_soc_ast2400_get_irq(AspeedSoCState *s, int dev) 138 { 139 Aspeed2400SoCState *a = ASPEED2400_SOC(s); 140 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 141 142 return qdev_get_gpio_in(DEVICE(&a->vic), sc->irqmap[dev]); 143 } 144 145 static void aspeed_ast2400_soc_init(Object *obj) 146 { 147 Aspeed2400SoCState *a = ASPEED2400_SOC(obj); 148 AspeedSoCState *s = ASPEED_SOC(obj); 149 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 150 int i; 151 char socname[8]; 152 char typename[64]; 153 154 if (sscanf(sc->name, "%7s", socname) != 1) { 155 g_assert_not_reached(); 156 } 157 158 for (i = 0; i < sc->num_cpus; i++) { 159 object_initialize_child(obj, "cpu[*]", &a->cpu[i], 160 aspeed_soc_cpu_type(sc)); 161 } 162 163 snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname); 164 object_initialize_child(obj, "scu", &s->scu, typename); 165 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", 166 sc->silicon_rev); 167 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), 168 "hw-strap1"); 169 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), 170 "hw-strap2"); 171 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), 172 "hw-prot-key"); 173 174 object_initialize_child(obj, "vic", &a->vic, TYPE_ASPEED_VIC); 175 176 object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC); 177 178 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); 179 object_initialize_child(obj, "timerctrl", &s->timerctrl, typename); 180 181 snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname); 182 object_initialize_child(obj, "adc", &s->adc, typename); 183 184 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); 185 object_initialize_child(obj, "i2c", &s->i2c, typename); 186 187 object_initialize_child(obj, "peci", &s->peci, TYPE_ASPEED_PECI); 188 189 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); 190 object_initialize_child(obj, "fmc", &s->fmc, typename); 191 192 for (i = 0; i < sc->spis_num; i++) { 193 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname); 194 object_initialize_child(obj, "spi[*]", &s->spi[i], typename); 195 } 196 197 for (i = 0; i < sc->ehcis_num; i++) { 198 object_initialize_child(obj, "ehci[*]", &s->ehci[i], 199 TYPE_PLATFORM_EHCI); 200 } 201 202 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname); 203 object_initialize_child(obj, "sdmc", &s->sdmc, typename); 204 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), 205 "ram-size"); 206 207 for (i = 0; i < sc->wdts_num; i++) { 208 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); 209 object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename); 210 } 211 212 for (i = 0; i < sc->macs_num; i++) { 213 object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i], 214 TYPE_FTGMAC100); 215 } 216 217 for (i = 0; i < sc->uarts_num; i++) { 218 object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM); 219 } 220 221 snprintf(typename, sizeof(typename), TYPE_ASPEED_XDMA "-%s", socname); 222 object_initialize_child(obj, "xdma", &s->xdma, typename); 223 224 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); 225 object_initialize_child(obj, "gpio", &s->gpio, typename); 226 227 snprintf(typename, sizeof(typename), "aspeed.sdhci-%s", socname); 228 object_initialize_child(obj, "sdc", &s->sdhci, typename); 229 230 object_property_set_int(OBJECT(&s->sdhci), "num-slots", 2, &error_abort); 231 232 /* Init sd card slot class here so that they're under the correct parent */ 233 for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { 234 object_initialize_child(obj, "sdhci[*]", &s->sdhci.slots[i], 235 TYPE_SYSBUS_SDHCI); 236 } 237 238 object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC); 239 240 snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname); 241 object_initialize_child(obj, "hace", &s->hace, typename); 242 243 object_initialize_child(obj, "iomem", &s->iomem, TYPE_UNIMPLEMENTED_DEVICE); 244 object_initialize_child(obj, "video", &s->video, TYPE_UNIMPLEMENTED_DEVICE); 245 } 246 247 static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp) 248 { 249 int i; 250 Aspeed2400SoCState *a = ASPEED2400_SOC(dev); 251 AspeedSoCState *s = ASPEED_SOC(dev); 252 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 253 g_autofree char *sram_name = NULL; 254 255 /* Default boot region (SPI memory or ROMs) */ 256 memory_region_init(&s->spi_boot_container, OBJECT(s), 257 "aspeed.spi_boot_container", 0x10000000); 258 memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SPI_BOOT], 259 &s->spi_boot_container); 260 261 /* IO space */ 262 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem), "aspeed.io", 263 sc->memmap[ASPEED_DEV_IOMEM], 264 ASPEED_SOC_IOMEM_SIZE); 265 266 /* Video engine stub */ 267 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->video), "aspeed.video", 268 sc->memmap[ASPEED_DEV_VIDEO], 0x1000); 269 270 /* CPU */ 271 for (i = 0; i < sc->num_cpus; i++) { 272 object_property_set_link(OBJECT(&a->cpu[i]), "memory", 273 OBJECT(s->memory), &error_abort); 274 if (!qdev_realize(DEVICE(&a->cpu[i]), NULL, errp)) { 275 return; 276 } 277 } 278 279 /* SRAM */ 280 sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index); 281 if (!memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, 282 errp)) { 283 return; 284 } 285 memory_region_add_subregion(s->memory, 286 sc->memmap[ASPEED_DEV_SRAM], &s->sram); 287 288 /* SCU */ 289 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { 290 return; 291 } 292 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]); 293 294 /* VIC */ 295 if (!sysbus_realize(SYS_BUS_DEVICE(&a->vic), errp)) { 296 return; 297 } 298 aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->vic), 0, sc->memmap[ASPEED_DEV_VIC]); 299 sysbus_connect_irq(SYS_BUS_DEVICE(&a->vic), 0, 300 qdev_get_gpio_in(DEVICE(&a->cpu), ARM_CPU_IRQ)); 301 sysbus_connect_irq(SYS_BUS_DEVICE(&a->vic), 1, 302 qdev_get_gpio_in(DEVICE(&a->cpu), ARM_CPU_FIQ)); 303 304 /* RTC */ 305 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) { 306 return; 307 } 308 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]); 309 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, 310 aspeed_soc_get_irq(s, ASPEED_DEV_RTC)); 311 312 /* Timer */ 313 object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), 314 &error_abort); 315 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) { 316 return; 317 } 318 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->timerctrl), 0, 319 sc->memmap[ASPEED_DEV_TIMER1]); 320 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { 321 qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i); 322 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); 323 } 324 325 /* ADC */ 326 if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) { 327 return; 328 } 329 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]); 330 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, 331 aspeed_soc_get_irq(s, ASPEED_DEV_ADC)); 332 333 /* UART */ 334 if (!aspeed_soc_uart_realize(s, errp)) { 335 return; 336 } 337 338 /* I2C */ 339 object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr), 340 &error_abort); 341 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) { 342 return; 343 } 344 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]); 345 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0, 346 aspeed_soc_get_irq(s, ASPEED_DEV_I2C)); 347 348 /* PECI */ 349 if (!sysbus_realize(SYS_BUS_DEVICE(&s->peci), errp)) { 350 return; 351 } 352 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->peci), 0, 353 sc->memmap[ASPEED_DEV_PECI]); 354 sysbus_connect_irq(SYS_BUS_DEVICE(&s->peci), 0, 355 aspeed_soc_get_irq(s, ASPEED_DEV_PECI)); 356 357 /* FMC, The number of CS is set at the board level */ 358 object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr), 359 &error_abort); 360 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) { 361 return; 362 } 363 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]); 364 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 1, 365 ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base); 366 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, 367 aspeed_soc_get_irq(s, ASPEED_DEV_FMC)); 368 369 /* Set up an alias on the FMC CE0 region (boot default) */ 370 MemoryRegion *fmc0_mmio = &s->fmc.flashes[0].mmio; 371 memory_region_init_alias(&s->spi_boot, OBJECT(s), "aspeed.spi_boot", 372 fmc0_mmio, 0, memory_region_size(fmc0_mmio)); 373 memory_region_add_subregion(&s->spi_boot_container, 0x0, &s->spi_boot); 374 375 /* SPI */ 376 for (i = 0; i < sc->spis_num; i++) { 377 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { 378 return; 379 } 380 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 0, 381 sc->memmap[ASPEED_DEV_SPI1 + i]); 382 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 1, 383 ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base); 384 } 385 386 /* EHCI */ 387 for (i = 0; i < sc->ehcis_num; i++) { 388 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) { 389 return; 390 } 391 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ehci[i]), 0, 392 sc->memmap[ASPEED_DEV_EHCI1 + i]); 393 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, 394 aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i)); 395 } 396 397 /* SDMC - SDRAM Memory Controller */ 398 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) { 399 return; 400 } 401 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdmc), 0, 402 sc->memmap[ASPEED_DEV_SDMC]); 403 404 /* Watch dog */ 405 for (i = 0; i < sc->wdts_num; i++) { 406 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); 407 hwaddr wdt_offset = sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize; 408 409 object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu), 410 &error_abort); 411 if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { 412 return; 413 } 414 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset); 415 } 416 417 /* RAM */ 418 if (!aspeed_soc_dram_init(s, errp)) { 419 return; 420 } 421 422 /* Net */ 423 for (i = 0; i < sc->macs_num; i++) { 424 object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true, 425 &error_abort); 426 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) { 427 return; 428 } 429 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 430 sc->memmap[ASPEED_DEV_ETH1 + i]); 431 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 432 aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i)); 433 } 434 435 /* XDMA */ 436 if (!sysbus_realize(SYS_BUS_DEVICE(&s->xdma), errp)) { 437 return; 438 } 439 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->xdma), 0, 440 sc->memmap[ASPEED_DEV_XDMA]); 441 sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0, 442 aspeed_soc_get_irq(s, ASPEED_DEV_XDMA)); 443 444 /* GPIO */ 445 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { 446 return; 447 } 448 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio), 0, 449 sc->memmap[ASPEED_DEV_GPIO]); 450 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, 451 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO)); 452 453 /* SDHCI */ 454 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) { 455 return; 456 } 457 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdhci), 0, 458 sc->memmap[ASPEED_DEV_SDHCI]); 459 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, 460 aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI)); 461 462 /* LPC */ 463 if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) { 464 return; 465 } 466 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]); 467 468 /* Connect the LPC IRQ to the VIC */ 469 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0, 470 aspeed_soc_get_irq(s, ASPEED_DEV_LPC)); 471 472 /* 473 * On the AST2400 and AST2500 the one LPC IRQ is shared between all of the 474 * subdevices. Connect the LPC subdevice IRQs to the LPC controller IRQ (by 475 * contrast, on the AST2600, the subdevice IRQs are connected straight to 476 * the GIC). 477 * 478 * LPC subdevice IRQ sources are offset from 1 because the shared IRQ output 479 * to the VIC is at offset 0. 480 */ 481 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1, 482 qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_1)); 483 484 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2, 485 qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_2)); 486 487 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3, 488 qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_3)); 489 490 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4, 491 qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_4)); 492 493 /* HACE */ 494 object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(s->dram_mr), 495 &error_abort); 496 if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) { 497 return; 498 } 499 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->hace), 0, 500 sc->memmap[ASPEED_DEV_HACE]); 501 sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0, 502 aspeed_soc_get_irq(s, ASPEED_DEV_HACE)); 503 } 504 505 static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data) 506 { 507 static const char * const valid_cpu_types[] = { 508 ARM_CPU_TYPE_NAME("arm926"), 509 NULL 510 }; 511 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); 512 DeviceClass *dc = DEVICE_CLASS(oc); 513 514 dc->realize = aspeed_ast2400_soc_realize; 515 /* Reason: Uses serial_hds and nd_table in realize() directly */ 516 dc->user_creatable = false; 517 518 sc->name = "ast2400-a1"; 519 sc->valid_cpu_types = valid_cpu_types; 520 sc->silicon_rev = AST2400_A1_SILICON_REV; 521 sc->sram_size = 0x8000; 522 sc->spis_num = 1; 523 sc->ehcis_num = 1; 524 sc->wdts_num = 2; 525 sc->macs_num = 2; 526 sc->uarts_num = 5; 527 sc->uarts_base = ASPEED_DEV_UART1; 528 sc->irqmap = aspeed_soc_ast2400_irqmap; 529 sc->memmap = aspeed_soc_ast2400_memmap; 530 sc->num_cpus = 1; 531 sc->get_irq = aspeed_soc_ast2400_get_irq; 532 } 533 534 static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data) 535 { 536 static const char * const valid_cpu_types[] = { 537 ARM_CPU_TYPE_NAME("arm1176"), 538 NULL 539 }; 540 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); 541 DeviceClass *dc = DEVICE_CLASS(oc); 542 543 dc->realize = aspeed_ast2400_soc_realize; 544 /* Reason: Uses serial_hds and nd_table in realize() directly */ 545 dc->user_creatable = false; 546 547 sc->name = "ast2500-a1"; 548 sc->valid_cpu_types = valid_cpu_types; 549 sc->silicon_rev = AST2500_A1_SILICON_REV; 550 sc->sram_size = 0x9000; 551 sc->spis_num = 2; 552 sc->ehcis_num = 2; 553 sc->wdts_num = 3; 554 sc->macs_num = 2; 555 sc->uarts_num = 5; 556 sc->uarts_base = ASPEED_DEV_UART1; 557 sc->irqmap = aspeed_soc_ast2500_irqmap; 558 sc->memmap = aspeed_soc_ast2500_memmap; 559 sc->num_cpus = 1; 560 sc->get_irq = aspeed_soc_ast2400_get_irq; 561 } 562 563 static const TypeInfo aspeed_soc_ast2400_types[] = { 564 { 565 .name = TYPE_ASPEED2400_SOC, 566 .parent = TYPE_ASPEED_SOC, 567 .instance_init = aspeed_ast2400_soc_init, 568 .instance_size = sizeof(Aspeed2400SoCState), 569 .abstract = true, 570 }, { 571 .name = "ast2400-a1", 572 .parent = TYPE_ASPEED2400_SOC, 573 .class_init = aspeed_soc_ast2400_class_init, 574 }, { 575 .name = "ast2500-a1", 576 .parent = TYPE_ASPEED2400_SOC, 577 .class_init = aspeed_soc_ast2500_class_init, 578 }, 579 }; 580 581 DEFINE_TYPES(aspeed_soc_ast2400_types) 582