1 /* 2 * ASPEED Ast10x0 SoC 3 * 4 * Copyright (C) 2022 ASPEED Technology Inc. 5 * 6 * This code is licensed under the GPL version 2 or later. See 7 * the COPYING file in the top-level directory. 8 * 9 * Implementation extracted from the AST2600 and adapted for Ast10x0. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "exec/address-spaces.h" 15 #include "sysemu/sysemu.h" 16 #include "hw/qdev-clock.h" 17 #include "hw/misc/unimp.h" 18 #include "hw/arm/aspeed_soc.h" 19 20 #define ASPEED_SOC_IOMEM_SIZE 0x00200000 21 22 static const hwaddr aspeed_soc_ast1030_memmap[] = { 23 [ASPEED_DEV_SRAM] = 0x00000000, 24 [ASPEED_DEV_SBC] = 0x79000000, 25 [ASPEED_DEV_IOMEM] = 0x7E600000, 26 [ASPEED_DEV_PWM] = 0x7E610000, 27 [ASPEED_DEV_FMC] = 0x7E620000, 28 [ASPEED_DEV_SPI1] = 0x7E630000, 29 [ASPEED_DEV_SPI2] = 0x7E640000, 30 [ASPEED_DEV_SCU] = 0x7E6E2000, 31 [ASPEED_DEV_ADC] = 0x7E6E9000, 32 [ASPEED_DEV_SBC] = 0x7E6F2000, 33 [ASPEED_DEV_GPIO] = 0x7E780000, 34 [ASPEED_DEV_TIMER1] = 0x7E782000, 35 [ASPEED_DEV_UART1] = 0x7E783000, 36 [ASPEED_DEV_UART2] = 0x7E78D000, 37 [ASPEED_DEV_UART3] = 0x7E78E000, 38 [ASPEED_DEV_UART4] = 0x7E78F000, 39 [ASPEED_DEV_UART5] = 0x7E784000, 40 [ASPEED_DEV_UART6] = 0x7E790000, 41 [ASPEED_DEV_UART7] = 0x7E790100, 42 [ASPEED_DEV_UART8] = 0x7E790200, 43 [ASPEED_DEV_UART9] = 0x7E790300, 44 [ASPEED_DEV_UART10] = 0x7E790400, 45 [ASPEED_DEV_UART11] = 0x7E790500, 46 [ASPEED_DEV_UART12] = 0x7E790600, 47 [ASPEED_DEV_UART13] = 0x7E790700, 48 [ASPEED_DEV_WDT] = 0x7E785000, 49 [ASPEED_DEV_LPC] = 0x7E789000, 50 [ASPEED_DEV_I2C] = 0x7E7B0000, 51 }; 52 53 static const int aspeed_soc_ast1030_irqmap[] = { 54 [ASPEED_DEV_UART1] = 47, 55 [ASPEED_DEV_UART2] = 48, 56 [ASPEED_DEV_UART3] = 49, 57 [ASPEED_DEV_UART4] = 50, 58 [ASPEED_DEV_UART5] = 8, 59 [ASPEED_DEV_UART6] = 57, 60 [ASPEED_DEV_UART7] = 58, 61 [ASPEED_DEV_UART8] = 59, 62 [ASPEED_DEV_UART9] = 60, 63 [ASPEED_DEV_UART10] = 61, 64 [ASPEED_DEV_UART11] = 62, 65 [ASPEED_DEV_UART12] = 63, 66 [ASPEED_DEV_UART13] = 64, 67 [ASPEED_DEV_GPIO] = 11, 68 [ASPEED_DEV_TIMER1] = 16, 69 [ASPEED_DEV_TIMER2] = 17, 70 [ASPEED_DEV_TIMER3] = 18, 71 [ASPEED_DEV_TIMER4] = 19, 72 [ASPEED_DEV_TIMER5] = 20, 73 [ASPEED_DEV_TIMER6] = 21, 74 [ASPEED_DEV_TIMER7] = 22, 75 [ASPEED_DEV_TIMER8] = 23, 76 [ASPEED_DEV_WDT] = 24, 77 [ASPEED_DEV_LPC] = 35, 78 [ASPEED_DEV_FMC] = 39, 79 [ASPEED_DEV_PWM] = 44, 80 [ASPEED_DEV_ADC] = 46, 81 [ASPEED_DEV_SPI1] = 65, 82 [ASPEED_DEV_SPI2] = 66, 83 [ASPEED_DEV_I2C] = 110, /* 110 ~ 123 */ 84 [ASPEED_DEV_KCS] = 138, /* 138 -> 142 */ 85 }; 86 87 static qemu_irq aspeed_soc_ast1030_get_irq(AspeedSoCState *s, int dev) 88 { 89 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 90 91 return qdev_get_gpio_in(DEVICE(&s->armv7m), sc->irqmap[dev]); 92 } 93 94 static void aspeed_soc_ast1030_init(Object *obj) 95 { 96 AspeedSoCState *s = ASPEED_SOC(obj); 97 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 98 char socname[8]; 99 char typename[64]; 100 int i; 101 102 if (sscanf(sc->name, "%7s", socname) != 1) { 103 g_assert_not_reached(); 104 } 105 106 object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M); 107 108 s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0); 109 110 snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname); 111 object_initialize_child(obj, "scu", &s->scu, typename); 112 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", sc->silicon_rev); 113 114 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), "hw-strap1"); 115 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), "hw-strap2"); 116 117 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); 118 object_initialize_child(obj, "timerctrl", &s->timerctrl, typename); 119 120 snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname); 121 object_initialize_child(obj, "adc", &s->adc, typename); 122 123 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); 124 object_initialize_child(obj, "fmc", &s->fmc, typename); 125 126 for (i = 0; i < sc->spis_num; i++) { 127 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname); 128 object_initialize_child(obj, "spi[*]", &s->spi[i], typename); 129 } 130 131 object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC); 132 133 object_initialize_child(obj, "sbc", &s->sbc, TYPE_ASPEED_SBC); 134 135 for (i = 0; i < sc->wdts_num; i++) { 136 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); 137 object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename); 138 } 139 } 140 141 static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp) 142 { 143 AspeedSoCState *s = ASPEED_SOC(dev_soc); 144 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 145 MemoryRegion *system_memory = get_system_memory(); 146 DeviceState *armv7m; 147 Error *err = NULL; 148 int i; 149 150 if (!clock_has_source(s->sysclk)) { 151 error_setg(errp, "sysclk clock must be wired up by the board code"); 152 return; 153 } 154 155 /* General I/O memory space to catch all unimplemented device */ 156 create_unimplemented_device("aspeed.sbc", 157 sc->memmap[ASPEED_DEV_SBC], 158 0x40000); 159 create_unimplemented_device("aspeed.io", 160 sc->memmap[ASPEED_DEV_IOMEM], 161 ASPEED_SOC_IOMEM_SIZE); 162 163 /* AST1030 CPU Core */ 164 armv7m = DEVICE(&s->armv7m); 165 qdev_prop_set_uint32(armv7m, "num-irq", 256); 166 qdev_prop_set_string(armv7m, "cpu-type", sc->cpu_type); 167 qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk); 168 object_property_set_link(OBJECT(&s->armv7m), "memory", 169 OBJECT(system_memory), &error_abort); 170 sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), &error_abort); 171 172 /* Internal SRAM */ 173 memory_region_init_ram(&s->sram, NULL, "aspeed.sram", sc->sram_size, &err); 174 if (err != NULL) { 175 error_propagate(errp, err); 176 return; 177 } 178 memory_region_add_subregion(system_memory, 179 sc->memmap[ASPEED_DEV_SRAM], 180 &s->sram); 181 182 /* SCU */ 183 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { 184 return; 185 } 186 sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]); 187 188 /* LPC */ 189 if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) { 190 return; 191 } 192 sysbus_mmio_map(SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]); 193 194 /* Connect the LPC IRQ to the GIC. It is otherwise unused. */ 195 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0, 196 aspeed_soc_get_irq(s, ASPEED_DEV_LPC)); 197 198 /* 199 * On the AST1030 LPC subdevice IRQs are connected straight to the GIC. 200 */ 201 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1, 202 qdev_get_gpio_in(DEVICE(&s->armv7m), 203 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1)); 204 205 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2, 206 qdev_get_gpio_in(DEVICE(&s->armv7m), 207 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2)); 208 209 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3, 210 qdev_get_gpio_in(DEVICE(&s->armv7m), 211 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3)); 212 213 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4, 214 qdev_get_gpio_in(DEVICE(&s->armv7m), 215 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4)); 216 217 /* UART */ 218 aspeed_soc_uart_init(s); 219 220 /* Timer */ 221 object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), 222 &error_abort); 223 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) { 224 return; 225 } 226 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0, 227 sc->memmap[ASPEED_DEV_TIMER1]); 228 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { 229 qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i); 230 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); 231 } 232 233 /* ADC */ 234 if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) { 235 return; 236 } 237 sysbus_mmio_map(SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]); 238 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, 239 aspeed_soc_get_irq(s, ASPEED_DEV_ADC)); 240 241 /* FMC, The number of CS is set at the board level */ 242 object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(&s->sram), 243 &error_abort); 244 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) { 245 return; 246 } 247 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]); 248 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1, 249 ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base); 250 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, 251 aspeed_soc_get_irq(s, ASPEED_DEV_FMC)); 252 253 /* SPI */ 254 for (i = 0; i < sc->spis_num; i++) { 255 object_property_set_link(OBJECT(&s->spi[i]), "dram", 256 OBJECT(&s->sram), &error_abort); 257 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { 258 return; 259 } 260 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, 261 sc->memmap[ASPEED_DEV_SPI1 + i]); 262 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1, 263 ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base); 264 } 265 266 /* Secure Boot Controller */ 267 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sbc), errp)) { 268 return; 269 } 270 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sbc), 0, sc->memmap[ASPEED_DEV_SBC]); 271 272 /* Watch dog */ 273 for (i = 0; i < sc->wdts_num; i++) { 274 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); 275 276 object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu), 277 &error_abort); 278 if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { 279 return; 280 } 281 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, 282 sc->memmap[ASPEED_DEV_WDT] + i * awc->offset); 283 } 284 } 285 286 static void aspeed_soc_ast1030_class_init(ObjectClass *klass, void *data) 287 { 288 DeviceClass *dc = DEVICE_CLASS(klass); 289 AspeedSoCClass *sc = ASPEED_SOC_CLASS(dc); 290 291 dc->realize = aspeed_soc_ast1030_realize; 292 293 sc->name = "ast1030-a1"; 294 sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-m4"); 295 sc->silicon_rev = AST1030_A1_SILICON_REV; 296 sc->sram_size = 0xc0000; 297 sc->spis_num = 2; 298 sc->ehcis_num = 0; 299 sc->wdts_num = 4; 300 sc->macs_num = 1; 301 sc->uarts_num = 13; 302 sc->irqmap = aspeed_soc_ast1030_irqmap; 303 sc->memmap = aspeed_soc_ast1030_memmap; 304 sc->num_cpus = 1; 305 sc->get_irq = aspeed_soc_ast1030_get_irq; 306 } 307 308 static const TypeInfo aspeed_soc_ast1030_type_info = { 309 .name = "ast1030-a1", 310 .parent = TYPE_ASPEED_SOC, 311 .instance_size = sizeof(AspeedSoCState), 312 .instance_init = aspeed_soc_ast1030_init, 313 .class_init = aspeed_soc_ast1030_class_init, 314 .class_size = sizeof(AspeedSoCClass), 315 }; 316 317 static void aspeed_soc_register_types(void) 318 { 319 type_register_static(&aspeed_soc_ast1030_type_info); 320 } 321 322 type_init(aspeed_soc_register_types) 323