1 /* 2 * ASPEED Ast10x0 SoC 3 * 4 * Copyright (C) 2022 ASPEED Technology Inc. 5 * 6 * This code is licensed under the GPL version 2 or later. See 7 * the COPYING file in the top-level directory. 8 * 9 * Implementation extracted from the AST2600 and adapted for Ast10x0. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "exec/address-spaces.h" 15 #include "sysemu/sysemu.h" 16 #include "hw/qdev-clock.h" 17 #include "hw/misc/unimp.h" 18 #include "hw/arm/aspeed_soc.h" 19 20 #define ASPEED_SOC_IOMEM_SIZE 0x00200000 21 22 static const hwaddr aspeed_soc_ast1030_memmap[] = { 23 [ASPEED_DEV_SRAM] = 0x00000000, 24 [ASPEED_DEV_SBC] = 0x79000000, 25 [ASPEED_DEV_IOMEM] = 0x7E600000, 26 [ASPEED_DEV_PWM] = 0x7E610000, 27 [ASPEED_DEV_FMC] = 0x7E620000, 28 [ASPEED_DEV_SPI1] = 0x7E630000, 29 [ASPEED_DEV_SPI2] = 0x7E640000, 30 [ASPEED_DEV_UDC] = 0x7E6A2000, 31 [ASPEED_DEV_SCU] = 0x7E6E2000, 32 [ASPEED_DEV_JTAG0] = 0x7E6E4000, 33 [ASPEED_DEV_JTAG1] = 0x7E6E4100, 34 [ASPEED_DEV_ADC] = 0x7E6E9000, 35 [ASPEED_DEV_ESPI] = 0x7E6EE000, 36 [ASPEED_DEV_SBC] = 0x7E6F2000, 37 [ASPEED_DEV_GPIO] = 0x7E780000, 38 [ASPEED_DEV_SGPIOM] = 0x7E780500, 39 [ASPEED_DEV_TIMER1] = 0x7E782000, 40 [ASPEED_DEV_UART1] = 0x7E783000, 41 [ASPEED_DEV_UART2] = 0x7E78D000, 42 [ASPEED_DEV_UART3] = 0x7E78E000, 43 [ASPEED_DEV_UART4] = 0x7E78F000, 44 [ASPEED_DEV_UART5] = 0x7E784000, 45 [ASPEED_DEV_UART6] = 0x7E790000, 46 [ASPEED_DEV_UART7] = 0x7E790100, 47 [ASPEED_DEV_UART8] = 0x7E790200, 48 [ASPEED_DEV_UART9] = 0x7E790300, 49 [ASPEED_DEV_UART10] = 0x7E790400, 50 [ASPEED_DEV_UART11] = 0x7E790500, 51 [ASPEED_DEV_UART12] = 0x7E790600, 52 [ASPEED_DEV_UART13] = 0x7E790700, 53 [ASPEED_DEV_WDT] = 0x7E785000, 54 [ASPEED_DEV_LPC] = 0x7E789000, 55 [ASPEED_DEV_PECI] = 0x7E78B000, 56 [ASPEED_DEV_I3C] = 0x7E7A0000, 57 [ASPEED_DEV_I2C] = 0x7E7B0000, 58 }; 59 60 static const int aspeed_soc_ast1030_irqmap[] = { 61 [ASPEED_DEV_UART1] = 47, 62 [ASPEED_DEV_UART2] = 48, 63 [ASPEED_DEV_UART3] = 49, 64 [ASPEED_DEV_UART4] = 50, 65 [ASPEED_DEV_UART5] = 8, 66 [ASPEED_DEV_UART6] = 57, 67 [ASPEED_DEV_UART7] = 58, 68 [ASPEED_DEV_UART8] = 59, 69 [ASPEED_DEV_UART9] = 60, 70 [ASPEED_DEV_UART10] = 61, 71 [ASPEED_DEV_UART11] = 62, 72 [ASPEED_DEV_UART12] = 63, 73 [ASPEED_DEV_UART13] = 64, 74 [ASPEED_DEV_GPIO] = 11, 75 [ASPEED_DEV_TIMER1] = 16, 76 [ASPEED_DEV_TIMER2] = 17, 77 [ASPEED_DEV_TIMER3] = 18, 78 [ASPEED_DEV_TIMER4] = 19, 79 [ASPEED_DEV_TIMER5] = 20, 80 [ASPEED_DEV_TIMER6] = 21, 81 [ASPEED_DEV_TIMER7] = 22, 82 [ASPEED_DEV_TIMER8] = 23, 83 [ASPEED_DEV_WDT] = 24, 84 [ASPEED_DEV_LPC] = 35, 85 [ASPEED_DEV_PECI] = 38, 86 [ASPEED_DEV_FMC] = 39, 87 [ASPEED_DEV_ESPI] = 42, 88 [ASPEED_DEV_PWM] = 44, 89 [ASPEED_DEV_ADC] = 46, 90 [ASPEED_DEV_SPI1] = 65, 91 [ASPEED_DEV_SPI2] = 66, 92 [ASPEED_DEV_I3C] = 102, /* 102 -> 105 */ 93 [ASPEED_DEV_I2C] = 110, /* 110 ~ 123 */ 94 [ASPEED_DEV_KCS] = 138, /* 138 -> 142 */ 95 [ASPEED_DEV_UDC] = 9, 96 [ASPEED_DEV_SGPIOM] = 51, 97 [ASPEED_DEV_JTAG0] = 27, 98 [ASPEED_DEV_JTAG1] = 53, 99 }; 100 101 static qemu_irq aspeed_soc_ast1030_get_irq(AspeedSoCState *s, int dev) 102 { 103 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 104 105 return qdev_get_gpio_in(DEVICE(&s->armv7m), sc->irqmap[dev]); 106 } 107 108 static void aspeed_soc_ast1030_init(Object *obj) 109 { 110 AspeedSoCState *s = ASPEED_SOC(obj); 111 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 112 char socname[8]; 113 char typename[64]; 114 int i; 115 116 if (sscanf(sc->name, "%7s", socname) != 1) { 117 g_assert_not_reached(); 118 } 119 120 object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M); 121 122 s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0); 123 124 snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname); 125 object_initialize_child(obj, "scu", &s->scu, typename); 126 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", sc->silicon_rev); 127 128 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), "hw-strap1"); 129 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), "hw-strap2"); 130 131 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); 132 object_initialize_child(obj, "i2c", &s->i2c, typename); 133 134 object_initialize_child(obj, "i3c", &s->i3c, TYPE_ASPEED_I3C); 135 136 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); 137 object_initialize_child(obj, "timerctrl", &s->timerctrl, typename); 138 139 snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname); 140 object_initialize_child(obj, "adc", &s->adc, typename); 141 142 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); 143 object_initialize_child(obj, "fmc", &s->fmc, typename); 144 145 for (i = 0; i < sc->spis_num; i++) { 146 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname); 147 object_initialize_child(obj, "spi[*]", &s->spi[i], typename); 148 } 149 150 object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC); 151 152 object_initialize_child(obj, "peci", &s->peci, TYPE_ASPEED_PECI); 153 154 object_initialize_child(obj, "sbc", &s->sbc, TYPE_ASPEED_SBC); 155 156 for (i = 0; i < sc->wdts_num; i++) { 157 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); 158 object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename); 159 } 160 161 for (i = 0; i < sc->uarts_num; i++) { 162 object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM); 163 } 164 165 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); 166 object_initialize_child(obj, "gpio", &s->gpio, typename); 167 168 object_initialize_child(obj, "iomem", &s->iomem, TYPE_UNIMPLEMENTED_DEVICE); 169 object_initialize_child(obj, "sbc-unimplemented", &s->sbc_unimplemented, 170 TYPE_UNIMPLEMENTED_DEVICE); 171 object_initialize_child(obj, "pwm", &s->pwm, TYPE_UNIMPLEMENTED_DEVICE); 172 object_initialize_child(obj, "espi", &s->espi, TYPE_UNIMPLEMENTED_DEVICE); 173 object_initialize_child(obj, "udc", &s->udc, TYPE_UNIMPLEMENTED_DEVICE); 174 object_initialize_child(obj, "sgpiom", &s->sgpiom, 175 TYPE_UNIMPLEMENTED_DEVICE); 176 object_initialize_child(obj, "jtag[0]", &s->jtag[0], 177 TYPE_UNIMPLEMENTED_DEVICE); 178 object_initialize_child(obj, "jtag[1]", &s->jtag[1], 179 TYPE_UNIMPLEMENTED_DEVICE); 180 } 181 182 static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp) 183 { 184 AspeedSoCState *s = ASPEED_SOC(dev_soc); 185 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 186 DeviceState *armv7m; 187 Error *err = NULL; 188 int i; 189 g_autofree char *sram_name = NULL; 190 191 if (!clock_has_source(s->sysclk)) { 192 error_setg(errp, "sysclk clock must be wired up by the board code"); 193 return; 194 } 195 196 /* General I/O memory space to catch all unimplemented device */ 197 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem), "aspeed.io", 198 sc->memmap[ASPEED_DEV_IOMEM], 199 ASPEED_SOC_IOMEM_SIZE); 200 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->sbc_unimplemented), 201 "aspeed.sbc", sc->memmap[ASPEED_DEV_SBC], 202 0x40000); 203 204 /* AST1030 CPU Core */ 205 armv7m = DEVICE(&s->armv7m); 206 qdev_prop_set_uint32(armv7m, "num-irq", 256); 207 qdev_prop_set_string(armv7m, "cpu-type", sc->cpu_type); 208 qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk); 209 object_property_set_link(OBJECT(&s->armv7m), "memory", 210 OBJECT(s->memory), &error_abort); 211 sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), &error_abort); 212 213 /* Internal SRAM */ 214 sram_name = g_strdup_printf("aspeed.sram.%d", 215 CPU(s->armv7m.cpu)->cpu_index); 216 memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, &err); 217 if (err != NULL) { 218 error_propagate(errp, err); 219 return; 220 } 221 memory_region_add_subregion(s->memory, 222 sc->memmap[ASPEED_DEV_SRAM], 223 &s->sram); 224 225 /* SCU */ 226 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { 227 return; 228 } 229 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]); 230 231 /* I2C */ 232 233 object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(&s->sram), 234 &error_abort); 235 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) { 236 return; 237 } 238 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]); 239 for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) { 240 qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->armv7m), 241 sc->irqmap[ASPEED_DEV_I2C] + i); 242 /* The AST1030 I2C controller has one IRQ per bus. */ 243 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq); 244 } 245 246 /* I3C */ 247 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i3c), errp)) { 248 return; 249 } 250 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i3c), 0, sc->memmap[ASPEED_DEV_I3C]); 251 for (i = 0; i < ASPEED_I3C_NR_DEVICES; i++) { 252 qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->armv7m), 253 sc->irqmap[ASPEED_DEV_I3C] + i); 254 /* The AST1030 I3C controller has one IRQ per bus. */ 255 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq); 256 } 257 258 /* PECI */ 259 if (!sysbus_realize(SYS_BUS_DEVICE(&s->peci), errp)) { 260 return; 261 } 262 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->peci), 0, 263 sc->memmap[ASPEED_DEV_PECI]); 264 sysbus_connect_irq(SYS_BUS_DEVICE(&s->peci), 0, 265 aspeed_soc_get_irq(s, ASPEED_DEV_PECI)); 266 267 /* LPC */ 268 if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) { 269 return; 270 } 271 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]); 272 273 /* Connect the LPC IRQ to the GIC. It is otherwise unused. */ 274 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0, 275 aspeed_soc_get_irq(s, ASPEED_DEV_LPC)); 276 277 /* 278 * On the AST1030 LPC subdevice IRQs are connected straight to the GIC. 279 */ 280 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1, 281 qdev_get_gpio_in(DEVICE(&s->armv7m), 282 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1)); 283 284 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2, 285 qdev_get_gpio_in(DEVICE(&s->armv7m), 286 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2)); 287 288 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3, 289 qdev_get_gpio_in(DEVICE(&s->armv7m), 290 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3)); 291 292 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4, 293 qdev_get_gpio_in(DEVICE(&s->armv7m), 294 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4)); 295 296 /* UART */ 297 if (!aspeed_soc_uart_realize(s, errp)) { 298 return; 299 } 300 301 /* Timer */ 302 object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), 303 &error_abort); 304 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) { 305 return; 306 } 307 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->timerctrl), 0, 308 sc->memmap[ASPEED_DEV_TIMER1]); 309 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { 310 qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i); 311 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); 312 } 313 314 /* ADC */ 315 if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) { 316 return; 317 } 318 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]); 319 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, 320 aspeed_soc_get_irq(s, ASPEED_DEV_ADC)); 321 322 /* FMC, The number of CS is set at the board level */ 323 object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(&s->sram), 324 &error_abort); 325 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) { 326 return; 327 } 328 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]); 329 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 1, 330 ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base); 331 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, 332 aspeed_soc_get_irq(s, ASPEED_DEV_FMC)); 333 334 /* SPI */ 335 for (i = 0; i < sc->spis_num; i++) { 336 object_property_set_link(OBJECT(&s->spi[i]), "dram", 337 OBJECT(&s->sram), &error_abort); 338 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { 339 return; 340 } 341 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 0, 342 sc->memmap[ASPEED_DEV_SPI1 + i]); 343 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 1, 344 ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base); 345 } 346 347 /* Secure Boot Controller */ 348 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sbc), errp)) { 349 return; 350 } 351 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sbc), 0, sc->memmap[ASPEED_DEV_SBC]); 352 353 /* Watch dog */ 354 for (i = 0; i < sc->wdts_num; i++) { 355 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); 356 hwaddr wdt_offset = sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize; 357 358 object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu), 359 &error_abort); 360 if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { 361 return; 362 } 363 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset); 364 } 365 366 /* GPIO */ 367 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { 368 return; 369 } 370 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio), 0, 371 sc->memmap[ASPEED_DEV_GPIO]); 372 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, 373 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO)); 374 375 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->pwm), "aspeed.pwm", 376 sc->memmap[ASPEED_DEV_PWM], 0x100); 377 378 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->espi), "aspeed.espi", 379 sc->memmap[ASPEED_DEV_ESPI], 0x800); 380 381 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->udc), "aspeed.udc", 382 sc->memmap[ASPEED_DEV_UDC], 0x1000); 383 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->sgpiom), "aspeed.sgpiom", 384 sc->memmap[ASPEED_DEV_SGPIOM], 0x100); 385 386 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->jtag[0]), "aspeed.jtag", 387 sc->memmap[ASPEED_DEV_JTAG0], 0x20); 388 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->jtag[1]), "aspeed.jtag", 389 sc->memmap[ASPEED_DEV_JTAG1], 0x20); 390 } 391 392 static void aspeed_soc_ast1030_class_init(ObjectClass *klass, void *data) 393 { 394 DeviceClass *dc = DEVICE_CLASS(klass); 395 AspeedSoCClass *sc = ASPEED_SOC_CLASS(dc); 396 397 dc->realize = aspeed_soc_ast1030_realize; 398 399 sc->name = "ast1030-a1"; 400 sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-m4"); 401 sc->silicon_rev = AST1030_A1_SILICON_REV; 402 sc->sram_size = 0xc0000; 403 sc->spis_num = 2; 404 sc->ehcis_num = 0; 405 sc->wdts_num = 4; 406 sc->macs_num = 1; 407 sc->uarts_num = 13; 408 sc->irqmap = aspeed_soc_ast1030_irqmap; 409 sc->memmap = aspeed_soc_ast1030_memmap; 410 sc->num_cpus = 1; 411 sc->get_irq = aspeed_soc_ast1030_get_irq; 412 } 413 414 static const TypeInfo aspeed_soc_ast1030_type_info = { 415 .name = "ast1030-a1", 416 .parent = TYPE_ASPEED_SOC, 417 .instance_size = sizeof(AspeedSoCState), 418 .instance_init = aspeed_soc_ast1030_init, 419 .class_init = aspeed_soc_ast1030_class_init, 420 .class_size = sizeof(AspeedSoCClass), 421 }; 422 423 static void aspeed_soc_register_types(void) 424 { 425 type_register_static(&aspeed_soc_ast1030_type_info); 426 } 427 428 type_init(aspeed_soc_register_types) 429