1 /* 2 * OpenPOWER Palmetto BMC 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * 6 * Copyright 2016 IBM Corp. 7 * 8 * This code is licensed under the GPL version 2 or later. See 9 * the COPYING file in the top-level directory. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "hw/arm/boot.h" 15 #include "hw/arm/aspeed.h" 16 #include "hw/arm/aspeed_soc.h" 17 #include "hw/arm/aspeed_eeprom.h" 18 #include "hw/block/flash.h" 19 #include "hw/i2c/i2c_mux_pca954x.h" 20 #include "hw/i2c/smbus_eeprom.h" 21 #include "hw/gpio/pca9552.h" 22 #include "hw/nvram/eeprom_at24c.h" 23 #include "hw/sensor/tmp105.h" 24 #include "hw/misc/led.h" 25 #include "hw/qdev-properties.h" 26 #include "system/block-backend.h" 27 #include "system/reset.h" 28 #include "hw/loader.h" 29 #include "qemu/error-report.h" 30 #include "qemu/units.h" 31 #include "hw/qdev-clock.h" 32 #include "system/system.h" 33 34 static struct arm_boot_info aspeed_board_binfo = { 35 .board_id = -1, /* device-tree-only board */ 36 }; 37 38 struct AspeedMachineState { 39 /* Private */ 40 MachineState parent_obj; 41 /* Public */ 42 43 AspeedSoCState *soc; 44 MemoryRegion boot_rom; 45 bool mmio_exec; 46 uint32_t uart_chosen; 47 char *fmc_model; 48 char *spi_model; 49 uint32_t hw_strap1; 50 }; 51 52 /* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */ 53 #if HOST_LONG_BITS == 32 54 #define ASPEED_RAM_SIZE(sz) MIN((sz), 1 * GiB) 55 #else 56 #define ASPEED_RAM_SIZE(sz) (sz) 57 #endif 58 59 /* Palmetto hardware value: 0x120CE416 */ 60 #define PALMETTO_BMC_HW_STRAP1 ( \ 61 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) | \ 62 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \ 63 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 64 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \ 65 SCU_HW_STRAP_VGA_CLASS_CODE | \ 66 SCU_HW_STRAP_LPC_RESET_PIN | \ 67 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \ 68 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 69 SCU_HW_STRAP_SPI_WIDTH | \ 70 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 71 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 72 73 /* TODO: Find the actual hardware value */ 74 #define SUPERMICROX11_BMC_HW_STRAP1 ( \ 75 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \ 76 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2) | \ 77 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 78 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \ 79 SCU_HW_STRAP_VGA_CLASS_CODE | \ 80 SCU_HW_STRAP_LPC_RESET_PIN | \ 81 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \ 82 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 83 SCU_HW_STRAP_SPI_WIDTH | \ 84 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 85 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 86 87 /* TODO: Find the actual hardware value */ 88 #define SUPERMICRO_X11SPI_BMC_HW_STRAP1 ( \ 89 AST2500_HW_STRAP1_DEFAULTS | \ 90 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 91 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 92 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 93 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 94 SCU_HW_STRAP_SPI_WIDTH | \ 95 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN)) 96 97 /* AST2500 evb hardware value: 0xF100C2E6 */ 98 #define AST2500_EVB_HW_STRAP1 (( \ 99 AST2500_HW_STRAP1_DEFAULTS | \ 100 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 101 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 102 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 103 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 104 SCU_HW_STRAP_MAC1_RGMII | \ 105 SCU_HW_STRAP_MAC0_RGMII) & \ 106 ~SCU_HW_STRAP_2ND_BOOT_WDT) 107 108 /* Romulus hardware value: 0xF10AD206 */ 109 #define ROMULUS_BMC_HW_STRAP1 ( \ 110 AST2500_HW_STRAP1_DEFAULTS | \ 111 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 112 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 113 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 114 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 115 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \ 116 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER)) 117 118 /* Sonorapass hardware value: 0xF100D216 */ 119 #define SONORAPASS_BMC_HW_STRAP1 ( \ 120 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 121 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 122 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 123 SCU_AST2500_HW_STRAP_RESERVED28 | \ 124 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 125 SCU_HW_STRAP_VGA_CLASS_CODE | \ 126 SCU_HW_STRAP_LPC_RESET_PIN | \ 127 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 128 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 129 SCU_HW_STRAP_VGA_BIOS_ROM | \ 130 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 131 SCU_AST2500_HW_STRAP_RESERVED1) 132 133 #define G220A_BMC_HW_STRAP1 ( \ 134 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 135 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 136 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 137 SCU_AST2500_HW_STRAP_RESERVED28 | \ 138 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 139 SCU_HW_STRAP_2ND_BOOT_WDT | \ 140 SCU_HW_STRAP_VGA_CLASS_CODE | \ 141 SCU_HW_STRAP_LPC_RESET_PIN | \ 142 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 143 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 144 SCU_HW_STRAP_VGA_SIZE_SET(VGA_64M_DRAM) | \ 145 SCU_AST2500_HW_STRAP_RESERVED1) 146 147 /* FP5280G2 hardware value: 0XF100D286 */ 148 #define FP5280G2_BMC_HW_STRAP1 ( \ 149 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 150 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 151 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 152 SCU_AST2500_HW_STRAP_RESERVED28 | \ 153 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 154 SCU_HW_STRAP_VGA_CLASS_CODE | \ 155 SCU_HW_STRAP_LPC_RESET_PIN | \ 156 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 157 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 158 SCU_HW_STRAP_MAC1_RGMII | \ 159 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 160 SCU_AST2500_HW_STRAP_RESERVED1) 161 162 /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */ 163 #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1 164 165 /* Quanta-Q71l hardware value */ 166 #define QUANTA_Q71L_BMC_HW_STRAP1 ( \ 167 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \ 168 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2/* DDR3 with CL=6, CWL=5 */) | \ 169 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 170 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_24M_IN) | \ 171 SCU_HW_STRAP_VGA_CLASS_CODE | \ 172 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_PASS_THROUGH) | \ 173 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 174 SCU_HW_STRAP_SPI_WIDTH | \ 175 SCU_HW_STRAP_VGA_SIZE_SET(VGA_8M_DRAM) | \ 176 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 177 178 /* AST2600 evb hardware value */ 179 #define AST2600_EVB_HW_STRAP1 0x000000C0 180 #define AST2600_EVB_HW_STRAP2 0x00000003 181 182 #ifdef TARGET_AARCH64 183 /* AST2700 evb hardware value */ 184 /* SCU HW Strap1 */ 185 #define AST2700_EVB_HW_STRAP1 0x00000800 186 /* SCUIO HW Strap1 */ 187 #define AST2700_EVB_HW_STRAP2 0x00000700 188 #endif 189 190 /* Rainier hardware value: (QEMU prototype) */ 191 #define RAINIER_BMC_HW_STRAP1 (0x00422016 | SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC) 192 #define RAINIER_BMC_HW_STRAP2 0x80000848 193 194 /* Fuji hardware value */ 195 #define FUJI_BMC_HW_STRAP1 0x00000000 196 #define FUJI_BMC_HW_STRAP2 0x00000000 197 198 /* Bletchley hardware value */ 199 /* TODO: Leave same as EVB for now. */ 200 #define BLETCHLEY_BMC_HW_STRAP1 AST2600_EVB_HW_STRAP1 201 #define BLETCHLEY_BMC_HW_STRAP2 AST2600_EVB_HW_STRAP2 202 203 /* Qualcomm DC-SCM hardware value */ 204 #define QCOM_DC_SCM_V1_BMC_HW_STRAP1 0x00000000 205 #define QCOM_DC_SCM_V1_BMC_HW_STRAP2 0x00000041 206 207 #define AST_SMP_MAILBOX_BASE 0x1e6e2180 208 #define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0) 209 #define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4) 210 #define AST_SMP_MBOX_FIELD_READY (AST_SMP_MAILBOX_BASE + 0x8) 211 #define AST_SMP_MBOX_FIELD_POLLINSN (AST_SMP_MAILBOX_BASE + 0xc) 212 #define AST_SMP_MBOX_CODE (AST_SMP_MAILBOX_BASE + 0x10) 213 #define AST_SMP_MBOX_GOSIGN 0xabbaab00 214 215 static void aspeed_write_smpboot(ARMCPU *cpu, 216 const struct arm_boot_info *info) 217 { 218 AddressSpace *as = arm_boot_address_space(cpu, info); 219 static const ARMInsnFixup poll_mailbox_ready[] = { 220 /* 221 * r2 = per-cpu go sign value 222 * r1 = AST_SMP_MBOX_FIELD_ENTRY 223 * r0 = AST_SMP_MBOX_FIELD_GOSIGN 224 */ 225 { 0xee100fb0 }, /* mrc p15, 0, r0, c0, c0, 5 */ 226 { 0xe21000ff }, /* ands r0, r0, #255 */ 227 { 0xe59f201c }, /* ldr r2, [pc, #28] */ 228 { 0xe1822000 }, /* orr r2, r2, r0 */ 229 230 { 0xe59f1018 }, /* ldr r1, [pc, #24] */ 231 { 0xe59f0018 }, /* ldr r0, [pc, #24] */ 232 233 { 0xe320f002 }, /* wfe */ 234 { 0xe5904000 }, /* ldr r4, [r0] */ 235 { 0xe1520004 }, /* cmp r2, r4 */ 236 { 0x1afffffb }, /* bne <wfe> */ 237 { 0xe591f000 }, /* ldr pc, [r1] */ 238 { AST_SMP_MBOX_GOSIGN }, 239 { AST_SMP_MBOX_FIELD_ENTRY }, 240 { AST_SMP_MBOX_FIELD_GOSIGN }, 241 { 0, FIXUP_TERMINATOR } 242 }; 243 static const uint32_t fixupcontext[FIXUP_MAX] = { 0 }; 244 245 arm_write_bootloader("aspeed.smpboot", as, info->smp_loader_start, 246 poll_mailbox_ready, fixupcontext); 247 } 248 249 static void aspeed_reset_secondary(ARMCPU *cpu, 250 const struct arm_boot_info *info) 251 { 252 AddressSpace *as = arm_boot_address_space(cpu, info); 253 CPUState *cs = CPU(cpu); 254 255 /* info->smp_bootreg_addr */ 256 address_space_stl_notdirty(as, AST_SMP_MBOX_FIELD_GOSIGN, 0, 257 MEMTXATTRS_UNSPECIFIED, NULL); 258 cpu_set_pc(cs, info->smp_loader_start); 259 } 260 261 static void write_boot_rom(BlockBackend *blk, hwaddr addr, size_t rom_size, 262 Error **errp) 263 { 264 g_autofree void *storage = NULL; 265 int64_t size; 266 267 /* 268 * The block backend size should have already been 'validated' by 269 * the creation of the m25p80 object. 270 */ 271 size = blk_getlength(blk); 272 if (size <= 0) { 273 error_setg(errp, "failed to get flash size"); 274 return; 275 } 276 277 if (rom_size > size) { 278 rom_size = size; 279 } 280 281 storage = g_malloc0(rom_size); 282 if (blk_pread(blk, 0, rom_size, storage, 0) < 0) { 283 error_setg(errp, "failed to read the initial flash content"); 284 return; 285 } 286 287 rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr); 288 } 289 290 /* 291 * Create a ROM and copy the flash contents at the expected address 292 * (0x0). Boots faster than execute-in-place. 293 */ 294 static void aspeed_install_boot_rom(AspeedMachineState *bmc, BlockBackend *blk, 295 uint64_t rom_size) 296 { 297 AspeedSoCState *soc = bmc->soc; 298 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(soc); 299 300 memory_region_init_rom(&bmc->boot_rom, NULL, "aspeed.boot_rom", rom_size, 301 &error_abort); 302 memory_region_add_subregion_overlap(&soc->spi_boot_container, 0, 303 &bmc->boot_rom, 1); 304 write_boot_rom(blk, sc->memmap[ASPEED_DEV_SPI_BOOT], 305 rom_size, &error_abort); 306 } 307 308 void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype, 309 unsigned int count, int unit0) 310 { 311 int i; 312 313 if (!flashtype) { 314 return; 315 } 316 317 for (i = 0; i < count; ++i) { 318 DriveInfo *dinfo = drive_get(IF_MTD, 0, unit0 + i); 319 DeviceState *dev; 320 321 dev = qdev_new(flashtype); 322 if (dinfo) { 323 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo)); 324 } 325 qdev_prop_set_uint8(dev, "cs", i); 326 qdev_realize_and_unref(dev, BUS(s->spi), &error_fatal); 327 } 328 } 329 330 static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo, bool emmc, 331 bool boot_emmc) 332 { 333 DeviceState *card; 334 335 if (!dinfo) { 336 return; 337 } 338 card = qdev_new(emmc ? TYPE_EMMC : TYPE_SD_CARD); 339 340 /* 341 * Force the boot properties of the eMMC device only when the 342 * machine is strapped to boot from eMMC. Without these 343 * settings, the machine would not boot. 344 * 345 * This also allows the machine to use an eMMC device without 346 * boot areas when booting from the flash device (or -kernel) 347 * Ideally, the device and its properties should be defined on 348 * the command line. 349 */ 350 if (emmc && boot_emmc) { 351 qdev_prop_set_uint64(card, "boot-partition-size", 1 * MiB); 352 qdev_prop_set_uint8(card, "boot-config", 0x1 << 3); 353 } 354 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo), 355 &error_fatal); 356 qdev_realize_and_unref(card, 357 qdev_get_child_bus(DEVICE(sdhci), "sd-bus"), 358 &error_fatal); 359 } 360 361 static void connect_serial_hds_to_uarts(AspeedMachineState *bmc) 362 { 363 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc); 364 AspeedSoCState *s = bmc->soc; 365 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 366 int uart_chosen = bmc->uart_chosen ? bmc->uart_chosen : amc->uart_default; 367 368 aspeed_soc_uart_set_chr(s, uart_chosen, serial_hd(0)); 369 for (int i = 1, uart = sc->uarts_base; i < sc->uarts_num; uart++) { 370 if (uart == uart_chosen) { 371 continue; 372 } 373 aspeed_soc_uart_set_chr(s, uart, serial_hd(i++)); 374 } 375 } 376 377 static void aspeed_machine_init(MachineState *machine) 378 { 379 AspeedMachineState *bmc = ASPEED_MACHINE(machine); 380 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine); 381 AspeedSoCClass *sc; 382 int i; 383 DriveInfo *emmc0 = NULL; 384 bool boot_emmc; 385 386 bmc->soc = ASPEED_SOC(object_new(amc->soc_name)); 387 object_property_add_child(OBJECT(machine), "soc", OBJECT(bmc->soc)); 388 object_unref(OBJECT(bmc->soc)); 389 sc = ASPEED_SOC_GET_CLASS(bmc->soc); 390 391 /* 392 * This will error out if the RAM size is not supported by the 393 * memory controller of the SoC. 394 */ 395 object_property_set_uint(OBJECT(bmc->soc), "ram-size", machine->ram_size, 396 &error_fatal); 397 398 for (i = 0; i < sc->macs_num; i++) { 399 if ((amc->macs_mask & (1 << i)) && 400 !qemu_configure_nic_device(DEVICE(&bmc->soc->ftgmac100[i]), 401 true, NULL)) { 402 break; /* No configs left; stop asking */ 403 } 404 } 405 406 object_property_set_int(OBJECT(bmc->soc), "hw-strap1", bmc->hw_strap1, 407 &error_abort); 408 object_property_set_int(OBJECT(bmc->soc), "hw-strap2", amc->hw_strap2, 409 &error_abort); 410 object_property_set_link(OBJECT(bmc->soc), "memory", 411 OBJECT(get_system_memory()), &error_abort); 412 object_property_set_link(OBJECT(bmc->soc), "dram", 413 OBJECT(machine->ram), &error_abort); 414 if (amc->sdhci_wp_inverted) { 415 for (i = 0; i < bmc->soc->sdhci.num_slots; i++) { 416 object_property_set_bool(OBJECT(&bmc->soc->sdhci.slots[i]), 417 "wp-inverted", true, &error_abort); 418 } 419 } 420 if (machine->kernel_filename) { 421 /* 422 * When booting with a -kernel command line there is no u-boot 423 * that runs to unlock the SCU. In this case set the default to 424 * be unlocked as the kernel expects 425 */ 426 object_property_set_int(OBJECT(bmc->soc), "hw-prot-key", 427 ASPEED_SCU_PROT_KEY, &error_abort); 428 } 429 connect_serial_hds_to_uarts(bmc); 430 qdev_realize(DEVICE(bmc->soc), NULL, &error_abort); 431 432 if (defaults_enabled()) { 433 aspeed_board_init_flashes(&bmc->soc->fmc, 434 bmc->fmc_model ? bmc->fmc_model : amc->fmc_model, 435 amc->num_cs, 0); 436 aspeed_board_init_flashes(&bmc->soc->spi[0], 437 bmc->spi_model ? bmc->spi_model : amc->spi_model, 438 1, amc->num_cs); 439 } 440 441 if (machine->kernel_filename && sc->num_cpus > 1) { 442 /* With no u-boot we must set up a boot stub for the secondary CPU */ 443 MemoryRegion *smpboot = g_new(MemoryRegion, 1); 444 memory_region_init_ram(smpboot, NULL, "aspeed.smpboot", 445 0x80, &error_abort); 446 memory_region_add_subregion(get_system_memory(), 447 AST_SMP_MAILBOX_BASE, smpboot); 448 449 aspeed_board_binfo.write_secondary_boot = aspeed_write_smpboot; 450 aspeed_board_binfo.secondary_cpu_reset_hook = aspeed_reset_secondary; 451 aspeed_board_binfo.smp_loader_start = AST_SMP_MBOX_CODE; 452 } 453 454 aspeed_board_binfo.ram_size = machine->ram_size; 455 aspeed_board_binfo.loader_start = sc->memmap[ASPEED_DEV_SDRAM]; 456 457 if (amc->i2c_init) { 458 amc->i2c_init(bmc); 459 } 460 461 for (i = 0; i < bmc->soc->sdhci.num_slots && defaults_enabled(); i++) { 462 sdhci_attach_drive(&bmc->soc->sdhci.slots[i], 463 drive_get(IF_SD, 0, i), false, false); 464 } 465 466 boot_emmc = sc->boot_from_emmc(bmc->soc); 467 468 if (bmc->soc->emmc.num_slots && defaults_enabled()) { 469 emmc0 = drive_get(IF_SD, 0, bmc->soc->sdhci.num_slots); 470 sdhci_attach_drive(&bmc->soc->emmc.slots[0], emmc0, true, boot_emmc); 471 } 472 473 if (!bmc->mmio_exec) { 474 DeviceState *dev = ssi_get_cs(bmc->soc->fmc.spi, 0); 475 BlockBackend *fmc0 = dev ? m25p80_get_blk(dev) : NULL; 476 477 if (fmc0 && !boot_emmc) { 478 uint64_t rom_size = memory_region_size(&bmc->soc->spi_boot); 479 aspeed_install_boot_rom(bmc, fmc0, rom_size); 480 } else if (emmc0) { 481 aspeed_install_boot_rom(bmc, blk_by_legacy_dinfo(emmc0), 64 * KiB); 482 } 483 } 484 485 arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo); 486 } 487 488 static void palmetto_bmc_i2c_init(AspeedMachineState *bmc) 489 { 490 AspeedSoCState *soc = bmc->soc; 491 DeviceState *dev; 492 uint8_t *eeprom_buf = g_malloc0(32 * 1024); 493 494 /* 495 * The palmetto platform expects a ds3231 RTC but a ds1338 is 496 * enough to provide basic RTC features. Alarms will be missing 497 */ 498 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), "ds1338", 0x68); 499 500 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, 501 eeprom_buf); 502 503 /* add a TMP423 temperature sensor */ 504 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), 505 "tmp423", 0x4c)); 506 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 507 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 508 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 509 object_property_set_int(OBJECT(dev), "temperature3", 110000, &error_abort); 510 } 511 512 static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc) 513 { 514 AspeedSoCState *soc = bmc->soc; 515 516 /* 517 * The quanta-q71l platform expects tmp75s which are compatible with 518 * tmp105s. 519 */ 520 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4c); 521 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4e); 522 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4f); 523 524 /* TODO: i2c-1: Add baseboard FRU eeprom@54 24c64 */ 525 /* TODO: i2c-1: Add Frontpanel FRU eeprom@57 24c64 */ 526 /* TODO: Add Memory Riser i2c mux and eeproms. */ 527 528 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9546", 0x74); 529 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9548", 0x77); 530 531 /* TODO: i2c-3: Add BIOS FRU eeprom@56 24c64 */ 532 533 /* i2c-7 */ 534 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9546", 0x70); 535 /* - i2c@0: pmbus@59 */ 536 /* - i2c@1: pmbus@58 */ 537 /* - i2c@2: pmbus@58 */ 538 /* - i2c@3: pmbus@59 */ 539 540 /* TODO: i2c-7: Add PDB FRU eeprom@52 */ 541 /* TODO: i2c-8: Add BMC FRU eeprom@50 */ 542 } 543 544 static void ast2500_evb_i2c_init(AspeedMachineState *bmc) 545 { 546 AspeedSoCState *soc = bmc->soc; 547 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 548 549 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 3), 0x50, 550 eeprom_buf); 551 552 /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */ 553 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), 554 TYPE_TMP105, 0x4d); 555 } 556 557 static void ast2600_evb_i2c_init(AspeedMachineState *bmc) 558 { 559 AspeedSoCState *soc = bmc->soc; 560 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 561 562 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 563 eeprom_buf); 564 565 /* LM75 is compatible with TMP105 driver */ 566 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), 567 TYPE_TMP105, 0x4d); 568 } 569 570 static void yosemitev2_bmc_i2c_init(AspeedMachineState *bmc) 571 { 572 AspeedSoCState *soc = bmc->soc; 573 574 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x51, 128 * KiB); 575 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 128 * KiB, 576 yosemitev2_bmc_fruid, yosemitev2_bmc_fruid_len); 577 /* TMP421 */ 578 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "tmp421", 0x1f); 579 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp421", 0x4e); 580 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp421", 0x4f); 581 582 } 583 584 static void romulus_bmc_i2c_init(AspeedMachineState *bmc) 585 { 586 AspeedSoCState *soc = bmc->soc; 587 588 /* 589 * The romulus board expects Epson RX8900 I2C RTC but a ds1338 is 590 * good enough 591 */ 592 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32); 593 } 594 595 static void tiogapass_bmc_i2c_init(AspeedMachineState *bmc) 596 { 597 AspeedSoCState *soc = bmc->soc; 598 599 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, 128 * KiB); 600 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 6), 0x54, 128 * KiB, 601 tiogapass_bmc_fruid, tiogapass_bmc_fruid_len); 602 /* TMP421 */ 603 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "tmp421", 0x1f); 604 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp421", 0x4f); 605 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp421", 0x4e); 606 } 607 608 static void create_pca9552(AspeedSoCState *soc, int bus_id, int addr) 609 { 610 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, bus_id), 611 TYPE_PCA9552, addr); 612 } 613 614 static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc) 615 { 616 AspeedSoCState *soc = bmc->soc; 617 618 /* bus 2 : */ 619 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x48); 620 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x49); 621 /* bus 2 : pca9546 @ 0x73 */ 622 623 /* bus 3 : pca9548 @ 0x70 */ 624 625 /* bus 4 : */ 626 uint8_t *eeprom4_54 = g_malloc0(8 * 1024); 627 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, 628 eeprom4_54); 629 /* PCA9539 @ 0x76, but PCA9552 is compatible */ 630 create_pca9552(soc, 4, 0x76); 631 /* PCA9539 @ 0x77, but PCA9552 is compatible */ 632 create_pca9552(soc, 4, 0x77); 633 634 /* bus 6 : */ 635 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x48); 636 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x49); 637 /* bus 6 : pca9546 @ 0x73 */ 638 639 /* bus 8 : */ 640 uint8_t *eeprom8_56 = g_malloc0(8 * 1024); 641 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 8), 0x56, 642 eeprom8_56); 643 create_pca9552(soc, 8, 0x60); 644 create_pca9552(soc, 8, 0x61); 645 /* bus 8 : adc128d818 @ 0x1d */ 646 /* bus 8 : adc128d818 @ 0x1f */ 647 648 /* 649 * bus 13 : pca9548 @ 0x71 650 * - channel 3: 651 * - tmm421 @ 0x4c 652 * - tmp421 @ 0x4e 653 * - tmp421 @ 0x4f 654 */ 655 656 } 657 658 static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc) 659 { 660 static const struct { 661 unsigned gpio_id; 662 LEDColor color; 663 const char *description; 664 bool gpio_polarity; 665 } pca1_leds[] = { 666 {13, LED_COLOR_GREEN, "front-fault-4", GPIO_POLARITY_ACTIVE_LOW}, 667 {14, LED_COLOR_GREEN, "front-power-3", GPIO_POLARITY_ACTIVE_LOW}, 668 {15, LED_COLOR_GREEN, "front-id-5", GPIO_POLARITY_ACTIVE_LOW}, 669 }; 670 AspeedSoCState *soc = bmc->soc; 671 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 672 DeviceState *dev; 673 LEDState *led; 674 675 /* Bus 3: TODO bmp280@77 */ 676 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60)); 677 qdev_prop_set_string(dev, "description", "pca1"); 678 i2c_slave_realize_and_unref(I2C_SLAVE(dev), 679 aspeed_i2c_get_bus(&soc->i2c, 3), 680 &error_fatal); 681 682 for (size_t i = 0; i < ARRAY_SIZE(pca1_leds); i++) { 683 led = led_create_simple(OBJECT(bmc), 684 pca1_leds[i].gpio_polarity, 685 pca1_leds[i].color, 686 pca1_leds[i].description); 687 qdev_connect_gpio_out(dev, pca1_leds[i].gpio_id, 688 qdev_get_gpio_in(DEVICE(led), 0)); 689 } 690 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "dps310", 0x76); 691 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "max31785", 0x52); 692 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "tmp423", 0x4c); 693 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "tmp423", 0x4c); 694 695 /* The Witherspoon expects a TMP275 but a TMP105 is compatible */ 696 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), TYPE_TMP105, 697 0x4a); 698 699 /* 700 * The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is 701 * good enough 702 */ 703 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32); 704 705 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 11), 0x51, 706 eeprom_buf); 707 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60)); 708 qdev_prop_set_string(dev, "description", "pca0"); 709 i2c_slave_realize_and_unref(I2C_SLAVE(dev), 710 aspeed_i2c_get_bus(&soc->i2c, 11), 711 &error_fatal); 712 /* Bus 11: TODO ucd90160@64 */ 713 } 714 715 static void g220a_bmc_i2c_init(AspeedMachineState *bmc) 716 { 717 AspeedSoCState *soc = bmc->soc; 718 DeviceState *dev; 719 720 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), 721 "emc1413", 0x4c)); 722 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 723 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 724 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 725 726 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12), 727 "emc1413", 0x4c)); 728 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 729 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 730 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 731 732 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 13), 733 "emc1413", 0x4c)); 734 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 735 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 736 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 737 738 static uint8_t eeprom_buf[2 * 1024] = { 739 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0xfe, 740 0x01, 0x06, 0x00, 0xc9, 0x42, 0x79, 0x74, 0x65, 741 0x64, 0x61, 0x6e, 0x63, 0x65, 0xc5, 0x47, 0x32, 742 0x32, 0x30, 0x41, 0xc4, 0x41, 0x41, 0x42, 0x42, 743 0xc4, 0x43, 0x43, 0x44, 0x44, 0xc4, 0x45, 0x45, 744 0x46, 0x46, 0xc4, 0x48, 0x48, 0x47, 0x47, 0xc1, 745 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa7, 746 }; 747 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x57, 748 eeprom_buf); 749 } 750 751 static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc) 752 { 753 AspeedSoCState *soc = bmc->soc; 754 I2CSlave *i2c_mux; 755 756 /* The at24c256 */ 757 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 1), 0x50, 32768); 758 759 /* The fp5280g2 expects a TMP112 but a TMP105 is compatible */ 760 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105, 761 0x48); 762 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105, 763 0x49); 764 765 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), 766 "pca9546", 0x70); 767 /* It expects a TMP112 but a TMP105 is compatible */ 768 i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 0), TYPE_TMP105, 769 0x4a); 770 771 /* It expects a ds3232 but a ds1338 is good enough */ 772 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "ds1338", 0x68); 773 774 /* It expects a pca9555 but a pca9552 is compatible */ 775 create_pca9552(soc, 8, 0x30); 776 } 777 778 static void rainier_bmc_i2c_init(AspeedMachineState *bmc) 779 { 780 AspeedSoCState *soc = bmc->soc; 781 I2CSlave *i2c_mux; 782 783 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB); 784 785 create_pca9552(soc, 3, 0x61); 786 787 /* The rainier expects a TMP275 but a TMP105 is compatible */ 788 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, 789 0x48); 790 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, 791 0x49); 792 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, 793 0x4a); 794 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), 795 "pca9546", 0x70); 796 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 797 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 798 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x52, 64 * KiB); 799 create_pca9552(soc, 4, 0x60); 800 801 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105, 802 0x48); 803 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105, 804 0x49); 805 create_pca9552(soc, 5, 0x60); 806 create_pca9552(soc, 5, 0x61); 807 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), 808 "pca9546", 0x70); 809 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 810 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 811 812 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, 813 0x48); 814 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, 815 0x4a); 816 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, 817 0x4b); 818 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), 819 "pca9546", 0x70); 820 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 821 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 822 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x50, 64 * KiB); 823 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 3), 0x51, 64 * KiB); 824 825 create_pca9552(soc, 7, 0x30); 826 create_pca9552(soc, 7, 0x31); 827 create_pca9552(soc, 7, 0x32); 828 create_pca9552(soc, 7, 0x33); 829 create_pca9552(soc, 7, 0x60); 830 create_pca9552(soc, 7, 0x61); 831 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "dps310", 0x76); 832 /* Bus 7: TODO si7021-a20@20 */ 833 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), TYPE_TMP105, 834 0x48); 835 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "max31785", 0x52); 836 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 64 * KiB); 837 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x51, 64 * KiB); 838 839 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105, 840 0x48); 841 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105, 842 0x4a); 843 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x50, 844 64 * KiB, rainier_bb_fruid, rainier_bb_fruid_len); 845 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 846 64 * KiB, rainier_bmc_fruid, rainier_bmc_fruid_len); 847 create_pca9552(soc, 8, 0x60); 848 create_pca9552(soc, 8, 0x61); 849 /* Bus 8: ucd90320@11 */ 850 /* Bus 8: ucd90320@b */ 851 /* Bus 8: ucd90320@c */ 852 853 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c); 854 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4d); 855 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 9), 0x50, 128 * KiB); 856 857 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c); 858 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4d); 859 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 10), 0x50, 128 * KiB); 860 861 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105, 862 0x48); 863 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105, 864 0x49); 865 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), 866 "pca9546", 0x70); 867 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 868 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 869 create_pca9552(soc, 11, 0x60); 870 871 872 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 13), 0x50, 64 * KiB); 873 create_pca9552(soc, 13, 0x60); 874 875 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 14), 0x50, 64 * KiB); 876 create_pca9552(soc, 14, 0x60); 877 878 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 15), 0x50, 64 * KiB); 879 create_pca9552(soc, 15, 0x60); 880 } 881 882 static void get_pca9548_channels(I2CBus *bus, uint8_t mux_addr, 883 I2CBus **channels) 884 { 885 I2CSlave *mux = i2c_slave_create_simple(bus, "pca9548", mux_addr); 886 for (int i = 0; i < 8; i++) { 887 channels[i] = pca954x_i2c_get_bus(mux, i); 888 } 889 } 890 891 #define TYPE_LM75 TYPE_TMP105 892 #define TYPE_TMP75 TYPE_TMP105 893 #define TYPE_TMP422 "tmp422" 894 895 static void fuji_bmc_i2c_init(AspeedMachineState *bmc) 896 { 897 AspeedSoCState *soc = bmc->soc; 898 I2CBus *i2c[144] = {}; 899 900 for (int i = 0; i < 16; i++) { 901 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); 902 } 903 I2CBus *i2c180 = i2c[2]; 904 I2CBus *i2c480 = i2c[8]; 905 I2CBus *i2c600 = i2c[11]; 906 907 get_pca9548_channels(i2c180, 0x70, &i2c[16]); 908 get_pca9548_channels(i2c480, 0x70, &i2c[24]); 909 /* NOTE: The device tree skips [32, 40) in the alias numbering */ 910 get_pca9548_channels(i2c600, 0x77, &i2c[40]); 911 get_pca9548_channels(i2c[24], 0x71, &i2c[48]); 912 get_pca9548_channels(i2c[25], 0x72, &i2c[56]); 913 get_pca9548_channels(i2c[26], 0x76, &i2c[64]); 914 get_pca9548_channels(i2c[27], 0x76, &i2c[72]); 915 for (int i = 0; i < 8; i++) { 916 get_pca9548_channels(i2c[40 + i], 0x76, &i2c[80 + i * 8]); 917 } 918 919 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4c); 920 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4d); 921 922 /* 923 * EEPROM 24c64 size is 64Kbits or 8 Kbytes 924 * 24c02 size is 2Kbits or 256 bytes 925 */ 926 at24c_eeprom_init(i2c[19], 0x52, 8 * KiB); 927 at24c_eeprom_init(i2c[20], 0x50, 256); 928 at24c_eeprom_init(i2c[22], 0x52, 256); 929 930 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x48); 931 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x49); 932 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x4a); 933 i2c_slave_create_simple(i2c[3], TYPE_TMP422, 0x4c); 934 935 at24c_eeprom_init(i2c[8], 0x51, 8 * KiB); 936 i2c_slave_create_simple(i2c[8], TYPE_LM75, 0x4a); 937 938 i2c_slave_create_simple(i2c[50], TYPE_LM75, 0x4c); 939 at24c_eeprom_init(i2c[50], 0x52, 8 * KiB); 940 i2c_slave_create_simple(i2c[51], TYPE_TMP75, 0x48); 941 i2c_slave_create_simple(i2c[52], TYPE_TMP75, 0x49); 942 943 i2c_slave_create_simple(i2c[59], TYPE_TMP75, 0x48); 944 i2c_slave_create_simple(i2c[60], TYPE_TMP75, 0x49); 945 946 at24c_eeprom_init(i2c[65], 0x53, 8 * KiB); 947 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x49); 948 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x48); 949 at24c_eeprom_init(i2c[68], 0x52, 8 * KiB); 950 at24c_eeprom_init(i2c[69], 0x52, 8 * KiB); 951 at24c_eeprom_init(i2c[70], 0x52, 8 * KiB); 952 at24c_eeprom_init(i2c[71], 0x52, 8 * KiB); 953 954 at24c_eeprom_init(i2c[73], 0x53, 8 * KiB); 955 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x49); 956 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x48); 957 at24c_eeprom_init(i2c[76], 0x52, 8 * KiB); 958 at24c_eeprom_init(i2c[77], 0x52, 8 * KiB); 959 at24c_eeprom_init(i2c[78], 0x52, 8 * KiB); 960 at24c_eeprom_init(i2c[79], 0x52, 8 * KiB); 961 at24c_eeprom_init(i2c[28], 0x50, 256); 962 963 for (int i = 0; i < 8; i++) { 964 at24c_eeprom_init(i2c[81 + i * 8], 0x56, 64 * KiB); 965 i2c_slave_create_simple(i2c[82 + i * 8], TYPE_TMP75, 0x48); 966 i2c_slave_create_simple(i2c[83 + i * 8], TYPE_TMP75, 0x4b); 967 i2c_slave_create_simple(i2c[84 + i * 8], TYPE_TMP75, 0x4a); 968 } 969 } 970 971 #define TYPE_TMP421 "tmp421" 972 973 static void bletchley_bmc_i2c_init(AspeedMachineState *bmc) 974 { 975 AspeedSoCState *soc = bmc->soc; 976 I2CBus *i2c[13] = {}; 977 for (int i = 0; i < 13; i++) { 978 if ((i == 8) || (i == 11)) { 979 continue; 980 } 981 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); 982 } 983 984 /* Bus 0 - 5 all have the same config. */ 985 for (int i = 0; i < 6; i++) { 986 /* Missing model: ti,ina230 @ 0x45 */ 987 /* Missing model: mps,mp5023 @ 0x40 */ 988 i2c_slave_create_simple(i2c[i], TYPE_TMP421, 0x4f); 989 /* Missing model: nxp,pca9539 @ 0x76, but PCA9552 works enough */ 990 i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x76); 991 i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x67); 992 /* Missing model: fsc,fusb302 @ 0x22 */ 993 } 994 995 /* Bus 6 */ 996 at24c_eeprom_init(i2c[6], 0x56, 65536); 997 /* Missing model: nxp,pcf85263 @ 0x51 , but ds1338 works enough */ 998 i2c_slave_create_simple(i2c[6], "ds1338", 0x51); 999 1000 1001 /* Bus 7 */ 1002 at24c_eeprom_init(i2c[7], 0x54, 65536); 1003 1004 /* Bus 9 */ 1005 i2c_slave_create_simple(i2c[9], TYPE_TMP421, 0x4f); 1006 1007 /* Bus 10 */ 1008 i2c_slave_create_simple(i2c[10], TYPE_TMP421, 0x4f); 1009 /* Missing model: ti,hdc1080 @ 0x40 */ 1010 i2c_slave_create_simple(i2c[10], TYPE_PCA9552, 0x67); 1011 1012 /* Bus 12 */ 1013 /* Missing model: adi,adm1278 @ 0x11 */ 1014 i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4c); 1015 i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4d); 1016 i2c_slave_create_simple(i2c[12], TYPE_PCA9552, 0x67); 1017 } 1018 1019 static void fby35_i2c_init(AspeedMachineState *bmc) 1020 { 1021 AspeedSoCState *soc = bmc->soc; 1022 I2CBus *i2c[16]; 1023 1024 for (int i = 0; i < 16; i++) { 1025 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); 1026 } 1027 1028 i2c_slave_create_simple(i2c[2], TYPE_LM75, 0x4f); 1029 i2c_slave_create_simple(i2c[8], TYPE_TMP421, 0x1f); 1030 /* Hotswap controller is actually supposed to be mp5920 or ltc4282. */ 1031 i2c_slave_create_simple(i2c[11], "adm1272", 0x44); 1032 i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4e); 1033 i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4f); 1034 1035 at24c_eeprom_init(i2c[4], 0x51, 128 * KiB); 1036 at24c_eeprom_init(i2c[6], 0x51, 128 * KiB); 1037 at24c_eeprom_init_rom(i2c[8], 0x50, 32 * KiB, fby35_nic_fruid, 1038 fby35_nic_fruid_len); 1039 at24c_eeprom_init_rom(i2c[11], 0x51, 128 * KiB, fby35_bb_fruid, 1040 fby35_bb_fruid_len); 1041 at24c_eeprom_init_rom(i2c[11], 0x54, 128 * KiB, fby35_bmc_fruid, 1042 fby35_bmc_fruid_len); 1043 1044 /* 1045 * TODO: There is a multi-master i2c connection to an AST1030 MiniBMC on 1046 * buses 0, 1, 2, 3, and 9. Source address 0x10, target address 0x20 on 1047 * each. 1048 */ 1049 } 1050 1051 static void qcom_dc_scm_bmc_i2c_init(AspeedMachineState *bmc) 1052 { 1053 AspeedSoCState *soc = bmc->soc; 1054 1055 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 15), "tmp105", 0x4d); 1056 } 1057 1058 static void qcom_dc_scm_firework_i2c_init(AspeedMachineState *bmc) 1059 { 1060 AspeedSoCState *soc = bmc->soc; 1061 I2CSlave *therm_mux, *cpuvr_mux; 1062 1063 /* Create the generic DC-SCM hardware */ 1064 qcom_dc_scm_bmc_i2c_init(bmc); 1065 1066 /* Now create the Firework specific hardware */ 1067 1068 /* I2C7 CPUVR MUX */ 1069 cpuvr_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), 1070 "pca9546", 0x70); 1071 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 0), "pca9548", 0x72); 1072 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 1), "pca9548", 0x72); 1073 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 2), "pca9548", 0x72); 1074 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 3), "pca9548", 0x72); 1075 1076 /* I2C8 Thermal Diodes*/ 1077 therm_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), 1078 "pca9548", 0x70); 1079 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 0), TYPE_LM75, 0x4C); 1080 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 1), TYPE_LM75, 0x4C); 1081 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 2), TYPE_LM75, 0x48); 1082 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 3), TYPE_LM75, 0x48); 1083 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 4), TYPE_LM75, 0x48); 1084 1085 /* I2C9 Fan Controller (MAX31785) */ 1086 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x52); 1087 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x54); 1088 } 1089 1090 static bool aspeed_get_mmio_exec(Object *obj, Error **errp) 1091 { 1092 return ASPEED_MACHINE(obj)->mmio_exec; 1093 } 1094 1095 static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp) 1096 { 1097 ASPEED_MACHINE(obj)->mmio_exec = value; 1098 } 1099 1100 static void aspeed_machine_instance_init(Object *obj) 1101 { 1102 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(obj); 1103 1104 ASPEED_MACHINE(obj)->mmio_exec = false; 1105 ASPEED_MACHINE(obj)->hw_strap1 = amc->hw_strap1; 1106 } 1107 1108 static char *aspeed_get_fmc_model(Object *obj, Error **errp) 1109 { 1110 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1111 return g_strdup(bmc->fmc_model); 1112 } 1113 1114 static void aspeed_set_fmc_model(Object *obj, const char *value, Error **errp) 1115 { 1116 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1117 1118 g_free(bmc->fmc_model); 1119 bmc->fmc_model = g_strdup(value); 1120 } 1121 1122 static char *aspeed_get_spi_model(Object *obj, Error **errp) 1123 { 1124 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1125 return g_strdup(bmc->spi_model); 1126 } 1127 1128 static void aspeed_set_spi_model(Object *obj, const char *value, Error **errp) 1129 { 1130 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1131 1132 g_free(bmc->spi_model); 1133 bmc->spi_model = g_strdup(value); 1134 } 1135 1136 static char *aspeed_get_bmc_console(Object *obj, Error **errp) 1137 { 1138 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1139 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc); 1140 int uart_chosen = bmc->uart_chosen ? bmc->uart_chosen : amc->uart_default; 1141 1142 return g_strdup_printf("uart%d", aspeed_uart_index(uart_chosen)); 1143 } 1144 1145 static void aspeed_set_bmc_console(Object *obj, const char *value, Error **errp) 1146 { 1147 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1148 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc); 1149 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(amc->soc_name)); 1150 int val; 1151 int uart_first = aspeed_uart_first(sc); 1152 int uart_last = aspeed_uart_last(sc); 1153 1154 if (sscanf(value, "uart%u", &val) != 1) { 1155 error_setg(errp, "Bad value for \"uart\" property"); 1156 return; 1157 } 1158 1159 /* The number of UART depends on the SoC */ 1160 if (val < uart_first || val > uart_last) { 1161 error_setg(errp, "\"uart\" should be in range [%d - %d]", 1162 uart_first, uart_last); 1163 return; 1164 } 1165 bmc->uart_chosen = val + ASPEED_DEV_UART0; 1166 } 1167 1168 static void aspeed_machine_class_props_init(ObjectClass *oc) 1169 { 1170 object_class_property_add_bool(oc, "execute-in-place", 1171 aspeed_get_mmio_exec, 1172 aspeed_set_mmio_exec); 1173 object_class_property_set_description(oc, "execute-in-place", 1174 "boot directly from CE0 flash device"); 1175 1176 object_class_property_add_str(oc, "bmc-console", aspeed_get_bmc_console, 1177 aspeed_set_bmc_console); 1178 object_class_property_set_description(oc, "bmc-console", 1179 "Change the default UART to \"uartX\""); 1180 1181 object_class_property_add_str(oc, "fmc-model", aspeed_get_fmc_model, 1182 aspeed_set_fmc_model); 1183 object_class_property_set_description(oc, "fmc-model", 1184 "Change the FMC Flash model"); 1185 object_class_property_add_str(oc, "spi-model", aspeed_get_spi_model, 1186 aspeed_set_spi_model); 1187 object_class_property_set_description(oc, "spi-model", 1188 "Change the SPI Flash model"); 1189 } 1190 1191 static void aspeed_machine_class_init_cpus_defaults(MachineClass *mc) 1192 { 1193 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(mc); 1194 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(amc->soc_name)); 1195 1196 mc->default_cpus = sc->num_cpus; 1197 mc->min_cpus = sc->num_cpus; 1198 mc->max_cpus = sc->num_cpus; 1199 mc->valid_cpu_types = sc->valid_cpu_types; 1200 } 1201 1202 static bool aspeed_machine_ast2600_get_boot_from_emmc(Object *obj, Error **errp) 1203 { 1204 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1205 1206 return !!(bmc->hw_strap1 & SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC); 1207 } 1208 1209 static void aspeed_machine_ast2600_set_boot_from_emmc(Object *obj, bool value, 1210 Error **errp) 1211 { 1212 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1213 1214 if (value) { 1215 bmc->hw_strap1 |= SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC; 1216 } else { 1217 bmc->hw_strap1 &= ~SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC; 1218 } 1219 } 1220 1221 static void aspeed_machine_ast2600_class_emmc_init(ObjectClass *oc) 1222 { 1223 object_class_property_add_bool(oc, "boot-emmc", 1224 aspeed_machine_ast2600_get_boot_from_emmc, 1225 aspeed_machine_ast2600_set_boot_from_emmc); 1226 object_class_property_set_description(oc, "boot-emmc", 1227 "Set or unset boot from EMMC"); 1228 } 1229 1230 static void aspeed_machine_class_init(ObjectClass *oc, const void *data) 1231 { 1232 MachineClass *mc = MACHINE_CLASS(oc); 1233 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1234 1235 mc->init = aspeed_machine_init; 1236 mc->no_floppy = 1; 1237 mc->no_cdrom = 1; 1238 mc->no_parallel = 1; 1239 mc->default_ram_id = "ram"; 1240 amc->macs_mask = ASPEED_MAC0_ON; 1241 amc->uart_default = ASPEED_DEV_UART5; 1242 1243 aspeed_machine_class_props_init(oc); 1244 } 1245 1246 static void aspeed_machine_palmetto_class_init(ObjectClass *oc, 1247 const void *data) 1248 { 1249 MachineClass *mc = MACHINE_CLASS(oc); 1250 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1251 1252 mc->desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)"; 1253 amc->soc_name = "ast2400-a1"; 1254 amc->hw_strap1 = PALMETTO_BMC_HW_STRAP1; 1255 amc->fmc_model = "n25q256a"; 1256 amc->spi_model = "mx25l25635f"; 1257 amc->num_cs = 1; 1258 amc->i2c_init = palmetto_bmc_i2c_init; 1259 mc->auto_create_sdcard = true; 1260 mc->default_ram_size = 256 * MiB; 1261 aspeed_machine_class_init_cpus_defaults(mc); 1262 }; 1263 1264 static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc, 1265 const void *data) 1266 { 1267 MachineClass *mc = MACHINE_CLASS(oc); 1268 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1269 1270 mc->desc = "Quanta-Q71l BMC (ARM926EJ-S)"; 1271 amc->soc_name = "ast2400-a1"; 1272 amc->hw_strap1 = QUANTA_Q71L_BMC_HW_STRAP1; 1273 amc->fmc_model = "n25q256a"; 1274 amc->spi_model = "mx25l25635e"; 1275 amc->num_cs = 1; 1276 amc->i2c_init = quanta_q71l_bmc_i2c_init; 1277 mc->auto_create_sdcard = true; 1278 mc->default_ram_size = 128 * MiB; 1279 aspeed_machine_class_init_cpus_defaults(mc); 1280 } 1281 1282 static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc, 1283 const void *data) 1284 { 1285 MachineClass *mc = MACHINE_CLASS(oc); 1286 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1287 1288 mc->desc = "Supermicro X11 BMC (ARM926EJ-S)"; 1289 amc->soc_name = "ast2400-a1"; 1290 amc->hw_strap1 = SUPERMICROX11_BMC_HW_STRAP1; 1291 amc->fmc_model = "mx25l25635e"; 1292 amc->spi_model = "mx25l25635e"; 1293 amc->num_cs = 1; 1294 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1295 amc->i2c_init = palmetto_bmc_i2c_init; 1296 mc->auto_create_sdcard = true; 1297 mc->default_ram_size = 256 * MiB; 1298 aspeed_machine_class_init_cpus_defaults(mc); 1299 } 1300 1301 static void aspeed_machine_supermicro_x11spi_bmc_class_init(ObjectClass *oc, 1302 const void *data) 1303 { 1304 MachineClass *mc = MACHINE_CLASS(oc); 1305 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1306 1307 mc->desc = "Supermicro X11 SPI BMC (ARM1176)"; 1308 amc->soc_name = "ast2500-a1"; 1309 amc->hw_strap1 = SUPERMICRO_X11SPI_BMC_HW_STRAP1; 1310 amc->fmc_model = "mx25l25635e"; 1311 amc->spi_model = "mx25l25635e"; 1312 amc->num_cs = 1; 1313 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1314 amc->i2c_init = palmetto_bmc_i2c_init; 1315 mc->auto_create_sdcard = true; 1316 mc->default_ram_size = 512 * MiB; 1317 aspeed_machine_class_init_cpus_defaults(mc); 1318 } 1319 1320 static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, 1321 const void *data) 1322 { 1323 MachineClass *mc = MACHINE_CLASS(oc); 1324 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1325 1326 mc->desc = "Aspeed AST2500 EVB (ARM1176)"; 1327 amc->soc_name = "ast2500-a1"; 1328 amc->hw_strap1 = AST2500_EVB_HW_STRAP1; 1329 amc->fmc_model = "mx25l25635e"; 1330 amc->spi_model = "mx25l25635f"; 1331 amc->num_cs = 1; 1332 amc->i2c_init = ast2500_evb_i2c_init; 1333 mc->auto_create_sdcard = true; 1334 mc->default_ram_size = 512 * MiB; 1335 aspeed_machine_class_init_cpus_defaults(mc); 1336 }; 1337 1338 static void aspeed_machine_yosemitev2_class_init(ObjectClass *oc, 1339 const void *data) 1340 { 1341 MachineClass *mc = MACHINE_CLASS(oc); 1342 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1343 1344 mc->desc = "Facebook YosemiteV2 BMC (ARM1176)"; 1345 amc->soc_name = "ast2500-a1"; 1346 amc->hw_strap1 = AST2500_EVB_HW_STRAP1; 1347 amc->hw_strap2 = 0; 1348 amc->fmc_model = "n25q256a"; 1349 amc->spi_model = "mx25l25635e"; 1350 amc->num_cs = 2; 1351 amc->i2c_init = yosemitev2_bmc_i2c_init; 1352 mc->auto_create_sdcard = true; 1353 mc->default_ram_size = 512 * MiB; 1354 aspeed_machine_class_init_cpus_defaults(mc); 1355 }; 1356 1357 static void aspeed_machine_romulus_class_init(ObjectClass *oc, 1358 const void *data) 1359 { 1360 MachineClass *mc = MACHINE_CLASS(oc); 1361 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1362 1363 mc->desc = "OpenPOWER Romulus BMC (ARM1176)"; 1364 amc->soc_name = "ast2500-a1"; 1365 amc->hw_strap1 = ROMULUS_BMC_HW_STRAP1; 1366 amc->fmc_model = "n25q256a"; 1367 amc->spi_model = "mx66l1g45g"; 1368 amc->num_cs = 2; 1369 amc->i2c_init = romulus_bmc_i2c_init; 1370 mc->auto_create_sdcard = true; 1371 mc->default_ram_size = 512 * MiB; 1372 aspeed_machine_class_init_cpus_defaults(mc); 1373 }; 1374 1375 static void aspeed_machine_tiogapass_class_init(ObjectClass *oc, 1376 const void *data) 1377 { 1378 MachineClass *mc = MACHINE_CLASS(oc); 1379 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1380 1381 mc->desc = "Facebook Tiogapass BMC (ARM1176)"; 1382 amc->soc_name = "ast2500-a1"; 1383 amc->hw_strap1 = AST2500_EVB_HW_STRAP1; 1384 amc->hw_strap2 = 0; 1385 amc->fmc_model = "n25q256a"; 1386 amc->spi_model = "mx25l25635e"; 1387 amc->num_cs = 2; 1388 amc->i2c_init = tiogapass_bmc_i2c_init; 1389 mc->auto_create_sdcard = true; 1390 mc->default_ram_size = 1 * GiB; 1391 aspeed_machine_class_init_cpus_defaults(mc); 1392 }; 1393 1394 static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, 1395 const void *data) 1396 { 1397 MachineClass *mc = MACHINE_CLASS(oc); 1398 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1399 1400 mc->desc = "OCP SonoraPass BMC (ARM1176)"; 1401 amc->soc_name = "ast2500-a1"; 1402 amc->hw_strap1 = SONORAPASS_BMC_HW_STRAP1; 1403 amc->fmc_model = "mx66l1g45g"; 1404 amc->spi_model = "mx66l1g45g"; 1405 amc->num_cs = 2; 1406 amc->i2c_init = sonorapass_bmc_i2c_init; 1407 mc->auto_create_sdcard = true; 1408 mc->default_ram_size = 512 * MiB; 1409 aspeed_machine_class_init_cpus_defaults(mc); 1410 }; 1411 1412 static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, 1413 const void *data) 1414 { 1415 MachineClass *mc = MACHINE_CLASS(oc); 1416 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1417 1418 mc->desc = "OpenPOWER Witherspoon BMC (ARM1176)"; 1419 amc->soc_name = "ast2500-a1"; 1420 amc->hw_strap1 = WITHERSPOON_BMC_HW_STRAP1; 1421 amc->fmc_model = "mx25l25635f"; 1422 amc->spi_model = "mx66l1g45g"; 1423 amc->num_cs = 2; 1424 amc->i2c_init = witherspoon_bmc_i2c_init; 1425 mc->auto_create_sdcard = true; 1426 mc->default_ram_size = 512 * MiB; 1427 aspeed_machine_class_init_cpus_defaults(mc); 1428 }; 1429 1430 static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, 1431 const void *data) 1432 { 1433 MachineClass *mc = MACHINE_CLASS(oc); 1434 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1435 1436 mc->desc = "Aspeed AST2600 EVB (Cortex-A7)"; 1437 amc->soc_name = "ast2600-a3"; 1438 amc->hw_strap1 = AST2600_EVB_HW_STRAP1; 1439 amc->hw_strap2 = AST2600_EVB_HW_STRAP2; 1440 amc->fmc_model = "mx66u51235f"; 1441 amc->spi_model = "mx66u51235f"; 1442 amc->num_cs = 1; 1443 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON | 1444 ASPEED_MAC3_ON; 1445 amc->sdhci_wp_inverted = true; 1446 amc->i2c_init = ast2600_evb_i2c_init; 1447 mc->auto_create_sdcard = true; 1448 mc->default_ram_size = 1 * GiB; 1449 aspeed_machine_class_init_cpus_defaults(mc); 1450 aspeed_machine_ast2600_class_emmc_init(oc); 1451 }; 1452 1453 static void aspeed_machine_g220a_class_init(ObjectClass *oc, const void *data) 1454 { 1455 MachineClass *mc = MACHINE_CLASS(oc); 1456 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1457 1458 mc->desc = "Bytedance G220A BMC (ARM1176)"; 1459 amc->soc_name = "ast2500-a1"; 1460 amc->hw_strap1 = G220A_BMC_HW_STRAP1; 1461 amc->fmc_model = "n25q512a"; 1462 amc->spi_model = "mx25l25635e"; 1463 amc->num_cs = 2; 1464 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1465 amc->i2c_init = g220a_bmc_i2c_init; 1466 mc->auto_create_sdcard = true; 1467 mc->default_ram_size = 1024 * MiB; 1468 aspeed_machine_class_init_cpus_defaults(mc); 1469 }; 1470 1471 static void aspeed_machine_fp5280g2_class_init(ObjectClass *oc, 1472 const void *data) 1473 { 1474 MachineClass *mc = MACHINE_CLASS(oc); 1475 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1476 1477 mc->desc = "Inspur FP5280G2 BMC (ARM1176)"; 1478 amc->soc_name = "ast2500-a1"; 1479 amc->hw_strap1 = FP5280G2_BMC_HW_STRAP1; 1480 amc->fmc_model = "n25q512a"; 1481 amc->spi_model = "mx25l25635e"; 1482 amc->num_cs = 2; 1483 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1484 amc->i2c_init = fp5280g2_bmc_i2c_init; 1485 mc->auto_create_sdcard = true; 1486 mc->default_ram_size = 512 * MiB; 1487 aspeed_machine_class_init_cpus_defaults(mc); 1488 }; 1489 1490 static void aspeed_machine_rainier_class_init(ObjectClass *oc, const void *data) 1491 { 1492 MachineClass *mc = MACHINE_CLASS(oc); 1493 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1494 1495 mc->desc = "IBM Rainier BMC (Cortex-A7)"; 1496 amc->soc_name = "ast2600-a3"; 1497 amc->hw_strap1 = RAINIER_BMC_HW_STRAP1; 1498 amc->hw_strap2 = RAINIER_BMC_HW_STRAP2; 1499 amc->fmc_model = "mx66l1g45g"; 1500 amc->spi_model = "mx66l1g45g"; 1501 amc->num_cs = 2; 1502 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON; 1503 amc->i2c_init = rainier_bmc_i2c_init; 1504 mc->auto_create_sdcard = true; 1505 mc->default_ram_size = 1 * GiB; 1506 aspeed_machine_class_init_cpus_defaults(mc); 1507 aspeed_machine_ast2600_class_emmc_init(oc); 1508 }; 1509 1510 #define FUJI_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB) 1511 1512 static void aspeed_machine_fuji_class_init(ObjectClass *oc, const void *data) 1513 { 1514 MachineClass *mc = MACHINE_CLASS(oc); 1515 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1516 1517 mc->desc = "Facebook Fuji BMC (Cortex-A7)"; 1518 amc->soc_name = "ast2600-a3"; 1519 amc->hw_strap1 = FUJI_BMC_HW_STRAP1; 1520 amc->hw_strap2 = FUJI_BMC_HW_STRAP2; 1521 amc->fmc_model = "mx66l1g45g"; 1522 amc->spi_model = "mx66l1g45g"; 1523 amc->num_cs = 2; 1524 amc->macs_mask = ASPEED_MAC3_ON; 1525 amc->i2c_init = fuji_bmc_i2c_init; 1526 amc->uart_default = ASPEED_DEV_UART1; 1527 mc->auto_create_sdcard = true; 1528 mc->default_ram_size = FUJI_BMC_RAM_SIZE; 1529 aspeed_machine_class_init_cpus_defaults(mc); 1530 }; 1531 1532 #define BLETCHLEY_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB) 1533 1534 static void aspeed_machine_bletchley_class_init(ObjectClass *oc, 1535 const void *data) 1536 { 1537 MachineClass *mc = MACHINE_CLASS(oc); 1538 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1539 1540 mc->desc = "Facebook Bletchley BMC (Cortex-A7)"; 1541 amc->soc_name = "ast2600-a3"; 1542 amc->hw_strap1 = BLETCHLEY_BMC_HW_STRAP1; 1543 amc->hw_strap2 = BLETCHLEY_BMC_HW_STRAP2; 1544 amc->fmc_model = "w25q01jvq"; 1545 amc->spi_model = NULL; 1546 amc->num_cs = 2; 1547 amc->macs_mask = ASPEED_MAC2_ON; 1548 amc->i2c_init = bletchley_bmc_i2c_init; 1549 mc->auto_create_sdcard = true; 1550 mc->default_ram_size = BLETCHLEY_BMC_RAM_SIZE; 1551 aspeed_machine_class_init_cpus_defaults(mc); 1552 } 1553 1554 static void fby35_reset(MachineState *state, ResetType type) 1555 { 1556 AspeedMachineState *bmc = ASPEED_MACHINE(state); 1557 AspeedGPIOState *gpio = &bmc->soc->gpio; 1558 1559 qemu_devices_reset(type); 1560 1561 /* Board ID: 7 (Class-1, 4 slots) */ 1562 object_property_set_bool(OBJECT(gpio), "gpioV4", true, &error_fatal); 1563 object_property_set_bool(OBJECT(gpio), "gpioV5", true, &error_fatal); 1564 object_property_set_bool(OBJECT(gpio), "gpioV6", true, &error_fatal); 1565 object_property_set_bool(OBJECT(gpio), "gpioV7", false, &error_fatal); 1566 1567 /* Slot presence pins, inverse polarity. (False means present) */ 1568 object_property_set_bool(OBJECT(gpio), "gpioH4", false, &error_fatal); 1569 object_property_set_bool(OBJECT(gpio), "gpioH5", true, &error_fatal); 1570 object_property_set_bool(OBJECT(gpio), "gpioH6", true, &error_fatal); 1571 object_property_set_bool(OBJECT(gpio), "gpioH7", true, &error_fatal); 1572 1573 /* Slot 12v power pins, normal polarity. (True means powered-on) */ 1574 object_property_set_bool(OBJECT(gpio), "gpioB2", true, &error_fatal); 1575 object_property_set_bool(OBJECT(gpio), "gpioB3", false, &error_fatal); 1576 object_property_set_bool(OBJECT(gpio), "gpioB4", false, &error_fatal); 1577 object_property_set_bool(OBJECT(gpio), "gpioB5", false, &error_fatal); 1578 } 1579 1580 static void aspeed_machine_fby35_class_init(ObjectClass *oc, const void *data) 1581 { 1582 MachineClass *mc = MACHINE_CLASS(oc); 1583 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1584 1585 mc->desc = "Facebook fby35 BMC (Cortex-A7)"; 1586 mc->reset = fby35_reset; 1587 amc->fmc_model = "mx66l1g45g"; 1588 amc->num_cs = 2; 1589 amc->macs_mask = ASPEED_MAC3_ON; 1590 amc->i2c_init = fby35_i2c_init; 1591 mc->auto_create_sdcard = true; 1592 /* FIXME: Replace this macro with something more general */ 1593 mc->default_ram_size = FUJI_BMC_RAM_SIZE; 1594 aspeed_machine_class_init_cpus_defaults(mc); 1595 } 1596 1597 #define AST1030_INTERNAL_FLASH_SIZE (1024 * 1024) 1598 /* Main SYSCLK frequency in Hz (200MHz) */ 1599 #define SYSCLK_FRQ 200000000ULL 1600 1601 static void aspeed_minibmc_machine_init(MachineState *machine) 1602 { 1603 AspeedMachineState *bmc = ASPEED_MACHINE(machine); 1604 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine); 1605 Clock *sysclk; 1606 1607 sysclk = clock_new(OBJECT(machine), "SYSCLK"); 1608 clock_set_hz(sysclk, SYSCLK_FRQ); 1609 1610 bmc->soc = ASPEED_SOC(object_new(amc->soc_name)); 1611 object_property_add_child(OBJECT(machine), "soc", OBJECT(bmc->soc)); 1612 object_unref(OBJECT(bmc->soc)); 1613 qdev_connect_clock_in(DEVICE(bmc->soc), "sysclk", sysclk); 1614 1615 object_property_set_link(OBJECT(bmc->soc), "memory", 1616 OBJECT(get_system_memory()), &error_abort); 1617 connect_serial_hds_to_uarts(bmc); 1618 qdev_realize(DEVICE(bmc->soc), NULL, &error_abort); 1619 1620 if (defaults_enabled()) { 1621 aspeed_board_init_flashes(&bmc->soc->fmc, 1622 bmc->fmc_model ? bmc->fmc_model : amc->fmc_model, 1623 amc->num_cs, 1624 0); 1625 1626 aspeed_board_init_flashes(&bmc->soc->spi[0], 1627 bmc->spi_model ? bmc->spi_model : amc->spi_model, 1628 amc->num_cs, amc->num_cs); 1629 1630 aspeed_board_init_flashes(&bmc->soc->spi[1], 1631 bmc->spi_model ? bmc->spi_model : amc->spi_model, 1632 amc->num_cs, (amc->num_cs * 2)); 1633 } 1634 1635 if (amc->i2c_init) { 1636 amc->i2c_init(bmc); 1637 } 1638 1639 armv7m_load_kernel(ARM_CPU(first_cpu), 1640 machine->kernel_filename, 1641 0, 1642 AST1030_INTERNAL_FLASH_SIZE); 1643 } 1644 1645 static void ast1030_evb_i2c_init(AspeedMachineState *bmc) 1646 { 1647 AspeedSoCState *soc = bmc->soc; 1648 1649 /* U10 24C08 connects to SDA/SCL Group 1 by default */ 1650 uint8_t *eeprom_buf = g_malloc0(32 * 1024); 1651 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, eeprom_buf); 1652 1653 /* U11 LM75 connects to SDA/SCL Group 2 by default */ 1654 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4d); 1655 } 1656 1657 static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc, 1658 const void *data) 1659 { 1660 MachineClass *mc = MACHINE_CLASS(oc); 1661 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1662 1663 mc->desc = "Aspeed AST1030 MiniBMC (Cortex-M4)"; 1664 amc->soc_name = "ast1030-a1"; 1665 amc->hw_strap1 = 0; 1666 amc->hw_strap2 = 0; 1667 mc->init = aspeed_minibmc_machine_init; 1668 amc->i2c_init = ast1030_evb_i2c_init; 1669 mc->default_ram_size = 0; 1670 amc->fmc_model = "w25q80bl"; 1671 amc->spi_model = "w25q256"; 1672 amc->num_cs = 2; 1673 amc->macs_mask = 0; 1674 aspeed_machine_class_init_cpus_defaults(mc); 1675 } 1676 1677 #ifdef TARGET_AARCH64 1678 static void ast2700_evb_i2c_init(AspeedMachineState *bmc) 1679 { 1680 AspeedSoCState *soc = bmc->soc; 1681 1682 /* LM75 is compatible with TMP105 driver */ 1683 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), 1684 TYPE_TMP105, 0x4d); 1685 } 1686 1687 static void aspeed_machine_ast2700a0_evb_class_init(ObjectClass *oc, 1688 const void *data) 1689 { 1690 MachineClass *mc = MACHINE_CLASS(oc); 1691 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1692 1693 mc->alias = "ast2700-evb"; 1694 mc->desc = "Aspeed AST2700 A0 EVB (Cortex-A35)"; 1695 amc->soc_name = "ast2700-a0"; 1696 amc->hw_strap1 = AST2700_EVB_HW_STRAP1; 1697 amc->hw_strap2 = AST2700_EVB_HW_STRAP2; 1698 amc->fmc_model = "w25q01jvq"; 1699 amc->spi_model = "w25q512jv"; 1700 amc->num_cs = 2; 1701 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON; 1702 amc->uart_default = ASPEED_DEV_UART12; 1703 amc->i2c_init = ast2700_evb_i2c_init; 1704 mc->auto_create_sdcard = true; 1705 mc->default_ram_size = 1 * GiB; 1706 aspeed_machine_class_init_cpus_defaults(mc); 1707 } 1708 1709 static void aspeed_machine_ast2700a1_evb_class_init(ObjectClass *oc, 1710 const void *data) 1711 { 1712 MachineClass *mc = MACHINE_CLASS(oc); 1713 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1714 1715 mc->desc = "Aspeed AST2700 A1 EVB (Cortex-A35)"; 1716 amc->soc_name = "ast2700-a1"; 1717 amc->hw_strap1 = AST2700_EVB_HW_STRAP1; 1718 amc->hw_strap2 = AST2700_EVB_HW_STRAP2; 1719 amc->fmc_model = "w25q01jvq"; 1720 amc->spi_model = "w25q512jv"; 1721 amc->num_cs = 2; 1722 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON; 1723 amc->uart_default = ASPEED_DEV_UART12; 1724 amc->i2c_init = ast2700_evb_i2c_init; 1725 mc->auto_create_sdcard = true; 1726 mc->default_ram_size = 1 * GiB; 1727 aspeed_machine_class_init_cpus_defaults(mc); 1728 } 1729 #endif 1730 1731 static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc, 1732 const void *data) 1733 { 1734 MachineClass *mc = MACHINE_CLASS(oc); 1735 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1736 1737 mc->desc = "Qualcomm DC-SCM V1 BMC (Cortex A7)"; 1738 amc->soc_name = "ast2600-a3"; 1739 amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1; 1740 amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2; 1741 amc->fmc_model = "n25q512a"; 1742 amc->spi_model = "n25q512a"; 1743 amc->num_cs = 2; 1744 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON; 1745 amc->i2c_init = qcom_dc_scm_bmc_i2c_init; 1746 mc->auto_create_sdcard = true; 1747 mc->default_ram_size = 1 * GiB; 1748 aspeed_machine_class_init_cpus_defaults(mc); 1749 }; 1750 1751 static void aspeed_machine_qcom_firework_class_init(ObjectClass *oc, 1752 const void *data) 1753 { 1754 MachineClass *mc = MACHINE_CLASS(oc); 1755 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1756 1757 mc->desc = "Qualcomm DC-SCM V1/Firework BMC (Cortex A7)"; 1758 amc->soc_name = "ast2600-a3"; 1759 amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1; 1760 amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2; 1761 amc->fmc_model = "n25q512a"; 1762 amc->spi_model = "n25q512a"; 1763 amc->num_cs = 2; 1764 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON; 1765 amc->i2c_init = qcom_dc_scm_firework_i2c_init; 1766 mc->auto_create_sdcard = true; 1767 mc->default_ram_size = 1 * GiB; 1768 aspeed_machine_class_init_cpus_defaults(mc); 1769 }; 1770 1771 static const TypeInfo aspeed_machine_types[] = { 1772 { 1773 .name = MACHINE_TYPE_NAME("palmetto-bmc"), 1774 .parent = TYPE_ASPEED_MACHINE, 1775 .class_init = aspeed_machine_palmetto_class_init, 1776 }, { 1777 .name = MACHINE_TYPE_NAME("supermicrox11-bmc"), 1778 .parent = TYPE_ASPEED_MACHINE, 1779 .class_init = aspeed_machine_supermicrox11_bmc_class_init, 1780 }, { 1781 .name = MACHINE_TYPE_NAME("supermicro-x11spi-bmc"), 1782 .parent = TYPE_ASPEED_MACHINE, 1783 .class_init = aspeed_machine_supermicro_x11spi_bmc_class_init, 1784 }, { 1785 .name = MACHINE_TYPE_NAME("ast2500-evb"), 1786 .parent = TYPE_ASPEED_MACHINE, 1787 .class_init = aspeed_machine_ast2500_evb_class_init, 1788 }, { 1789 .name = MACHINE_TYPE_NAME("romulus-bmc"), 1790 .parent = TYPE_ASPEED_MACHINE, 1791 .class_init = aspeed_machine_romulus_class_init, 1792 }, { 1793 .name = MACHINE_TYPE_NAME("sonorapass-bmc"), 1794 .parent = TYPE_ASPEED_MACHINE, 1795 .class_init = aspeed_machine_sonorapass_class_init, 1796 }, { 1797 .name = MACHINE_TYPE_NAME("witherspoon-bmc"), 1798 .parent = TYPE_ASPEED_MACHINE, 1799 .class_init = aspeed_machine_witherspoon_class_init, 1800 }, { 1801 .name = MACHINE_TYPE_NAME("ast2600-evb"), 1802 .parent = TYPE_ASPEED_MACHINE, 1803 .class_init = aspeed_machine_ast2600_evb_class_init, 1804 }, { 1805 .name = MACHINE_TYPE_NAME("yosemitev2-bmc"), 1806 .parent = TYPE_ASPEED_MACHINE, 1807 .class_init = aspeed_machine_yosemitev2_class_init, 1808 }, { 1809 .name = MACHINE_TYPE_NAME("tiogapass-bmc"), 1810 .parent = TYPE_ASPEED_MACHINE, 1811 .class_init = aspeed_machine_tiogapass_class_init, 1812 }, { 1813 .name = MACHINE_TYPE_NAME("g220a-bmc"), 1814 .parent = TYPE_ASPEED_MACHINE, 1815 .class_init = aspeed_machine_g220a_class_init, 1816 }, { 1817 .name = MACHINE_TYPE_NAME("qcom-dc-scm-v1-bmc"), 1818 .parent = TYPE_ASPEED_MACHINE, 1819 .class_init = aspeed_machine_qcom_dc_scm_v1_class_init, 1820 }, { 1821 .name = MACHINE_TYPE_NAME("qcom-firework-bmc"), 1822 .parent = TYPE_ASPEED_MACHINE, 1823 .class_init = aspeed_machine_qcom_firework_class_init, 1824 }, { 1825 .name = MACHINE_TYPE_NAME("fp5280g2-bmc"), 1826 .parent = TYPE_ASPEED_MACHINE, 1827 .class_init = aspeed_machine_fp5280g2_class_init, 1828 }, { 1829 .name = MACHINE_TYPE_NAME("quanta-q71l-bmc"), 1830 .parent = TYPE_ASPEED_MACHINE, 1831 .class_init = aspeed_machine_quanta_q71l_class_init, 1832 }, { 1833 .name = MACHINE_TYPE_NAME("rainier-bmc"), 1834 .parent = TYPE_ASPEED_MACHINE, 1835 .class_init = aspeed_machine_rainier_class_init, 1836 }, { 1837 .name = MACHINE_TYPE_NAME("fuji-bmc"), 1838 .parent = TYPE_ASPEED_MACHINE, 1839 .class_init = aspeed_machine_fuji_class_init, 1840 }, { 1841 .name = MACHINE_TYPE_NAME("bletchley-bmc"), 1842 .parent = TYPE_ASPEED_MACHINE, 1843 .class_init = aspeed_machine_bletchley_class_init, 1844 }, { 1845 .name = MACHINE_TYPE_NAME("fby35-bmc"), 1846 .parent = MACHINE_TYPE_NAME("ast2600-evb"), 1847 .class_init = aspeed_machine_fby35_class_init, 1848 }, { 1849 .name = MACHINE_TYPE_NAME("ast1030-evb"), 1850 .parent = TYPE_ASPEED_MACHINE, 1851 .class_init = aspeed_minibmc_machine_ast1030_evb_class_init, 1852 #ifdef TARGET_AARCH64 1853 }, { 1854 .name = MACHINE_TYPE_NAME("ast2700a0-evb"), 1855 .parent = TYPE_ASPEED_MACHINE, 1856 .class_init = aspeed_machine_ast2700a0_evb_class_init, 1857 }, { 1858 .name = MACHINE_TYPE_NAME("ast2700a1-evb"), 1859 .parent = TYPE_ASPEED_MACHINE, 1860 .class_init = aspeed_machine_ast2700a1_evb_class_init, 1861 #endif 1862 }, { 1863 .name = TYPE_ASPEED_MACHINE, 1864 .parent = TYPE_MACHINE, 1865 .instance_size = sizeof(AspeedMachineState), 1866 .instance_init = aspeed_machine_instance_init, 1867 .class_size = sizeof(AspeedMachineClass), 1868 .class_init = aspeed_machine_class_init, 1869 .abstract = true, 1870 } 1871 }; 1872 1873 DEFINE_TYPES(aspeed_machine_types) 1874