1 /* 2 * OpenPOWER Palmetto BMC 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * 6 * Copyright 2016 IBM Corp. 7 * 8 * This code is licensed under the GPL version 2 or later. See 9 * the COPYING file in the top-level directory. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "hw/arm/boot.h" 15 #include "hw/arm/aspeed.h" 16 #include "hw/arm/aspeed_soc.h" 17 #include "hw/i2c/i2c_mux_pca954x.h" 18 #include "hw/i2c/smbus_eeprom.h" 19 #include "hw/misc/pca9552.h" 20 #include "hw/sensor/tmp105.h" 21 #include "hw/misc/led.h" 22 #include "hw/qdev-properties.h" 23 #include "sysemu/block-backend.h" 24 #include "sysemu/reset.h" 25 #include "hw/loader.h" 26 #include "qemu/error-report.h" 27 #include "qemu/units.h" 28 #include "hw/qdev-clock.h" 29 30 static struct arm_boot_info aspeed_board_binfo = { 31 .board_id = -1, /* device-tree-only board */ 32 }; 33 34 struct AspeedMachineState { 35 /* Private */ 36 MachineState parent_obj; 37 /* Public */ 38 39 AspeedSoCState soc; 40 MemoryRegion ram_container; 41 MemoryRegion max_ram; 42 bool mmio_exec; 43 char *fmc_model; 44 char *spi_model; 45 }; 46 47 /* Palmetto hardware value: 0x120CE416 */ 48 #define PALMETTO_BMC_HW_STRAP1 ( \ 49 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) | \ 50 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \ 51 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 52 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \ 53 SCU_HW_STRAP_VGA_CLASS_CODE | \ 54 SCU_HW_STRAP_LPC_RESET_PIN | \ 55 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \ 56 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 57 SCU_HW_STRAP_SPI_WIDTH | \ 58 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 59 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 60 61 /* TODO: Find the actual hardware value */ 62 #define SUPERMICROX11_BMC_HW_STRAP1 ( \ 63 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \ 64 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2) | \ 65 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 66 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \ 67 SCU_HW_STRAP_VGA_CLASS_CODE | \ 68 SCU_HW_STRAP_LPC_RESET_PIN | \ 69 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \ 70 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 71 SCU_HW_STRAP_SPI_WIDTH | \ 72 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 73 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 74 75 /* AST2500 evb hardware value: 0xF100C2E6 */ 76 #define AST2500_EVB_HW_STRAP1 (( \ 77 AST2500_HW_STRAP1_DEFAULTS | \ 78 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 79 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 80 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 81 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 82 SCU_HW_STRAP_MAC1_RGMII | \ 83 SCU_HW_STRAP_MAC0_RGMII) & \ 84 ~SCU_HW_STRAP_2ND_BOOT_WDT) 85 86 /* Romulus hardware value: 0xF10AD206 */ 87 #define ROMULUS_BMC_HW_STRAP1 ( \ 88 AST2500_HW_STRAP1_DEFAULTS | \ 89 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 90 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 91 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 92 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 93 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \ 94 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER)) 95 96 /* Sonorapass hardware value: 0xF100D216 */ 97 #define SONORAPASS_BMC_HW_STRAP1 ( \ 98 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 99 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 100 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 101 SCU_AST2500_HW_STRAP_RESERVED28 | \ 102 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 103 SCU_HW_STRAP_VGA_CLASS_CODE | \ 104 SCU_HW_STRAP_LPC_RESET_PIN | \ 105 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 106 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 107 SCU_HW_STRAP_VGA_BIOS_ROM | \ 108 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 109 SCU_AST2500_HW_STRAP_RESERVED1) 110 111 #define G220A_BMC_HW_STRAP1 ( \ 112 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 113 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 114 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 115 SCU_AST2500_HW_STRAP_RESERVED28 | \ 116 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 117 SCU_HW_STRAP_2ND_BOOT_WDT | \ 118 SCU_HW_STRAP_VGA_CLASS_CODE | \ 119 SCU_HW_STRAP_LPC_RESET_PIN | \ 120 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 121 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 122 SCU_HW_STRAP_VGA_SIZE_SET(VGA_64M_DRAM) | \ 123 SCU_AST2500_HW_STRAP_RESERVED1) 124 125 /* FP5280G2 hardware value: 0XF100D286 */ 126 #define FP5280G2_BMC_HW_STRAP1 ( \ 127 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 128 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 129 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 130 SCU_AST2500_HW_STRAP_RESERVED28 | \ 131 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 132 SCU_HW_STRAP_VGA_CLASS_CODE | \ 133 SCU_HW_STRAP_LPC_RESET_PIN | \ 134 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 135 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 136 SCU_HW_STRAP_MAC1_RGMII | \ 137 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 138 SCU_AST2500_HW_STRAP_RESERVED1) 139 140 /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */ 141 #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1 142 143 /* Quanta-Q71l hardware value */ 144 #define QUANTA_Q71L_BMC_HW_STRAP1 ( \ 145 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \ 146 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2/* DDR3 with CL=6, CWL=5 */) | \ 147 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 148 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_24M_IN) | \ 149 SCU_HW_STRAP_VGA_CLASS_CODE | \ 150 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_PASS_THROUGH) | \ 151 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 152 SCU_HW_STRAP_SPI_WIDTH | \ 153 SCU_HW_STRAP_VGA_SIZE_SET(VGA_8M_DRAM) | \ 154 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 155 156 /* AST2600 evb hardware value */ 157 #define AST2600_EVB_HW_STRAP1 0x000000C0 158 #define AST2600_EVB_HW_STRAP2 0x00000003 159 160 /* Tacoma hardware value */ 161 #define TACOMA_BMC_HW_STRAP1 0x00000000 162 #define TACOMA_BMC_HW_STRAP2 0x00000040 163 164 /* Rainier hardware value: (QEMU prototype) */ 165 #define RAINIER_BMC_HW_STRAP1 0x00422016 166 #define RAINIER_BMC_HW_STRAP2 0x80000848 167 168 /* Fuji hardware value */ 169 #define FUJI_BMC_HW_STRAP1 0x00000000 170 #define FUJI_BMC_HW_STRAP2 0x00000000 171 172 /* Bletchley hardware value */ 173 /* TODO: Leave same as EVB for now. */ 174 #define BLETCHLEY_BMC_HW_STRAP1 AST2600_EVB_HW_STRAP1 175 #define BLETCHLEY_BMC_HW_STRAP2 AST2600_EVB_HW_STRAP2 176 177 /* 178 * The max ram region is for firmwares that scan the address space 179 * with load/store to guess how much RAM the SoC has. 180 */ 181 static uint64_t max_ram_read(void *opaque, hwaddr offset, unsigned size) 182 { 183 return 0; 184 } 185 186 static void max_ram_write(void *opaque, hwaddr offset, uint64_t value, 187 unsigned size) 188 { 189 /* Discard writes */ 190 } 191 192 static const MemoryRegionOps max_ram_ops = { 193 .read = max_ram_read, 194 .write = max_ram_write, 195 .endianness = DEVICE_NATIVE_ENDIAN, 196 }; 197 198 #define AST_SMP_MAILBOX_BASE 0x1e6e2180 199 #define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0) 200 #define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4) 201 #define AST_SMP_MBOX_FIELD_READY (AST_SMP_MAILBOX_BASE + 0x8) 202 #define AST_SMP_MBOX_FIELD_POLLINSN (AST_SMP_MAILBOX_BASE + 0xc) 203 #define AST_SMP_MBOX_CODE (AST_SMP_MAILBOX_BASE + 0x10) 204 #define AST_SMP_MBOX_GOSIGN 0xabbaab00 205 206 static void aspeed_write_smpboot(ARMCPU *cpu, 207 const struct arm_boot_info *info) 208 { 209 static const uint32_t poll_mailbox_ready[] = { 210 /* 211 * r2 = per-cpu go sign value 212 * r1 = AST_SMP_MBOX_FIELD_ENTRY 213 * r0 = AST_SMP_MBOX_FIELD_GOSIGN 214 */ 215 0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 */ 216 0xe21000ff, /* ands r0, r0, #255 */ 217 0xe59f201c, /* ldr r2, [pc, #28] */ 218 0xe1822000, /* orr r2, r2, r0 */ 219 220 0xe59f1018, /* ldr r1, [pc, #24] */ 221 0xe59f0018, /* ldr r0, [pc, #24] */ 222 223 0xe320f002, /* wfe */ 224 0xe5904000, /* ldr r4, [r0] */ 225 0xe1520004, /* cmp r2, r4 */ 226 0x1afffffb, /* bne <wfe> */ 227 0xe591f000, /* ldr pc, [r1] */ 228 AST_SMP_MBOX_GOSIGN, 229 AST_SMP_MBOX_FIELD_ENTRY, 230 AST_SMP_MBOX_FIELD_GOSIGN, 231 }; 232 233 rom_add_blob_fixed("aspeed.smpboot", poll_mailbox_ready, 234 sizeof(poll_mailbox_ready), 235 info->smp_loader_start); 236 } 237 238 static void aspeed_reset_secondary(ARMCPU *cpu, 239 const struct arm_boot_info *info) 240 { 241 AddressSpace *as = arm_boot_address_space(cpu, info); 242 CPUState *cs = CPU(cpu); 243 244 /* info->smp_bootreg_addr */ 245 address_space_stl_notdirty(as, AST_SMP_MBOX_FIELD_GOSIGN, 0, 246 MEMTXATTRS_UNSPECIFIED, NULL); 247 cpu_set_pc(cs, info->smp_loader_start); 248 } 249 250 #define FIRMWARE_ADDR 0x0 251 252 static void write_boot_rom(DriveInfo *dinfo, hwaddr addr, size_t rom_size, 253 Error **errp) 254 { 255 BlockBackend *blk = blk_by_legacy_dinfo(dinfo); 256 g_autofree void *storage = NULL; 257 int64_t size; 258 259 /* The block backend size should have already been 'validated' by 260 * the creation of the m25p80 object. 261 */ 262 size = blk_getlength(blk); 263 if (size <= 0) { 264 error_setg(errp, "failed to get flash size"); 265 return; 266 } 267 268 if (rom_size > size) { 269 rom_size = size; 270 } 271 272 storage = g_malloc0(rom_size); 273 if (blk_pread(blk, 0, storage, rom_size) < 0) { 274 error_setg(errp, "failed to read the initial flash content"); 275 return; 276 } 277 278 rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr); 279 } 280 281 static void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype, 282 unsigned int count, int unit0) 283 { 284 int i; 285 286 if (!flashtype) { 287 return; 288 } 289 290 for (i = 0; i < count; ++i) { 291 DriveInfo *dinfo = drive_get(IF_MTD, 0, unit0 + i); 292 qemu_irq cs_line; 293 DeviceState *dev; 294 295 dev = qdev_new(flashtype); 296 if (dinfo) { 297 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo)); 298 } 299 qdev_realize_and_unref(dev, BUS(s->spi), &error_fatal); 300 301 cs_line = qdev_get_gpio_in_named(dev, SSI_GPIO_CS, 0); 302 sysbus_connect_irq(SYS_BUS_DEVICE(s), i + 1, cs_line); 303 } 304 } 305 306 static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo) 307 { 308 DeviceState *card; 309 310 if (!dinfo) { 311 return; 312 } 313 card = qdev_new(TYPE_SD_CARD); 314 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo), 315 &error_fatal); 316 qdev_realize_and_unref(card, 317 qdev_get_child_bus(DEVICE(sdhci), "sd-bus"), 318 &error_fatal); 319 } 320 321 static void aspeed_machine_init(MachineState *machine) 322 { 323 AspeedMachineState *bmc = ASPEED_MACHINE(machine); 324 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine); 325 AspeedSoCClass *sc; 326 DriveInfo *drive0 = drive_get(IF_MTD, 0, 0); 327 ram_addr_t max_ram_size; 328 int i; 329 NICInfo *nd = &nd_table[0]; 330 331 memory_region_init(&bmc->ram_container, NULL, "aspeed-ram-container", 332 4 * GiB); 333 memory_region_add_subregion(&bmc->ram_container, 0, machine->ram); 334 335 object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name); 336 337 sc = ASPEED_SOC_GET_CLASS(&bmc->soc); 338 339 /* 340 * This will error out if isize is not supported by memory controller. 341 */ 342 object_property_set_uint(OBJECT(&bmc->soc), "ram-size", machine->ram_size, 343 &error_fatal); 344 345 for (i = 0; i < sc->macs_num; i++) { 346 if ((amc->macs_mask & (1 << i)) && nd->used) { 347 qemu_check_nic_model(nd, TYPE_FTGMAC100); 348 qdev_set_nic_properties(DEVICE(&bmc->soc.ftgmac100[i]), nd); 349 nd++; 350 } 351 } 352 353 object_property_set_int(OBJECT(&bmc->soc), "hw-strap1", amc->hw_strap1, 354 &error_abort); 355 object_property_set_int(OBJECT(&bmc->soc), "hw-strap2", amc->hw_strap2, 356 &error_abort); 357 object_property_set_link(OBJECT(&bmc->soc), "dram", 358 OBJECT(machine->ram), &error_abort); 359 if (machine->kernel_filename) { 360 /* 361 * When booting with a -kernel command line there is no u-boot 362 * that runs to unlock the SCU. In this case set the default to 363 * be unlocked as the kernel expects 364 */ 365 object_property_set_int(OBJECT(&bmc->soc), "hw-prot-key", 366 ASPEED_SCU_PROT_KEY, &error_abort); 367 } 368 qdev_prop_set_uint32(DEVICE(&bmc->soc), "uart-default", 369 amc->uart_default); 370 qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort); 371 372 memory_region_add_subregion(get_system_memory(), 373 sc->memmap[ASPEED_DEV_SDRAM], 374 &bmc->ram_container); 375 376 max_ram_size = object_property_get_uint(OBJECT(&bmc->soc), "max-ram-size", 377 &error_abort); 378 memory_region_init_io(&bmc->max_ram, NULL, &max_ram_ops, NULL, 379 "max_ram", max_ram_size - machine->ram_size); 380 memory_region_add_subregion(&bmc->ram_container, machine->ram_size, &bmc->max_ram); 381 382 aspeed_board_init_flashes(&bmc->soc.fmc, 383 bmc->fmc_model ? bmc->fmc_model : amc->fmc_model, 384 amc->num_cs, 0); 385 aspeed_board_init_flashes(&bmc->soc.spi[0], 386 bmc->spi_model ? bmc->spi_model : amc->spi_model, 387 1, amc->num_cs); 388 389 /* Install first FMC flash content as a boot rom. */ 390 if (drive0) { 391 AspeedSMCFlash *fl = &bmc->soc.fmc.flashes[0]; 392 MemoryRegion *boot_rom = g_new(MemoryRegion, 1); 393 uint64_t size = memory_region_size(&fl->mmio); 394 395 /* 396 * create a ROM region using the default mapping window size of 397 * the flash module. The window size is 64MB for the AST2400 398 * SoC and 128MB for the AST2500 SoC, which is twice as big as 399 * needed by the flash modules of the Aspeed machines. 400 */ 401 if (ASPEED_MACHINE(machine)->mmio_exec) { 402 memory_region_init_alias(boot_rom, NULL, "aspeed.boot_rom", 403 &fl->mmio, 0, size); 404 memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR, 405 boot_rom); 406 } else { 407 memory_region_init_rom(boot_rom, NULL, "aspeed.boot_rom", 408 size, &error_abort); 409 memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR, 410 boot_rom); 411 write_boot_rom(drive0, FIRMWARE_ADDR, size, &error_abort); 412 } 413 } 414 415 if (machine->kernel_filename && sc->num_cpus > 1) { 416 /* With no u-boot we must set up a boot stub for the secondary CPU */ 417 MemoryRegion *smpboot = g_new(MemoryRegion, 1); 418 memory_region_init_ram(smpboot, NULL, "aspeed.smpboot", 419 0x80, &error_abort); 420 memory_region_add_subregion(get_system_memory(), 421 AST_SMP_MAILBOX_BASE, smpboot); 422 423 aspeed_board_binfo.write_secondary_boot = aspeed_write_smpboot; 424 aspeed_board_binfo.secondary_cpu_reset_hook = aspeed_reset_secondary; 425 aspeed_board_binfo.smp_loader_start = AST_SMP_MBOX_CODE; 426 } 427 428 aspeed_board_binfo.ram_size = machine->ram_size; 429 aspeed_board_binfo.loader_start = sc->memmap[ASPEED_DEV_SDRAM]; 430 431 if (amc->i2c_init) { 432 amc->i2c_init(bmc); 433 } 434 435 for (i = 0; i < bmc->soc.sdhci.num_slots; i++) { 436 sdhci_attach_drive(&bmc->soc.sdhci.slots[i], 437 drive_get(IF_SD, 0, i)); 438 } 439 440 if (bmc->soc.emmc.num_slots) { 441 sdhci_attach_drive(&bmc->soc.emmc.slots[0], 442 drive_get(IF_SD, 0, bmc->soc.sdhci.num_slots)); 443 } 444 445 arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo); 446 } 447 448 static void at24c_eeprom_init(I2CBus *bus, uint8_t addr, uint32_t rsize) 449 { 450 I2CSlave *i2c_dev = i2c_slave_new("at24c-eeprom", addr); 451 DeviceState *dev = DEVICE(i2c_dev); 452 453 qdev_prop_set_uint32(dev, "rom-size", rsize); 454 i2c_slave_realize_and_unref(i2c_dev, bus, &error_abort); 455 } 456 457 static void palmetto_bmc_i2c_init(AspeedMachineState *bmc) 458 { 459 AspeedSoCState *soc = &bmc->soc; 460 DeviceState *dev; 461 uint8_t *eeprom_buf = g_malloc0(32 * 1024); 462 463 /* The palmetto platform expects a ds3231 RTC but a ds1338 is 464 * enough to provide basic RTC features. Alarms will be missing */ 465 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), "ds1338", 0x68); 466 467 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, 468 eeprom_buf); 469 470 /* add a TMP423 temperature sensor */ 471 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), 472 "tmp423", 0x4c)); 473 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 474 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 475 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 476 object_property_set_int(OBJECT(dev), "temperature3", 110000, &error_abort); 477 } 478 479 static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc) 480 { 481 AspeedSoCState *soc = &bmc->soc; 482 483 /* 484 * The quanta-q71l platform expects tmp75s which are compatible with 485 * tmp105s. 486 */ 487 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4c); 488 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4e); 489 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4f); 490 491 /* TODO: i2c-1: Add baseboard FRU eeprom@54 24c64 */ 492 /* TODO: i2c-1: Add Frontpanel FRU eeprom@57 24c64 */ 493 /* TODO: Add Memory Riser i2c mux and eeproms. */ 494 495 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9546", 0x74); 496 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9548", 0x77); 497 498 /* TODO: i2c-3: Add BIOS FRU eeprom@56 24c64 */ 499 500 /* i2c-7 */ 501 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9546", 0x70); 502 /* - i2c@0: pmbus@59 */ 503 /* - i2c@1: pmbus@58 */ 504 /* - i2c@2: pmbus@58 */ 505 /* - i2c@3: pmbus@59 */ 506 507 /* TODO: i2c-7: Add PDB FRU eeprom@52 */ 508 /* TODO: i2c-8: Add BMC FRU eeprom@50 */ 509 } 510 511 static void ast2500_evb_i2c_init(AspeedMachineState *bmc) 512 { 513 AspeedSoCState *soc = &bmc->soc; 514 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 515 516 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 3), 0x50, 517 eeprom_buf); 518 519 /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */ 520 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), 521 TYPE_TMP105, 0x4d); 522 523 /* The AST2500 EVB does not have an RTC. Let's pretend that one is 524 * plugged on the I2C bus header */ 525 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32); 526 } 527 528 static void ast2600_evb_i2c_init(AspeedMachineState *bmc) 529 { 530 /* Start with some devices on our I2C busses */ 531 ast2500_evb_i2c_init(bmc); 532 } 533 534 static void romulus_bmc_i2c_init(AspeedMachineState *bmc) 535 { 536 AspeedSoCState *soc = &bmc->soc; 537 538 /* The romulus board expects Epson RX8900 I2C RTC but a ds1338 is 539 * good enough */ 540 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32); 541 } 542 543 static void create_pca9552(AspeedSoCState *soc, int bus_id, int addr) 544 { 545 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, bus_id), 546 TYPE_PCA9552, addr); 547 } 548 549 static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc) 550 { 551 AspeedSoCState *soc = &bmc->soc; 552 553 /* bus 2 : */ 554 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x48); 555 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x49); 556 /* bus 2 : pca9546 @ 0x73 */ 557 558 /* bus 3 : pca9548 @ 0x70 */ 559 560 /* bus 4 : */ 561 uint8_t *eeprom4_54 = g_malloc0(8 * 1024); 562 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, 563 eeprom4_54); 564 /* PCA9539 @ 0x76, but PCA9552 is compatible */ 565 create_pca9552(soc, 4, 0x76); 566 /* PCA9539 @ 0x77, but PCA9552 is compatible */ 567 create_pca9552(soc, 4, 0x77); 568 569 /* bus 6 : */ 570 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x48); 571 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x49); 572 /* bus 6 : pca9546 @ 0x73 */ 573 574 /* bus 8 : */ 575 uint8_t *eeprom8_56 = g_malloc0(8 * 1024); 576 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 8), 0x56, 577 eeprom8_56); 578 create_pca9552(soc, 8, 0x60); 579 create_pca9552(soc, 8, 0x61); 580 /* bus 8 : adc128d818 @ 0x1d */ 581 /* bus 8 : adc128d818 @ 0x1f */ 582 583 /* 584 * bus 13 : pca9548 @ 0x71 585 * - channel 3: 586 * - tmm421 @ 0x4c 587 * - tmp421 @ 0x4e 588 * - tmp421 @ 0x4f 589 */ 590 591 } 592 593 static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc) 594 { 595 static const struct { 596 unsigned gpio_id; 597 LEDColor color; 598 const char *description; 599 bool gpio_polarity; 600 } pca1_leds[] = { 601 {13, LED_COLOR_GREEN, "front-fault-4", GPIO_POLARITY_ACTIVE_LOW}, 602 {14, LED_COLOR_GREEN, "front-power-3", GPIO_POLARITY_ACTIVE_LOW}, 603 {15, LED_COLOR_GREEN, "front-id-5", GPIO_POLARITY_ACTIVE_LOW}, 604 }; 605 AspeedSoCState *soc = &bmc->soc; 606 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 607 DeviceState *dev; 608 LEDState *led; 609 610 /* Bus 3: TODO bmp280@77 */ 611 /* Bus 3: TODO max31785@52 */ 612 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60)); 613 qdev_prop_set_string(dev, "description", "pca1"); 614 i2c_slave_realize_and_unref(I2C_SLAVE(dev), 615 aspeed_i2c_get_bus(&soc->i2c, 3), 616 &error_fatal); 617 618 for (size_t i = 0; i < ARRAY_SIZE(pca1_leds); i++) { 619 led = led_create_simple(OBJECT(bmc), 620 pca1_leds[i].gpio_polarity, 621 pca1_leds[i].color, 622 pca1_leds[i].description); 623 qdev_connect_gpio_out(dev, pca1_leds[i].gpio_id, 624 qdev_get_gpio_in(DEVICE(led), 0)); 625 } 626 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "dps310", 0x76); 627 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "tmp423", 0x4c); 628 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "tmp423", 0x4c); 629 630 /* The Witherspoon expects a TMP275 but a TMP105 is compatible */ 631 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), TYPE_TMP105, 632 0x4a); 633 634 /* The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is 635 * good enough */ 636 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32); 637 638 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 11), 0x51, 639 eeprom_buf); 640 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60)); 641 qdev_prop_set_string(dev, "description", "pca0"); 642 i2c_slave_realize_and_unref(I2C_SLAVE(dev), 643 aspeed_i2c_get_bus(&soc->i2c, 11), 644 &error_fatal); 645 /* Bus 11: TODO ucd90160@64 */ 646 } 647 648 static void g220a_bmc_i2c_init(AspeedMachineState *bmc) 649 { 650 AspeedSoCState *soc = &bmc->soc; 651 DeviceState *dev; 652 653 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), 654 "emc1413", 0x4c)); 655 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 656 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 657 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 658 659 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12), 660 "emc1413", 0x4c)); 661 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 662 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 663 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 664 665 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 13), 666 "emc1413", 0x4c)); 667 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 668 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 669 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 670 671 static uint8_t eeprom_buf[2 * 1024] = { 672 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0xfe, 673 0x01, 0x06, 0x00, 0xc9, 0x42, 0x79, 0x74, 0x65, 674 0x64, 0x61, 0x6e, 0x63, 0x65, 0xc5, 0x47, 0x32, 675 0x32, 0x30, 0x41, 0xc4, 0x41, 0x41, 0x42, 0x42, 676 0xc4, 0x43, 0x43, 0x44, 0x44, 0xc4, 0x45, 0x45, 677 0x46, 0x46, 0xc4, 0x48, 0x48, 0x47, 0x47, 0xc1, 678 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa7, 679 }; 680 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x57, 681 eeprom_buf); 682 } 683 684 static void aspeed_eeprom_init(I2CBus *bus, uint8_t addr, uint32_t rsize) 685 { 686 I2CSlave *i2c_dev = i2c_slave_new("at24c-eeprom", addr); 687 DeviceState *dev = DEVICE(i2c_dev); 688 689 qdev_prop_set_uint32(dev, "rom-size", rsize); 690 i2c_slave_realize_and_unref(i2c_dev, bus, &error_abort); 691 } 692 693 static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc) 694 { 695 AspeedSoCState *soc = &bmc->soc; 696 I2CSlave *i2c_mux; 697 698 /* The at24c256 */ 699 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 1), 0x50, 32768); 700 701 /* The fp5280g2 expects a TMP112 but a TMP105 is compatible */ 702 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105, 703 0x48); 704 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105, 705 0x49); 706 707 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), 708 "pca9546", 0x70); 709 /* It expects a TMP112 but a TMP105 is compatible */ 710 i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 0), TYPE_TMP105, 711 0x4a); 712 713 /* It expects a ds3232 but a ds1338 is good enough */ 714 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "ds1338", 0x68); 715 716 /* It expects a pca9555 but a pca9552 is compatible */ 717 create_pca9552(soc, 8, 0x30); 718 } 719 720 static void rainier_bmc_i2c_init(AspeedMachineState *bmc) 721 { 722 AspeedSoCState *soc = &bmc->soc; 723 I2CSlave *i2c_mux; 724 725 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB); 726 727 create_pca9552(soc, 3, 0x61); 728 729 /* The rainier expects a TMP275 but a TMP105 is compatible */ 730 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, 731 0x48); 732 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, 733 0x49); 734 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, 735 0x4a); 736 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), 737 "pca9546", 0x70); 738 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 739 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 740 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x52, 64 * KiB); 741 create_pca9552(soc, 4, 0x60); 742 743 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105, 744 0x48); 745 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105, 746 0x49); 747 create_pca9552(soc, 5, 0x60); 748 create_pca9552(soc, 5, 0x61); 749 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), 750 "pca9546", 0x70); 751 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 752 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 753 754 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, 755 0x48); 756 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, 757 0x4a); 758 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, 759 0x4b); 760 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), 761 "pca9546", 0x70); 762 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 763 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 764 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x50, 64 * KiB); 765 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 3), 0x51, 64 * KiB); 766 767 create_pca9552(soc, 7, 0x30); 768 create_pca9552(soc, 7, 0x31); 769 create_pca9552(soc, 7, 0x32); 770 create_pca9552(soc, 7, 0x33); 771 /* Bus 7: TODO max31785@52 */ 772 create_pca9552(soc, 7, 0x60); 773 create_pca9552(soc, 7, 0x61); 774 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "dps310", 0x76); 775 /* Bus 7: TODO si7021-a20@20 */ 776 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), TYPE_TMP105, 777 0x48); 778 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 64 * KiB); 779 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x51, 64 * KiB); 780 781 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105, 782 0x48); 783 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105, 784 0x4a); 785 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x50, 64 * KiB); 786 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 64 * KiB); 787 create_pca9552(soc, 8, 0x60); 788 create_pca9552(soc, 8, 0x61); 789 /* Bus 8: ucd90320@11 */ 790 /* Bus 8: ucd90320@b */ 791 /* Bus 8: ucd90320@c */ 792 793 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c); 794 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4d); 795 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 9), 0x50, 128 * KiB); 796 797 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c); 798 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4d); 799 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 10), 0x50, 128 * KiB); 800 801 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105, 802 0x48); 803 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105, 804 0x49); 805 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), 806 "pca9546", 0x70); 807 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 808 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 809 create_pca9552(soc, 11, 0x60); 810 811 812 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 13), 0x50, 64 * KiB); 813 create_pca9552(soc, 13, 0x60); 814 815 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 14), 0x50, 64 * KiB); 816 create_pca9552(soc, 14, 0x60); 817 818 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 15), 0x50, 64 * KiB); 819 create_pca9552(soc, 15, 0x60); 820 } 821 822 static void get_pca9548_channels(I2CBus *bus, uint8_t mux_addr, 823 I2CBus **channels) 824 { 825 I2CSlave *mux = i2c_slave_create_simple(bus, "pca9548", mux_addr); 826 for (int i = 0; i < 8; i++) { 827 channels[i] = pca954x_i2c_get_bus(mux, i); 828 } 829 } 830 831 #define TYPE_LM75 TYPE_TMP105 832 #define TYPE_TMP75 TYPE_TMP105 833 #define TYPE_TMP422 "tmp422" 834 835 static void fuji_bmc_i2c_init(AspeedMachineState *bmc) 836 { 837 AspeedSoCState *soc = &bmc->soc; 838 I2CBus *i2c[144] = {}; 839 840 for (int i = 0; i < 16; i++) { 841 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); 842 } 843 I2CBus *i2c180 = i2c[2]; 844 I2CBus *i2c480 = i2c[8]; 845 I2CBus *i2c600 = i2c[11]; 846 847 get_pca9548_channels(i2c180, 0x70, &i2c[16]); 848 get_pca9548_channels(i2c480, 0x70, &i2c[24]); 849 /* NOTE: The device tree skips [32, 40) in the alias numbering */ 850 get_pca9548_channels(i2c600, 0x77, &i2c[40]); 851 get_pca9548_channels(i2c[24], 0x71, &i2c[48]); 852 get_pca9548_channels(i2c[25], 0x72, &i2c[56]); 853 get_pca9548_channels(i2c[26], 0x76, &i2c[64]); 854 get_pca9548_channels(i2c[27], 0x76, &i2c[72]); 855 for (int i = 0; i < 8; i++) { 856 get_pca9548_channels(i2c[40 + i], 0x76, &i2c[80 + i * 8]); 857 } 858 859 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4c); 860 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4d); 861 862 aspeed_eeprom_init(i2c[19], 0x52, 64 * KiB); 863 aspeed_eeprom_init(i2c[20], 0x50, 2 * KiB); 864 aspeed_eeprom_init(i2c[22], 0x52, 2 * KiB); 865 866 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x48); 867 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x49); 868 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x4a); 869 i2c_slave_create_simple(i2c[3], TYPE_TMP422, 0x4c); 870 871 aspeed_eeprom_init(i2c[8], 0x51, 64 * KiB); 872 i2c_slave_create_simple(i2c[8], TYPE_LM75, 0x4a); 873 874 i2c_slave_create_simple(i2c[50], TYPE_LM75, 0x4c); 875 aspeed_eeprom_init(i2c[50], 0x52, 64 * KiB); 876 i2c_slave_create_simple(i2c[51], TYPE_TMP75, 0x48); 877 i2c_slave_create_simple(i2c[52], TYPE_TMP75, 0x49); 878 879 i2c_slave_create_simple(i2c[59], TYPE_TMP75, 0x48); 880 i2c_slave_create_simple(i2c[60], TYPE_TMP75, 0x49); 881 882 aspeed_eeprom_init(i2c[65], 0x53, 64 * KiB); 883 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x49); 884 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x48); 885 aspeed_eeprom_init(i2c[68], 0x52, 64 * KiB); 886 aspeed_eeprom_init(i2c[69], 0x52, 64 * KiB); 887 aspeed_eeprom_init(i2c[70], 0x52, 64 * KiB); 888 aspeed_eeprom_init(i2c[71], 0x52, 64 * KiB); 889 890 aspeed_eeprom_init(i2c[73], 0x53, 64 * KiB); 891 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x49); 892 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x48); 893 aspeed_eeprom_init(i2c[76], 0x52, 64 * KiB); 894 aspeed_eeprom_init(i2c[77], 0x52, 64 * KiB); 895 aspeed_eeprom_init(i2c[78], 0x52, 64 * KiB); 896 aspeed_eeprom_init(i2c[79], 0x52, 64 * KiB); 897 aspeed_eeprom_init(i2c[28], 0x50, 2 * KiB); 898 899 for (int i = 0; i < 8; i++) { 900 aspeed_eeprom_init(i2c[81 + i * 8], 0x56, 64 * KiB); 901 i2c_slave_create_simple(i2c[82 + i * 8], TYPE_TMP75, 0x48); 902 i2c_slave_create_simple(i2c[83 + i * 8], TYPE_TMP75, 0x4b); 903 i2c_slave_create_simple(i2c[84 + i * 8], TYPE_TMP75, 0x4a); 904 } 905 } 906 907 #define TYPE_TMP421 "tmp421" 908 909 static void bletchley_bmc_i2c_init(AspeedMachineState *bmc) 910 { 911 AspeedSoCState *soc = &bmc->soc; 912 I2CBus *i2c[13] = {}; 913 for (int i = 0; i < 13; i++) { 914 if ((i == 8) || (i == 11)) { 915 continue; 916 } 917 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); 918 } 919 920 /* Bus 0 - 5 all have the same config. */ 921 for (int i = 0; i < 6; i++) { 922 /* Missing model: ti,ina230 @ 0x45 */ 923 /* Missing model: mps,mp5023 @ 0x40 */ 924 i2c_slave_create_simple(i2c[i], TYPE_TMP421, 0x4f); 925 /* Missing model: nxp,pca9539 @ 0x76, but PCA9552 works enough */ 926 i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x76); 927 i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x67); 928 /* Missing model: fsc,fusb302 @ 0x22 */ 929 } 930 931 /* Bus 6 */ 932 at24c_eeprom_init(i2c[6], 0x56, 65536); 933 /* Missing model: nxp,pcf85263 @ 0x51 , but ds1338 works enough */ 934 i2c_slave_create_simple(i2c[6], "ds1338", 0x51); 935 936 937 /* Bus 7 */ 938 at24c_eeprom_init(i2c[7], 0x54, 65536); 939 940 /* Bus 9 */ 941 i2c_slave_create_simple(i2c[9], TYPE_TMP421, 0x4f); 942 943 /* Bus 10 */ 944 i2c_slave_create_simple(i2c[10], TYPE_TMP421, 0x4f); 945 /* Missing model: ti,hdc1080 @ 0x40 */ 946 i2c_slave_create_simple(i2c[10], TYPE_PCA9552, 0x67); 947 948 /* Bus 12 */ 949 /* Missing model: adi,adm1278 @ 0x11 */ 950 i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4c); 951 i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4d); 952 i2c_slave_create_simple(i2c[12], TYPE_PCA9552, 0x67); 953 } 954 955 static void fby35_i2c_init(AspeedMachineState *bmc) 956 { 957 AspeedSoCState *soc = &bmc->soc; 958 I2CBus *i2c[16]; 959 960 for (int i = 0; i < 16; i++) { 961 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); 962 } 963 964 i2c_slave_create_simple(i2c[2], TYPE_LM75, 0x4f); 965 i2c_slave_create_simple(i2c[8], TYPE_TMP421, 0x1f); 966 /* Hotswap controller is actually supposed to be mp5920 or ltc4282. */ 967 i2c_slave_create_simple(i2c[11], "adm1272", 0x44); 968 i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4e); 969 i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4f); 970 971 aspeed_eeprom_init(i2c[4], 0x51, 128 * KiB); 972 aspeed_eeprom_init(i2c[6], 0x51, 128 * KiB); 973 aspeed_eeprom_init(i2c[8], 0x50, 32 * KiB); 974 aspeed_eeprom_init(i2c[11], 0x51, 128 * KiB); 975 aspeed_eeprom_init(i2c[11], 0x54, 128 * KiB); 976 977 /* 978 * TODO: There is a multi-master i2c connection to an AST1030 MiniBMC on 979 * buses 0, 1, 2, 3, and 9. Source address 0x10, target address 0x20 on 980 * each. 981 */ 982 } 983 984 static bool aspeed_get_mmio_exec(Object *obj, Error **errp) 985 { 986 return ASPEED_MACHINE(obj)->mmio_exec; 987 } 988 989 static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp) 990 { 991 ASPEED_MACHINE(obj)->mmio_exec = value; 992 } 993 994 static void aspeed_machine_instance_init(Object *obj) 995 { 996 ASPEED_MACHINE(obj)->mmio_exec = false; 997 } 998 999 static char *aspeed_get_fmc_model(Object *obj, Error **errp) 1000 { 1001 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1002 return g_strdup(bmc->fmc_model); 1003 } 1004 1005 static void aspeed_set_fmc_model(Object *obj, const char *value, Error **errp) 1006 { 1007 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1008 1009 g_free(bmc->fmc_model); 1010 bmc->fmc_model = g_strdup(value); 1011 } 1012 1013 static char *aspeed_get_spi_model(Object *obj, Error **errp) 1014 { 1015 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1016 return g_strdup(bmc->spi_model); 1017 } 1018 1019 static void aspeed_set_spi_model(Object *obj, const char *value, Error **errp) 1020 { 1021 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1022 1023 g_free(bmc->spi_model); 1024 bmc->spi_model = g_strdup(value); 1025 } 1026 1027 static void aspeed_machine_class_props_init(ObjectClass *oc) 1028 { 1029 object_class_property_add_bool(oc, "execute-in-place", 1030 aspeed_get_mmio_exec, 1031 aspeed_set_mmio_exec); 1032 object_class_property_set_description(oc, "execute-in-place", 1033 "boot directly from CE0 flash device"); 1034 1035 object_class_property_add_str(oc, "fmc-model", aspeed_get_fmc_model, 1036 aspeed_set_fmc_model); 1037 object_class_property_set_description(oc, "fmc-model", 1038 "Change the FMC Flash model"); 1039 object_class_property_add_str(oc, "spi-model", aspeed_get_spi_model, 1040 aspeed_set_spi_model); 1041 object_class_property_set_description(oc, "spi-model", 1042 "Change the SPI Flash model"); 1043 } 1044 1045 static int aspeed_soc_num_cpus(const char *soc_name) 1046 { 1047 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(soc_name)); 1048 return sc->num_cpus; 1049 } 1050 1051 static void aspeed_machine_class_init(ObjectClass *oc, void *data) 1052 { 1053 MachineClass *mc = MACHINE_CLASS(oc); 1054 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1055 1056 mc->init = aspeed_machine_init; 1057 mc->no_floppy = 1; 1058 mc->no_cdrom = 1; 1059 mc->no_parallel = 1; 1060 mc->default_ram_id = "ram"; 1061 amc->macs_mask = ASPEED_MAC0_ON; 1062 amc->uart_default = ASPEED_DEV_UART5; 1063 1064 aspeed_machine_class_props_init(oc); 1065 } 1066 1067 static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data) 1068 { 1069 MachineClass *mc = MACHINE_CLASS(oc); 1070 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1071 1072 mc->desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)"; 1073 amc->soc_name = "ast2400-a1"; 1074 amc->hw_strap1 = PALMETTO_BMC_HW_STRAP1; 1075 amc->fmc_model = "n25q256a"; 1076 amc->spi_model = "mx25l25635e"; 1077 amc->num_cs = 1; 1078 amc->i2c_init = palmetto_bmc_i2c_init; 1079 mc->default_ram_size = 256 * MiB; 1080 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1081 aspeed_soc_num_cpus(amc->soc_name); 1082 }; 1083 1084 static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc, void *data) 1085 { 1086 MachineClass *mc = MACHINE_CLASS(oc); 1087 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1088 1089 mc->desc = "Quanta-Q71l BMC (ARM926EJ-S)"; 1090 amc->soc_name = "ast2400-a1"; 1091 amc->hw_strap1 = QUANTA_Q71L_BMC_HW_STRAP1; 1092 amc->fmc_model = "n25q256a"; 1093 amc->spi_model = "mx25l25635e"; 1094 amc->num_cs = 1; 1095 amc->i2c_init = quanta_q71l_bmc_i2c_init; 1096 mc->default_ram_size = 128 * MiB; 1097 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1098 aspeed_soc_num_cpus(amc->soc_name); 1099 } 1100 1101 static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc, 1102 void *data) 1103 { 1104 MachineClass *mc = MACHINE_CLASS(oc); 1105 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1106 1107 mc->desc = "Supermicro X11 BMC (ARM926EJ-S)"; 1108 amc->soc_name = "ast2400-a1"; 1109 amc->hw_strap1 = SUPERMICROX11_BMC_HW_STRAP1; 1110 amc->fmc_model = "mx25l25635e"; 1111 amc->spi_model = "mx25l25635e"; 1112 amc->num_cs = 1; 1113 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1114 amc->i2c_init = palmetto_bmc_i2c_init; 1115 mc->default_ram_size = 256 * MiB; 1116 } 1117 1118 static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data) 1119 { 1120 MachineClass *mc = MACHINE_CLASS(oc); 1121 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1122 1123 mc->desc = "Aspeed AST2500 EVB (ARM1176)"; 1124 amc->soc_name = "ast2500-a1"; 1125 amc->hw_strap1 = AST2500_EVB_HW_STRAP1; 1126 amc->fmc_model = "mx25l25635e"; 1127 amc->spi_model = "mx25l25635e"; 1128 amc->num_cs = 1; 1129 amc->i2c_init = ast2500_evb_i2c_init; 1130 mc->default_ram_size = 512 * MiB; 1131 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1132 aspeed_soc_num_cpus(amc->soc_name); 1133 }; 1134 1135 static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data) 1136 { 1137 MachineClass *mc = MACHINE_CLASS(oc); 1138 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1139 1140 mc->desc = "OpenPOWER Romulus BMC (ARM1176)"; 1141 amc->soc_name = "ast2500-a1"; 1142 amc->hw_strap1 = ROMULUS_BMC_HW_STRAP1; 1143 amc->fmc_model = "n25q256a"; 1144 amc->spi_model = "mx66l1g45g"; 1145 amc->num_cs = 2; 1146 amc->i2c_init = romulus_bmc_i2c_init; 1147 mc->default_ram_size = 512 * MiB; 1148 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1149 aspeed_soc_num_cpus(amc->soc_name); 1150 }; 1151 1152 static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data) 1153 { 1154 MachineClass *mc = MACHINE_CLASS(oc); 1155 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1156 1157 mc->desc = "OCP SonoraPass BMC (ARM1176)"; 1158 amc->soc_name = "ast2500-a1"; 1159 amc->hw_strap1 = SONORAPASS_BMC_HW_STRAP1; 1160 amc->fmc_model = "mx66l1g45g"; 1161 amc->spi_model = "mx66l1g45g"; 1162 amc->num_cs = 2; 1163 amc->i2c_init = sonorapass_bmc_i2c_init; 1164 mc->default_ram_size = 512 * MiB; 1165 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1166 aspeed_soc_num_cpus(amc->soc_name); 1167 }; 1168 1169 static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data) 1170 { 1171 MachineClass *mc = MACHINE_CLASS(oc); 1172 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1173 1174 mc->desc = "OpenPOWER Witherspoon BMC (ARM1176)"; 1175 amc->soc_name = "ast2500-a1"; 1176 amc->hw_strap1 = WITHERSPOON_BMC_HW_STRAP1; 1177 amc->fmc_model = "mx25l25635e"; 1178 amc->spi_model = "mx66l1g45g"; 1179 amc->num_cs = 2; 1180 amc->i2c_init = witherspoon_bmc_i2c_init; 1181 mc->default_ram_size = 512 * MiB; 1182 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1183 aspeed_soc_num_cpus(amc->soc_name); 1184 }; 1185 1186 static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data) 1187 { 1188 MachineClass *mc = MACHINE_CLASS(oc); 1189 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1190 1191 mc->desc = "Aspeed AST2600 EVB (Cortex-A7)"; 1192 amc->soc_name = "ast2600-a3"; 1193 amc->hw_strap1 = AST2600_EVB_HW_STRAP1; 1194 amc->hw_strap2 = AST2600_EVB_HW_STRAP2; 1195 amc->fmc_model = "mx66u51235f"; 1196 amc->spi_model = "mx66u51235f"; 1197 amc->num_cs = 1; 1198 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON | 1199 ASPEED_MAC3_ON; 1200 amc->i2c_init = ast2600_evb_i2c_init; 1201 mc->default_ram_size = 1 * GiB; 1202 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1203 aspeed_soc_num_cpus(amc->soc_name); 1204 }; 1205 1206 static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data) 1207 { 1208 MachineClass *mc = MACHINE_CLASS(oc); 1209 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1210 1211 mc->desc = "OpenPOWER Tacoma BMC (Cortex-A7)"; 1212 amc->soc_name = "ast2600-a3"; 1213 amc->hw_strap1 = TACOMA_BMC_HW_STRAP1; 1214 amc->hw_strap2 = TACOMA_BMC_HW_STRAP2; 1215 amc->fmc_model = "mx66l1g45g"; 1216 amc->spi_model = "mx66l1g45g"; 1217 amc->num_cs = 2; 1218 amc->macs_mask = ASPEED_MAC2_ON; 1219 amc->i2c_init = witherspoon_bmc_i2c_init; /* Same board layout */ 1220 mc->default_ram_size = 1 * GiB; 1221 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1222 aspeed_soc_num_cpus(amc->soc_name); 1223 }; 1224 1225 static void aspeed_machine_g220a_class_init(ObjectClass *oc, void *data) 1226 { 1227 MachineClass *mc = MACHINE_CLASS(oc); 1228 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1229 1230 mc->desc = "Bytedance G220A BMC (ARM1176)"; 1231 amc->soc_name = "ast2500-a1"; 1232 amc->hw_strap1 = G220A_BMC_HW_STRAP1; 1233 amc->fmc_model = "n25q512a"; 1234 amc->spi_model = "mx25l25635e"; 1235 amc->num_cs = 2; 1236 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1237 amc->i2c_init = g220a_bmc_i2c_init; 1238 mc->default_ram_size = 1024 * MiB; 1239 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1240 aspeed_soc_num_cpus(amc->soc_name); 1241 }; 1242 1243 static void aspeed_machine_fp5280g2_class_init(ObjectClass *oc, void *data) 1244 { 1245 MachineClass *mc = MACHINE_CLASS(oc); 1246 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1247 1248 mc->desc = "Inspur FP5280G2 BMC (ARM1176)"; 1249 amc->soc_name = "ast2500-a1"; 1250 amc->hw_strap1 = FP5280G2_BMC_HW_STRAP1; 1251 amc->fmc_model = "n25q512a"; 1252 amc->spi_model = "mx25l25635e"; 1253 amc->num_cs = 2; 1254 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1255 amc->i2c_init = fp5280g2_bmc_i2c_init; 1256 mc->default_ram_size = 512 * MiB; 1257 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1258 aspeed_soc_num_cpus(amc->soc_name); 1259 }; 1260 1261 static void aspeed_machine_rainier_class_init(ObjectClass *oc, void *data) 1262 { 1263 MachineClass *mc = MACHINE_CLASS(oc); 1264 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1265 1266 mc->desc = "IBM Rainier BMC (Cortex-A7)"; 1267 amc->soc_name = "ast2600-a3"; 1268 amc->hw_strap1 = RAINIER_BMC_HW_STRAP1; 1269 amc->hw_strap2 = RAINIER_BMC_HW_STRAP2; 1270 amc->fmc_model = "mx66l1g45g"; 1271 amc->spi_model = "mx66l1g45g"; 1272 amc->num_cs = 2; 1273 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON; 1274 amc->i2c_init = rainier_bmc_i2c_init; 1275 mc->default_ram_size = 1 * GiB; 1276 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1277 aspeed_soc_num_cpus(amc->soc_name); 1278 }; 1279 1280 /* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */ 1281 #if HOST_LONG_BITS == 32 1282 #define FUJI_BMC_RAM_SIZE (1 * GiB) 1283 #else 1284 #define FUJI_BMC_RAM_SIZE (2 * GiB) 1285 #endif 1286 1287 static void aspeed_machine_fuji_class_init(ObjectClass *oc, void *data) 1288 { 1289 MachineClass *mc = MACHINE_CLASS(oc); 1290 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1291 1292 mc->desc = "Facebook Fuji BMC (Cortex-A7)"; 1293 amc->soc_name = "ast2600-a3"; 1294 amc->hw_strap1 = FUJI_BMC_HW_STRAP1; 1295 amc->hw_strap2 = FUJI_BMC_HW_STRAP2; 1296 amc->fmc_model = "mx66l1g45g"; 1297 amc->spi_model = "mx66l1g45g"; 1298 amc->num_cs = 2; 1299 amc->macs_mask = ASPEED_MAC3_ON; 1300 amc->i2c_init = fuji_bmc_i2c_init; 1301 amc->uart_default = ASPEED_DEV_UART1; 1302 mc->default_ram_size = FUJI_BMC_RAM_SIZE; 1303 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1304 aspeed_soc_num_cpus(amc->soc_name); 1305 }; 1306 1307 static void aspeed_machine_bletchley_class_init(ObjectClass *oc, void *data) 1308 { 1309 MachineClass *mc = MACHINE_CLASS(oc); 1310 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1311 1312 mc->desc = "Facebook Bletchley BMC (Cortex-A7)"; 1313 amc->soc_name = "ast2600-a3"; 1314 amc->hw_strap1 = BLETCHLEY_BMC_HW_STRAP1; 1315 amc->hw_strap2 = BLETCHLEY_BMC_HW_STRAP2; 1316 amc->fmc_model = "w25q01jvq"; 1317 amc->spi_model = NULL; 1318 amc->num_cs = 2; 1319 amc->macs_mask = ASPEED_MAC2_ON; 1320 amc->i2c_init = bletchley_bmc_i2c_init; 1321 mc->default_ram_size = 512 * MiB; 1322 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1323 aspeed_soc_num_cpus(amc->soc_name); 1324 } 1325 1326 static void fby35_reset(MachineState *state) 1327 { 1328 AspeedMachineState *bmc = ASPEED_MACHINE(state); 1329 AspeedGPIOState *gpio = &bmc->soc.gpio; 1330 1331 qemu_devices_reset(); 1332 1333 /* Board ID */ 1334 object_property_set_bool(OBJECT(gpio), "gpioV4", true, &error_fatal); 1335 object_property_set_bool(OBJECT(gpio), "gpioV5", true, &error_fatal); 1336 object_property_set_bool(OBJECT(gpio), "gpioV6", true, &error_fatal); 1337 object_property_set_bool(OBJECT(gpio), "gpioV7", false, &error_fatal); 1338 } 1339 1340 static void aspeed_machine_fby35_class_init(ObjectClass *oc, void *data) 1341 { 1342 MachineClass *mc = MACHINE_CLASS(oc); 1343 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1344 1345 mc->desc = "Facebook fby35 BMC (Cortex-A7)"; 1346 mc->reset = fby35_reset; 1347 amc->fmc_model = "mx66l1g45g"; 1348 amc->num_cs = 2; 1349 amc->macs_mask = ASPEED_MAC3_ON; 1350 amc->i2c_init = fby35_i2c_init; 1351 /* FIXME: Replace this macro with something more general */ 1352 mc->default_ram_size = FUJI_BMC_RAM_SIZE; 1353 } 1354 1355 #define AST1030_INTERNAL_FLASH_SIZE (1024 * 1024) 1356 /* Main SYSCLK frequency in Hz (200MHz) */ 1357 #define SYSCLK_FRQ 200000000ULL 1358 1359 static void aspeed_minibmc_machine_init(MachineState *machine) 1360 { 1361 AspeedMachineState *bmc = ASPEED_MACHINE(machine); 1362 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine); 1363 Clock *sysclk; 1364 1365 sysclk = clock_new(OBJECT(machine), "SYSCLK"); 1366 clock_set_hz(sysclk, SYSCLK_FRQ); 1367 1368 object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name); 1369 qdev_connect_clock_in(DEVICE(&bmc->soc), "sysclk", sysclk); 1370 1371 qdev_prop_set_uint32(DEVICE(&bmc->soc), "uart-default", 1372 amc->uart_default); 1373 qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort); 1374 1375 aspeed_board_init_flashes(&bmc->soc.fmc, 1376 bmc->fmc_model ? bmc->fmc_model : amc->fmc_model, 1377 amc->num_cs, 1378 0); 1379 1380 aspeed_board_init_flashes(&bmc->soc.spi[0], 1381 bmc->spi_model ? bmc->spi_model : amc->spi_model, 1382 amc->num_cs, amc->num_cs); 1383 1384 aspeed_board_init_flashes(&bmc->soc.spi[1], 1385 bmc->spi_model ? bmc->spi_model : amc->spi_model, 1386 amc->num_cs, (amc->num_cs * 2)); 1387 1388 if (amc->i2c_init) { 1389 amc->i2c_init(bmc); 1390 } 1391 1392 armv7m_load_kernel(ARM_CPU(first_cpu), 1393 machine->kernel_filename, 1394 AST1030_INTERNAL_FLASH_SIZE); 1395 } 1396 1397 static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc, 1398 void *data) 1399 { 1400 MachineClass *mc = MACHINE_CLASS(oc); 1401 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1402 1403 mc->desc = "Aspeed AST1030 MiniBMC (Cortex-M4)"; 1404 amc->soc_name = "ast1030-a1"; 1405 amc->hw_strap1 = 0; 1406 amc->hw_strap2 = 0; 1407 mc->init = aspeed_minibmc_machine_init; 1408 mc->default_ram_size = 0; 1409 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1; 1410 amc->fmc_model = "sst25vf032b"; 1411 amc->spi_model = "sst25vf032b"; 1412 amc->num_cs = 2; 1413 amc->macs_mask = 0; 1414 } 1415 1416 static const TypeInfo aspeed_machine_types[] = { 1417 { 1418 .name = MACHINE_TYPE_NAME("palmetto-bmc"), 1419 .parent = TYPE_ASPEED_MACHINE, 1420 .class_init = aspeed_machine_palmetto_class_init, 1421 }, { 1422 .name = MACHINE_TYPE_NAME("supermicrox11-bmc"), 1423 .parent = TYPE_ASPEED_MACHINE, 1424 .class_init = aspeed_machine_supermicrox11_bmc_class_init, 1425 }, { 1426 .name = MACHINE_TYPE_NAME("ast2500-evb"), 1427 .parent = TYPE_ASPEED_MACHINE, 1428 .class_init = aspeed_machine_ast2500_evb_class_init, 1429 }, { 1430 .name = MACHINE_TYPE_NAME("romulus-bmc"), 1431 .parent = TYPE_ASPEED_MACHINE, 1432 .class_init = aspeed_machine_romulus_class_init, 1433 }, { 1434 .name = MACHINE_TYPE_NAME("sonorapass-bmc"), 1435 .parent = TYPE_ASPEED_MACHINE, 1436 .class_init = aspeed_machine_sonorapass_class_init, 1437 }, { 1438 .name = MACHINE_TYPE_NAME("witherspoon-bmc"), 1439 .parent = TYPE_ASPEED_MACHINE, 1440 .class_init = aspeed_machine_witherspoon_class_init, 1441 }, { 1442 .name = MACHINE_TYPE_NAME("ast2600-evb"), 1443 .parent = TYPE_ASPEED_MACHINE, 1444 .class_init = aspeed_machine_ast2600_evb_class_init, 1445 }, { 1446 .name = MACHINE_TYPE_NAME("tacoma-bmc"), 1447 .parent = TYPE_ASPEED_MACHINE, 1448 .class_init = aspeed_machine_tacoma_class_init, 1449 }, { 1450 .name = MACHINE_TYPE_NAME("g220a-bmc"), 1451 .parent = TYPE_ASPEED_MACHINE, 1452 .class_init = aspeed_machine_g220a_class_init, 1453 }, { 1454 .name = MACHINE_TYPE_NAME("fp5280g2-bmc"), 1455 .parent = TYPE_ASPEED_MACHINE, 1456 .class_init = aspeed_machine_fp5280g2_class_init, 1457 }, { 1458 .name = MACHINE_TYPE_NAME("quanta-q71l-bmc"), 1459 .parent = TYPE_ASPEED_MACHINE, 1460 .class_init = aspeed_machine_quanta_q71l_class_init, 1461 }, { 1462 .name = MACHINE_TYPE_NAME("rainier-bmc"), 1463 .parent = TYPE_ASPEED_MACHINE, 1464 .class_init = aspeed_machine_rainier_class_init, 1465 }, { 1466 .name = MACHINE_TYPE_NAME("fuji-bmc"), 1467 .parent = TYPE_ASPEED_MACHINE, 1468 .class_init = aspeed_machine_fuji_class_init, 1469 }, { 1470 .name = MACHINE_TYPE_NAME("bletchley-bmc"), 1471 .parent = TYPE_ASPEED_MACHINE, 1472 .class_init = aspeed_machine_bletchley_class_init, 1473 }, { 1474 .name = MACHINE_TYPE_NAME("fby35-bmc"), 1475 .parent = MACHINE_TYPE_NAME("ast2600-evb"), 1476 .class_init = aspeed_machine_fby35_class_init, 1477 }, { 1478 .name = MACHINE_TYPE_NAME("ast1030-evb"), 1479 .parent = TYPE_ASPEED_MACHINE, 1480 .class_init = aspeed_minibmc_machine_ast1030_evb_class_init, 1481 }, { 1482 .name = TYPE_ASPEED_MACHINE, 1483 .parent = TYPE_MACHINE, 1484 .instance_size = sizeof(AspeedMachineState), 1485 .instance_init = aspeed_machine_instance_init, 1486 .class_size = sizeof(AspeedMachineClass), 1487 .class_init = aspeed_machine_class_init, 1488 .abstract = true, 1489 } 1490 }; 1491 1492 DEFINE_TYPES(aspeed_machine_types) 1493