1 /* 2 * OpenPOWER Palmetto BMC 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * 6 * Copyright 2016 IBM Corp. 7 * 8 * This code is licensed under the GPL version 2 or later. See 9 * the COPYING file in the top-level directory. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "hw/arm/boot.h" 15 #include "hw/arm/aspeed.h" 16 #include "hw/arm/aspeed_soc.h" 17 #include "hw/arm/aspeed_eeprom.h" 18 #include "hw/block/flash.h" 19 #include "hw/i2c/i2c_mux_pca954x.h" 20 #include "hw/i2c/smbus_eeprom.h" 21 #include "hw/gpio/pca9552.h" 22 #include "hw/nvram/eeprom_at24c.h" 23 #include "hw/sensor/tmp105.h" 24 #include "hw/misc/led.h" 25 #include "hw/qdev-properties.h" 26 #include "sysemu/block-backend.h" 27 #include "sysemu/reset.h" 28 #include "hw/loader.h" 29 #include "qemu/error-report.h" 30 #include "qemu/units.h" 31 #include "hw/qdev-clock.h" 32 #include "sysemu/sysemu.h" 33 34 static struct arm_boot_info aspeed_board_binfo = { 35 .board_id = -1, /* device-tree-only board */ 36 }; 37 38 struct AspeedMachineState { 39 /* Private */ 40 MachineState parent_obj; 41 /* Public */ 42 43 AspeedSoCState *soc; 44 MemoryRegion boot_rom; 45 bool mmio_exec; 46 uint32_t uart_chosen; 47 char *fmc_model; 48 char *spi_model; 49 uint32_t hw_strap1; 50 }; 51 52 /* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */ 53 #if HOST_LONG_BITS == 32 54 #define ASPEED_RAM_SIZE(sz) MIN((sz), 1 * GiB) 55 #else 56 #define ASPEED_RAM_SIZE(sz) (sz) 57 #endif 58 59 /* Palmetto hardware value: 0x120CE416 */ 60 #define PALMETTO_BMC_HW_STRAP1 ( \ 61 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) | \ 62 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \ 63 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 64 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \ 65 SCU_HW_STRAP_VGA_CLASS_CODE | \ 66 SCU_HW_STRAP_LPC_RESET_PIN | \ 67 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \ 68 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 69 SCU_HW_STRAP_SPI_WIDTH | \ 70 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 71 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 72 73 /* TODO: Find the actual hardware value */ 74 #define SUPERMICROX11_BMC_HW_STRAP1 ( \ 75 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \ 76 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2) | \ 77 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 78 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \ 79 SCU_HW_STRAP_VGA_CLASS_CODE | \ 80 SCU_HW_STRAP_LPC_RESET_PIN | \ 81 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \ 82 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 83 SCU_HW_STRAP_SPI_WIDTH | \ 84 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 85 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 86 87 /* TODO: Find the actual hardware value */ 88 #define SUPERMICRO_X11SPI_BMC_HW_STRAP1 ( \ 89 AST2500_HW_STRAP1_DEFAULTS | \ 90 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 91 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 92 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 93 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 94 SCU_HW_STRAP_SPI_WIDTH | \ 95 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN)) 96 97 /* AST2500 evb hardware value: 0xF100C2E6 */ 98 #define AST2500_EVB_HW_STRAP1 (( \ 99 AST2500_HW_STRAP1_DEFAULTS | \ 100 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 101 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 102 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 103 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 104 SCU_HW_STRAP_MAC1_RGMII | \ 105 SCU_HW_STRAP_MAC0_RGMII) & \ 106 ~SCU_HW_STRAP_2ND_BOOT_WDT) 107 108 /* Romulus hardware value: 0xF10AD206 */ 109 #define ROMULUS_BMC_HW_STRAP1 ( \ 110 AST2500_HW_STRAP1_DEFAULTS | \ 111 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 112 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 113 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 114 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 115 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \ 116 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER)) 117 118 /* Sonorapass hardware value: 0xF100D216 */ 119 #define SONORAPASS_BMC_HW_STRAP1 ( \ 120 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 121 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 122 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 123 SCU_AST2500_HW_STRAP_RESERVED28 | \ 124 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 125 SCU_HW_STRAP_VGA_CLASS_CODE | \ 126 SCU_HW_STRAP_LPC_RESET_PIN | \ 127 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 128 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 129 SCU_HW_STRAP_VGA_BIOS_ROM | \ 130 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 131 SCU_AST2500_HW_STRAP_RESERVED1) 132 133 #define G220A_BMC_HW_STRAP1 ( \ 134 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 135 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 136 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 137 SCU_AST2500_HW_STRAP_RESERVED28 | \ 138 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 139 SCU_HW_STRAP_2ND_BOOT_WDT | \ 140 SCU_HW_STRAP_VGA_CLASS_CODE | \ 141 SCU_HW_STRAP_LPC_RESET_PIN | \ 142 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 143 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 144 SCU_HW_STRAP_VGA_SIZE_SET(VGA_64M_DRAM) | \ 145 SCU_AST2500_HW_STRAP_RESERVED1) 146 147 /* FP5280G2 hardware value: 0XF100D286 */ 148 #define FP5280G2_BMC_HW_STRAP1 ( \ 149 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 150 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 151 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 152 SCU_AST2500_HW_STRAP_RESERVED28 | \ 153 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 154 SCU_HW_STRAP_VGA_CLASS_CODE | \ 155 SCU_HW_STRAP_LPC_RESET_PIN | \ 156 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 157 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 158 SCU_HW_STRAP_MAC1_RGMII | \ 159 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 160 SCU_AST2500_HW_STRAP_RESERVED1) 161 162 /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */ 163 #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1 164 165 /* Quanta-Q71l hardware value */ 166 #define QUANTA_Q71L_BMC_HW_STRAP1 ( \ 167 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \ 168 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2/* DDR3 with CL=6, CWL=5 */) | \ 169 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 170 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_24M_IN) | \ 171 SCU_HW_STRAP_VGA_CLASS_CODE | \ 172 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_PASS_THROUGH) | \ 173 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 174 SCU_HW_STRAP_SPI_WIDTH | \ 175 SCU_HW_STRAP_VGA_SIZE_SET(VGA_8M_DRAM) | \ 176 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 177 178 /* AST2600 evb hardware value */ 179 #define AST2600_EVB_HW_STRAP1 0x000000C0 180 #define AST2600_EVB_HW_STRAP2 0x00000003 181 182 #ifdef TARGET_AARCH64 183 /* AST2700 evb hardware value */ 184 #define AST2700_EVB_HW_STRAP1 0x000000C0 185 #define AST2700_EVB_HW_STRAP2 0x00000003 186 #endif 187 188 /* Tacoma hardware value */ 189 #define TACOMA_BMC_HW_STRAP1 0x00000000 190 #define TACOMA_BMC_HW_STRAP2 0x00000040 191 192 /* Rainier hardware value: (QEMU prototype) */ 193 #define RAINIER_BMC_HW_STRAP1 (0x00422016 | SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC) 194 #define RAINIER_BMC_HW_STRAP2 0x80000848 195 196 /* Fuji hardware value */ 197 #define FUJI_BMC_HW_STRAP1 0x00000000 198 #define FUJI_BMC_HW_STRAP2 0x00000000 199 200 /* Bletchley hardware value */ 201 /* TODO: Leave same as EVB for now. */ 202 #define BLETCHLEY_BMC_HW_STRAP1 AST2600_EVB_HW_STRAP1 203 #define BLETCHLEY_BMC_HW_STRAP2 AST2600_EVB_HW_STRAP2 204 205 /* Qualcomm DC-SCM hardware value */ 206 #define QCOM_DC_SCM_V1_BMC_HW_STRAP1 0x00000000 207 #define QCOM_DC_SCM_V1_BMC_HW_STRAP2 0x00000041 208 209 #define AST_SMP_MAILBOX_BASE 0x1e6e2180 210 #define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0) 211 #define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4) 212 #define AST_SMP_MBOX_FIELD_READY (AST_SMP_MAILBOX_BASE + 0x8) 213 #define AST_SMP_MBOX_FIELD_POLLINSN (AST_SMP_MAILBOX_BASE + 0xc) 214 #define AST_SMP_MBOX_CODE (AST_SMP_MAILBOX_BASE + 0x10) 215 #define AST_SMP_MBOX_GOSIGN 0xabbaab00 216 217 static void aspeed_write_smpboot(ARMCPU *cpu, 218 const struct arm_boot_info *info) 219 { 220 AddressSpace *as = arm_boot_address_space(cpu, info); 221 static const ARMInsnFixup poll_mailbox_ready[] = { 222 /* 223 * r2 = per-cpu go sign value 224 * r1 = AST_SMP_MBOX_FIELD_ENTRY 225 * r0 = AST_SMP_MBOX_FIELD_GOSIGN 226 */ 227 { 0xee100fb0 }, /* mrc p15, 0, r0, c0, c0, 5 */ 228 { 0xe21000ff }, /* ands r0, r0, #255 */ 229 { 0xe59f201c }, /* ldr r2, [pc, #28] */ 230 { 0xe1822000 }, /* orr r2, r2, r0 */ 231 232 { 0xe59f1018 }, /* ldr r1, [pc, #24] */ 233 { 0xe59f0018 }, /* ldr r0, [pc, #24] */ 234 235 { 0xe320f002 }, /* wfe */ 236 { 0xe5904000 }, /* ldr r4, [r0] */ 237 { 0xe1520004 }, /* cmp r2, r4 */ 238 { 0x1afffffb }, /* bne <wfe> */ 239 { 0xe591f000 }, /* ldr pc, [r1] */ 240 { AST_SMP_MBOX_GOSIGN }, 241 { AST_SMP_MBOX_FIELD_ENTRY }, 242 { AST_SMP_MBOX_FIELD_GOSIGN }, 243 { 0, FIXUP_TERMINATOR } 244 }; 245 static const uint32_t fixupcontext[FIXUP_MAX] = { 0 }; 246 247 arm_write_bootloader("aspeed.smpboot", as, info->smp_loader_start, 248 poll_mailbox_ready, fixupcontext); 249 } 250 251 static void aspeed_reset_secondary(ARMCPU *cpu, 252 const struct arm_boot_info *info) 253 { 254 AddressSpace *as = arm_boot_address_space(cpu, info); 255 CPUState *cs = CPU(cpu); 256 257 /* info->smp_bootreg_addr */ 258 address_space_stl_notdirty(as, AST_SMP_MBOX_FIELD_GOSIGN, 0, 259 MEMTXATTRS_UNSPECIFIED, NULL); 260 cpu_set_pc(cs, info->smp_loader_start); 261 } 262 263 static void write_boot_rom(BlockBackend *blk, hwaddr addr, size_t rom_size, 264 Error **errp) 265 { 266 g_autofree void *storage = NULL; 267 int64_t size; 268 269 /* The block backend size should have already been 'validated' by 270 * the creation of the m25p80 object. 271 */ 272 size = blk_getlength(blk); 273 if (size <= 0) { 274 error_setg(errp, "failed to get flash size"); 275 return; 276 } 277 278 if (rom_size > size) { 279 rom_size = size; 280 } 281 282 storage = g_malloc0(rom_size); 283 if (blk_pread(blk, 0, rom_size, storage, 0) < 0) { 284 error_setg(errp, "failed to read the initial flash content"); 285 return; 286 } 287 288 rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr); 289 } 290 291 /* 292 * Create a ROM and copy the flash contents at the expected address 293 * (0x0). Boots faster than execute-in-place. 294 */ 295 static void aspeed_install_boot_rom(AspeedMachineState *bmc, BlockBackend *blk, 296 uint64_t rom_size) 297 { 298 AspeedSoCState *soc = bmc->soc; 299 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(soc); 300 301 memory_region_init_rom(&bmc->boot_rom, NULL, "aspeed.boot_rom", rom_size, 302 &error_abort); 303 memory_region_add_subregion_overlap(&soc->spi_boot_container, 0, 304 &bmc->boot_rom, 1); 305 write_boot_rom(blk, sc->memmap[ASPEED_DEV_SPI_BOOT], 306 rom_size, &error_abort); 307 } 308 309 void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype, 310 unsigned int count, int unit0) 311 { 312 int i; 313 314 if (!flashtype) { 315 return; 316 } 317 318 for (i = 0; i < count; ++i) { 319 DriveInfo *dinfo = drive_get(IF_MTD, 0, unit0 + i); 320 DeviceState *dev; 321 322 dev = qdev_new(flashtype); 323 if (dinfo) { 324 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo)); 325 } 326 qdev_prop_set_uint8(dev, "cs", i); 327 qdev_realize_and_unref(dev, BUS(s->spi), &error_fatal); 328 } 329 } 330 331 static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo, bool emmc, 332 bool boot_emmc) 333 { 334 DeviceState *card; 335 336 if (!dinfo) { 337 return; 338 } 339 card = qdev_new(emmc ? TYPE_EMMC : TYPE_SD_CARD); 340 if (emmc) { 341 qdev_prop_set_uint64(card, "boot-partition-size", 1 * MiB); 342 qdev_prop_set_uint8(card, "boot-config", 343 boot_emmc ? 0x1 << 3 : 0x0); 344 } 345 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo), 346 &error_fatal); 347 qdev_realize_and_unref(card, 348 qdev_get_child_bus(DEVICE(sdhci), "sd-bus"), 349 &error_fatal); 350 } 351 352 static void connect_serial_hds_to_uarts(AspeedMachineState *bmc) 353 { 354 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc); 355 AspeedSoCState *s = bmc->soc; 356 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 357 int uart_chosen = bmc->uart_chosen ? bmc->uart_chosen : amc->uart_default; 358 359 aspeed_soc_uart_set_chr(s, uart_chosen, serial_hd(0)); 360 for (int i = 1, uart = sc->uarts_base; i < sc->uarts_num; i++, uart++) { 361 if (uart == uart_chosen) { 362 continue; 363 } 364 aspeed_soc_uart_set_chr(s, uart, serial_hd(i)); 365 } 366 } 367 368 static void aspeed_machine_init(MachineState *machine) 369 { 370 AspeedMachineState *bmc = ASPEED_MACHINE(machine); 371 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine); 372 AspeedSoCClass *sc; 373 int i; 374 DriveInfo *emmc0 = NULL; 375 bool boot_emmc; 376 377 bmc->soc = ASPEED_SOC(object_new(amc->soc_name)); 378 object_property_add_child(OBJECT(machine), "soc", OBJECT(bmc->soc)); 379 object_unref(OBJECT(bmc->soc)); 380 sc = ASPEED_SOC_GET_CLASS(bmc->soc); 381 382 /* 383 * This will error out if the RAM size is not supported by the 384 * memory controller of the SoC. 385 */ 386 object_property_set_uint(OBJECT(bmc->soc), "ram-size", machine->ram_size, 387 &error_fatal); 388 389 for (i = 0; i < sc->macs_num; i++) { 390 if ((amc->macs_mask & (1 << i)) && 391 !qemu_configure_nic_device(DEVICE(&bmc->soc->ftgmac100[i]), 392 true, NULL)) { 393 break; /* No configs left; stop asking */ 394 } 395 } 396 397 object_property_set_int(OBJECT(bmc->soc), "hw-strap1", bmc->hw_strap1, 398 &error_abort); 399 object_property_set_int(OBJECT(bmc->soc), "hw-strap2", amc->hw_strap2, 400 &error_abort); 401 object_property_set_link(OBJECT(bmc->soc), "memory", 402 OBJECT(get_system_memory()), &error_abort); 403 object_property_set_link(OBJECT(bmc->soc), "dram", 404 OBJECT(machine->ram), &error_abort); 405 if (machine->kernel_filename) { 406 /* 407 * When booting with a -kernel command line there is no u-boot 408 * that runs to unlock the SCU. In this case set the default to 409 * be unlocked as the kernel expects 410 */ 411 object_property_set_int(OBJECT(bmc->soc), "hw-prot-key", 412 ASPEED_SCU_PROT_KEY, &error_abort); 413 } 414 connect_serial_hds_to_uarts(bmc); 415 qdev_realize(DEVICE(bmc->soc), NULL, &error_abort); 416 417 if (defaults_enabled()) { 418 aspeed_board_init_flashes(&bmc->soc->fmc, 419 bmc->fmc_model ? bmc->fmc_model : amc->fmc_model, 420 amc->num_cs, 0); 421 aspeed_board_init_flashes(&bmc->soc->spi[0], 422 bmc->spi_model ? bmc->spi_model : amc->spi_model, 423 1, amc->num_cs); 424 } 425 426 if (machine->kernel_filename && sc->num_cpus > 1) { 427 /* With no u-boot we must set up a boot stub for the secondary CPU */ 428 MemoryRegion *smpboot = g_new(MemoryRegion, 1); 429 memory_region_init_ram(smpboot, NULL, "aspeed.smpboot", 430 0x80, &error_abort); 431 memory_region_add_subregion(get_system_memory(), 432 AST_SMP_MAILBOX_BASE, smpboot); 433 434 aspeed_board_binfo.write_secondary_boot = aspeed_write_smpboot; 435 aspeed_board_binfo.secondary_cpu_reset_hook = aspeed_reset_secondary; 436 aspeed_board_binfo.smp_loader_start = AST_SMP_MBOX_CODE; 437 } 438 439 aspeed_board_binfo.ram_size = machine->ram_size; 440 aspeed_board_binfo.loader_start = sc->memmap[ASPEED_DEV_SDRAM]; 441 442 if (amc->i2c_init) { 443 amc->i2c_init(bmc); 444 } 445 446 for (i = 0; i < bmc->soc->sdhci.num_slots; i++) { 447 sdhci_attach_drive(&bmc->soc->sdhci.slots[i], 448 drive_get(IF_SD, 0, i), false, false); 449 } 450 451 boot_emmc = sc->boot_from_emmc(bmc->soc); 452 453 if (bmc->soc->emmc.num_slots) { 454 emmc0 = drive_get(IF_SD, 0, bmc->soc->sdhci.num_slots); 455 sdhci_attach_drive(&bmc->soc->emmc.slots[0], emmc0, true, boot_emmc); 456 } 457 458 if (!bmc->mmio_exec) { 459 DeviceState *dev = ssi_get_cs(bmc->soc->fmc.spi, 0); 460 BlockBackend *fmc0 = dev ? m25p80_get_blk(dev) : NULL; 461 462 if (fmc0 && !boot_emmc) { 463 uint64_t rom_size = memory_region_size(&bmc->soc->spi_boot); 464 aspeed_install_boot_rom(bmc, fmc0, rom_size); 465 } else if (emmc0) { 466 aspeed_install_boot_rom(bmc, blk_by_legacy_dinfo(emmc0), 64 * KiB); 467 } 468 } 469 470 arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo); 471 } 472 473 static void palmetto_bmc_i2c_init(AspeedMachineState *bmc) 474 { 475 AspeedSoCState *soc = bmc->soc; 476 DeviceState *dev; 477 uint8_t *eeprom_buf = g_malloc0(32 * 1024); 478 479 /* The palmetto platform expects a ds3231 RTC but a ds1338 is 480 * enough to provide basic RTC features. Alarms will be missing */ 481 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), "ds1338", 0x68); 482 483 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, 484 eeprom_buf); 485 486 /* add a TMP423 temperature sensor */ 487 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), 488 "tmp423", 0x4c)); 489 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 490 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 491 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 492 object_property_set_int(OBJECT(dev), "temperature3", 110000, &error_abort); 493 } 494 495 static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc) 496 { 497 AspeedSoCState *soc = bmc->soc; 498 499 /* 500 * The quanta-q71l platform expects tmp75s which are compatible with 501 * tmp105s. 502 */ 503 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4c); 504 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4e); 505 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4f); 506 507 /* TODO: i2c-1: Add baseboard FRU eeprom@54 24c64 */ 508 /* TODO: i2c-1: Add Frontpanel FRU eeprom@57 24c64 */ 509 /* TODO: Add Memory Riser i2c mux and eeproms. */ 510 511 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9546", 0x74); 512 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9548", 0x77); 513 514 /* TODO: i2c-3: Add BIOS FRU eeprom@56 24c64 */ 515 516 /* i2c-7 */ 517 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9546", 0x70); 518 /* - i2c@0: pmbus@59 */ 519 /* - i2c@1: pmbus@58 */ 520 /* - i2c@2: pmbus@58 */ 521 /* - i2c@3: pmbus@59 */ 522 523 /* TODO: i2c-7: Add PDB FRU eeprom@52 */ 524 /* TODO: i2c-8: Add BMC FRU eeprom@50 */ 525 } 526 527 static void ast2500_evb_i2c_init(AspeedMachineState *bmc) 528 { 529 AspeedSoCState *soc = bmc->soc; 530 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 531 532 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 3), 0x50, 533 eeprom_buf); 534 535 /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */ 536 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), 537 TYPE_TMP105, 0x4d); 538 } 539 540 static void ast2600_evb_i2c_init(AspeedMachineState *bmc) 541 { 542 AspeedSoCState *soc = bmc->soc; 543 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 544 545 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 546 eeprom_buf); 547 548 /* LM75 is compatible with TMP105 driver */ 549 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), 550 TYPE_TMP105, 0x4d); 551 } 552 553 static void yosemitev2_bmc_i2c_init(AspeedMachineState *bmc) 554 { 555 AspeedSoCState *soc = bmc->soc; 556 557 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x51, 128 * KiB); 558 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 128 * KiB, 559 yosemitev2_bmc_fruid, yosemitev2_bmc_fruid_len); 560 /* TMP421 */ 561 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "tmp421", 0x1f); 562 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp421", 0x4e); 563 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp421", 0x4f); 564 565 } 566 567 static void romulus_bmc_i2c_init(AspeedMachineState *bmc) 568 { 569 AspeedSoCState *soc = bmc->soc; 570 571 /* The romulus board expects Epson RX8900 I2C RTC but a ds1338 is 572 * good enough */ 573 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32); 574 } 575 576 static void tiogapass_bmc_i2c_init(AspeedMachineState *bmc) 577 { 578 AspeedSoCState *soc = bmc->soc; 579 580 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, 128 * KiB); 581 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 6), 0x54, 128 * KiB, 582 tiogapass_bmc_fruid, tiogapass_bmc_fruid_len); 583 /* TMP421 */ 584 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "tmp421", 0x1f); 585 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp421", 0x4f); 586 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp421", 0x4e); 587 } 588 589 static void create_pca9552(AspeedSoCState *soc, int bus_id, int addr) 590 { 591 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, bus_id), 592 TYPE_PCA9552, addr); 593 } 594 595 static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc) 596 { 597 AspeedSoCState *soc = bmc->soc; 598 599 /* bus 2 : */ 600 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x48); 601 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x49); 602 /* bus 2 : pca9546 @ 0x73 */ 603 604 /* bus 3 : pca9548 @ 0x70 */ 605 606 /* bus 4 : */ 607 uint8_t *eeprom4_54 = g_malloc0(8 * 1024); 608 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, 609 eeprom4_54); 610 /* PCA9539 @ 0x76, but PCA9552 is compatible */ 611 create_pca9552(soc, 4, 0x76); 612 /* PCA9539 @ 0x77, but PCA9552 is compatible */ 613 create_pca9552(soc, 4, 0x77); 614 615 /* bus 6 : */ 616 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x48); 617 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x49); 618 /* bus 6 : pca9546 @ 0x73 */ 619 620 /* bus 8 : */ 621 uint8_t *eeprom8_56 = g_malloc0(8 * 1024); 622 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 8), 0x56, 623 eeprom8_56); 624 create_pca9552(soc, 8, 0x60); 625 create_pca9552(soc, 8, 0x61); 626 /* bus 8 : adc128d818 @ 0x1d */ 627 /* bus 8 : adc128d818 @ 0x1f */ 628 629 /* 630 * bus 13 : pca9548 @ 0x71 631 * - channel 3: 632 * - tmm421 @ 0x4c 633 * - tmp421 @ 0x4e 634 * - tmp421 @ 0x4f 635 */ 636 637 } 638 639 static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc) 640 { 641 static const struct { 642 unsigned gpio_id; 643 LEDColor color; 644 const char *description; 645 bool gpio_polarity; 646 } pca1_leds[] = { 647 {13, LED_COLOR_GREEN, "front-fault-4", GPIO_POLARITY_ACTIVE_LOW}, 648 {14, LED_COLOR_GREEN, "front-power-3", GPIO_POLARITY_ACTIVE_LOW}, 649 {15, LED_COLOR_GREEN, "front-id-5", GPIO_POLARITY_ACTIVE_LOW}, 650 }; 651 AspeedSoCState *soc = bmc->soc; 652 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 653 DeviceState *dev; 654 LEDState *led; 655 656 /* Bus 3: TODO bmp280@77 */ 657 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60)); 658 qdev_prop_set_string(dev, "description", "pca1"); 659 i2c_slave_realize_and_unref(I2C_SLAVE(dev), 660 aspeed_i2c_get_bus(&soc->i2c, 3), 661 &error_fatal); 662 663 for (size_t i = 0; i < ARRAY_SIZE(pca1_leds); i++) { 664 led = led_create_simple(OBJECT(bmc), 665 pca1_leds[i].gpio_polarity, 666 pca1_leds[i].color, 667 pca1_leds[i].description); 668 qdev_connect_gpio_out(dev, pca1_leds[i].gpio_id, 669 qdev_get_gpio_in(DEVICE(led), 0)); 670 } 671 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "dps310", 0x76); 672 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "max31785", 0x52); 673 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "tmp423", 0x4c); 674 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "tmp423", 0x4c); 675 676 /* The Witherspoon expects a TMP275 but a TMP105 is compatible */ 677 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), TYPE_TMP105, 678 0x4a); 679 680 /* The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is 681 * good enough */ 682 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32); 683 684 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 11), 0x51, 685 eeprom_buf); 686 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60)); 687 qdev_prop_set_string(dev, "description", "pca0"); 688 i2c_slave_realize_and_unref(I2C_SLAVE(dev), 689 aspeed_i2c_get_bus(&soc->i2c, 11), 690 &error_fatal); 691 /* Bus 11: TODO ucd90160@64 */ 692 } 693 694 static void g220a_bmc_i2c_init(AspeedMachineState *bmc) 695 { 696 AspeedSoCState *soc = bmc->soc; 697 DeviceState *dev; 698 699 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), 700 "emc1413", 0x4c)); 701 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 702 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 703 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 704 705 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12), 706 "emc1413", 0x4c)); 707 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 708 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 709 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 710 711 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 13), 712 "emc1413", 0x4c)); 713 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 714 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 715 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 716 717 static uint8_t eeprom_buf[2 * 1024] = { 718 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0xfe, 719 0x01, 0x06, 0x00, 0xc9, 0x42, 0x79, 0x74, 0x65, 720 0x64, 0x61, 0x6e, 0x63, 0x65, 0xc5, 0x47, 0x32, 721 0x32, 0x30, 0x41, 0xc4, 0x41, 0x41, 0x42, 0x42, 722 0xc4, 0x43, 0x43, 0x44, 0x44, 0xc4, 0x45, 0x45, 723 0x46, 0x46, 0xc4, 0x48, 0x48, 0x47, 0x47, 0xc1, 724 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa7, 725 }; 726 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x57, 727 eeprom_buf); 728 } 729 730 static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc) 731 { 732 AspeedSoCState *soc = bmc->soc; 733 I2CSlave *i2c_mux; 734 735 /* The at24c256 */ 736 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 1), 0x50, 32768); 737 738 /* The fp5280g2 expects a TMP112 but a TMP105 is compatible */ 739 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105, 740 0x48); 741 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105, 742 0x49); 743 744 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), 745 "pca9546", 0x70); 746 /* It expects a TMP112 but a TMP105 is compatible */ 747 i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 0), TYPE_TMP105, 748 0x4a); 749 750 /* It expects a ds3232 but a ds1338 is good enough */ 751 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "ds1338", 0x68); 752 753 /* It expects a pca9555 but a pca9552 is compatible */ 754 create_pca9552(soc, 8, 0x30); 755 } 756 757 static void rainier_bmc_i2c_init(AspeedMachineState *bmc) 758 { 759 AspeedSoCState *soc = bmc->soc; 760 I2CSlave *i2c_mux; 761 762 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB); 763 764 create_pca9552(soc, 3, 0x61); 765 766 /* The rainier expects a TMP275 but a TMP105 is compatible */ 767 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, 768 0x48); 769 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, 770 0x49); 771 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, 772 0x4a); 773 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), 774 "pca9546", 0x70); 775 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 776 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 777 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x52, 64 * KiB); 778 create_pca9552(soc, 4, 0x60); 779 780 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105, 781 0x48); 782 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105, 783 0x49); 784 create_pca9552(soc, 5, 0x60); 785 create_pca9552(soc, 5, 0x61); 786 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), 787 "pca9546", 0x70); 788 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 789 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 790 791 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, 792 0x48); 793 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, 794 0x4a); 795 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, 796 0x4b); 797 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), 798 "pca9546", 0x70); 799 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 800 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 801 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x50, 64 * KiB); 802 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 3), 0x51, 64 * KiB); 803 804 create_pca9552(soc, 7, 0x30); 805 create_pca9552(soc, 7, 0x31); 806 create_pca9552(soc, 7, 0x32); 807 create_pca9552(soc, 7, 0x33); 808 create_pca9552(soc, 7, 0x60); 809 create_pca9552(soc, 7, 0x61); 810 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "dps310", 0x76); 811 /* Bus 7: TODO si7021-a20@20 */ 812 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), TYPE_TMP105, 813 0x48); 814 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "max31785", 0x52); 815 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 64 * KiB); 816 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x51, 64 * KiB); 817 818 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105, 819 0x48); 820 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105, 821 0x4a); 822 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x50, 823 64 * KiB, rainier_bb_fruid, rainier_bb_fruid_len); 824 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 825 64 * KiB, rainier_bmc_fruid, rainier_bmc_fruid_len); 826 create_pca9552(soc, 8, 0x60); 827 create_pca9552(soc, 8, 0x61); 828 /* Bus 8: ucd90320@11 */ 829 /* Bus 8: ucd90320@b */ 830 /* Bus 8: ucd90320@c */ 831 832 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c); 833 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4d); 834 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 9), 0x50, 128 * KiB); 835 836 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c); 837 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4d); 838 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 10), 0x50, 128 * KiB); 839 840 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105, 841 0x48); 842 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105, 843 0x49); 844 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), 845 "pca9546", 0x70); 846 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 847 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 848 create_pca9552(soc, 11, 0x60); 849 850 851 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 13), 0x50, 64 * KiB); 852 create_pca9552(soc, 13, 0x60); 853 854 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 14), 0x50, 64 * KiB); 855 create_pca9552(soc, 14, 0x60); 856 857 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 15), 0x50, 64 * KiB); 858 create_pca9552(soc, 15, 0x60); 859 } 860 861 static void get_pca9548_channels(I2CBus *bus, uint8_t mux_addr, 862 I2CBus **channels) 863 { 864 I2CSlave *mux = i2c_slave_create_simple(bus, "pca9548", mux_addr); 865 for (int i = 0; i < 8; i++) { 866 channels[i] = pca954x_i2c_get_bus(mux, i); 867 } 868 } 869 870 #define TYPE_LM75 TYPE_TMP105 871 #define TYPE_TMP75 TYPE_TMP105 872 #define TYPE_TMP422 "tmp422" 873 874 static void fuji_bmc_i2c_init(AspeedMachineState *bmc) 875 { 876 AspeedSoCState *soc = bmc->soc; 877 I2CBus *i2c[144] = {}; 878 879 for (int i = 0; i < 16; i++) { 880 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); 881 } 882 I2CBus *i2c180 = i2c[2]; 883 I2CBus *i2c480 = i2c[8]; 884 I2CBus *i2c600 = i2c[11]; 885 886 get_pca9548_channels(i2c180, 0x70, &i2c[16]); 887 get_pca9548_channels(i2c480, 0x70, &i2c[24]); 888 /* NOTE: The device tree skips [32, 40) in the alias numbering */ 889 get_pca9548_channels(i2c600, 0x77, &i2c[40]); 890 get_pca9548_channels(i2c[24], 0x71, &i2c[48]); 891 get_pca9548_channels(i2c[25], 0x72, &i2c[56]); 892 get_pca9548_channels(i2c[26], 0x76, &i2c[64]); 893 get_pca9548_channels(i2c[27], 0x76, &i2c[72]); 894 for (int i = 0; i < 8; i++) { 895 get_pca9548_channels(i2c[40 + i], 0x76, &i2c[80 + i * 8]); 896 } 897 898 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4c); 899 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4d); 900 901 /* 902 * EEPROM 24c64 size is 64Kbits or 8 Kbytes 903 * 24c02 size is 2Kbits or 256 bytes 904 */ 905 at24c_eeprom_init(i2c[19], 0x52, 8 * KiB); 906 at24c_eeprom_init(i2c[20], 0x50, 256); 907 at24c_eeprom_init(i2c[22], 0x52, 256); 908 909 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x48); 910 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x49); 911 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x4a); 912 i2c_slave_create_simple(i2c[3], TYPE_TMP422, 0x4c); 913 914 at24c_eeprom_init(i2c[8], 0x51, 8 * KiB); 915 i2c_slave_create_simple(i2c[8], TYPE_LM75, 0x4a); 916 917 i2c_slave_create_simple(i2c[50], TYPE_LM75, 0x4c); 918 at24c_eeprom_init(i2c[50], 0x52, 8 * KiB); 919 i2c_slave_create_simple(i2c[51], TYPE_TMP75, 0x48); 920 i2c_slave_create_simple(i2c[52], TYPE_TMP75, 0x49); 921 922 i2c_slave_create_simple(i2c[59], TYPE_TMP75, 0x48); 923 i2c_slave_create_simple(i2c[60], TYPE_TMP75, 0x49); 924 925 at24c_eeprom_init(i2c[65], 0x53, 8 * KiB); 926 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x49); 927 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x48); 928 at24c_eeprom_init(i2c[68], 0x52, 8 * KiB); 929 at24c_eeprom_init(i2c[69], 0x52, 8 * KiB); 930 at24c_eeprom_init(i2c[70], 0x52, 8 * KiB); 931 at24c_eeprom_init(i2c[71], 0x52, 8 * KiB); 932 933 at24c_eeprom_init(i2c[73], 0x53, 8 * KiB); 934 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x49); 935 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x48); 936 at24c_eeprom_init(i2c[76], 0x52, 8 * KiB); 937 at24c_eeprom_init(i2c[77], 0x52, 8 * KiB); 938 at24c_eeprom_init(i2c[78], 0x52, 8 * KiB); 939 at24c_eeprom_init(i2c[79], 0x52, 8 * KiB); 940 at24c_eeprom_init(i2c[28], 0x50, 256); 941 942 for (int i = 0; i < 8; i++) { 943 at24c_eeprom_init(i2c[81 + i * 8], 0x56, 64 * KiB); 944 i2c_slave_create_simple(i2c[82 + i * 8], TYPE_TMP75, 0x48); 945 i2c_slave_create_simple(i2c[83 + i * 8], TYPE_TMP75, 0x4b); 946 i2c_slave_create_simple(i2c[84 + i * 8], TYPE_TMP75, 0x4a); 947 } 948 } 949 950 #define TYPE_TMP421 "tmp421" 951 952 static void bletchley_bmc_i2c_init(AspeedMachineState *bmc) 953 { 954 AspeedSoCState *soc = bmc->soc; 955 I2CBus *i2c[13] = {}; 956 for (int i = 0; i < 13; i++) { 957 if ((i == 8) || (i == 11)) { 958 continue; 959 } 960 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); 961 } 962 963 /* Bus 0 - 5 all have the same config. */ 964 for (int i = 0; i < 6; i++) { 965 /* Missing model: ti,ina230 @ 0x45 */ 966 /* Missing model: mps,mp5023 @ 0x40 */ 967 i2c_slave_create_simple(i2c[i], TYPE_TMP421, 0x4f); 968 /* Missing model: nxp,pca9539 @ 0x76, but PCA9552 works enough */ 969 i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x76); 970 i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x67); 971 /* Missing model: fsc,fusb302 @ 0x22 */ 972 } 973 974 /* Bus 6 */ 975 at24c_eeprom_init(i2c[6], 0x56, 65536); 976 /* Missing model: nxp,pcf85263 @ 0x51 , but ds1338 works enough */ 977 i2c_slave_create_simple(i2c[6], "ds1338", 0x51); 978 979 980 /* Bus 7 */ 981 at24c_eeprom_init(i2c[7], 0x54, 65536); 982 983 /* Bus 9 */ 984 i2c_slave_create_simple(i2c[9], TYPE_TMP421, 0x4f); 985 986 /* Bus 10 */ 987 i2c_slave_create_simple(i2c[10], TYPE_TMP421, 0x4f); 988 /* Missing model: ti,hdc1080 @ 0x40 */ 989 i2c_slave_create_simple(i2c[10], TYPE_PCA9552, 0x67); 990 991 /* Bus 12 */ 992 /* Missing model: adi,adm1278 @ 0x11 */ 993 i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4c); 994 i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4d); 995 i2c_slave_create_simple(i2c[12], TYPE_PCA9552, 0x67); 996 } 997 998 static void fby35_i2c_init(AspeedMachineState *bmc) 999 { 1000 AspeedSoCState *soc = bmc->soc; 1001 I2CBus *i2c[16]; 1002 1003 for (int i = 0; i < 16; i++) { 1004 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); 1005 } 1006 1007 i2c_slave_create_simple(i2c[2], TYPE_LM75, 0x4f); 1008 i2c_slave_create_simple(i2c[8], TYPE_TMP421, 0x1f); 1009 /* Hotswap controller is actually supposed to be mp5920 or ltc4282. */ 1010 i2c_slave_create_simple(i2c[11], "adm1272", 0x44); 1011 i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4e); 1012 i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4f); 1013 1014 at24c_eeprom_init(i2c[4], 0x51, 128 * KiB); 1015 at24c_eeprom_init(i2c[6], 0x51, 128 * KiB); 1016 at24c_eeprom_init_rom(i2c[8], 0x50, 32 * KiB, fby35_nic_fruid, 1017 fby35_nic_fruid_len); 1018 at24c_eeprom_init_rom(i2c[11], 0x51, 128 * KiB, fby35_bb_fruid, 1019 fby35_bb_fruid_len); 1020 at24c_eeprom_init_rom(i2c[11], 0x54, 128 * KiB, fby35_bmc_fruid, 1021 fby35_bmc_fruid_len); 1022 1023 /* 1024 * TODO: There is a multi-master i2c connection to an AST1030 MiniBMC on 1025 * buses 0, 1, 2, 3, and 9. Source address 0x10, target address 0x20 on 1026 * each. 1027 */ 1028 } 1029 1030 static void qcom_dc_scm_bmc_i2c_init(AspeedMachineState *bmc) 1031 { 1032 AspeedSoCState *soc = bmc->soc; 1033 1034 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 15), "tmp105", 0x4d); 1035 } 1036 1037 static void qcom_dc_scm_firework_i2c_init(AspeedMachineState *bmc) 1038 { 1039 AspeedSoCState *soc = bmc->soc; 1040 I2CSlave *therm_mux, *cpuvr_mux; 1041 1042 /* Create the generic DC-SCM hardware */ 1043 qcom_dc_scm_bmc_i2c_init(bmc); 1044 1045 /* Now create the Firework specific hardware */ 1046 1047 /* I2C7 CPUVR MUX */ 1048 cpuvr_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), 1049 "pca9546", 0x70); 1050 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 0), "pca9548", 0x72); 1051 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 1), "pca9548", 0x72); 1052 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 2), "pca9548", 0x72); 1053 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 3), "pca9548", 0x72); 1054 1055 /* I2C8 Thermal Diodes*/ 1056 therm_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), 1057 "pca9548", 0x70); 1058 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 0), TYPE_LM75, 0x4C); 1059 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 1), TYPE_LM75, 0x4C); 1060 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 2), TYPE_LM75, 0x48); 1061 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 3), TYPE_LM75, 0x48); 1062 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 4), TYPE_LM75, 0x48); 1063 1064 /* I2C9 Fan Controller (MAX31785) */ 1065 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x52); 1066 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x54); 1067 } 1068 1069 static bool aspeed_get_mmio_exec(Object *obj, Error **errp) 1070 { 1071 return ASPEED_MACHINE(obj)->mmio_exec; 1072 } 1073 1074 static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp) 1075 { 1076 ASPEED_MACHINE(obj)->mmio_exec = value; 1077 } 1078 1079 static void aspeed_machine_instance_init(Object *obj) 1080 { 1081 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(obj); 1082 1083 ASPEED_MACHINE(obj)->mmio_exec = false; 1084 ASPEED_MACHINE(obj)->hw_strap1 = amc->hw_strap1; 1085 } 1086 1087 static char *aspeed_get_fmc_model(Object *obj, Error **errp) 1088 { 1089 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1090 return g_strdup(bmc->fmc_model); 1091 } 1092 1093 static void aspeed_set_fmc_model(Object *obj, const char *value, Error **errp) 1094 { 1095 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1096 1097 g_free(bmc->fmc_model); 1098 bmc->fmc_model = g_strdup(value); 1099 } 1100 1101 static char *aspeed_get_spi_model(Object *obj, Error **errp) 1102 { 1103 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1104 return g_strdup(bmc->spi_model); 1105 } 1106 1107 static void aspeed_set_spi_model(Object *obj, const char *value, Error **errp) 1108 { 1109 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1110 1111 g_free(bmc->spi_model); 1112 bmc->spi_model = g_strdup(value); 1113 } 1114 1115 static char *aspeed_get_bmc_console(Object *obj, Error **errp) 1116 { 1117 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1118 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc); 1119 int uart_chosen = bmc->uart_chosen ? bmc->uart_chosen : amc->uart_default; 1120 1121 return g_strdup_printf("uart%d", aspeed_uart_index(uart_chosen)); 1122 } 1123 1124 static void aspeed_set_bmc_console(Object *obj, const char *value, Error **errp) 1125 { 1126 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1127 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc); 1128 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(amc->soc_name)); 1129 int val; 1130 int uart_first = aspeed_uart_first(sc); 1131 int uart_last = aspeed_uart_last(sc); 1132 1133 if (sscanf(value, "uart%u", &val) != 1) { 1134 error_setg(errp, "Bad value for \"uart\" property"); 1135 return; 1136 } 1137 1138 /* The number of UART depends on the SoC */ 1139 if (val < uart_first || val > uart_last) { 1140 error_setg(errp, "\"uart\" should be in range [%d - %d]", 1141 uart_first, uart_last); 1142 return; 1143 } 1144 bmc->uart_chosen = val + ASPEED_DEV_UART0; 1145 } 1146 1147 static void aspeed_machine_class_props_init(ObjectClass *oc) 1148 { 1149 object_class_property_add_bool(oc, "execute-in-place", 1150 aspeed_get_mmio_exec, 1151 aspeed_set_mmio_exec); 1152 object_class_property_set_description(oc, "execute-in-place", 1153 "boot directly from CE0 flash device"); 1154 1155 object_class_property_add_str(oc, "bmc-console", aspeed_get_bmc_console, 1156 aspeed_set_bmc_console); 1157 object_class_property_set_description(oc, "bmc-console", 1158 "Change the default UART to \"uartX\""); 1159 1160 object_class_property_add_str(oc, "fmc-model", aspeed_get_fmc_model, 1161 aspeed_set_fmc_model); 1162 object_class_property_set_description(oc, "fmc-model", 1163 "Change the FMC Flash model"); 1164 object_class_property_add_str(oc, "spi-model", aspeed_get_spi_model, 1165 aspeed_set_spi_model); 1166 object_class_property_set_description(oc, "spi-model", 1167 "Change the SPI Flash model"); 1168 } 1169 1170 static void aspeed_machine_class_init_cpus_defaults(MachineClass *mc) 1171 { 1172 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(mc); 1173 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(amc->soc_name)); 1174 1175 mc->default_cpus = sc->num_cpus; 1176 mc->min_cpus = sc->num_cpus; 1177 mc->max_cpus = sc->num_cpus; 1178 mc->valid_cpu_types = sc->valid_cpu_types; 1179 } 1180 1181 static bool aspeed_machine_ast2600_get_boot_from_emmc(Object *obj, Error **errp) 1182 { 1183 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1184 1185 return !!(bmc->hw_strap1 & SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC); 1186 } 1187 1188 static void aspeed_machine_ast2600_set_boot_from_emmc(Object *obj, bool value, 1189 Error **errp) 1190 { 1191 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1192 1193 if (value) { 1194 bmc->hw_strap1 |= SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC; 1195 } else { 1196 bmc->hw_strap1 &= ~SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC; 1197 } 1198 } 1199 1200 static void aspeed_machine_ast2600_class_emmc_init(ObjectClass *oc) 1201 { 1202 object_class_property_add_bool(oc, "boot-emmc", 1203 aspeed_machine_ast2600_get_boot_from_emmc, 1204 aspeed_machine_ast2600_set_boot_from_emmc); 1205 object_class_property_set_description(oc, "boot-emmc", 1206 "Set or unset boot from EMMC"); 1207 } 1208 1209 static void aspeed_machine_class_init(ObjectClass *oc, void *data) 1210 { 1211 MachineClass *mc = MACHINE_CLASS(oc); 1212 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1213 1214 mc->init = aspeed_machine_init; 1215 mc->no_floppy = 1; 1216 mc->no_cdrom = 1; 1217 mc->no_parallel = 1; 1218 mc->default_ram_id = "ram"; 1219 amc->macs_mask = ASPEED_MAC0_ON; 1220 amc->uart_default = ASPEED_DEV_UART5; 1221 1222 aspeed_machine_class_props_init(oc); 1223 } 1224 1225 static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data) 1226 { 1227 MachineClass *mc = MACHINE_CLASS(oc); 1228 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1229 1230 mc->desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)"; 1231 amc->soc_name = "ast2400-a1"; 1232 amc->hw_strap1 = PALMETTO_BMC_HW_STRAP1; 1233 amc->fmc_model = "n25q256a"; 1234 amc->spi_model = "mx25l25635f"; 1235 amc->num_cs = 1; 1236 amc->i2c_init = palmetto_bmc_i2c_init; 1237 mc->default_ram_size = 256 * MiB; 1238 aspeed_machine_class_init_cpus_defaults(mc); 1239 }; 1240 1241 static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc, void *data) 1242 { 1243 MachineClass *mc = MACHINE_CLASS(oc); 1244 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1245 1246 mc->desc = "Quanta-Q71l BMC (ARM926EJ-S)"; 1247 amc->soc_name = "ast2400-a1"; 1248 amc->hw_strap1 = QUANTA_Q71L_BMC_HW_STRAP1; 1249 amc->fmc_model = "n25q256a"; 1250 amc->spi_model = "mx25l25635e"; 1251 amc->num_cs = 1; 1252 amc->i2c_init = quanta_q71l_bmc_i2c_init; 1253 mc->default_ram_size = 128 * MiB; 1254 aspeed_machine_class_init_cpus_defaults(mc); 1255 } 1256 1257 static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc, 1258 void *data) 1259 { 1260 MachineClass *mc = MACHINE_CLASS(oc); 1261 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1262 1263 mc->desc = "Supermicro X11 BMC (ARM926EJ-S)"; 1264 amc->soc_name = "ast2400-a1"; 1265 amc->hw_strap1 = SUPERMICROX11_BMC_HW_STRAP1; 1266 amc->fmc_model = "mx25l25635e"; 1267 amc->spi_model = "mx25l25635e"; 1268 amc->num_cs = 1; 1269 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1270 amc->i2c_init = palmetto_bmc_i2c_init; 1271 mc->default_ram_size = 256 * MiB; 1272 aspeed_machine_class_init_cpus_defaults(mc); 1273 } 1274 1275 static void aspeed_machine_supermicro_x11spi_bmc_class_init(ObjectClass *oc, 1276 void *data) 1277 { 1278 MachineClass *mc = MACHINE_CLASS(oc); 1279 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1280 1281 mc->desc = "Supermicro X11 SPI BMC (ARM1176)"; 1282 amc->soc_name = "ast2500-a1"; 1283 amc->hw_strap1 = SUPERMICRO_X11SPI_BMC_HW_STRAP1; 1284 amc->fmc_model = "mx25l25635e"; 1285 amc->spi_model = "mx25l25635e"; 1286 amc->num_cs = 1; 1287 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1288 amc->i2c_init = palmetto_bmc_i2c_init; 1289 mc->default_ram_size = 512 * MiB; 1290 aspeed_machine_class_init_cpus_defaults(mc); 1291 } 1292 1293 static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data) 1294 { 1295 MachineClass *mc = MACHINE_CLASS(oc); 1296 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1297 1298 mc->desc = "Aspeed AST2500 EVB (ARM1176)"; 1299 amc->soc_name = "ast2500-a1"; 1300 amc->hw_strap1 = AST2500_EVB_HW_STRAP1; 1301 amc->fmc_model = "mx25l25635e"; 1302 amc->spi_model = "mx25l25635f"; 1303 amc->num_cs = 1; 1304 amc->i2c_init = ast2500_evb_i2c_init; 1305 mc->default_ram_size = 512 * MiB; 1306 aspeed_machine_class_init_cpus_defaults(mc); 1307 }; 1308 1309 static void aspeed_machine_yosemitev2_class_init(ObjectClass *oc, void *data) 1310 { 1311 MachineClass *mc = MACHINE_CLASS(oc); 1312 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1313 1314 mc->desc = "Facebook YosemiteV2 BMC (ARM1176)"; 1315 amc->soc_name = "ast2500-a1"; 1316 amc->hw_strap1 = AST2500_EVB_HW_STRAP1; 1317 amc->hw_strap2 = 0; 1318 amc->fmc_model = "n25q256a"; 1319 amc->spi_model = "mx25l25635e"; 1320 amc->num_cs = 2; 1321 amc->i2c_init = yosemitev2_bmc_i2c_init; 1322 mc->default_ram_size = 512 * MiB; 1323 aspeed_machine_class_init_cpus_defaults(mc); 1324 }; 1325 1326 static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data) 1327 { 1328 MachineClass *mc = MACHINE_CLASS(oc); 1329 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1330 1331 mc->desc = "OpenPOWER Romulus BMC (ARM1176)"; 1332 amc->soc_name = "ast2500-a1"; 1333 amc->hw_strap1 = ROMULUS_BMC_HW_STRAP1; 1334 amc->fmc_model = "n25q256a"; 1335 amc->spi_model = "mx66l1g45g"; 1336 amc->num_cs = 2; 1337 amc->i2c_init = romulus_bmc_i2c_init; 1338 mc->default_ram_size = 512 * MiB; 1339 aspeed_machine_class_init_cpus_defaults(mc); 1340 }; 1341 1342 static void aspeed_machine_tiogapass_class_init(ObjectClass *oc, void *data) 1343 { 1344 MachineClass *mc = MACHINE_CLASS(oc); 1345 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1346 1347 mc->desc = "Facebook Tiogapass BMC (ARM1176)"; 1348 amc->soc_name = "ast2500-a1"; 1349 amc->hw_strap1 = AST2500_EVB_HW_STRAP1; 1350 amc->hw_strap2 = 0; 1351 amc->fmc_model = "n25q256a"; 1352 amc->spi_model = "mx25l25635e"; 1353 amc->num_cs = 2; 1354 amc->i2c_init = tiogapass_bmc_i2c_init; 1355 mc->default_ram_size = 1 * GiB; 1356 aspeed_machine_class_init_cpus_defaults(mc); 1357 }; 1358 1359 static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data) 1360 { 1361 MachineClass *mc = MACHINE_CLASS(oc); 1362 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1363 1364 mc->desc = "OCP SonoraPass BMC (ARM1176)"; 1365 amc->soc_name = "ast2500-a1"; 1366 amc->hw_strap1 = SONORAPASS_BMC_HW_STRAP1; 1367 amc->fmc_model = "mx66l1g45g"; 1368 amc->spi_model = "mx66l1g45g"; 1369 amc->num_cs = 2; 1370 amc->i2c_init = sonorapass_bmc_i2c_init; 1371 mc->default_ram_size = 512 * MiB; 1372 aspeed_machine_class_init_cpus_defaults(mc); 1373 }; 1374 1375 static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data) 1376 { 1377 MachineClass *mc = MACHINE_CLASS(oc); 1378 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1379 1380 mc->desc = "OpenPOWER Witherspoon BMC (ARM1176)"; 1381 amc->soc_name = "ast2500-a1"; 1382 amc->hw_strap1 = WITHERSPOON_BMC_HW_STRAP1; 1383 amc->fmc_model = "mx25l25635f"; 1384 amc->spi_model = "mx66l1g45g"; 1385 amc->num_cs = 2; 1386 amc->i2c_init = witherspoon_bmc_i2c_init; 1387 mc->default_ram_size = 512 * MiB; 1388 aspeed_machine_class_init_cpus_defaults(mc); 1389 }; 1390 1391 static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data) 1392 { 1393 MachineClass *mc = MACHINE_CLASS(oc); 1394 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1395 1396 mc->desc = "Aspeed AST2600 EVB (Cortex-A7)"; 1397 amc->soc_name = "ast2600-a3"; 1398 amc->hw_strap1 = AST2600_EVB_HW_STRAP1; 1399 amc->hw_strap2 = AST2600_EVB_HW_STRAP2; 1400 amc->fmc_model = "mx66u51235f"; 1401 amc->spi_model = "mx66u51235f"; 1402 amc->num_cs = 1; 1403 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON | 1404 ASPEED_MAC3_ON; 1405 amc->i2c_init = ast2600_evb_i2c_init; 1406 mc->default_ram_size = 1 * GiB; 1407 aspeed_machine_class_init_cpus_defaults(mc); 1408 aspeed_machine_ast2600_class_emmc_init(oc); 1409 }; 1410 1411 static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data) 1412 { 1413 MachineClass *mc = MACHINE_CLASS(oc); 1414 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1415 1416 mc->desc = "OpenPOWER Tacoma BMC (Cortex-A7)"; 1417 amc->soc_name = "ast2600-a3"; 1418 amc->hw_strap1 = TACOMA_BMC_HW_STRAP1; 1419 amc->hw_strap2 = TACOMA_BMC_HW_STRAP2; 1420 amc->fmc_model = "mx66l1g45g"; 1421 amc->spi_model = "mx66l1g45g"; 1422 amc->num_cs = 2; 1423 amc->macs_mask = ASPEED_MAC2_ON; 1424 amc->i2c_init = witherspoon_bmc_i2c_init; /* Same board layout */ 1425 mc->default_ram_size = 1 * GiB; 1426 aspeed_machine_class_init_cpus_defaults(mc); 1427 1428 mc->deprecation_reason = "Please use the similar 'rainier-bmc' machine"; 1429 }; 1430 1431 static void aspeed_machine_g220a_class_init(ObjectClass *oc, void *data) 1432 { 1433 MachineClass *mc = MACHINE_CLASS(oc); 1434 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1435 1436 mc->desc = "Bytedance G220A BMC (ARM1176)"; 1437 amc->soc_name = "ast2500-a1"; 1438 amc->hw_strap1 = G220A_BMC_HW_STRAP1; 1439 amc->fmc_model = "n25q512a"; 1440 amc->spi_model = "mx25l25635e"; 1441 amc->num_cs = 2; 1442 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1443 amc->i2c_init = g220a_bmc_i2c_init; 1444 mc->default_ram_size = 1024 * MiB; 1445 aspeed_machine_class_init_cpus_defaults(mc); 1446 }; 1447 1448 static void aspeed_machine_fp5280g2_class_init(ObjectClass *oc, void *data) 1449 { 1450 MachineClass *mc = MACHINE_CLASS(oc); 1451 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1452 1453 mc->desc = "Inspur FP5280G2 BMC (ARM1176)"; 1454 amc->soc_name = "ast2500-a1"; 1455 amc->hw_strap1 = FP5280G2_BMC_HW_STRAP1; 1456 amc->fmc_model = "n25q512a"; 1457 amc->spi_model = "mx25l25635e"; 1458 amc->num_cs = 2; 1459 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1460 amc->i2c_init = fp5280g2_bmc_i2c_init; 1461 mc->default_ram_size = 512 * MiB; 1462 aspeed_machine_class_init_cpus_defaults(mc); 1463 }; 1464 1465 static void aspeed_machine_rainier_class_init(ObjectClass *oc, void *data) 1466 { 1467 MachineClass *mc = MACHINE_CLASS(oc); 1468 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1469 1470 mc->desc = "IBM Rainier BMC (Cortex-A7)"; 1471 amc->soc_name = "ast2600-a3"; 1472 amc->hw_strap1 = RAINIER_BMC_HW_STRAP1; 1473 amc->hw_strap2 = RAINIER_BMC_HW_STRAP2; 1474 amc->fmc_model = "mx66l1g45g"; 1475 amc->spi_model = "mx66l1g45g"; 1476 amc->num_cs = 2; 1477 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON; 1478 amc->i2c_init = rainier_bmc_i2c_init; 1479 mc->default_ram_size = 1 * GiB; 1480 aspeed_machine_class_init_cpus_defaults(mc); 1481 aspeed_machine_ast2600_class_emmc_init(oc); 1482 }; 1483 1484 #define FUJI_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB) 1485 1486 static void aspeed_machine_fuji_class_init(ObjectClass *oc, void *data) 1487 { 1488 MachineClass *mc = MACHINE_CLASS(oc); 1489 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1490 1491 mc->desc = "Facebook Fuji BMC (Cortex-A7)"; 1492 amc->soc_name = "ast2600-a3"; 1493 amc->hw_strap1 = FUJI_BMC_HW_STRAP1; 1494 amc->hw_strap2 = FUJI_BMC_HW_STRAP2; 1495 amc->fmc_model = "mx66l1g45g"; 1496 amc->spi_model = "mx66l1g45g"; 1497 amc->num_cs = 2; 1498 amc->macs_mask = ASPEED_MAC3_ON; 1499 amc->i2c_init = fuji_bmc_i2c_init; 1500 amc->uart_default = ASPEED_DEV_UART1; 1501 mc->default_ram_size = FUJI_BMC_RAM_SIZE; 1502 aspeed_machine_class_init_cpus_defaults(mc); 1503 }; 1504 1505 #define BLETCHLEY_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB) 1506 1507 static void aspeed_machine_bletchley_class_init(ObjectClass *oc, void *data) 1508 { 1509 MachineClass *mc = MACHINE_CLASS(oc); 1510 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1511 1512 mc->desc = "Facebook Bletchley BMC (Cortex-A7)"; 1513 amc->soc_name = "ast2600-a3"; 1514 amc->hw_strap1 = BLETCHLEY_BMC_HW_STRAP1; 1515 amc->hw_strap2 = BLETCHLEY_BMC_HW_STRAP2; 1516 amc->fmc_model = "w25q01jvq"; 1517 amc->spi_model = NULL; 1518 amc->num_cs = 2; 1519 amc->macs_mask = ASPEED_MAC2_ON; 1520 amc->i2c_init = bletchley_bmc_i2c_init; 1521 mc->default_ram_size = BLETCHLEY_BMC_RAM_SIZE; 1522 aspeed_machine_class_init_cpus_defaults(mc); 1523 } 1524 1525 static void fby35_reset(MachineState *state, ShutdownCause reason) 1526 { 1527 AspeedMachineState *bmc = ASPEED_MACHINE(state); 1528 AspeedGPIOState *gpio = &bmc->soc->gpio; 1529 1530 qemu_devices_reset(reason); 1531 1532 /* Board ID: 7 (Class-1, 4 slots) */ 1533 object_property_set_bool(OBJECT(gpio), "gpioV4", true, &error_fatal); 1534 object_property_set_bool(OBJECT(gpio), "gpioV5", true, &error_fatal); 1535 object_property_set_bool(OBJECT(gpio), "gpioV6", true, &error_fatal); 1536 object_property_set_bool(OBJECT(gpio), "gpioV7", false, &error_fatal); 1537 1538 /* Slot presence pins, inverse polarity. (False means present) */ 1539 object_property_set_bool(OBJECT(gpio), "gpioH4", false, &error_fatal); 1540 object_property_set_bool(OBJECT(gpio), "gpioH5", true, &error_fatal); 1541 object_property_set_bool(OBJECT(gpio), "gpioH6", true, &error_fatal); 1542 object_property_set_bool(OBJECT(gpio), "gpioH7", true, &error_fatal); 1543 1544 /* Slot 12v power pins, normal polarity. (True means powered-on) */ 1545 object_property_set_bool(OBJECT(gpio), "gpioB2", true, &error_fatal); 1546 object_property_set_bool(OBJECT(gpio), "gpioB3", false, &error_fatal); 1547 object_property_set_bool(OBJECT(gpio), "gpioB4", false, &error_fatal); 1548 object_property_set_bool(OBJECT(gpio), "gpioB5", false, &error_fatal); 1549 } 1550 1551 static void aspeed_machine_fby35_class_init(ObjectClass *oc, void *data) 1552 { 1553 MachineClass *mc = MACHINE_CLASS(oc); 1554 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1555 1556 mc->desc = "Facebook fby35 BMC (Cortex-A7)"; 1557 mc->reset = fby35_reset; 1558 amc->fmc_model = "mx66l1g45g"; 1559 amc->num_cs = 2; 1560 amc->macs_mask = ASPEED_MAC3_ON; 1561 amc->i2c_init = fby35_i2c_init; 1562 /* FIXME: Replace this macro with something more general */ 1563 mc->default_ram_size = FUJI_BMC_RAM_SIZE; 1564 aspeed_machine_class_init_cpus_defaults(mc); 1565 } 1566 1567 #define AST1030_INTERNAL_FLASH_SIZE (1024 * 1024) 1568 /* Main SYSCLK frequency in Hz (200MHz) */ 1569 #define SYSCLK_FRQ 200000000ULL 1570 1571 static void aspeed_minibmc_machine_init(MachineState *machine) 1572 { 1573 AspeedMachineState *bmc = ASPEED_MACHINE(machine); 1574 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine); 1575 Clock *sysclk; 1576 1577 sysclk = clock_new(OBJECT(machine), "SYSCLK"); 1578 clock_set_hz(sysclk, SYSCLK_FRQ); 1579 1580 bmc->soc = ASPEED_SOC(object_new(amc->soc_name)); 1581 object_property_add_child(OBJECT(machine), "soc", OBJECT(bmc->soc)); 1582 object_unref(OBJECT(bmc->soc)); 1583 qdev_connect_clock_in(DEVICE(bmc->soc), "sysclk", sysclk); 1584 1585 object_property_set_link(OBJECT(bmc->soc), "memory", 1586 OBJECT(get_system_memory()), &error_abort); 1587 connect_serial_hds_to_uarts(bmc); 1588 qdev_realize(DEVICE(bmc->soc), NULL, &error_abort); 1589 1590 aspeed_board_init_flashes(&bmc->soc->fmc, 1591 bmc->fmc_model ? bmc->fmc_model : amc->fmc_model, 1592 amc->num_cs, 1593 0); 1594 1595 aspeed_board_init_flashes(&bmc->soc->spi[0], 1596 bmc->spi_model ? bmc->spi_model : amc->spi_model, 1597 amc->num_cs, amc->num_cs); 1598 1599 aspeed_board_init_flashes(&bmc->soc->spi[1], 1600 bmc->spi_model ? bmc->spi_model : amc->spi_model, 1601 amc->num_cs, (amc->num_cs * 2)); 1602 1603 if (amc->i2c_init) { 1604 amc->i2c_init(bmc); 1605 } 1606 1607 armv7m_load_kernel(ARM_CPU(first_cpu), 1608 machine->kernel_filename, 1609 0, 1610 AST1030_INTERNAL_FLASH_SIZE); 1611 } 1612 1613 static void ast1030_evb_i2c_init(AspeedMachineState *bmc) 1614 { 1615 AspeedSoCState *soc = bmc->soc; 1616 1617 /* U10 24C08 connects to SDA/SCL Group 1 by default */ 1618 uint8_t *eeprom_buf = g_malloc0(32 * 1024); 1619 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, eeprom_buf); 1620 1621 /* U11 LM75 connects to SDA/SCL Group 2 by default */ 1622 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4d); 1623 } 1624 1625 static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc, 1626 void *data) 1627 { 1628 MachineClass *mc = MACHINE_CLASS(oc); 1629 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1630 1631 mc->desc = "Aspeed AST1030 MiniBMC (Cortex-M4)"; 1632 amc->soc_name = "ast1030-a1"; 1633 amc->hw_strap1 = 0; 1634 amc->hw_strap2 = 0; 1635 mc->init = aspeed_minibmc_machine_init; 1636 amc->i2c_init = ast1030_evb_i2c_init; 1637 mc->default_ram_size = 0; 1638 amc->fmc_model = "sst25vf032b"; 1639 amc->spi_model = "sst25vf032b"; 1640 amc->num_cs = 2; 1641 amc->macs_mask = 0; 1642 aspeed_machine_class_init_cpus_defaults(mc); 1643 } 1644 1645 #ifdef TARGET_AARCH64 1646 static void aspeed_machine_ast2700_evb_class_init(ObjectClass *oc, void *data) 1647 { 1648 MachineClass *mc = MACHINE_CLASS(oc); 1649 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1650 1651 mc->desc = "Aspeed AST2700 EVB (Cortex-A35)"; 1652 amc->soc_name = "ast2700-a0"; 1653 amc->hw_strap1 = AST2700_EVB_HW_STRAP1; 1654 amc->hw_strap2 = AST2700_EVB_HW_STRAP2; 1655 amc->fmc_model = "w25q01jvq"; 1656 amc->spi_model = "w25q512jv"; 1657 amc->num_cs = 2; 1658 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON; 1659 amc->uart_default = ASPEED_DEV_UART12; 1660 mc->default_ram_size = 1 * GiB; 1661 aspeed_machine_class_init_cpus_defaults(mc); 1662 } 1663 #endif 1664 1665 static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc, 1666 void *data) 1667 { 1668 MachineClass *mc = MACHINE_CLASS(oc); 1669 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1670 1671 mc->desc = "Qualcomm DC-SCM V1 BMC (Cortex A7)"; 1672 amc->soc_name = "ast2600-a3"; 1673 amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1; 1674 amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2; 1675 amc->fmc_model = "n25q512a"; 1676 amc->spi_model = "n25q512a"; 1677 amc->num_cs = 2; 1678 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON; 1679 amc->i2c_init = qcom_dc_scm_bmc_i2c_init; 1680 mc->default_ram_size = 1 * GiB; 1681 aspeed_machine_class_init_cpus_defaults(mc); 1682 }; 1683 1684 static void aspeed_machine_qcom_firework_class_init(ObjectClass *oc, 1685 void *data) 1686 { 1687 MachineClass *mc = MACHINE_CLASS(oc); 1688 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1689 1690 mc->desc = "Qualcomm DC-SCM V1/Firework BMC (Cortex A7)"; 1691 amc->soc_name = "ast2600-a3"; 1692 amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1; 1693 amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2; 1694 amc->fmc_model = "n25q512a"; 1695 amc->spi_model = "n25q512a"; 1696 amc->num_cs = 2; 1697 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON; 1698 amc->i2c_init = qcom_dc_scm_firework_i2c_init; 1699 mc->default_ram_size = 1 * GiB; 1700 aspeed_machine_class_init_cpus_defaults(mc); 1701 }; 1702 1703 static const TypeInfo aspeed_machine_types[] = { 1704 { 1705 .name = MACHINE_TYPE_NAME("palmetto-bmc"), 1706 .parent = TYPE_ASPEED_MACHINE, 1707 .class_init = aspeed_machine_palmetto_class_init, 1708 }, { 1709 .name = MACHINE_TYPE_NAME("supermicrox11-bmc"), 1710 .parent = TYPE_ASPEED_MACHINE, 1711 .class_init = aspeed_machine_supermicrox11_bmc_class_init, 1712 }, { 1713 .name = MACHINE_TYPE_NAME("supermicro-x11spi-bmc"), 1714 .parent = TYPE_ASPEED_MACHINE, 1715 .class_init = aspeed_machine_supermicro_x11spi_bmc_class_init, 1716 }, { 1717 .name = MACHINE_TYPE_NAME("ast2500-evb"), 1718 .parent = TYPE_ASPEED_MACHINE, 1719 .class_init = aspeed_machine_ast2500_evb_class_init, 1720 }, { 1721 .name = MACHINE_TYPE_NAME("romulus-bmc"), 1722 .parent = TYPE_ASPEED_MACHINE, 1723 .class_init = aspeed_machine_romulus_class_init, 1724 }, { 1725 .name = MACHINE_TYPE_NAME("sonorapass-bmc"), 1726 .parent = TYPE_ASPEED_MACHINE, 1727 .class_init = aspeed_machine_sonorapass_class_init, 1728 }, { 1729 .name = MACHINE_TYPE_NAME("witherspoon-bmc"), 1730 .parent = TYPE_ASPEED_MACHINE, 1731 .class_init = aspeed_machine_witherspoon_class_init, 1732 }, { 1733 .name = MACHINE_TYPE_NAME("ast2600-evb"), 1734 .parent = TYPE_ASPEED_MACHINE, 1735 .class_init = aspeed_machine_ast2600_evb_class_init, 1736 }, { 1737 .name = MACHINE_TYPE_NAME("yosemitev2-bmc"), 1738 .parent = TYPE_ASPEED_MACHINE, 1739 .class_init = aspeed_machine_yosemitev2_class_init, 1740 }, { 1741 .name = MACHINE_TYPE_NAME("tacoma-bmc"), 1742 .parent = TYPE_ASPEED_MACHINE, 1743 .class_init = aspeed_machine_tacoma_class_init, 1744 }, { 1745 .name = MACHINE_TYPE_NAME("tiogapass-bmc"), 1746 .parent = TYPE_ASPEED_MACHINE, 1747 .class_init = aspeed_machine_tiogapass_class_init, 1748 }, { 1749 .name = MACHINE_TYPE_NAME("g220a-bmc"), 1750 .parent = TYPE_ASPEED_MACHINE, 1751 .class_init = aspeed_machine_g220a_class_init, 1752 }, { 1753 .name = MACHINE_TYPE_NAME("qcom-dc-scm-v1-bmc"), 1754 .parent = TYPE_ASPEED_MACHINE, 1755 .class_init = aspeed_machine_qcom_dc_scm_v1_class_init, 1756 }, { 1757 .name = MACHINE_TYPE_NAME("qcom-firework-bmc"), 1758 .parent = TYPE_ASPEED_MACHINE, 1759 .class_init = aspeed_machine_qcom_firework_class_init, 1760 }, { 1761 .name = MACHINE_TYPE_NAME("fp5280g2-bmc"), 1762 .parent = TYPE_ASPEED_MACHINE, 1763 .class_init = aspeed_machine_fp5280g2_class_init, 1764 }, { 1765 .name = MACHINE_TYPE_NAME("quanta-q71l-bmc"), 1766 .parent = TYPE_ASPEED_MACHINE, 1767 .class_init = aspeed_machine_quanta_q71l_class_init, 1768 }, { 1769 .name = MACHINE_TYPE_NAME("rainier-bmc"), 1770 .parent = TYPE_ASPEED_MACHINE, 1771 .class_init = aspeed_machine_rainier_class_init, 1772 }, { 1773 .name = MACHINE_TYPE_NAME("fuji-bmc"), 1774 .parent = TYPE_ASPEED_MACHINE, 1775 .class_init = aspeed_machine_fuji_class_init, 1776 }, { 1777 .name = MACHINE_TYPE_NAME("bletchley-bmc"), 1778 .parent = TYPE_ASPEED_MACHINE, 1779 .class_init = aspeed_machine_bletchley_class_init, 1780 }, { 1781 .name = MACHINE_TYPE_NAME("fby35-bmc"), 1782 .parent = MACHINE_TYPE_NAME("ast2600-evb"), 1783 .class_init = aspeed_machine_fby35_class_init, 1784 }, { 1785 .name = MACHINE_TYPE_NAME("ast1030-evb"), 1786 .parent = TYPE_ASPEED_MACHINE, 1787 .class_init = aspeed_minibmc_machine_ast1030_evb_class_init, 1788 #ifdef TARGET_AARCH64 1789 }, { 1790 .name = MACHINE_TYPE_NAME("ast2700-evb"), 1791 .parent = TYPE_ASPEED_MACHINE, 1792 .class_init = aspeed_machine_ast2700_evb_class_init, 1793 #endif 1794 }, { 1795 .name = TYPE_ASPEED_MACHINE, 1796 .parent = TYPE_MACHINE, 1797 .instance_size = sizeof(AspeedMachineState), 1798 .instance_init = aspeed_machine_instance_init, 1799 .class_size = sizeof(AspeedMachineClass), 1800 .class_init = aspeed_machine_class_init, 1801 .abstract = true, 1802 } 1803 }; 1804 1805 DEFINE_TYPES(aspeed_machine_types) 1806