1 /* 2 * Arm SSE (Subsystems for Embedded): IoTKit 3 * 4 * Copyright (c) 2018 Linaro Limited 5 * Written by Peter Maydell 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 or 9 * (at your option) any later version. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qemu/log.h" 14 #include "qemu/module.h" 15 #include "qemu/bitops.h" 16 #include "qapi/error.h" 17 #include "trace.h" 18 #include "hw/sysbus.h" 19 #include "migration/vmstate.h" 20 #include "hw/registerfields.h" 21 #include "hw/arm/armsse.h" 22 #include "hw/arm/armsse-version.h" 23 #include "hw/arm/boot.h" 24 #include "hw/irq.h" 25 #include "hw/qdev-clock.h" 26 27 struct ARMSSEInfo { 28 const char *name; 29 uint32_t sse_version; 30 int sram_banks; 31 int num_cpus; 32 uint32_t sys_version; 33 uint32_t cpuwait_rst; 34 bool has_mhus; 35 bool has_ppus; 36 bool has_cachectrl; 37 bool has_cpusecctrl; 38 bool has_cpuid; 39 Property *props; 40 }; 41 42 static Property iotkit_properties[] = { 43 DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION, 44 MemoryRegion *), 45 DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64), 46 DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15), 47 DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000), 48 DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true), 49 DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], true), 50 DEFINE_PROP_END_OF_LIST() 51 }; 52 53 static Property armsse_properties[] = { 54 DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION, 55 MemoryRegion *), 56 DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64), 57 DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15), 58 DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000), 59 DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], false), 60 DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], false), 61 DEFINE_PROP_BOOL("CPU1_FPU", ARMSSE, cpu_fpu[1], true), 62 DEFINE_PROP_BOOL("CPU1_DSP", ARMSSE, cpu_dsp[1], true), 63 DEFINE_PROP_END_OF_LIST() 64 }; 65 66 static const ARMSSEInfo armsse_variants[] = { 67 { 68 .name = TYPE_IOTKIT, 69 .sse_version = ARMSSE_IOTKIT, 70 .sram_banks = 1, 71 .num_cpus = 1, 72 .sys_version = 0x41743, 73 .cpuwait_rst = 0, 74 .has_mhus = false, 75 .has_ppus = false, 76 .has_cachectrl = false, 77 .has_cpusecctrl = false, 78 .has_cpuid = false, 79 .props = iotkit_properties, 80 }, 81 { 82 .name = TYPE_SSE200, 83 .sse_version = ARMSSE_SSE200, 84 .sram_banks = 4, 85 .num_cpus = 2, 86 .sys_version = 0x22041743, 87 .cpuwait_rst = 2, 88 .has_mhus = true, 89 .has_ppus = true, 90 .has_cachectrl = true, 91 .has_cpusecctrl = true, 92 .has_cpuid = true, 93 .props = armsse_properties, 94 }, 95 }; 96 97 static uint32_t armsse_sys_config_value(ARMSSE *s, const ARMSSEInfo *info) 98 { 99 /* Return the SYS_CONFIG value for this SSE */ 100 uint32_t sys_config; 101 102 switch (info->sse_version) { 103 case ARMSSE_IOTKIT: 104 sys_config = 0; 105 sys_config = deposit32(sys_config, 0, 4, info->sram_banks); 106 sys_config = deposit32(sys_config, 4, 4, s->sram_addr_width - 12); 107 break; 108 case ARMSSE_SSE200: 109 sys_config = 0; 110 sys_config = deposit32(sys_config, 0, 4, info->sram_banks); 111 sys_config = deposit32(sys_config, 4, 5, s->sram_addr_width); 112 sys_config = deposit32(sys_config, 24, 4, 2); 113 if (info->num_cpus > 1) { 114 sys_config = deposit32(sys_config, 10, 1, 1); 115 sys_config = deposit32(sys_config, 20, 4, info->sram_banks - 1); 116 sys_config = deposit32(sys_config, 28, 4, 2); 117 } 118 break; 119 case ARMSSE_SSE300: 120 sys_config = 0; 121 sys_config = deposit32(sys_config, 0, 4, info->sram_banks); 122 sys_config = deposit32(sys_config, 4, 5, s->sram_addr_width); 123 sys_config = deposit32(sys_config, 16, 3, 3); /* CPU0 = Cortex-M55 */ 124 break; 125 default: 126 g_assert_not_reached(); 127 } 128 return sys_config; 129 } 130 131 /* Clock frequency in HZ of the 32KHz "slow clock" */ 132 #define S32KCLK (32 * 1000) 133 134 /* Is internal IRQ n shared between CPUs in a multi-core SSE ? */ 135 static bool irq_is_common[32] = { 136 [0 ... 5] = true, 137 /* 6, 7: per-CPU MHU interrupts */ 138 [8 ... 12] = true, 139 /* 13: per-CPU icache interrupt */ 140 /* 14: reserved */ 141 [15 ... 20] = true, 142 /* 21: reserved */ 143 [22 ... 26] = true, 144 /* 27: reserved */ 145 /* 28, 29: per-CPU CTI interrupts */ 146 /* 30, 31: reserved */ 147 }; 148 149 /* 150 * Create an alias region in @container of @size bytes starting at @base 151 * which mirrors the memory starting at @orig. 152 */ 153 static void make_alias(ARMSSE *s, MemoryRegion *mr, MemoryRegion *container, 154 const char *name, hwaddr base, hwaddr size, hwaddr orig) 155 { 156 memory_region_init_alias(mr, NULL, name, container, orig, size); 157 /* The alias is even lower priority than unimplemented_device regions */ 158 memory_region_add_subregion_overlap(container, base, mr, -1500); 159 } 160 161 static void irq_status_forwarder(void *opaque, int n, int level) 162 { 163 qemu_irq destirq = opaque; 164 165 qemu_set_irq(destirq, level); 166 } 167 168 static void nsccfg_handler(void *opaque, int n, int level) 169 { 170 ARMSSE *s = ARM_SSE(opaque); 171 172 s->nsccfg = level; 173 } 174 175 static void armsse_forward_ppc(ARMSSE *s, const char *ppcname, int ppcnum) 176 { 177 /* Each of the 4 AHB and 4 APB PPCs that might be present in a 178 * system using the ARMSSE has a collection of control lines which 179 * are provided by the security controller and which we want to 180 * expose as control lines on the ARMSSE device itself, so the 181 * code using the ARMSSE can wire them up to the PPCs. 182 */ 183 SplitIRQ *splitter = &s->ppc_irq_splitter[ppcnum]; 184 DeviceState *armssedev = DEVICE(s); 185 DeviceState *dev_secctl = DEVICE(&s->secctl); 186 DeviceState *dev_splitter = DEVICE(splitter); 187 char *name; 188 189 name = g_strdup_printf("%s_nonsec", ppcname); 190 qdev_pass_gpios(dev_secctl, armssedev, name); 191 g_free(name); 192 name = g_strdup_printf("%s_ap", ppcname); 193 qdev_pass_gpios(dev_secctl, armssedev, name); 194 g_free(name); 195 name = g_strdup_printf("%s_irq_enable", ppcname); 196 qdev_pass_gpios(dev_secctl, armssedev, name); 197 g_free(name); 198 name = g_strdup_printf("%s_irq_clear", ppcname); 199 qdev_pass_gpios(dev_secctl, armssedev, name); 200 g_free(name); 201 202 /* irq_status is a little more tricky, because we need to 203 * split it so we can send it both to the security controller 204 * and to our OR gate for the NVIC interrupt line. 205 * Connect up the splitter's outputs, and create a GPIO input 206 * which will pass the line state to the input splitter. 207 */ 208 name = g_strdup_printf("%s_irq_status", ppcname); 209 qdev_connect_gpio_out(dev_splitter, 0, 210 qdev_get_gpio_in_named(dev_secctl, 211 name, 0)); 212 qdev_connect_gpio_out(dev_splitter, 1, 213 qdev_get_gpio_in(DEVICE(&s->ppc_irq_orgate), ppcnum)); 214 s->irq_status_in[ppcnum] = qdev_get_gpio_in(dev_splitter, 0); 215 qdev_init_gpio_in_named_with_opaque(armssedev, irq_status_forwarder, 216 s->irq_status_in[ppcnum], name, 1); 217 g_free(name); 218 } 219 220 static void armsse_forward_sec_resp_cfg(ARMSSE *s) 221 { 222 /* Forward the 3rd output from the splitter device as a 223 * named GPIO output of the armsse object. 224 */ 225 DeviceState *dev = DEVICE(s); 226 DeviceState *dev_splitter = DEVICE(&s->sec_resp_splitter); 227 228 qdev_init_gpio_out_named(dev, &s->sec_resp_cfg, "sec_resp_cfg", 1); 229 s->sec_resp_cfg_in = qemu_allocate_irq(irq_status_forwarder, 230 s->sec_resp_cfg, 1); 231 qdev_connect_gpio_out(dev_splitter, 2, s->sec_resp_cfg_in); 232 } 233 234 static void armsse_mainclk_update(void *opaque, ClockEvent event) 235 { 236 ARMSSE *s = ARM_SSE(opaque); 237 238 /* 239 * Set system_clock_scale from our Clock input; this is what 240 * controls the tick rate of the CPU SysTick timer. 241 */ 242 system_clock_scale = clock_ticks_to_ns(s->mainclk, 1); 243 } 244 245 static void armsse_init(Object *obj) 246 { 247 ARMSSE *s = ARM_SSE(obj); 248 ARMSSEClass *asc = ARM_SSE_GET_CLASS(obj); 249 const ARMSSEInfo *info = asc->info; 250 int i; 251 252 assert(info->sram_banks <= MAX_SRAM_BANKS); 253 assert(info->num_cpus <= SSE_MAX_CPUS); 254 255 s->mainclk = qdev_init_clock_in(DEVICE(s), "MAINCLK", 256 armsse_mainclk_update, s, ClockUpdate); 257 s->s32kclk = qdev_init_clock_in(DEVICE(s), "S32KCLK", NULL, NULL, 0); 258 259 memory_region_init(&s->container, obj, "armsse-container", UINT64_MAX); 260 261 for (i = 0; i < info->num_cpus; i++) { 262 /* 263 * We put each CPU in its own cluster as they are logically 264 * distinct and may be configured differently. 265 */ 266 char *name; 267 268 name = g_strdup_printf("cluster%d", i); 269 object_initialize_child(obj, name, &s->cluster[i], TYPE_CPU_CLUSTER); 270 qdev_prop_set_uint32(DEVICE(&s->cluster[i]), "cluster-id", i); 271 g_free(name); 272 273 name = g_strdup_printf("armv7m%d", i); 274 object_initialize_child(OBJECT(&s->cluster[i]), name, &s->armv7m[i], 275 TYPE_ARMV7M); 276 qdev_prop_set_string(DEVICE(&s->armv7m[i]), "cpu-type", 277 ARM_CPU_TYPE_NAME("cortex-m33")); 278 g_free(name); 279 name = g_strdup_printf("arm-sse-cpu-container%d", i); 280 memory_region_init(&s->cpu_container[i], obj, name, UINT64_MAX); 281 g_free(name); 282 if (i > 0) { 283 name = g_strdup_printf("arm-sse-container-alias%d", i); 284 memory_region_init_alias(&s->container_alias[i - 1], obj, 285 name, &s->container, 0, UINT64_MAX); 286 g_free(name); 287 } 288 } 289 290 object_initialize_child(obj, "secctl", &s->secctl, TYPE_IOTKIT_SECCTL); 291 object_initialize_child(obj, "apb-ppc0", &s->apb_ppc0, TYPE_TZ_PPC); 292 object_initialize_child(obj, "apb-ppc1", &s->apb_ppc1, TYPE_TZ_PPC); 293 for (i = 0; i < info->sram_banks; i++) { 294 char *name = g_strdup_printf("mpc%d", i); 295 object_initialize_child(obj, name, &s->mpc[i], TYPE_TZ_MPC); 296 g_free(name); 297 } 298 object_initialize_child(obj, "mpc-irq-orgate", &s->mpc_irq_orgate, 299 TYPE_OR_IRQ); 300 301 for (i = 0; i < IOTS_NUM_EXP_MPC + info->sram_banks; i++) { 302 char *name = g_strdup_printf("mpc-irq-splitter-%d", i); 303 SplitIRQ *splitter = &s->mpc_irq_splitter[i]; 304 305 object_initialize_child(obj, name, splitter, TYPE_SPLIT_IRQ); 306 g_free(name); 307 } 308 object_initialize_child(obj, "timer0", &s->timer0, TYPE_CMSDK_APB_TIMER); 309 object_initialize_child(obj, "timer1", &s->timer1, TYPE_CMSDK_APB_TIMER); 310 object_initialize_child(obj, "s32ktimer", &s->s32ktimer, 311 TYPE_CMSDK_APB_TIMER); 312 object_initialize_child(obj, "dualtimer", &s->dualtimer, 313 TYPE_CMSDK_APB_DUALTIMER); 314 object_initialize_child(obj, "s32kwatchdog", &s->s32kwatchdog, 315 TYPE_CMSDK_APB_WATCHDOG); 316 object_initialize_child(obj, "nswatchdog", &s->nswatchdog, 317 TYPE_CMSDK_APB_WATCHDOG); 318 object_initialize_child(obj, "swatchdog", &s->swatchdog, 319 TYPE_CMSDK_APB_WATCHDOG); 320 object_initialize_child(obj, "armsse-sysctl", &s->sysctl, 321 TYPE_IOTKIT_SYSCTL); 322 object_initialize_child(obj, "armsse-sysinfo", &s->sysinfo, 323 TYPE_IOTKIT_SYSINFO); 324 if (info->has_mhus) { 325 object_initialize_child(obj, "mhu0", &s->mhu[0], TYPE_ARMSSE_MHU); 326 object_initialize_child(obj, "mhu1", &s->mhu[1], TYPE_ARMSSE_MHU); 327 } 328 if (info->has_ppus) { 329 for (i = 0; i < info->num_cpus; i++) { 330 char *name = g_strdup_printf("CPU%dCORE_PPU", i); 331 int ppuidx = CPU0CORE_PPU + i; 332 333 object_initialize_child(obj, name, &s->ppu[ppuidx], 334 TYPE_UNIMPLEMENTED_DEVICE); 335 g_free(name); 336 } 337 object_initialize_child(obj, "DBG_PPU", &s->ppu[DBG_PPU], 338 TYPE_UNIMPLEMENTED_DEVICE); 339 for (i = 0; i < info->sram_banks; i++) { 340 char *name = g_strdup_printf("RAM%d_PPU", i); 341 int ppuidx = RAM0_PPU + i; 342 343 object_initialize_child(obj, name, &s->ppu[ppuidx], 344 TYPE_UNIMPLEMENTED_DEVICE); 345 g_free(name); 346 } 347 } 348 if (info->has_cachectrl) { 349 for (i = 0; i < info->num_cpus; i++) { 350 char *name = g_strdup_printf("cachectrl%d", i); 351 352 object_initialize_child(obj, name, &s->cachectrl[i], 353 TYPE_UNIMPLEMENTED_DEVICE); 354 g_free(name); 355 } 356 } 357 if (info->has_cpusecctrl) { 358 for (i = 0; i < info->num_cpus; i++) { 359 char *name = g_strdup_printf("cpusecctrl%d", i); 360 361 object_initialize_child(obj, name, &s->cpusecctrl[i], 362 TYPE_UNIMPLEMENTED_DEVICE); 363 g_free(name); 364 } 365 } 366 if (info->has_cpuid) { 367 for (i = 0; i < info->num_cpus; i++) { 368 char *name = g_strdup_printf("cpuid%d", i); 369 370 object_initialize_child(obj, name, &s->cpuid[i], 371 TYPE_ARMSSE_CPUID); 372 g_free(name); 373 } 374 } 375 object_initialize_child(obj, "nmi-orgate", &s->nmi_orgate, TYPE_OR_IRQ); 376 object_initialize_child(obj, "ppc-irq-orgate", &s->ppc_irq_orgate, 377 TYPE_OR_IRQ); 378 object_initialize_child(obj, "sec-resp-splitter", &s->sec_resp_splitter, 379 TYPE_SPLIT_IRQ); 380 for (i = 0; i < ARRAY_SIZE(s->ppc_irq_splitter); i++) { 381 char *name = g_strdup_printf("ppc-irq-splitter-%d", i); 382 SplitIRQ *splitter = &s->ppc_irq_splitter[i]; 383 384 object_initialize_child(obj, name, splitter, TYPE_SPLIT_IRQ); 385 g_free(name); 386 } 387 if (info->num_cpus > 1) { 388 for (i = 0; i < ARRAY_SIZE(s->cpu_irq_splitter); i++) { 389 if (irq_is_common[i]) { 390 char *name = g_strdup_printf("cpu-irq-splitter%d", i); 391 SplitIRQ *splitter = &s->cpu_irq_splitter[i]; 392 393 object_initialize_child(obj, name, splitter, TYPE_SPLIT_IRQ); 394 g_free(name); 395 } 396 } 397 } 398 } 399 400 static void armsse_exp_irq(void *opaque, int n, int level) 401 { 402 qemu_irq *irqarray = opaque; 403 404 qemu_set_irq(irqarray[n], level); 405 } 406 407 static void armsse_mpcexp_status(void *opaque, int n, int level) 408 { 409 ARMSSE *s = ARM_SSE(opaque); 410 qemu_set_irq(s->mpcexp_status_in[n], level); 411 } 412 413 static qemu_irq armsse_get_common_irq_in(ARMSSE *s, int irqno) 414 { 415 /* 416 * Return a qemu_irq which can be used to signal IRQ n to 417 * all CPUs in the SSE. 418 */ 419 ARMSSEClass *asc = ARM_SSE_GET_CLASS(s); 420 const ARMSSEInfo *info = asc->info; 421 422 assert(irq_is_common[irqno]); 423 424 if (info->num_cpus == 1) { 425 /* Only one CPU -- just connect directly to it */ 426 return qdev_get_gpio_in(DEVICE(&s->armv7m[0]), irqno); 427 } else { 428 /* Connect to the splitter which feeds all CPUs */ 429 return qdev_get_gpio_in(DEVICE(&s->cpu_irq_splitter[irqno]), 0); 430 } 431 } 432 433 static void map_ppu(ARMSSE *s, int ppuidx, const char *name, hwaddr addr) 434 { 435 /* Map a PPU unimplemented device stub */ 436 DeviceState *dev = DEVICE(&s->ppu[ppuidx]); 437 438 qdev_prop_set_string(dev, "name", name); 439 qdev_prop_set_uint64(dev, "size", 0x1000); 440 sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal); 441 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ppu[ppuidx]), 0, addr); 442 } 443 444 static void armsse_realize(DeviceState *dev, Error **errp) 445 { 446 ARMSSE *s = ARM_SSE(dev); 447 ARMSSEClass *asc = ARM_SSE_GET_CLASS(dev); 448 const ARMSSEInfo *info = asc->info; 449 int i; 450 MemoryRegion *mr; 451 Error *err = NULL; 452 SysBusDevice *sbd_apb_ppc0; 453 SysBusDevice *sbd_secctl; 454 DeviceState *dev_apb_ppc0; 455 DeviceState *dev_apb_ppc1; 456 DeviceState *dev_secctl; 457 DeviceState *dev_splitter; 458 uint32_t addr_width_max; 459 460 if (!s->board_memory) { 461 error_setg(errp, "memory property was not set"); 462 return; 463 } 464 465 if (!clock_has_source(s->mainclk)) { 466 error_setg(errp, "MAINCLK clock was not connected"); 467 } 468 if (!clock_has_source(s->s32kclk)) { 469 error_setg(errp, "S32KCLK clock was not connected"); 470 } 471 472 assert(info->num_cpus <= SSE_MAX_CPUS); 473 474 /* max SRAM_ADDR_WIDTH: 24 - log2(SRAM_NUM_BANK) */ 475 assert(is_power_of_2(info->sram_banks)); 476 addr_width_max = 24 - ctz32(info->sram_banks); 477 if (s->sram_addr_width < 1 || s->sram_addr_width > addr_width_max) { 478 error_setg(errp, "SRAM_ADDR_WIDTH must be between 1 and %d", 479 addr_width_max); 480 return; 481 } 482 483 /* Handling of which devices should be available only to secure 484 * code is usually done differently for M profile than for A profile. 485 * Instead of putting some devices only into the secure address space, 486 * devices exist in both address spaces but with hard-wired security 487 * permissions that will cause the CPU to fault for non-secure accesses. 488 * 489 * The ARMSSE has an IDAU (Implementation Defined Access Unit), 490 * which specifies hard-wired security permissions for different 491 * areas of the physical address space. For the ARMSSE IDAU, the 492 * top 4 bits of the physical address are the IDAU region ID, and 493 * if bit 28 (ie the lowest bit of the ID) is 0 then this is an NS 494 * region, otherwise it is an S region. 495 * 496 * The various devices and RAMs are generally all mapped twice, 497 * once into a region that the IDAU defines as secure and once 498 * into a non-secure region. They sit behind either a Memory 499 * Protection Controller (for RAM) or a Peripheral Protection 500 * Controller (for devices), which allow a more fine grained 501 * configuration of whether non-secure accesses are permitted. 502 * 503 * (The other place that guest software can configure security 504 * permissions is in the architected SAU (Security Attribution 505 * Unit), which is entirely inside the CPU. The IDAU can upgrade 506 * the security attributes for a region to more restrictive than 507 * the SAU specifies, but cannot downgrade them.) 508 * 509 * 0x10000000..0x1fffffff alias of 0x00000000..0x0fffffff 510 * 0x20000000..0x2007ffff 32KB FPGA block RAM 511 * 0x30000000..0x3fffffff alias of 0x20000000..0x2fffffff 512 * 0x40000000..0x4000ffff base peripheral region 1 513 * 0x40010000..0x4001ffff CPU peripherals (none for ARMSSE) 514 * 0x40020000..0x4002ffff system control element peripherals 515 * 0x40080000..0x400fffff base peripheral region 2 516 * 0x50000000..0x5fffffff alias of 0x40000000..0x4fffffff 517 */ 518 519 memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -2); 520 521 for (i = 0; i < info->num_cpus; i++) { 522 DeviceState *cpudev = DEVICE(&s->armv7m[i]); 523 Object *cpuobj = OBJECT(&s->armv7m[i]); 524 int j; 525 char *gpioname; 526 527 qdev_prop_set_uint32(cpudev, "num-irq", s->exp_numirq + 32); 528 /* 529 * In real hardware the initial Secure VTOR is set from the INITSVTOR* 530 * registers in the IoT Kit System Control Register block. In QEMU 531 * we set the initial value here, and also the reset value of the 532 * sysctl register, from this object's QOM init-svtor property. 533 * If the guest changes the INITSVTOR* registers at runtime then the 534 * code in iotkit-sysctl.c will update the CPU init-svtor property 535 * (which will then take effect on the next CPU warm-reset). 536 * 537 * Note that typically a board using the SSE-200 will have a system 538 * control processor whose boot firmware initializes the INITSVTOR* 539 * registers before powering up the CPUs. QEMU doesn't emulate 540 * the control processor, so instead we behave in the way that the 541 * firmware does: the initial value should be set by the board code 542 * (using the init-svtor property on the ARMSSE object) to match 543 * whatever its firmware does. 544 */ 545 qdev_prop_set_uint32(cpudev, "init-svtor", s->init_svtor); 546 /* 547 * CPUs start powered down if the corresponding bit in the CPUWAIT 548 * register is 1. In real hardware the CPUWAIT register reset value is 549 * a configurable property of the SSE-200 (via the CPUWAIT0_RST and 550 * CPUWAIT1_RST parameters), but since all the boards we care about 551 * start CPU0 and leave CPU1 powered off, we hard-code that in 552 * info->cpuwait_rst for now. We can add QOM properties for this 553 * later if necessary. 554 */ 555 if (extract32(info->cpuwait_rst, i, 1)) { 556 if (!object_property_set_bool(cpuobj, "start-powered-off", true, 557 errp)) { 558 return; 559 } 560 } 561 if (!s->cpu_fpu[i]) { 562 if (!object_property_set_bool(cpuobj, "vfp", false, errp)) { 563 return; 564 } 565 } 566 if (!s->cpu_dsp[i]) { 567 if (!object_property_set_bool(cpuobj, "dsp", false, errp)) { 568 return; 569 } 570 } 571 572 if (i > 0) { 573 memory_region_add_subregion_overlap(&s->cpu_container[i], 0, 574 &s->container_alias[i - 1], -1); 575 } else { 576 memory_region_add_subregion_overlap(&s->cpu_container[i], 0, 577 &s->container, -1); 578 } 579 object_property_set_link(cpuobj, "memory", 580 OBJECT(&s->cpu_container[i]), &error_abort); 581 object_property_set_link(cpuobj, "idau", OBJECT(s), &error_abort); 582 if (!sysbus_realize(SYS_BUS_DEVICE(cpuobj), errp)) { 583 return; 584 } 585 /* 586 * The cluster must be realized after the armv7m container, as 587 * the container's CPU object is only created on realize, and the 588 * CPU must exist and have been parented into the cluster before 589 * the cluster is realized. 590 */ 591 if (!qdev_realize(DEVICE(&s->cluster[i]), NULL, errp)) { 592 return; 593 } 594 595 /* Connect EXP_IRQ/EXP_CPUn_IRQ GPIOs to the NVIC's lines 32 and up */ 596 s->exp_irqs[i] = g_new(qemu_irq, s->exp_numirq); 597 for (j = 0; j < s->exp_numirq; j++) { 598 s->exp_irqs[i][j] = qdev_get_gpio_in(cpudev, j + 32); 599 } 600 if (i == 0) { 601 gpioname = g_strdup("EXP_IRQ"); 602 } else { 603 gpioname = g_strdup_printf("EXP_CPU%d_IRQ", i); 604 } 605 qdev_init_gpio_in_named_with_opaque(dev, armsse_exp_irq, 606 s->exp_irqs[i], 607 gpioname, s->exp_numirq); 608 g_free(gpioname); 609 } 610 611 /* Wire up the splitters that connect common IRQs to all CPUs */ 612 if (info->num_cpus > 1) { 613 for (i = 0; i < ARRAY_SIZE(s->cpu_irq_splitter); i++) { 614 if (irq_is_common[i]) { 615 Object *splitter = OBJECT(&s->cpu_irq_splitter[i]); 616 DeviceState *devs = DEVICE(splitter); 617 int cpunum; 618 619 if (!object_property_set_int(splitter, "num-lines", 620 info->num_cpus, errp)) { 621 return; 622 } 623 if (!qdev_realize(DEVICE(splitter), NULL, errp)) { 624 return; 625 } 626 for (cpunum = 0; cpunum < info->num_cpus; cpunum++) { 627 DeviceState *cpudev = DEVICE(&s->armv7m[cpunum]); 628 629 qdev_connect_gpio_out(devs, cpunum, 630 qdev_get_gpio_in(cpudev, i)); 631 } 632 } 633 } 634 } 635 636 /* Set up the big aliases first */ 637 make_alias(s, &s->alias1, &s->container, "alias 1", 638 0x10000000, 0x10000000, 0x00000000); 639 make_alias(s, &s->alias2, &s->container, 640 "alias 2", 0x30000000, 0x10000000, 0x20000000); 641 /* The 0x50000000..0x5fffffff region is not a pure alias: it has 642 * a few extra devices that only appear there (generally the 643 * control interfaces for the protection controllers). 644 * We implement this by mapping those devices over the top of this 645 * alias MR at a higher priority. Some of the devices in this range 646 * are per-CPU, so we must put this alias in the per-cpu containers. 647 */ 648 for (i = 0; i < info->num_cpus; i++) { 649 make_alias(s, &s->alias3[i], &s->cpu_container[i], 650 "alias 3", 0x50000000, 0x10000000, 0x40000000); 651 } 652 653 /* Security controller */ 654 object_property_set_int(OBJECT(&s->secctl), "sse-version", 655 info->sse_version, &error_abort); 656 if (!sysbus_realize(SYS_BUS_DEVICE(&s->secctl), errp)) { 657 return; 658 } 659 sbd_secctl = SYS_BUS_DEVICE(&s->secctl); 660 dev_secctl = DEVICE(&s->secctl); 661 sysbus_mmio_map(sbd_secctl, 0, 0x50080000); 662 sysbus_mmio_map(sbd_secctl, 1, 0x40080000); 663 664 s->nsc_cfg_in = qemu_allocate_irq(nsccfg_handler, s, 1); 665 qdev_connect_gpio_out_named(dev_secctl, "nsc_cfg", 0, s->nsc_cfg_in); 666 667 /* The sec_resp_cfg output from the security controller must be split into 668 * multiple lines, one for each of the PPCs within the ARMSSE and one 669 * that will be an output from the ARMSSE to the system. 670 */ 671 if (!object_property_set_int(OBJECT(&s->sec_resp_splitter), 672 "num-lines", 3, errp)) { 673 return; 674 } 675 if (!qdev_realize(DEVICE(&s->sec_resp_splitter), NULL, errp)) { 676 return; 677 } 678 dev_splitter = DEVICE(&s->sec_resp_splitter); 679 qdev_connect_gpio_out_named(dev_secctl, "sec_resp_cfg", 0, 680 qdev_get_gpio_in(dev_splitter, 0)); 681 682 /* Each SRAM bank lives behind its own Memory Protection Controller */ 683 for (i = 0; i < info->sram_banks; i++) { 684 char *ramname = g_strdup_printf("armsse.sram%d", i); 685 SysBusDevice *sbd_mpc; 686 uint32_t sram_bank_size = 1 << s->sram_addr_width; 687 688 memory_region_init_ram(&s->sram[i], NULL, ramname, 689 sram_bank_size, &err); 690 g_free(ramname); 691 if (err) { 692 error_propagate(errp, err); 693 return; 694 } 695 object_property_set_link(OBJECT(&s->mpc[i]), "downstream", 696 OBJECT(&s->sram[i]), &error_abort); 697 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mpc[i]), errp)) { 698 return; 699 } 700 /* Map the upstream end of the MPC into the right place... */ 701 sbd_mpc = SYS_BUS_DEVICE(&s->mpc[i]); 702 memory_region_add_subregion(&s->container, 703 0x20000000 + i * sram_bank_size, 704 sysbus_mmio_get_region(sbd_mpc, 1)); 705 /* ...and its register interface */ 706 memory_region_add_subregion(&s->container, 0x50083000 + i * 0x1000, 707 sysbus_mmio_get_region(sbd_mpc, 0)); 708 } 709 710 /* We must OR together lines from the MPC splitters to go to the NVIC */ 711 if (!object_property_set_int(OBJECT(&s->mpc_irq_orgate), "num-lines", 712 IOTS_NUM_EXP_MPC + info->sram_banks, 713 errp)) { 714 return; 715 } 716 if (!qdev_realize(DEVICE(&s->mpc_irq_orgate), NULL, errp)) { 717 return; 718 } 719 qdev_connect_gpio_out(DEVICE(&s->mpc_irq_orgate), 0, 720 armsse_get_common_irq_in(s, 9)); 721 722 /* Devices behind APB PPC0: 723 * 0x40000000: timer0 724 * 0x40001000: timer1 725 * 0x40002000: dual timer 726 * 0x40003000: MHU0 (SSE-200 only) 727 * 0x40004000: MHU1 (SSE-200 only) 728 * We must configure and realize each downstream device and connect 729 * it to the appropriate PPC port; then we can realize the PPC and 730 * map its upstream ends to the right place in the container. 731 */ 732 qdev_connect_clock_in(DEVICE(&s->timer0), "pclk", s->mainclk); 733 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer0), errp)) { 734 return; 735 } 736 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer0), 0, 737 armsse_get_common_irq_in(s, 3)); 738 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->timer0), 0); 739 object_property_set_link(OBJECT(&s->apb_ppc0), "port[0]", OBJECT(mr), 740 &error_abort); 741 742 qdev_connect_clock_in(DEVICE(&s->timer1), "pclk", s->mainclk); 743 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer1), errp)) { 744 return; 745 } 746 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer1), 0, 747 armsse_get_common_irq_in(s, 4)); 748 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->timer1), 0); 749 object_property_set_link(OBJECT(&s->apb_ppc0), "port[1]", OBJECT(mr), 750 &error_abort); 751 752 qdev_connect_clock_in(DEVICE(&s->dualtimer), "TIMCLK", s->mainclk); 753 if (!sysbus_realize(SYS_BUS_DEVICE(&s->dualtimer), errp)) { 754 return; 755 } 756 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dualtimer), 0, 757 armsse_get_common_irq_in(s, 5)); 758 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->dualtimer), 0); 759 object_property_set_link(OBJECT(&s->apb_ppc0), "port[2]", OBJECT(mr), 760 &error_abort); 761 762 if (info->has_mhus) { 763 /* 764 * An SSE-200 with only one CPU should have only one MHU created, 765 * with the region where the second MHU usually is being RAZ/WI. 766 * We don't implement that SSE-200 config; if we want to support 767 * it then this code needs to be enhanced to handle creating the 768 * RAZ/WI region instead of the second MHU. 769 */ 770 assert(info->num_cpus == ARRAY_SIZE(s->mhu)); 771 772 for (i = 0; i < ARRAY_SIZE(s->mhu); i++) { 773 char *port; 774 int cpunum; 775 SysBusDevice *mhu_sbd = SYS_BUS_DEVICE(&s->mhu[i]); 776 777 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mhu[i]), errp)) { 778 return; 779 } 780 port = g_strdup_printf("port[%d]", i + 3); 781 mr = sysbus_mmio_get_region(mhu_sbd, 0); 782 object_property_set_link(OBJECT(&s->apb_ppc0), port, OBJECT(mr), 783 &error_abort); 784 g_free(port); 785 786 /* 787 * Each MHU has an irq line for each CPU: 788 * MHU 0 irq line 0 -> CPU 0 IRQ 6 789 * MHU 0 irq line 1 -> CPU 1 IRQ 6 790 * MHU 1 irq line 0 -> CPU 0 IRQ 7 791 * MHU 1 irq line 1 -> CPU 1 IRQ 7 792 */ 793 for (cpunum = 0; cpunum < info->num_cpus; cpunum++) { 794 DeviceState *cpudev = DEVICE(&s->armv7m[cpunum]); 795 796 sysbus_connect_irq(mhu_sbd, cpunum, 797 qdev_get_gpio_in(cpudev, 6 + i)); 798 } 799 } 800 } 801 802 if (!sysbus_realize(SYS_BUS_DEVICE(&s->apb_ppc0), errp)) { 803 return; 804 } 805 806 sbd_apb_ppc0 = SYS_BUS_DEVICE(&s->apb_ppc0); 807 dev_apb_ppc0 = DEVICE(&s->apb_ppc0); 808 809 mr = sysbus_mmio_get_region(sbd_apb_ppc0, 0); 810 memory_region_add_subregion(&s->container, 0x40000000, mr); 811 mr = sysbus_mmio_get_region(sbd_apb_ppc0, 1); 812 memory_region_add_subregion(&s->container, 0x40001000, mr); 813 mr = sysbus_mmio_get_region(sbd_apb_ppc0, 2); 814 memory_region_add_subregion(&s->container, 0x40002000, mr); 815 if (info->has_mhus) { 816 mr = sysbus_mmio_get_region(sbd_apb_ppc0, 3); 817 memory_region_add_subregion(&s->container, 0x40003000, mr); 818 mr = sysbus_mmio_get_region(sbd_apb_ppc0, 4); 819 memory_region_add_subregion(&s->container, 0x40004000, mr); 820 } 821 for (i = 0; i < IOTS_APB_PPC0_NUM_PORTS; i++) { 822 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_nonsec", i, 823 qdev_get_gpio_in_named(dev_apb_ppc0, 824 "cfg_nonsec", i)); 825 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_ap", i, 826 qdev_get_gpio_in_named(dev_apb_ppc0, 827 "cfg_ap", i)); 828 } 829 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_irq_enable", 0, 830 qdev_get_gpio_in_named(dev_apb_ppc0, 831 "irq_enable", 0)); 832 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_irq_clear", 0, 833 qdev_get_gpio_in_named(dev_apb_ppc0, 834 "irq_clear", 0)); 835 qdev_connect_gpio_out(dev_splitter, 0, 836 qdev_get_gpio_in_named(dev_apb_ppc0, 837 "cfg_sec_resp", 0)); 838 839 /* All the PPC irq lines (from the 2 internal PPCs and the 8 external 840 * ones) are sent individually to the security controller, and also 841 * ORed together to give a single combined PPC interrupt to the NVIC. 842 */ 843 if (!object_property_set_int(OBJECT(&s->ppc_irq_orgate), 844 "num-lines", NUM_PPCS, errp)) { 845 return; 846 } 847 if (!qdev_realize(DEVICE(&s->ppc_irq_orgate), NULL, errp)) { 848 return; 849 } 850 qdev_connect_gpio_out(DEVICE(&s->ppc_irq_orgate), 0, 851 armsse_get_common_irq_in(s, 10)); 852 853 /* 854 * 0x40010000 .. 0x4001ffff (and the 0x5001000... secure-only alias): 855 * private per-CPU region (all these devices are SSE-200 only): 856 * 0x50010000: L1 icache control registers 857 * 0x50011000: CPUSECCTRL (CPU local security control registers) 858 * 0x4001f000 and 0x5001f000: CPU_IDENTITY register block 859 */ 860 if (info->has_cachectrl) { 861 for (i = 0; i < info->num_cpus; i++) { 862 char *name = g_strdup_printf("cachectrl%d", i); 863 MemoryRegion *mr; 864 865 qdev_prop_set_string(DEVICE(&s->cachectrl[i]), "name", name); 866 g_free(name); 867 qdev_prop_set_uint64(DEVICE(&s->cachectrl[i]), "size", 0x1000); 868 if (!sysbus_realize(SYS_BUS_DEVICE(&s->cachectrl[i]), errp)) { 869 return; 870 } 871 872 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cachectrl[i]), 0); 873 memory_region_add_subregion(&s->cpu_container[i], 0x50010000, mr); 874 } 875 } 876 if (info->has_cpusecctrl) { 877 for (i = 0; i < info->num_cpus; i++) { 878 char *name = g_strdup_printf("CPUSECCTRL%d", i); 879 MemoryRegion *mr; 880 881 qdev_prop_set_string(DEVICE(&s->cpusecctrl[i]), "name", name); 882 g_free(name); 883 qdev_prop_set_uint64(DEVICE(&s->cpusecctrl[i]), "size", 0x1000); 884 if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpusecctrl[i]), errp)) { 885 return; 886 } 887 888 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpusecctrl[i]), 0); 889 memory_region_add_subregion(&s->cpu_container[i], 0x50011000, mr); 890 } 891 } 892 if (info->has_cpuid) { 893 for (i = 0; i < info->num_cpus; i++) { 894 MemoryRegion *mr; 895 896 qdev_prop_set_uint32(DEVICE(&s->cpuid[i]), "CPUID", i); 897 if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpuid[i]), errp)) { 898 return; 899 } 900 901 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpuid[i]), 0); 902 memory_region_add_subregion(&s->cpu_container[i], 0x4001F000, mr); 903 } 904 } 905 906 /* 0x40020000 .. 0x4002ffff : ARMSSE system control peripheral region */ 907 /* Devices behind APB PPC1: 908 * 0x4002f000: S32K timer 909 */ 910 qdev_connect_clock_in(DEVICE(&s->s32ktimer), "pclk", s->s32kclk); 911 if (!sysbus_realize(SYS_BUS_DEVICE(&s->s32ktimer), errp)) { 912 return; 913 } 914 sysbus_connect_irq(SYS_BUS_DEVICE(&s->s32ktimer), 0, 915 armsse_get_common_irq_in(s, 2)); 916 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->s32ktimer), 0); 917 object_property_set_link(OBJECT(&s->apb_ppc1), "port[0]", OBJECT(mr), 918 &error_abort); 919 920 if (!sysbus_realize(SYS_BUS_DEVICE(&s->apb_ppc1), errp)) { 921 return; 922 } 923 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->apb_ppc1), 0); 924 memory_region_add_subregion(&s->container, 0x4002f000, mr); 925 926 dev_apb_ppc1 = DEVICE(&s->apb_ppc1); 927 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_nonsec", 0, 928 qdev_get_gpio_in_named(dev_apb_ppc1, 929 "cfg_nonsec", 0)); 930 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_ap", 0, 931 qdev_get_gpio_in_named(dev_apb_ppc1, 932 "cfg_ap", 0)); 933 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_irq_enable", 0, 934 qdev_get_gpio_in_named(dev_apb_ppc1, 935 "irq_enable", 0)); 936 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_irq_clear", 0, 937 qdev_get_gpio_in_named(dev_apb_ppc1, 938 "irq_clear", 0)); 939 qdev_connect_gpio_out(dev_splitter, 1, 940 qdev_get_gpio_in_named(dev_apb_ppc1, 941 "cfg_sec_resp", 0)); 942 943 if (!object_property_set_int(OBJECT(&s->sysinfo), "SYS_VERSION", 944 info->sys_version, errp)) { 945 return; 946 } 947 if (!object_property_set_int(OBJECT(&s->sysinfo), "SYS_CONFIG", 948 armsse_sys_config_value(s, info), errp)) { 949 return; 950 } 951 object_property_set_int(OBJECT(&s->sysinfo), "sse-version", 952 info->sse_version, &error_abort); 953 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sysinfo), errp)) { 954 return; 955 } 956 /* System information registers */ 957 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysinfo), 0, 0x40020000); 958 /* System control registers */ 959 object_property_set_int(OBJECT(&s->sysctl), "sse-version", 960 info->sse_version, &error_abort); 961 object_property_set_int(OBJECT(&s->sysctl), "CPUWAIT_RST", 962 info->cpuwait_rst, &error_abort); 963 object_property_set_int(OBJECT(&s->sysctl), "INITSVTOR0_RST", 964 s->init_svtor, &error_abort); 965 object_property_set_int(OBJECT(&s->sysctl), "INITSVTOR1_RST", 966 s->init_svtor, &error_abort); 967 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sysctl), errp)) { 968 return; 969 } 970 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysctl), 0, 0x50021000); 971 972 if (info->has_ppus) { 973 /* CPUnCORE_PPU for each CPU */ 974 for (i = 0; i < info->num_cpus; i++) { 975 char *name = g_strdup_printf("CPU%dCORE_PPU", i); 976 977 map_ppu(s, CPU0CORE_PPU + i, name, 0x50023000 + i * 0x2000); 978 /* 979 * We don't support CPU debug so don't create the 980 * CPU0DEBUG_PPU at 0x50024000 and 0x50026000. 981 */ 982 g_free(name); 983 } 984 map_ppu(s, DBG_PPU, "DBG_PPU", 0x50029000); 985 986 for (i = 0; i < info->sram_banks; i++) { 987 char *name = g_strdup_printf("RAM%d_PPU", i); 988 989 map_ppu(s, RAM0_PPU + i, name, 0x5002a000 + i * 0x1000); 990 g_free(name); 991 } 992 } 993 994 /* This OR gate wires together outputs from the secure watchdogs to NMI */ 995 if (!object_property_set_int(OBJECT(&s->nmi_orgate), "num-lines", 2, 996 errp)) { 997 return; 998 } 999 if (!qdev_realize(DEVICE(&s->nmi_orgate), NULL, errp)) { 1000 return; 1001 } 1002 qdev_connect_gpio_out(DEVICE(&s->nmi_orgate), 0, 1003 qdev_get_gpio_in_named(DEVICE(&s->armv7m), "NMI", 0)); 1004 1005 qdev_connect_clock_in(DEVICE(&s->s32kwatchdog), "WDOGCLK", s->s32kclk); 1006 if (!sysbus_realize(SYS_BUS_DEVICE(&s->s32kwatchdog), errp)) { 1007 return; 1008 } 1009 sysbus_connect_irq(SYS_BUS_DEVICE(&s->s32kwatchdog), 0, 1010 qdev_get_gpio_in(DEVICE(&s->nmi_orgate), 0)); 1011 sysbus_mmio_map(SYS_BUS_DEVICE(&s->s32kwatchdog), 0, 0x5002e000); 1012 1013 /* 0x40080000 .. 0x4008ffff : ARMSSE second Base peripheral region */ 1014 1015 qdev_connect_clock_in(DEVICE(&s->nswatchdog), "WDOGCLK", s->mainclk); 1016 if (!sysbus_realize(SYS_BUS_DEVICE(&s->nswatchdog), errp)) { 1017 return; 1018 } 1019 sysbus_connect_irq(SYS_BUS_DEVICE(&s->nswatchdog), 0, 1020 armsse_get_common_irq_in(s, 1)); 1021 sysbus_mmio_map(SYS_BUS_DEVICE(&s->nswatchdog), 0, 0x40081000); 1022 1023 qdev_connect_clock_in(DEVICE(&s->swatchdog), "WDOGCLK", s->mainclk); 1024 if (!sysbus_realize(SYS_BUS_DEVICE(&s->swatchdog), errp)) { 1025 return; 1026 } 1027 sysbus_connect_irq(SYS_BUS_DEVICE(&s->swatchdog), 0, 1028 qdev_get_gpio_in(DEVICE(&s->nmi_orgate), 1)); 1029 sysbus_mmio_map(SYS_BUS_DEVICE(&s->swatchdog), 0, 0x50081000); 1030 1031 for (i = 0; i < ARRAY_SIZE(s->ppc_irq_splitter); i++) { 1032 Object *splitter = OBJECT(&s->ppc_irq_splitter[i]); 1033 1034 if (!object_property_set_int(splitter, "num-lines", 2, errp)) { 1035 return; 1036 } 1037 if (!qdev_realize(DEVICE(splitter), NULL, errp)) { 1038 return; 1039 } 1040 } 1041 1042 for (i = 0; i < IOTS_NUM_AHB_EXP_PPC; i++) { 1043 char *ppcname = g_strdup_printf("ahb_ppcexp%d", i); 1044 1045 armsse_forward_ppc(s, ppcname, i); 1046 g_free(ppcname); 1047 } 1048 1049 for (i = 0; i < IOTS_NUM_APB_EXP_PPC; i++) { 1050 char *ppcname = g_strdup_printf("apb_ppcexp%d", i); 1051 1052 armsse_forward_ppc(s, ppcname, i + IOTS_NUM_AHB_EXP_PPC); 1053 g_free(ppcname); 1054 } 1055 1056 for (i = NUM_EXTERNAL_PPCS; i < NUM_PPCS; i++) { 1057 /* Wire up IRQ splitter for internal PPCs */ 1058 DeviceState *devs = DEVICE(&s->ppc_irq_splitter[i]); 1059 char *gpioname = g_strdup_printf("apb_ppc%d_irq_status", 1060 i - NUM_EXTERNAL_PPCS); 1061 TZPPC *ppc = (i == NUM_EXTERNAL_PPCS) ? &s->apb_ppc0 : &s->apb_ppc1; 1062 1063 qdev_connect_gpio_out(devs, 0, 1064 qdev_get_gpio_in_named(dev_secctl, gpioname, 0)); 1065 qdev_connect_gpio_out(devs, 1, 1066 qdev_get_gpio_in(DEVICE(&s->ppc_irq_orgate), i)); 1067 qdev_connect_gpio_out_named(DEVICE(ppc), "irq", 0, 1068 qdev_get_gpio_in(devs, 0)); 1069 g_free(gpioname); 1070 } 1071 1072 /* Wire up the splitters for the MPC IRQs */ 1073 for (i = 0; i < IOTS_NUM_EXP_MPC + info->sram_banks; i++) { 1074 SplitIRQ *splitter = &s->mpc_irq_splitter[i]; 1075 DeviceState *dev_splitter = DEVICE(splitter); 1076 1077 if (!object_property_set_int(OBJECT(splitter), "num-lines", 2, 1078 errp)) { 1079 return; 1080 } 1081 if (!qdev_realize(DEVICE(splitter), NULL, errp)) { 1082 return; 1083 } 1084 1085 if (i < IOTS_NUM_EXP_MPC) { 1086 /* Splitter input is from GPIO input line */ 1087 s->mpcexp_status_in[i] = qdev_get_gpio_in(dev_splitter, 0); 1088 qdev_connect_gpio_out(dev_splitter, 0, 1089 qdev_get_gpio_in_named(dev_secctl, 1090 "mpcexp_status", i)); 1091 } else { 1092 /* Splitter input is from our own MPC */ 1093 qdev_connect_gpio_out_named(DEVICE(&s->mpc[i - IOTS_NUM_EXP_MPC]), 1094 "irq", 0, 1095 qdev_get_gpio_in(dev_splitter, 0)); 1096 qdev_connect_gpio_out(dev_splitter, 0, 1097 qdev_get_gpio_in_named(dev_secctl, 1098 "mpc_status", 1099 i - IOTS_NUM_EXP_MPC)); 1100 } 1101 1102 qdev_connect_gpio_out(dev_splitter, 1, 1103 qdev_get_gpio_in(DEVICE(&s->mpc_irq_orgate), i)); 1104 } 1105 /* Create GPIO inputs which will pass the line state for our 1106 * mpcexp_irq inputs to the correct splitter devices. 1107 */ 1108 qdev_init_gpio_in_named(dev, armsse_mpcexp_status, "mpcexp_status", 1109 IOTS_NUM_EXP_MPC); 1110 1111 armsse_forward_sec_resp_cfg(s); 1112 1113 /* Forward the MSC related signals */ 1114 qdev_pass_gpios(dev_secctl, dev, "mscexp_status"); 1115 qdev_pass_gpios(dev_secctl, dev, "mscexp_clear"); 1116 qdev_pass_gpios(dev_secctl, dev, "mscexp_ns"); 1117 qdev_connect_gpio_out_named(dev_secctl, "msc_irq", 0, 1118 armsse_get_common_irq_in(s, 11)); 1119 1120 /* 1121 * Expose our container region to the board model; this corresponds 1122 * to the AHB Slave Expansion ports which allow bus master devices 1123 * (eg DMA controllers) in the board model to make transactions into 1124 * devices in the ARMSSE. 1125 */ 1126 sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->container); 1127 1128 /* Set initial system_clock_scale from MAINCLK */ 1129 armsse_mainclk_update(s, ClockUpdate); 1130 } 1131 1132 static void armsse_idau_check(IDAUInterface *ii, uint32_t address, 1133 int *iregion, bool *exempt, bool *ns, bool *nsc) 1134 { 1135 /* 1136 * For ARMSSE systems the IDAU responses are simple logical functions 1137 * of the address bits. The NSC attribute is guest-adjustable via the 1138 * NSCCFG register in the security controller. 1139 */ 1140 ARMSSE *s = ARM_SSE(ii); 1141 int region = extract32(address, 28, 4); 1142 1143 *ns = !(region & 1); 1144 *nsc = (region == 1 && (s->nsccfg & 1)) || (region == 3 && (s->nsccfg & 2)); 1145 /* 0xe0000000..0xe00fffff and 0xf0000000..0xf00fffff are exempt */ 1146 *exempt = (address & 0xeff00000) == 0xe0000000; 1147 *iregion = region; 1148 } 1149 1150 static const VMStateDescription armsse_vmstate = { 1151 .name = "iotkit", 1152 .version_id = 2, 1153 .minimum_version_id = 2, 1154 .fields = (VMStateField[]) { 1155 VMSTATE_CLOCK(mainclk, ARMSSE), 1156 VMSTATE_CLOCK(s32kclk, ARMSSE), 1157 VMSTATE_UINT32(nsccfg, ARMSSE), 1158 VMSTATE_END_OF_LIST() 1159 } 1160 }; 1161 1162 static void armsse_reset(DeviceState *dev) 1163 { 1164 ARMSSE *s = ARM_SSE(dev); 1165 1166 s->nsccfg = 0; 1167 } 1168 1169 static void armsse_class_init(ObjectClass *klass, void *data) 1170 { 1171 DeviceClass *dc = DEVICE_CLASS(klass); 1172 IDAUInterfaceClass *iic = IDAU_INTERFACE_CLASS(klass); 1173 ARMSSEClass *asc = ARM_SSE_CLASS(klass); 1174 const ARMSSEInfo *info = data; 1175 1176 dc->realize = armsse_realize; 1177 dc->vmsd = &armsse_vmstate; 1178 device_class_set_props(dc, info->props); 1179 dc->reset = armsse_reset; 1180 iic->check = armsse_idau_check; 1181 asc->info = info; 1182 } 1183 1184 static const TypeInfo armsse_info = { 1185 .name = TYPE_ARM_SSE, 1186 .parent = TYPE_SYS_BUS_DEVICE, 1187 .instance_size = sizeof(ARMSSE), 1188 .class_size = sizeof(ARMSSEClass), 1189 .instance_init = armsse_init, 1190 .abstract = true, 1191 .interfaces = (InterfaceInfo[]) { 1192 { TYPE_IDAU_INTERFACE }, 1193 { } 1194 } 1195 }; 1196 1197 static void armsse_register_types(void) 1198 { 1199 int i; 1200 1201 type_register_static(&armsse_info); 1202 1203 for (i = 0; i < ARRAY_SIZE(armsse_variants); i++) { 1204 TypeInfo ti = { 1205 .name = armsse_variants[i].name, 1206 .parent = TYPE_ARM_SSE, 1207 .class_init = armsse_class_init, 1208 .class_data = (void *)&armsse_variants[i], 1209 }; 1210 type_register(&ti); 1211 } 1212 } 1213 1214 type_init(armsse_register_types); 1215